1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 2/* Copyright(c) 2018-2019  Realtek Corporation
 3 */
 4
 5#ifndef __RTW_RX_H_
 6#define __RTW_RX_H_
 7
 8enum rtw_rx_desc_enc {
 9	RX_DESC_ENC_NONE	= 0,
10	RX_DESC_ENC_WEP40	= 1,
11	RX_DESC_ENC_TKIP_WO_MIC	= 2,
12	RX_DESC_ENC_TKIP_MIC	= 3,
13	RX_DESC_ENC_AES		= 4,
14	RX_DESC_ENC_WEP104	= 5,
15};
16
17struct rtw_rx_desc {
18	__le32 w0;
19	__le32 w1;
20	__le32 w2;
21	__le32 w3;
22	__le32 w4;
23	__le32 w5;
24} __packed;
25
26#define RTW_RX_DESC_W0_PKT_LEN		GENMASK(13, 0)
27#define RTW_RX_DESC_W0_CRC32		BIT(14)
28#define RTW_RX_DESC_W0_ICV_ERR		BIT(15)
29#define RTW_RX_DESC_W0_DRV_INFO_SIZE	GENMASK(19, 16)
30#define RTW_RX_DESC_W0_ENC_TYPE		GENMASK(22, 20)
31#define RTW_RX_DESC_W0_SHIFT		GENMASK(25, 24)
32#define RTW_RX_DESC_W0_PHYST		BIT(26)
33#define RTW_RX_DESC_W0_SWDEC		BIT(27)
34
35#define RTW_RX_DESC_W1_MACID		GENMASK(6, 0)
36
37#define RTW_RX_DESC_W2_C2H		BIT(28)
38#define RTW_RX_DESC_W2_PPDU_CNT		GENMASK(30, 29)
39
40#define RTW_RX_DESC_W3_RX_RATE		GENMASK(6, 0)
41
42#define RTW_RX_DESC_W4_BW		GENMASK(5, 4)
43
44#define RTW_RX_DESC_W5_TSFL		GENMASK(31, 0)
45
46void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
47		  struct sk_buff *skb);
48void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
49			  struct rtw_rx_pkt_stat *pkt_stat,
50			  struct ieee80211_rx_status *rx_status);
51void rtw_update_rx_freq_from_ie(struct rtw_dev *rtwdev, struct sk_buff *skb,
52				struct ieee80211_rx_status *rx_status,
53				struct rtw_rx_pkt_stat *pkt_stat);
54
55static inline
56void rtw_update_rx_freq_for_invalid(struct rtw_dev *rtwdev, struct sk_buff *skb,
57				    struct ieee80211_rx_status *rx_status,
58				    struct rtw_rx_pkt_stat *pkt_stat)
59{
60	if (pkt_stat->channel_invalid)
61		rtw_update_rx_freq_from_ie(rtwdev, skb, rx_status, pkt_stat);
62}
63
64
65#endif