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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/devcoredump.h>
6
7#include "main.h"
8#include "regd.h"
9#include "fw.h"
10#include "ps.h"
11#include "sec.h"
12#include "mac.h"
13#include "coex.h"
14#include "phy.h"
15#include "reg.h"
16#include "efuse.h"
17#include "tx.h"
18#include "debug.h"
19#include "bf.h"
20#include "sar.h"
21#include "sdio.h"
22
23bool rtw_disable_lps_deep_mode;
24EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
25bool rtw_bf_support = true;
26unsigned int rtw_debug_mask;
27EXPORT_SYMBOL(rtw_debug_mask);
28/* EDCCA is enabled during normal behavior. For debugging purpose in
29 * a noisy environment, it can be disabled via edcca debugfs. Because
30 * all rtw88 devices will probably be affected if environment is noisy,
31 * rtw_edcca_enabled is just declared by driver instead of by device.
32 * So, turning it off will take effect for all rtw88 devices before
33 * there is a tough reason to maintain rtw_edcca_enabled by device.
34 */
35bool rtw_edcca_enabled = true;
36
37module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
38module_param_named(support_bf, rtw_bf_support, bool, 0644);
39module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
40
41MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
42MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
43MODULE_PARM_DESC(debug_mask, "Debugging mask");
44
45static struct ieee80211_channel rtw_channeltable_2g[] = {
46 {.center_freq = 2412, .hw_value = 1,},
47 {.center_freq = 2417, .hw_value = 2,},
48 {.center_freq = 2422, .hw_value = 3,},
49 {.center_freq = 2427, .hw_value = 4,},
50 {.center_freq = 2432, .hw_value = 5,},
51 {.center_freq = 2437, .hw_value = 6,},
52 {.center_freq = 2442, .hw_value = 7,},
53 {.center_freq = 2447, .hw_value = 8,},
54 {.center_freq = 2452, .hw_value = 9,},
55 {.center_freq = 2457, .hw_value = 10,},
56 {.center_freq = 2462, .hw_value = 11,},
57 {.center_freq = 2467, .hw_value = 12,},
58 {.center_freq = 2472, .hw_value = 13,},
59 {.center_freq = 2484, .hw_value = 14,},
60};
61
62static struct ieee80211_channel rtw_channeltable_5g[] = {
63 {.center_freq = 5180, .hw_value = 36,},
64 {.center_freq = 5200, .hw_value = 40,},
65 {.center_freq = 5220, .hw_value = 44,},
66 {.center_freq = 5240, .hw_value = 48,},
67 {.center_freq = 5260, .hw_value = 52,},
68 {.center_freq = 5280, .hw_value = 56,},
69 {.center_freq = 5300, .hw_value = 60,},
70 {.center_freq = 5320, .hw_value = 64,},
71 {.center_freq = 5500, .hw_value = 100,},
72 {.center_freq = 5520, .hw_value = 104,},
73 {.center_freq = 5540, .hw_value = 108,},
74 {.center_freq = 5560, .hw_value = 112,},
75 {.center_freq = 5580, .hw_value = 116,},
76 {.center_freq = 5600, .hw_value = 120,},
77 {.center_freq = 5620, .hw_value = 124,},
78 {.center_freq = 5640, .hw_value = 128,},
79 {.center_freq = 5660, .hw_value = 132,},
80 {.center_freq = 5680, .hw_value = 136,},
81 {.center_freq = 5700, .hw_value = 140,},
82 {.center_freq = 5720, .hw_value = 144,},
83 {.center_freq = 5745, .hw_value = 149,},
84 {.center_freq = 5765, .hw_value = 153,},
85 {.center_freq = 5785, .hw_value = 157,},
86 {.center_freq = 5805, .hw_value = 161,},
87 {.center_freq = 5825, .hw_value = 165,
88 .flags = IEEE80211_CHAN_NO_HT40MINUS},
89};
90
91static struct ieee80211_rate rtw_ratetable[] = {
92 {.bitrate = 10, .hw_value = 0x00,},
93 {.bitrate = 20, .hw_value = 0x01,},
94 {.bitrate = 55, .hw_value = 0x02,},
95 {.bitrate = 110, .hw_value = 0x03,},
96 {.bitrate = 60, .hw_value = 0x04,},
97 {.bitrate = 90, .hw_value = 0x05,},
98 {.bitrate = 120, .hw_value = 0x06,},
99 {.bitrate = 180, .hw_value = 0x07,},
100 {.bitrate = 240, .hw_value = 0x08,},
101 {.bitrate = 360, .hw_value = 0x09,},
102 {.bitrate = 480, .hw_value = 0x0a,},
103 {.bitrate = 540, .hw_value = 0x0b,},
104};
105
106static const struct ieee80211_iface_limit rtw_iface_limits[] = {
107 {
108 .max = 1,
109 .types = BIT(NL80211_IFTYPE_STATION),
110 },
111 {
112 .max = 1,
113 .types = BIT(NL80211_IFTYPE_AP),
114 }
115};
116
117static const struct ieee80211_iface_combination rtw_iface_combs[] = {
118 {
119 .limits = rtw_iface_limits,
120 .n_limits = ARRAY_SIZE(rtw_iface_limits),
121 .max_interfaces = 2,
122 .num_different_channels = 1,
123 }
124};
125
126u16 rtw_desc_to_bitrate(u8 desc_rate)
127{
128 struct ieee80211_rate rate;
129
130 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
131 return 0;
132
133 rate = rtw_ratetable[desc_rate];
134
135 return rate.bitrate;
136}
137
138static struct ieee80211_supported_band rtw_band_2ghz = {
139 .band = NL80211_BAND_2GHZ,
140
141 .channels = rtw_channeltable_2g,
142 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
143
144 .bitrates = rtw_ratetable,
145 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
146
147 .ht_cap = {0},
148 .vht_cap = {0},
149};
150
151static struct ieee80211_supported_band rtw_band_5ghz = {
152 .band = NL80211_BAND_5GHZ,
153
154 .channels = rtw_channeltable_5g,
155 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
156
157 /* 5G has no CCK rates */
158 .bitrates = rtw_ratetable + 4,
159 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
160
161 .ht_cap = {0},
162 .vht_cap = {0},
163};
164
165struct rtw_watch_dog_iter_data {
166 struct rtw_dev *rtwdev;
167 struct rtw_vif *rtwvif;
168};
169
170static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
171{
172 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
173 u8 fix_rate_enable = 0;
174 u8 new_csi_rate_idx;
175
176 if (rtwvif->bfee.role != RTW_BFEE_SU &&
177 rtwvif->bfee.role != RTW_BFEE_MU)
178 return;
179
180 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
181 bf_info->cur_csi_rpt_rate,
182 fix_rate_enable, &new_csi_rate_idx);
183
184 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
185 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
186}
187
188static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif)
189{
190 struct rtw_watch_dog_iter_data *iter_data = data;
191 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
192
193 if (vif->type == NL80211_IFTYPE_STATION)
194 if (vif->cfg.assoc)
195 iter_data->rtwvif = rtwvif;
196
197 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
198
199 rtwvif->stats.tx_unicast = 0;
200 rtwvif->stats.rx_unicast = 0;
201 rtwvif->stats.tx_cnt = 0;
202 rtwvif->stats.rx_cnt = 0;
203}
204
205static void rtw_sw_beacon_loss_check(struct rtw_dev *rtwdev,
206 struct rtw_vif *rtwvif, int received_beacons)
207{
208 int watchdog_delay = 2000000 / 1024; /* TU */
209 int beacon_int, expected_beacons;
210
211 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER) || !rtwvif)
212 return;
213
214 beacon_int = rtwvif_to_vif(rtwvif)->bss_conf.beacon_int;
215 expected_beacons = DIV_ROUND_UP(watchdog_delay, beacon_int);
216
217 rtwdev->beacon_loss = received_beacons < expected_beacons / 2;
218}
219
220/* process TX/RX statistics periodically for hardware,
221 * the information helps hardware to enhance performance
222 */
223static void rtw_watch_dog_work(struct work_struct *work)
224{
225 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
226 watch_dog_work.work);
227 struct rtw_traffic_stats *stats = &rtwdev->stats;
228 struct rtw_watch_dog_iter_data data = {};
229 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
230 int received_beacons = rtwdev->dm_info.cur_pkt_count.num_bcn_pkt;
231 u32 tx_unicast_mbps, rx_unicast_mbps;
232 bool ps_active;
233
234 mutex_lock(&rtwdev->mutex);
235
236 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
237 goto unlock;
238
239 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
240 RTW_WATCH_DOG_DELAY_TIME);
241
242 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
243 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
244 else
245 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
246
247 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
248 rtw_coex_wl_status_change_notify(rtwdev, 0);
249
250 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
251 stats->rx_cnt > RTW_LPS_THRESHOLD)
252 ps_active = true;
253 else
254 ps_active = false;
255
256 tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT;
257 rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT;
258
259 ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps);
260 ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps);
261 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
262 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
263
264 /* reset tx/rx statictics */
265 stats->tx_unicast = 0;
266 stats->rx_unicast = 0;
267 stats->tx_cnt = 0;
268 stats->rx_cnt = 0;
269
270 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
271 goto unlock;
272
273 /* make sure BB/RF is working for dynamic mech */
274 rtw_leave_lps(rtwdev);
275 rtw_coex_wl_status_check(rtwdev);
276 rtw_coex_query_bt_hid_list(rtwdev);
277 rtw_coex_active_query_bt_info(rtwdev);
278
279 rtw_phy_dynamic_mechanism(rtwdev);
280
281 rtw_hci_dynamic_rx_agg(rtwdev,
282 tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1);
283
284 data.rtwdev = rtwdev;
285 /* rtw_iterate_vifs internally uses an atomic iterator which is needed
286 * to avoid taking local->iflist_mtx mutex
287 */
288 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data);
289
290 rtw_sw_beacon_loss_check(rtwdev, data.rtwvif, received_beacons);
291
292 /* fw supports only one station associated to enter lps, if there are
293 * more than two stations associated to the AP, then we can not enter
294 * lps, because fw does not handle the overlapped beacon interval
295 *
296 * rtw_recalc_lps() iterate vifs and determine if driver can enter
297 * ps by vif->type and vif->cfg.ps, all we need to do here is to
298 * get that vif and check if device is having traffic more than the
299 * threshold.
300 */
301 if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
302 !rtwdev->beacon_loss && !rtwdev->ap_active)
303 rtw_enter_lps(rtwdev, data.rtwvif->port);
304
305 rtwdev->watch_dog_cnt++;
306
307unlock:
308 mutex_unlock(&rtwdev->mutex);
309}
310
311static void rtw_c2h_work(struct work_struct *work)
312{
313 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
314 struct sk_buff *skb, *tmp;
315
316 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
317 skb_unlink(skb, &rtwdev->c2h_queue);
318 rtw_fw_c2h_cmd_handle(rtwdev, skb);
319 dev_kfree_skb_any(skb);
320 }
321}
322
323static void rtw_ips_work(struct work_struct *work)
324{
325 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
326
327 mutex_lock(&rtwdev->mutex);
328 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
329 rtw_enter_ips(rtwdev);
330 mutex_unlock(&rtwdev->mutex);
331}
332
333static void rtw_sta_rc_work(struct work_struct *work)
334{
335 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info,
336 rc_work);
337 struct rtw_dev *rtwdev = si->rtwdev;
338
339 mutex_lock(&rtwdev->mutex);
340 rtw_update_sta_info(rtwdev, si, true);
341 mutex_unlock(&rtwdev->mutex);
342}
343
344int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
345 struct ieee80211_vif *vif)
346{
347 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
348 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
349 int i;
350
351 if (vif->type == NL80211_IFTYPE_STATION) {
352 si->mac_id = rtwvif->mac_id;
353 } else {
354 si->mac_id = rtw_acquire_macid(rtwdev);
355 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
356 return -ENOSPC;
357 }
358
359 si->rtwdev = rtwdev;
360 si->sta = sta;
361 si->vif = vif;
362 si->init_ra_lv = 1;
363 ewma_rssi_init(&si->avg_rssi);
364 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
365 rtw_txq_init(rtwdev, sta->txq[i]);
366 INIT_WORK(&si->rc_work, rtw_sta_rc_work);
367
368 rtw_update_sta_info(rtwdev, si, true);
369 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
370
371 rtwdev->sta_cnt++;
372 rtwdev->beacon_loss = false;
373 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
374 sta->addr, si->mac_id);
375
376 return 0;
377}
378
379void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
380 bool fw_exist)
381{
382 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
383 struct ieee80211_vif *vif = si->vif;
384 int i;
385
386 cancel_work_sync(&si->rc_work);
387
388 if (vif->type != NL80211_IFTYPE_STATION)
389 rtw_release_macid(rtwdev, si->mac_id);
390 if (fw_exist)
391 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
392
393 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
394 rtw_txq_cleanup(rtwdev, sta->txq[i]);
395
396 kfree(si->mask);
397
398 rtwdev->sta_cnt--;
399 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
400 sta->addr, si->mac_id);
401}
402
403struct rtw_fwcd_hdr {
404 u32 item;
405 u32 size;
406 u32 padding1;
407 u32 padding2;
408} __packed;
409
410static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
411{
412 const struct rtw_chip_info *chip = rtwdev->chip;
413 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
414 const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
415 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
416 u8 i;
417
418 if (segs) {
419 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
420
421 for (i = 0; i < segs->num; i++)
422 prep_size += segs->segs[i];
423 }
424
425 desc->data = vmalloc(prep_size);
426 if (!desc->data)
427 return -ENOMEM;
428
429 desc->size = prep_size;
430 desc->next = desc->data;
431
432 return 0;
433}
434
435static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
436{
437 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
438 struct rtw_fwcd_hdr *hdr;
439 u8 *next;
440
441 if (!desc->data) {
442 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
443 return NULL;
444 }
445
446 next = desc->next + sizeof(struct rtw_fwcd_hdr);
447 if (next - desc->data + size > desc->size) {
448 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
449 return NULL;
450 }
451
452 hdr = (struct rtw_fwcd_hdr *)(desc->next);
453 hdr->item = item;
454 hdr->size = size;
455 hdr->padding1 = 0x01234567;
456 hdr->padding2 = 0x89abcdef;
457 desc->next = next + size;
458
459 return next;
460}
461
462static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
463{
464 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
465
466 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
467
468 /* Data will be freed after lifetime of device coredump. After calling
469 * dev_coredump, data is supposed to be handled by the device coredump
470 * framework. Note that a new dump will be discarded if a previous one
471 * hasn't been released yet.
472 */
473 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
474}
475
476static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
477{
478 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
479
480 if (free_self) {
481 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
482 vfree(desc->data);
483 }
484
485 desc->data = NULL;
486 desc->next = NULL;
487}
488
489static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
490{
491 u32 size = rtwdev->chip->fw_rxff_size;
492 u32 *buf;
493 u8 seq;
494
495 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
496 if (!buf)
497 return -ENOMEM;
498
499 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
500 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
501 return -EINVAL;
502 }
503
504 if (GET_FW_DUMP_LEN(buf) == 0) {
505 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
506 return -EINVAL;
507 }
508
509 seq = GET_FW_DUMP_SEQ(buf);
510 if (seq > 0) {
511 rtw_dbg(rtwdev, RTW_DBG_FW,
512 "fw crash dump's seq is wrong: %d\n", seq);
513 return -EINVAL;
514 }
515
516 return 0;
517}
518
519int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
520 u32 fwcd_item)
521{
522 u32 rxff = rtwdev->chip->fw_rxff_size;
523 u32 dump_size, done_size = 0;
524 u8 *buf;
525 int ret;
526
527 buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
528 if (!buf)
529 return -ENOMEM;
530
531 while (size) {
532 dump_size = size > rxff ? rxff : size;
533
534 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
535 dump_size);
536 if (ret) {
537 rtw_err(rtwdev,
538 "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
539 ocp_src, done_size);
540 return ret;
541 }
542
543 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
544 dump_size, (u32 *)(buf + done_size));
545 if (ret) {
546 rtw_err(rtwdev,
547 "dump fw 0x%x [+0x%x] from fw fifo fail\n",
548 ocp_src, done_size);
549 return ret;
550 }
551
552 size -= dump_size;
553 done_size += dump_size;
554 }
555
556 return 0;
557}
558EXPORT_SYMBOL(rtw_dump_fw);
559
560int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
561{
562 u8 *buf;
563 u32 i;
564
565 if (addr & 0x3) {
566 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
567 return -EINVAL;
568 }
569
570 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
571 if (!buf)
572 return -ENOMEM;
573
574 for (i = 0; i < size; i += 4)
575 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
576
577 return 0;
578}
579EXPORT_SYMBOL(rtw_dump_reg);
580
581void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
582 struct ieee80211_bss_conf *conf)
583{
584 struct ieee80211_vif *vif = NULL;
585
586 if (conf)
587 vif = container_of(conf, struct ieee80211_vif, bss_conf);
588
589 if (conf && vif->cfg.assoc) {
590 rtwvif->aid = vif->cfg.aid;
591 rtwvif->net_type = RTW_NET_MGD_LINKED;
592 } else {
593 rtwvif->aid = 0;
594 rtwvif->net_type = RTW_NET_NO_LINK;
595 }
596}
597
598static void rtw_reset_key_iter(struct ieee80211_hw *hw,
599 struct ieee80211_vif *vif,
600 struct ieee80211_sta *sta,
601 struct ieee80211_key_conf *key,
602 void *data)
603{
604 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
605 struct rtw_sec_desc *sec = &rtwdev->sec;
606
607 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
608}
609
610static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
611{
612 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
613
614 if (rtwdev->sta_cnt == 0) {
615 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
616 return;
617 }
618 rtw_sta_remove(rtwdev, sta, false);
619}
620
621static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
622{
623 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
624 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
625
626 rtw_bf_disassoc(rtwdev, vif, NULL);
627 rtw_vif_assoc_changed(rtwvif, NULL);
628 rtw_txq_cleanup(rtwdev, vif->txq);
629
630 rtw_release_macid(rtwdev, rtwvif->mac_id);
631}
632
633void rtw_fw_recovery(struct rtw_dev *rtwdev)
634{
635 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
636 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
637}
638
639static void __fw_recovery_work(struct rtw_dev *rtwdev)
640{
641 int ret = 0;
642
643 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
644 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
645
646 ret = rtw_fwcd_prep(rtwdev);
647 if (ret)
648 goto free;
649 ret = rtw_fw_dump_crash_log(rtwdev);
650 if (ret)
651 goto free;
652 ret = rtw_chip_dump_fw_crash(rtwdev);
653 if (ret)
654 goto free;
655
656 rtw_fwcd_dump(rtwdev);
657free:
658 rtw_fwcd_free(rtwdev, !!ret);
659 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
660
661 WARN(1, "firmware crash, start reset and recover\n");
662
663 rcu_read_lock();
664 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
665 rcu_read_unlock();
666 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
667 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
668 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM);
669 rtw_enter_ips(rtwdev);
670}
671
672static void rtw_fw_recovery_work(struct work_struct *work)
673{
674 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
675 fw_recovery_work);
676
677 mutex_lock(&rtwdev->mutex);
678 __fw_recovery_work(rtwdev);
679 mutex_unlock(&rtwdev->mutex);
680
681 ieee80211_restart_hw(rtwdev->hw);
682}
683
684struct rtw_txq_ba_iter_data {
685};
686
687static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
688{
689 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
690 int ret;
691 u8 tid;
692
693 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
694 while (tid != IEEE80211_NUM_TIDS) {
695 clear_bit(tid, si->tid_ba);
696 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
697 if (ret == -EINVAL) {
698 struct ieee80211_txq *txq;
699 struct rtw_txq *rtwtxq;
700
701 txq = sta->txq[tid];
702 rtwtxq = (struct rtw_txq *)txq->drv_priv;
703 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
704 }
705
706 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
707 }
708}
709
710static void rtw_txq_ba_work(struct work_struct *work)
711{
712 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
713 struct rtw_txq_ba_iter_data data;
714
715 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
716}
717
718void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
719{
720 if (IS_CH_2G_BAND(channel))
721 pkt_stat->band = NL80211_BAND_2GHZ;
722 else if (IS_CH_5G_BAND(channel))
723 pkt_stat->band = NL80211_BAND_5GHZ;
724 else
725 return;
726
727 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
728}
729EXPORT_SYMBOL(rtw_set_rx_freq_band);
730
731void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
732{
733 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
734 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
735}
736
737void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
738 u8 primary_channel, enum rtw_supported_band band,
739 enum rtw_bandwidth bandwidth)
740{
741 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
742 struct rtw_hal *hal = &rtwdev->hal;
743 u8 *cch_by_bw = hal->cch_by_bw;
744 u32 center_freq, primary_freq;
745 enum rtw_sar_bands sar_band;
746 u8 primary_channel_idx;
747
748 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
749 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
750
751 /* assign the center channel used while 20M bw is selected */
752 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
753
754 /* assign the center channel used while current bw is selected */
755 cch_by_bw[bandwidth] = center_channel;
756
757 switch (bandwidth) {
758 case RTW_CHANNEL_WIDTH_20:
759 default:
760 primary_channel_idx = RTW_SC_DONT_CARE;
761 break;
762 case RTW_CHANNEL_WIDTH_40:
763 if (primary_freq > center_freq)
764 primary_channel_idx = RTW_SC_20_UPPER;
765 else
766 primary_channel_idx = RTW_SC_20_LOWER;
767 break;
768 case RTW_CHANNEL_WIDTH_80:
769 if (primary_freq > center_freq) {
770 if (primary_freq - center_freq == 10)
771 primary_channel_idx = RTW_SC_20_UPPER;
772 else
773 primary_channel_idx = RTW_SC_20_UPMOST;
774
775 /* assign the center channel used
776 * while 40M bw is selected
777 */
778 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
779 } else {
780 if (center_freq - primary_freq == 10)
781 primary_channel_idx = RTW_SC_20_LOWER;
782 else
783 primary_channel_idx = RTW_SC_20_LOWEST;
784
785 /* assign the center channel used
786 * while 40M bw is selected
787 */
788 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
789 }
790 break;
791 }
792
793 switch (center_channel) {
794 case 1 ... 14:
795 sar_band = RTW_SAR_BAND_0;
796 break;
797 case 36 ... 64:
798 sar_band = RTW_SAR_BAND_1;
799 break;
800 case 100 ... 144:
801 sar_band = RTW_SAR_BAND_3;
802 break;
803 case 149 ... 177:
804 sar_band = RTW_SAR_BAND_4;
805 break;
806 default:
807 WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
808 sar_band = RTW_SAR_BAND_0;
809 break;
810 }
811
812 hal->current_primary_channel_index = primary_channel_idx;
813 hal->current_band_width = bandwidth;
814 hal->primary_channel = primary_channel;
815 hal->current_channel = center_channel;
816 hal->current_band_type = band;
817 hal->sar_band = sar_band;
818}
819
820void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
821 struct rtw_channel_params *chan_params)
822{
823 struct ieee80211_channel *channel = chandef->chan;
824 enum nl80211_chan_width width = chandef->width;
825 u32 primary_freq, center_freq;
826 u8 center_chan;
827 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
828
829 center_chan = channel->hw_value;
830 primary_freq = channel->center_freq;
831 center_freq = chandef->center_freq1;
832
833 switch (width) {
834 case NL80211_CHAN_WIDTH_20_NOHT:
835 case NL80211_CHAN_WIDTH_20:
836 bandwidth = RTW_CHANNEL_WIDTH_20;
837 break;
838 case NL80211_CHAN_WIDTH_40:
839 bandwidth = RTW_CHANNEL_WIDTH_40;
840 if (primary_freq > center_freq)
841 center_chan -= 2;
842 else
843 center_chan += 2;
844 break;
845 case NL80211_CHAN_WIDTH_80:
846 bandwidth = RTW_CHANNEL_WIDTH_80;
847 if (primary_freq > center_freq) {
848 if (primary_freq - center_freq == 10)
849 center_chan -= 2;
850 else
851 center_chan -= 6;
852 } else {
853 if (center_freq - primary_freq == 10)
854 center_chan += 2;
855 else
856 center_chan += 6;
857 }
858 break;
859 default:
860 center_chan = 0;
861 break;
862 }
863
864 chan_params->center_chan = center_chan;
865 chan_params->bandwidth = bandwidth;
866 chan_params->primary_chan = channel->hw_value;
867}
868
869void rtw_set_channel(struct rtw_dev *rtwdev)
870{
871 const struct rtw_chip_info *chip = rtwdev->chip;
872 struct ieee80211_hw *hw = rtwdev->hw;
873 struct rtw_hal *hal = &rtwdev->hal;
874 struct rtw_channel_params ch_param;
875 u8 center_chan, primary_chan, bandwidth, band;
876
877 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
878 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
879 return;
880
881 center_chan = ch_param.center_chan;
882 primary_chan = ch_param.primary_chan;
883 bandwidth = ch_param.bandwidth;
884 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
885
886 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
887
888 if (rtwdev->scan_info.op_chan)
889 rtw_store_op_chan(rtwdev, true);
890
891 chip->ops->set_channel(rtwdev, center_chan, bandwidth,
892 hal->current_primary_channel_index);
893
894 if (hal->current_band_type == RTW_BAND_5G) {
895 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
896 } else {
897 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
898 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
899 else
900 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
901 }
902
903 rtw_phy_set_tx_power_level(rtwdev, center_chan);
904
905 /* if the channel isn't set for scanning, we will do RF calibration
906 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
907 * during scanning on each channel takes too long.
908 */
909 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
910 rtwdev->need_rfk = true;
911}
912
913void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
914{
915 const struct rtw_chip_info *chip = rtwdev->chip;
916
917 if (rtwdev->need_rfk) {
918 rtwdev->need_rfk = false;
919 chip->ops->phy_calibration(rtwdev);
920 }
921}
922
923static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
924{
925 int i;
926
927 for (i = 0; i < ETH_ALEN; i++)
928 rtw_write8(rtwdev, start + i, addr[i]);
929}
930
931void rtw_vif_port_config(struct rtw_dev *rtwdev,
932 struct rtw_vif *rtwvif,
933 u32 config)
934{
935 u32 addr, mask;
936
937 if (config & PORT_SET_MAC_ADDR) {
938 addr = rtwvif->conf->mac_addr.addr;
939 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
940 }
941 if (config & PORT_SET_BSSID) {
942 addr = rtwvif->conf->bssid.addr;
943 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
944 }
945 if (config & PORT_SET_NET_TYPE) {
946 addr = rtwvif->conf->net_type.addr;
947 mask = rtwvif->conf->net_type.mask;
948 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
949 }
950 if (config & PORT_SET_AID) {
951 addr = rtwvif->conf->aid.addr;
952 mask = rtwvif->conf->aid.mask;
953 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
954 }
955 if (config & PORT_SET_BCN_CTRL) {
956 addr = rtwvif->conf->bcn_ctrl.addr;
957 mask = rtwvif->conf->bcn_ctrl.mask;
958 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
959 }
960}
961
962static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
963{
964 u8 bw = 0;
965
966 switch (bw_cap) {
967 case EFUSE_HW_CAP_IGNORE:
968 case EFUSE_HW_CAP_SUPP_BW80:
969 bw |= BIT(RTW_CHANNEL_WIDTH_80);
970 fallthrough;
971 case EFUSE_HW_CAP_SUPP_BW40:
972 bw |= BIT(RTW_CHANNEL_WIDTH_40);
973 fallthrough;
974 default:
975 bw |= BIT(RTW_CHANNEL_WIDTH_20);
976 break;
977 }
978
979 return bw;
980}
981
982static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
983{
984 const struct rtw_chip_info *chip = rtwdev->chip;
985 struct rtw_hal *hal = &rtwdev->hal;
986
987 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
988 hw_ant_num >= hal->rf_path_num)
989 return;
990
991 switch (hw_ant_num) {
992 case 1:
993 hal->rf_type = RF_1T1R;
994 hal->rf_path_num = 1;
995 if (!chip->fix_rf_phy_num)
996 hal->rf_phy_num = hal->rf_path_num;
997 hal->antenna_tx = BB_PATH_A;
998 hal->antenna_rx = BB_PATH_A;
999 break;
1000 default:
1001 WARN(1, "invalid hw configuration from efuse\n");
1002 break;
1003 }
1004}
1005
1006static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
1007{
1008 u64 ra_mask = 0;
1009 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
1010 u8 vht_mcs_cap;
1011 int i, nss;
1012
1013 /* 4SS, every two bits for MCS7/8/9 */
1014 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
1015 vht_mcs_cap = mcs_map & 0x3;
1016 switch (vht_mcs_cap) {
1017 case 2: /* MCS9 */
1018 ra_mask |= 0x3ffULL << nss;
1019 break;
1020 case 1: /* MCS8 */
1021 ra_mask |= 0x1ffULL << nss;
1022 break;
1023 case 0: /* MCS7 */
1024 ra_mask |= 0x0ffULL << nss;
1025 break;
1026 default:
1027 break;
1028 }
1029 }
1030
1031 return ra_mask;
1032}
1033
1034static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
1035{
1036 u8 rate_id = 0;
1037
1038 switch (wireless_set) {
1039 case WIRELESS_CCK:
1040 rate_id = RTW_RATEID_B_20M;
1041 break;
1042 case WIRELESS_OFDM:
1043 rate_id = RTW_RATEID_G;
1044 break;
1045 case WIRELESS_CCK | WIRELESS_OFDM:
1046 rate_id = RTW_RATEID_BG;
1047 break;
1048 case WIRELESS_OFDM | WIRELESS_HT:
1049 if (tx_num == 1)
1050 rate_id = RTW_RATEID_GN_N1SS;
1051 else if (tx_num == 2)
1052 rate_id = RTW_RATEID_GN_N2SS;
1053 else if (tx_num == 3)
1054 rate_id = RTW_RATEID_ARFR5_N_3SS;
1055 break;
1056 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
1057 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
1058 if (tx_num == 1)
1059 rate_id = RTW_RATEID_BGN_40M_1SS;
1060 else if (tx_num == 2)
1061 rate_id = RTW_RATEID_BGN_40M_2SS;
1062 else if (tx_num == 3)
1063 rate_id = RTW_RATEID_ARFR5_N_3SS;
1064 else if (tx_num == 4)
1065 rate_id = RTW_RATEID_ARFR7_N_4SS;
1066 } else {
1067 if (tx_num == 1)
1068 rate_id = RTW_RATEID_BGN_20M_1SS;
1069 else if (tx_num == 2)
1070 rate_id = RTW_RATEID_BGN_20M_2SS;
1071 else if (tx_num == 3)
1072 rate_id = RTW_RATEID_ARFR5_N_3SS;
1073 else if (tx_num == 4)
1074 rate_id = RTW_RATEID_ARFR7_N_4SS;
1075 }
1076 break;
1077 case WIRELESS_OFDM | WIRELESS_VHT:
1078 if (tx_num == 1)
1079 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1080 else if (tx_num == 2)
1081 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1082 else if (tx_num == 3)
1083 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1084 else if (tx_num == 4)
1085 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1086 break;
1087 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
1088 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
1089 if (tx_num == 1)
1090 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1091 else if (tx_num == 2)
1092 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1093 else if (tx_num == 3)
1094 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1095 else if (tx_num == 4)
1096 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1097 } else {
1098 if (tx_num == 1)
1099 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
1100 else if (tx_num == 2)
1101 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
1102 else if (tx_num == 3)
1103 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1104 else if (tx_num == 4)
1105 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1106 }
1107 break;
1108 default:
1109 break;
1110 }
1111
1112 return rate_id;
1113}
1114
1115#define RA_MASK_CCK_RATES 0x0000f
1116#define RA_MASK_OFDM_RATES 0x00ff0
1117#define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
1118#define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
1119#define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
1120#define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
1121 RA_MASK_HT_RATES_2SS | \
1122 RA_MASK_HT_RATES_3SS)
1123#define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
1124#define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
1125#define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
1126#define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
1127 RA_MASK_VHT_RATES_2SS | \
1128 RA_MASK_VHT_RATES_3SS)
1129#define RA_MASK_CCK_IN_BG 0x00005
1130#define RA_MASK_CCK_IN_HT 0x00005
1131#define RA_MASK_CCK_IN_VHT 0x00005
1132#define RA_MASK_OFDM_IN_VHT 0x00010
1133#define RA_MASK_OFDM_IN_HT_2G 0x00010
1134#define RA_MASK_OFDM_IN_HT_5G 0x00030
1135
1136static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
1137{
1138 u8 rssi_level = si->rssi_level;
1139
1140 if (wireless_set == WIRELESS_CCK)
1141 return 0xffffffffffffffffULL;
1142
1143 if (rssi_level == 0)
1144 return 0xffffffffffffffffULL;
1145 else if (rssi_level == 1)
1146 return 0xfffffffffffffff0ULL;
1147 else if (rssi_level == 2)
1148 return 0xffffffffffffefe0ULL;
1149 else if (rssi_level == 3)
1150 return 0xffffffffffffcfc0ULL;
1151 else if (rssi_level == 4)
1152 return 0xffffffffffff8f80ULL;
1153 else
1154 return 0xffffffffffff0f00ULL;
1155}
1156
1157static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
1158{
1159 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
1160 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1161
1162 if (ra_mask == 0)
1163 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1164
1165 return ra_mask;
1166}
1167
1168static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1169 u64 ra_mask, bool is_vht_enable)
1170{
1171 struct rtw_hal *hal = &rtwdev->hal;
1172 const struct cfg80211_bitrate_mask *mask = si->mask;
1173 u64 cfg_mask = GENMASK_ULL(63, 0);
1174 u8 band;
1175
1176 if (!si->use_cfg_mask)
1177 return ra_mask;
1178
1179 band = hal->current_band_type;
1180 if (band == RTW_BAND_2G) {
1181 band = NL80211_BAND_2GHZ;
1182 cfg_mask = mask->control[band].legacy;
1183 } else if (band == RTW_BAND_5G) {
1184 band = NL80211_BAND_5GHZ;
1185 cfg_mask = u64_encode_bits(mask->control[band].legacy,
1186 RA_MASK_OFDM_RATES);
1187 }
1188
1189 if (!is_vht_enable) {
1190 if (ra_mask & RA_MASK_HT_RATES_1SS)
1191 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1192 RA_MASK_HT_RATES_1SS);
1193 if (ra_mask & RA_MASK_HT_RATES_2SS)
1194 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1195 RA_MASK_HT_RATES_2SS);
1196 } else {
1197 if (ra_mask & RA_MASK_VHT_RATES_1SS)
1198 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1199 RA_MASK_VHT_RATES_1SS);
1200 if (ra_mask & RA_MASK_VHT_RATES_2SS)
1201 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1202 RA_MASK_VHT_RATES_2SS);
1203 }
1204
1205 ra_mask &= cfg_mask;
1206
1207 return ra_mask;
1208}
1209
1210void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1211 bool reset_ra_mask)
1212{
1213 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1214 struct ieee80211_sta *sta = si->sta;
1215 struct rtw_efuse *efuse = &rtwdev->efuse;
1216 struct rtw_hal *hal = &rtwdev->hal;
1217 u8 wireless_set;
1218 u8 bw_mode;
1219 u8 rate_id;
1220 u8 rf_type = RF_1T1R;
1221 u8 stbc_en = 0;
1222 u8 ldpc_en = 0;
1223 u8 tx_num = 1;
1224 u64 ra_mask = 0;
1225 u64 ra_mask_bak = 0;
1226 bool is_vht_enable = false;
1227 bool is_support_sgi = false;
1228
1229 if (sta->deflink.vht_cap.vht_supported) {
1230 is_vht_enable = true;
1231 ra_mask |= get_vht_ra_mask(sta);
1232 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1233 stbc_en = VHT_STBC_EN;
1234 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1235 ldpc_en = VHT_LDPC_EN;
1236 } else if (sta->deflink.ht_cap.ht_supported) {
1237 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1238 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1239 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1240 stbc_en = HT_STBC_EN;
1241 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1242 ldpc_en = HT_LDPC_EN;
1243 }
1244
1245 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1246 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1247
1248 if (hal->current_band_type == RTW_BAND_5G) {
1249 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1250 ra_mask_bak = ra_mask;
1251 if (sta->deflink.vht_cap.vht_supported) {
1252 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1253 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1254 } else if (sta->deflink.ht_cap.ht_supported) {
1255 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1256 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1257 } else {
1258 wireless_set = WIRELESS_OFDM;
1259 }
1260 dm_info->rrsr_val_init = RRSR_INIT_5G;
1261 } else if (hal->current_band_type == RTW_BAND_2G) {
1262 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1263 ra_mask_bak = ra_mask;
1264 if (sta->deflink.vht_cap.vht_supported) {
1265 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1266 RA_MASK_OFDM_IN_VHT;
1267 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1268 WIRELESS_HT | WIRELESS_VHT;
1269 } else if (sta->deflink.ht_cap.ht_supported) {
1270 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1271 RA_MASK_OFDM_IN_HT_2G;
1272 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1273 WIRELESS_HT;
1274 } else if (sta->deflink.supp_rates[0] <= 0xf) {
1275 wireless_set = WIRELESS_CCK;
1276 } else {
1277 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
1278 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1279 }
1280 dm_info->rrsr_val_init = RRSR_INIT_2G;
1281 } else {
1282 rtw_err(rtwdev, "Unknown band type\n");
1283 ra_mask_bak = ra_mask;
1284 wireless_set = 0;
1285 }
1286
1287 switch (sta->deflink.bandwidth) {
1288 case IEEE80211_STA_RX_BW_80:
1289 bw_mode = RTW_CHANNEL_WIDTH_80;
1290 is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1291 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1292 break;
1293 case IEEE80211_STA_RX_BW_40:
1294 bw_mode = RTW_CHANNEL_WIDTH_40;
1295 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1296 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1297 break;
1298 default:
1299 bw_mode = RTW_CHANNEL_WIDTH_20;
1300 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1301 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1302 break;
1303 }
1304
1305 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
1306 tx_num = 2;
1307 rf_type = RF_2T2R;
1308 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
1309 tx_num = 2;
1310 rf_type = RF_2T2R;
1311 }
1312
1313 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1314
1315 ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
1316 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
1317 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
1318
1319 si->bw_mode = bw_mode;
1320 si->stbc_en = stbc_en;
1321 si->ldpc_en = ldpc_en;
1322 si->rf_type = rf_type;
1323 si->sgi_enable = is_support_sgi;
1324 si->vht_enable = is_vht_enable;
1325 si->ra_mask = ra_mask;
1326 si->rate_id = rate_id;
1327
1328 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
1329}
1330
1331int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1332{
1333 const struct rtw_chip_info *chip = rtwdev->chip;
1334 struct rtw_fw_state *fw;
1335 int ret = 0;
1336
1337 fw = &rtwdev->fw;
1338 wait_for_completion(&fw->completion);
1339 if (!fw->firmware)
1340 ret = -EINVAL;
1341
1342 if (chip->wow_fw_name) {
1343 fw = &rtwdev->wow_fw;
1344 wait_for_completion(&fw->completion);
1345 if (!fw->firmware)
1346 ret = -EINVAL;
1347 }
1348
1349 return ret;
1350}
1351EXPORT_SYMBOL(rtw_wait_firmware_completion);
1352
1353static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1354 struct rtw_fw_state *fw)
1355{
1356 const struct rtw_chip_info *chip = rtwdev->chip;
1357
1358 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1359 !fw->feature)
1360 return LPS_DEEP_MODE_NONE;
1361
1362 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1363 rtw_fw_feature_check(fw, FW_FEATURE_PG))
1364 return LPS_DEEP_MODE_PG;
1365
1366 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1367 rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1368 return LPS_DEEP_MODE_LCLK;
1369
1370 return LPS_DEEP_MODE_NONE;
1371}
1372
1373int rtw_power_on(struct rtw_dev *rtwdev)
1374{
1375 const struct rtw_chip_info *chip = rtwdev->chip;
1376 struct rtw_fw_state *fw = &rtwdev->fw;
1377 bool wifi_only;
1378 int ret;
1379
1380 ret = rtw_hci_setup(rtwdev);
1381 if (ret) {
1382 rtw_err(rtwdev, "failed to setup hci\n");
1383 goto err;
1384 }
1385
1386 /* power on MAC before firmware downloaded */
1387 ret = rtw_mac_power_on(rtwdev);
1388 if (ret) {
1389 rtw_err(rtwdev, "failed to power on mac\n");
1390 goto err;
1391 }
1392
1393 ret = rtw_wait_firmware_completion(rtwdev);
1394 if (ret) {
1395 rtw_err(rtwdev, "failed to wait firmware completion\n");
1396 goto err_off;
1397 }
1398
1399 ret = rtw_download_firmware(rtwdev, fw);
1400 if (ret) {
1401 rtw_err(rtwdev, "failed to download firmware\n");
1402 goto err_off;
1403 }
1404
1405 /* config mac after firmware downloaded */
1406 ret = rtw_mac_init(rtwdev);
1407 if (ret) {
1408 rtw_err(rtwdev, "failed to configure mac\n");
1409 goto err_off;
1410 }
1411
1412 chip->ops->phy_set_param(rtwdev);
1413
1414 ret = rtw_hci_start(rtwdev);
1415 if (ret) {
1416 rtw_err(rtwdev, "failed to start hci\n");
1417 goto err_off;
1418 }
1419
1420 /* send H2C after HCI has started */
1421 rtw_fw_send_general_info(rtwdev);
1422 rtw_fw_send_phydm_info(rtwdev);
1423
1424 wifi_only = !rtwdev->efuse.btcoex;
1425 rtw_coex_power_on_setting(rtwdev);
1426 rtw_coex_init_hw_config(rtwdev, wifi_only);
1427
1428 return 0;
1429
1430err_off:
1431 rtw_mac_power_off(rtwdev);
1432
1433err:
1434 return ret;
1435}
1436EXPORT_SYMBOL(rtw_power_on);
1437
1438void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1439{
1440 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1441 return;
1442
1443 if (start) {
1444 rtw_fw_scan_notify(rtwdev, true);
1445 } else {
1446 reinit_completion(&rtwdev->fw_scan_density);
1447 rtw_fw_scan_notify(rtwdev, false);
1448 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1449 SCAN_NOTIFY_TIMEOUT))
1450 rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1451 }
1452}
1453
1454void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1455 const u8 *mac_addr, bool hw_scan)
1456{
1457 u32 config = 0;
1458 int ret = 0;
1459
1460 rtw_leave_lps(rtwdev);
1461
1462 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1463 ret = rtw_leave_ips(rtwdev);
1464 if (ret) {
1465 rtw_err(rtwdev, "failed to leave idle state\n");
1466 return;
1467 }
1468 }
1469
1470 ether_addr_copy(rtwvif->mac_addr, mac_addr);
1471 config |= PORT_SET_MAC_ADDR;
1472 rtw_vif_port_config(rtwdev, rtwvif, config);
1473
1474 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
1475 rtw_core_fw_scan_notify(rtwdev, true);
1476
1477 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1478 set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1479}
1480
1481void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
1482 bool hw_scan)
1483{
1484 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1485 u32 config = 0;
1486
1487 if (!rtwvif)
1488 return;
1489
1490 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1491 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1492
1493 rtw_core_fw_scan_notify(rtwdev, false);
1494
1495 ether_addr_copy(rtwvif->mac_addr, vif->addr);
1496 config |= PORT_SET_MAC_ADDR;
1497 rtw_vif_port_config(rtwdev, rtwvif, config);
1498
1499 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
1500
1501 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1502 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1503}
1504
1505int rtw_core_start(struct rtw_dev *rtwdev)
1506{
1507 int ret;
1508
1509 ret = rtwdev->chip->ops->power_on(rtwdev);
1510 if (ret)
1511 return ret;
1512
1513 rtw_sec_enable_sec_engine(rtwdev);
1514
1515 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1516 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1517
1518 /* rcr reset after powered on */
1519 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1520
1521 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1522 RTW_WATCH_DOG_DELAY_TIME);
1523
1524 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1525
1526 return 0;
1527}
1528
1529void rtw_power_off(struct rtw_dev *rtwdev)
1530{
1531 rtw_hci_stop(rtwdev);
1532 rtw_coex_power_off_setting(rtwdev);
1533 rtw_mac_power_off(rtwdev);
1534}
1535EXPORT_SYMBOL(rtw_power_off);
1536
1537void rtw_core_stop(struct rtw_dev *rtwdev)
1538{
1539 struct rtw_coex *coex = &rtwdev->coex;
1540
1541 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1542 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1543
1544 mutex_unlock(&rtwdev->mutex);
1545
1546 cancel_work_sync(&rtwdev->c2h_work);
1547 cancel_work_sync(&rtwdev->update_beacon_work);
1548 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1549 cancel_delayed_work_sync(&coex->bt_relink_work);
1550 cancel_delayed_work_sync(&coex->bt_reenable_work);
1551 cancel_delayed_work_sync(&coex->defreeze_work);
1552 cancel_delayed_work_sync(&coex->wl_remain_work);
1553 cancel_delayed_work_sync(&coex->bt_remain_work);
1554 cancel_delayed_work_sync(&coex->wl_connecting_work);
1555 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1556 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1557
1558 mutex_lock(&rtwdev->mutex);
1559
1560 rtwdev->chip->ops->power_off(rtwdev);
1561}
1562
1563static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1564 struct ieee80211_sta_ht_cap *ht_cap)
1565{
1566 const struct rtw_chip_info *chip = rtwdev->chip;
1567 struct rtw_efuse *efuse = &rtwdev->efuse;
1568
1569 ht_cap->ht_supported = true;
1570 ht_cap->cap = 0;
1571 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1572 IEEE80211_HT_CAP_MAX_AMSDU |
1573 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1574
1575 if (rtw_chip_has_rx_ldpc(rtwdev))
1576 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1577 if (rtw_chip_has_tx_stbc(rtwdev))
1578 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1579
1580 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1581 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1582 IEEE80211_HT_CAP_DSSSCCK40 |
1583 IEEE80211_HT_CAP_SGI_40;
1584 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1585 ht_cap->ampdu_density = chip->ampdu_density;
1586 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1587 if (efuse->hw_cap.nss > 1) {
1588 ht_cap->mcs.rx_mask[0] = 0xFF;
1589 ht_cap->mcs.rx_mask[1] = 0xFF;
1590 ht_cap->mcs.rx_mask[4] = 0x01;
1591 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1592 } else {
1593 ht_cap->mcs.rx_mask[0] = 0xFF;
1594 ht_cap->mcs.rx_mask[1] = 0x00;
1595 ht_cap->mcs.rx_mask[4] = 0x01;
1596 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1597 }
1598}
1599
1600static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1601 struct ieee80211_sta_vht_cap *vht_cap)
1602{
1603 struct rtw_efuse *efuse = &rtwdev->efuse;
1604 u16 mcs_map;
1605 __le16 highest;
1606
1607 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1608 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1609 return;
1610
1611 vht_cap->vht_supported = true;
1612 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1613 IEEE80211_VHT_CAP_SHORT_GI_80 |
1614 IEEE80211_VHT_CAP_RXSTBC_1 |
1615 IEEE80211_VHT_CAP_HTC_VHT |
1616 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1617 0;
1618 if (rtwdev->hal.rf_path_num > 1)
1619 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1620 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1621 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1622 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1623 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1624
1625 if (rtw_chip_has_rx_ldpc(rtwdev))
1626 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1627
1628 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1629 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1630 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1631 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1632 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1633 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1634 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1635 if (efuse->hw_cap.nss > 1) {
1636 highest = cpu_to_le16(780);
1637 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1638 } else {
1639 highest = cpu_to_le16(390);
1640 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1641 }
1642
1643 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1644 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1645 vht_cap->vht_mcs.rx_highest = highest;
1646 vht_cap->vht_mcs.tx_highest = highest;
1647}
1648
1649static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
1650{
1651 u16 len;
1652
1653 len = rtwdev->chip->max_scan_ie_len;
1654
1655 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
1656 rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
1657 len = IEEE80211_MAX_DATA_LEN;
1658 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
1659 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
1660
1661 return len;
1662}
1663
1664static void rtw_set_supported_band(struct ieee80211_hw *hw,
1665 const struct rtw_chip_info *chip)
1666{
1667 struct rtw_dev *rtwdev = hw->priv;
1668 struct ieee80211_supported_band *sband;
1669
1670 if (chip->band & RTW_BAND_2G) {
1671 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1672 if (!sband)
1673 goto err_out;
1674 if (chip->ht_supported)
1675 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1676 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1677 }
1678
1679 if (chip->band & RTW_BAND_5G) {
1680 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1681 if (!sband)
1682 goto err_out;
1683 if (chip->ht_supported)
1684 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1685 if (chip->vht_supported)
1686 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1687 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1688 }
1689
1690 return;
1691
1692err_out:
1693 rtw_err(rtwdev, "failed to set supported band\n");
1694}
1695
1696static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1697 const struct rtw_chip_info *chip)
1698{
1699 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1700 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1701}
1702
1703static void rtw_vif_smps_iter(void *data, u8 *mac,
1704 struct ieee80211_vif *vif)
1705{
1706 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
1707
1708 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1709 return;
1710
1711 if (rtwdev->hal.txrx_1ss)
1712 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
1713 else
1714 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
1715}
1716
1717void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
1718{
1719 const struct rtw_chip_info *chip = rtwdev->chip;
1720 struct rtw_hal *hal = &rtwdev->hal;
1721
1722 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1723 return;
1724
1725 rtwdev->hal.txrx_1ss = txrx_1ss;
1726 if (txrx_1ss)
1727 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1728 else
1729 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1730 hal->antenna_rx, false);
1731 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
1732}
1733
1734static void __update_firmware_feature(struct rtw_dev *rtwdev,
1735 struct rtw_fw_state *fw)
1736{
1737 u32 feature;
1738 const struct rtw_fw_hdr *fw_hdr =
1739 (const struct rtw_fw_hdr *)fw->firmware->data;
1740
1741 feature = le32_to_cpu(fw_hdr->feature);
1742 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1743
1744 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
1745 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
1746 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
1747}
1748
1749static void __update_firmware_info(struct rtw_dev *rtwdev,
1750 struct rtw_fw_state *fw)
1751{
1752 const struct rtw_fw_hdr *fw_hdr =
1753 (const struct rtw_fw_hdr *)fw->firmware->data;
1754
1755 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1756 fw->version = le16_to_cpu(fw_hdr->version);
1757 fw->sub_version = fw_hdr->subversion;
1758 fw->sub_index = fw_hdr->subindex;
1759
1760 __update_firmware_feature(rtwdev, fw);
1761}
1762
1763static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1764 struct rtw_fw_state *fw)
1765{
1766 struct rtw_fw_hdr_legacy *legacy =
1767 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1768
1769 fw->h2c_version = 0;
1770 fw->version = le16_to_cpu(legacy->version);
1771 fw->sub_version = legacy->subversion1;
1772 fw->sub_index = legacy->subversion2;
1773}
1774
1775static void update_firmware_info(struct rtw_dev *rtwdev,
1776 struct rtw_fw_state *fw)
1777{
1778 if (rtw_chip_wcpu_11n(rtwdev))
1779 __update_firmware_info_legacy(rtwdev, fw);
1780 else
1781 __update_firmware_info(rtwdev, fw);
1782}
1783
1784static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1785{
1786 struct rtw_fw_state *fw = context;
1787 struct rtw_dev *rtwdev = fw->rtwdev;
1788
1789 if (!firmware || !firmware->data) {
1790 rtw_err(rtwdev, "failed to request firmware\n");
1791 complete_all(&fw->completion);
1792 return;
1793 }
1794
1795 fw->firmware = firmware;
1796 update_firmware_info(rtwdev, fw);
1797 complete_all(&fw->completion);
1798
1799 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
1800 fw->type == RTW_WOWLAN_FW ? "WOW " : "",
1801 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1802}
1803
1804static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1805{
1806 const char *fw_name;
1807 struct rtw_fw_state *fw;
1808 int ret;
1809
1810 switch (type) {
1811 case RTW_WOWLAN_FW:
1812 fw = &rtwdev->wow_fw;
1813 fw_name = rtwdev->chip->wow_fw_name;
1814 break;
1815
1816 case RTW_NORMAL_FW:
1817 fw = &rtwdev->fw;
1818 fw_name = rtwdev->chip->fw_name;
1819 break;
1820
1821 default:
1822 rtw_warn(rtwdev, "unsupported firmware type\n");
1823 return -ENOENT;
1824 }
1825
1826 fw->type = type;
1827 fw->rtwdev = rtwdev;
1828 init_completion(&fw->completion);
1829
1830 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1831 GFP_KERNEL, fw, rtw_load_firmware_cb);
1832 if (ret) {
1833 rtw_err(rtwdev, "failed to async firmware request\n");
1834 return ret;
1835 }
1836
1837 return 0;
1838}
1839
1840static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1841{
1842 const struct rtw_chip_info *chip = rtwdev->chip;
1843 struct rtw_hal *hal = &rtwdev->hal;
1844 struct rtw_efuse *efuse = &rtwdev->efuse;
1845
1846 switch (rtw_hci_type(rtwdev)) {
1847 case RTW_HCI_TYPE_PCIE:
1848 rtwdev->hci.rpwm_addr = 0x03d9;
1849 rtwdev->hci.cpwm_addr = 0x03da;
1850 break;
1851 case RTW_HCI_TYPE_SDIO:
1852 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1;
1853 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2;
1854 break;
1855 case RTW_HCI_TYPE_USB:
1856 rtwdev->hci.rpwm_addr = 0xfe58;
1857 rtwdev->hci.cpwm_addr = 0xfe57;
1858 break;
1859 default:
1860 rtw_err(rtwdev, "unsupported hci type\n");
1861 return -EINVAL;
1862 }
1863
1864 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1865 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1866 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1867 if (hal->chip_version & BIT_RF_TYPE_ID) {
1868 hal->rf_type = RF_2T2R;
1869 hal->rf_path_num = 2;
1870 hal->antenna_tx = BB_PATH_AB;
1871 hal->antenna_rx = BB_PATH_AB;
1872 } else {
1873 hal->rf_type = RF_1T1R;
1874 hal->rf_path_num = 1;
1875 hal->antenna_tx = BB_PATH_A;
1876 hal->antenna_rx = BB_PATH_A;
1877 }
1878 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1879 hal->rf_path_num;
1880
1881 efuse->physical_size = chip->phy_efuse_size;
1882 efuse->logical_size = chip->log_efuse_size;
1883 efuse->protect_size = chip->ptct_efuse_size;
1884
1885 /* default use ack */
1886 rtwdev->hal.rcr |= BIT_VHT_DACK;
1887
1888 hal->bfee_sts_cap = 3;
1889
1890 return 0;
1891}
1892
1893static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1894{
1895 struct rtw_fw_state *fw = &rtwdev->fw;
1896 int ret;
1897
1898 ret = rtw_hci_setup(rtwdev);
1899 if (ret) {
1900 rtw_err(rtwdev, "failed to setup hci\n");
1901 goto err;
1902 }
1903
1904 ret = rtw_mac_power_on(rtwdev);
1905 if (ret) {
1906 rtw_err(rtwdev, "failed to power on mac\n");
1907 goto err;
1908 }
1909
1910 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1911
1912 wait_for_completion(&fw->completion);
1913 if (!fw->firmware) {
1914 ret = -EINVAL;
1915 rtw_err(rtwdev, "failed to load firmware\n");
1916 goto err;
1917 }
1918
1919 ret = rtw_download_firmware(rtwdev, fw);
1920 if (ret) {
1921 rtw_err(rtwdev, "failed to download firmware\n");
1922 goto err_off;
1923 }
1924
1925 return 0;
1926
1927err_off:
1928 rtw_mac_power_off(rtwdev);
1929
1930err:
1931 return ret;
1932}
1933
1934static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1935{
1936 struct rtw_efuse *efuse = &rtwdev->efuse;
1937 u8 hw_feature[HW_FEATURE_LEN];
1938 u8 id;
1939 u8 bw;
1940 int i;
1941
1942 if (!rtwdev->chip->hw_feature_report)
1943 return 0;
1944
1945 id = rtw_read8(rtwdev, REG_C2HEVT);
1946 if (id != C2H_HW_FEATURE_REPORT) {
1947 rtw_err(rtwdev, "failed to read hw feature report\n");
1948 return -EBUSY;
1949 }
1950
1951 for (i = 0; i < HW_FEATURE_LEN; i++)
1952 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1953
1954 rtw_write8(rtwdev, REG_C2HEVT, 0);
1955
1956 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1957 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1958 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1959 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1960 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1961 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1962
1963 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1964
1965 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1966 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1967 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1968
1969 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1970 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1971 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1972 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1973
1974 return 0;
1975}
1976
1977static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1978{
1979 rtw_hci_stop(rtwdev);
1980 rtw_mac_power_off(rtwdev);
1981}
1982
1983static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1984{
1985 struct rtw_efuse *efuse = &rtwdev->efuse;
1986 int ret;
1987
1988 mutex_lock(&rtwdev->mutex);
1989
1990 /* power on mac to read efuse */
1991 ret = rtw_chip_efuse_enable(rtwdev);
1992 if (ret)
1993 goto out_unlock;
1994
1995 ret = rtw_parse_efuse_map(rtwdev);
1996 if (ret)
1997 goto out_disable;
1998
1999 ret = rtw_dump_hw_feature(rtwdev);
2000 if (ret)
2001 goto out_disable;
2002
2003 ret = rtw_check_supported_rfe(rtwdev);
2004 if (ret)
2005 goto out_disable;
2006
2007 if (efuse->crystal_cap == 0xff)
2008 efuse->crystal_cap = 0;
2009 if (efuse->pa_type_2g == 0xff)
2010 efuse->pa_type_2g = 0;
2011 if (efuse->pa_type_5g == 0xff)
2012 efuse->pa_type_5g = 0;
2013 if (efuse->lna_type_2g == 0xff)
2014 efuse->lna_type_2g = 0;
2015 if (efuse->lna_type_5g == 0xff)
2016 efuse->lna_type_5g = 0;
2017 if (efuse->channel_plan == 0xff)
2018 efuse->channel_plan = 0x7f;
2019 if (efuse->rf_board_option == 0xff)
2020 efuse->rf_board_option = 0;
2021 if (efuse->bt_setting & BIT(0))
2022 efuse->share_ant = true;
2023 if (efuse->regd == 0xff)
2024 efuse->regd = 0;
2025 if (efuse->tx_bb_swing_setting_2g == 0xff)
2026 efuse->tx_bb_swing_setting_2g = 0;
2027 if (efuse->tx_bb_swing_setting_5g == 0xff)
2028 efuse->tx_bb_swing_setting_5g = 0;
2029
2030 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
2031 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
2032 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
2033 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
2034 efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
2035
2036 if (!is_valid_ether_addr(efuse->addr)) {
2037 eth_random_addr(efuse->addr);
2038 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n");
2039 }
2040
2041out_disable:
2042 rtw_chip_efuse_disable(rtwdev);
2043
2044out_unlock:
2045 mutex_unlock(&rtwdev->mutex);
2046 return ret;
2047}
2048
2049static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
2050{
2051 struct rtw_hal *hal = &rtwdev->hal;
2052 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
2053
2054 if (!rfe_def)
2055 return -ENODEV;
2056
2057 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type);
2058
2059 rtw_phy_init_tx_power(rtwdev);
2060 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
2061 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
2062 rtw_phy_tx_power_by_rate_config(hal);
2063 rtw_phy_tx_power_limit_config(hal);
2064
2065 return 0;
2066}
2067
2068int rtw_chip_info_setup(struct rtw_dev *rtwdev)
2069{
2070 int ret;
2071
2072 ret = rtw_chip_parameter_setup(rtwdev);
2073 if (ret) {
2074 rtw_err(rtwdev, "failed to setup chip parameters\n");
2075 goto err_out;
2076 }
2077
2078 ret = rtw_chip_efuse_info_setup(rtwdev);
2079 if (ret) {
2080 rtw_err(rtwdev, "failed to setup chip efuse info\n");
2081 goto err_out;
2082 }
2083
2084 ret = rtw_chip_board_info_setup(rtwdev);
2085 if (ret) {
2086 rtw_err(rtwdev, "failed to setup chip board info\n");
2087 goto err_out;
2088 }
2089
2090 return 0;
2091
2092err_out:
2093 return ret;
2094}
2095EXPORT_SYMBOL(rtw_chip_info_setup);
2096
2097static void rtw_stats_init(struct rtw_dev *rtwdev)
2098{
2099 struct rtw_traffic_stats *stats = &rtwdev->stats;
2100 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2101 int i;
2102
2103 ewma_tp_init(&stats->tx_ewma_tp);
2104 ewma_tp_init(&stats->rx_ewma_tp);
2105
2106 for (i = 0; i < RTW_EVM_NUM; i++)
2107 ewma_evm_init(&dm_info->ewma_evm[i]);
2108 for (i = 0; i < RTW_SNR_NUM; i++)
2109 ewma_snr_init(&dm_info->ewma_snr[i]);
2110}
2111
2112int rtw_core_init(struct rtw_dev *rtwdev)
2113{
2114 const struct rtw_chip_info *chip = rtwdev->chip;
2115 struct rtw_coex *coex = &rtwdev->coex;
2116 int ret;
2117
2118 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
2119 INIT_LIST_HEAD(&rtwdev->txqs);
2120
2121 timer_setup(&rtwdev->tx_report.purge_timer,
2122 rtw_tx_report_purge_timer, 0);
2123 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
2124 if (!rtwdev->tx_wq) {
2125 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
2126 return -ENOMEM;
2127 }
2128
2129 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2130 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2131 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2132 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2133 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2134 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2135 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2136 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2137 rtw_coex_bt_multi_link_remain_work);
2138 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2139 INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2140 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2141 INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2142 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2143 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2144 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2145 skb_queue_head_init(&rtwdev->c2h_queue);
2146 skb_queue_head_init(&rtwdev->coex.queue);
2147 skb_queue_head_init(&rtwdev->tx_report.queue);
2148
2149 spin_lock_init(&rtwdev->txq_lock);
2150 spin_lock_init(&rtwdev->tx_report.q_lock);
2151
2152 mutex_init(&rtwdev->mutex);
2153 mutex_init(&rtwdev->hal.tx_power_mutex);
2154
2155 init_waitqueue_head(&rtwdev->coex.wait);
2156 init_completion(&rtwdev->lps_leave_check);
2157 init_completion(&rtwdev->fw_scan_density);
2158
2159 rtwdev->sec.total_cam_num = 32;
2160 rtwdev->hal.current_channel = 1;
2161 rtwdev->dm_info.fix_rate = U8_MAX;
2162
2163 rtw_stats_init(rtwdev);
2164
2165 /* default rx filter setting */
2166 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2167 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
2168 BIT_AB | BIT_AM | BIT_APM;
2169
2170 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
2171 if (ret) {
2172 rtw_warn(rtwdev, "no firmware loaded\n");
2173 goto out;
2174 }
2175
2176 if (chip->wow_fw_name) {
2177 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
2178 if (ret) {
2179 rtw_warn(rtwdev, "no wow firmware loaded\n");
2180 wait_for_completion(&rtwdev->fw.completion);
2181 if (rtwdev->fw.firmware)
2182 release_firmware(rtwdev->fw.firmware);
2183 goto out;
2184 }
2185 }
2186
2187 return 0;
2188
2189out:
2190 destroy_workqueue(rtwdev->tx_wq);
2191 return ret;
2192}
2193EXPORT_SYMBOL(rtw_core_init);
2194
2195void rtw_core_deinit(struct rtw_dev *rtwdev)
2196{
2197 struct rtw_fw_state *fw = &rtwdev->fw;
2198 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2199 struct rtw_rsvd_page *rsvd_pkt, *tmp;
2200 unsigned long flags;
2201
2202 rtw_wait_firmware_completion(rtwdev);
2203
2204 if (fw->firmware)
2205 release_firmware(fw->firmware);
2206
2207 if (wow_fw->firmware)
2208 release_firmware(wow_fw->firmware);
2209
2210 destroy_workqueue(rtwdev->tx_wq);
2211 timer_delete_sync(&rtwdev->tx_report.purge_timer);
2212 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2213 skb_queue_purge(&rtwdev->tx_report.queue);
2214 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2215 skb_queue_purge(&rtwdev->coex.queue);
2216 skb_queue_purge(&rtwdev->c2h_queue);
2217
2218 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2219 build_list) {
2220 list_del(&rsvd_pkt->build_list);
2221 kfree(rsvd_pkt);
2222 }
2223
2224 mutex_destroy(&rtwdev->mutex);
2225 mutex_destroy(&rtwdev->hal.tx_power_mutex);
2226}
2227EXPORT_SYMBOL(rtw_core_deinit);
2228
2229int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2230{
2231 bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO;
2232 struct rtw_hal *hal = &rtwdev->hal;
2233 int max_tx_headroom = 0;
2234 int ret;
2235
2236 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2237
2238 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
2239 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN;
2240
2241 hw->extra_tx_headroom = max_tx_headroom;
2242 hw->queues = IEEE80211_NUM_ACS;
2243 hw->txq_data_size = sizeof(struct rtw_txq);
2244 hw->sta_data_size = sizeof(struct rtw_sta_info);
2245 hw->vif_data_size = sizeof(struct rtw_vif);
2246
2247 ieee80211_hw_set(hw, SIGNAL_DBM);
2248 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2249 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2250 ieee80211_hw_set(hw, MFP_CAPABLE);
2251 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2252 ieee80211_hw_set(hw, SUPPORTS_PS);
2253 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
2254 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
2255 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
2256 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
2257 ieee80211_hw_set(hw, TX_AMSDU);
2258 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
2259
2260 if (sta_mode_only)
2261 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2262 else
2263 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2264 BIT(NL80211_IFTYPE_AP) |
2265 BIT(NL80211_IFTYPE_ADHOC);
2266 hw->wiphy->available_antennas_tx = hal->antenna_tx;
2267 hw->wiphy->available_antennas_rx = hal->antenna_rx;
2268
2269 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2270 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
2271
2272 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2273 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2274 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
2275
2276 if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
2277 hw->wiphy->iface_combinations = rtw_iface_combs;
2278 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
2279 }
2280
2281 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2282 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2283 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2284
2285#ifdef CONFIG_PM
2286 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2287 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2288#endif
2289 rtw_set_supported_band(hw, rtwdev->chip);
2290 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2291
2292 hw->wiphy->sar_capa = &rtw_sar_capa;
2293
2294 ret = rtw_regd_init(rtwdev);
2295 if (ret) {
2296 rtw_err(rtwdev, "failed to init regd\n");
2297 return ret;
2298 }
2299
2300 ret = ieee80211_register_hw(hw);
2301 if (ret) {
2302 rtw_err(rtwdev, "failed to register hw\n");
2303 return ret;
2304 }
2305
2306 ret = rtw_regd_hint(rtwdev);
2307 if (ret) {
2308 rtw_err(rtwdev, "failed to hint regd\n");
2309 return ret;
2310 }
2311
2312 rtw_debugfs_init(rtwdev);
2313
2314 rtwdev->bf_info.bfer_mu_cnt = 0;
2315 rtwdev->bf_info.bfer_su_cnt = 0;
2316
2317 return 0;
2318}
2319EXPORT_SYMBOL(rtw_register_hw);
2320
2321void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2322{
2323 const struct rtw_chip_info *chip = rtwdev->chip;
2324
2325 ieee80211_unregister_hw(hw);
2326 rtw_unset_supported_band(hw, chip);
2327 rtw_debugfs_deinit(rtwdev);
2328}
2329EXPORT_SYMBOL(rtw_unregister_hw);
2330
2331static
2332void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2333 const struct rtw_hw_reg *reg2, u8 nbytes)
2334{
2335 u8 i;
2336
2337 for (i = 0; i < nbytes; i++) {
2338 u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
2339 u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
2340
2341 rtw_write8(rtwdev, reg1->addr + i, v2);
2342 rtw_write8(rtwdev, reg2->addr + i, v1);
2343 }
2344}
2345
2346static
2347void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2348 const struct rtw_hw_reg *reg2)
2349{
2350 u32 v1, v2;
2351
2352 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
2353 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
2354 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
2355 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
2356}
2357
2358struct rtw_iter_port_switch_data {
2359 struct rtw_dev *rtwdev;
2360 struct rtw_vif *rtwvif_ap;
2361};
2362
2363static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif)
2364{
2365 struct rtw_iter_port_switch_data *iter_data = data;
2366 struct rtw_dev *rtwdev = iter_data->rtwdev;
2367 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv;
2368 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap;
2369 const struct rtw_hw_reg *reg1, *reg2;
2370
2371 if (rtwvif_target->port != RTW_PORT_0)
2372 return;
2373
2374 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
2375 rtwvif_ap->port, rtwvif_target->port);
2376
2377 /* Leave LPS so the value swapped are not in PS mode */
2378 rtw_leave_lps(rtwdev);
2379
2380 reg1 = &rtwvif_ap->conf->net_type;
2381 reg2 = &rtwvif_target->conf->net_type;
2382 rtw_swap_reg_mask(rtwdev, reg1, reg2);
2383
2384 reg1 = &rtwvif_ap->conf->mac_addr;
2385 reg2 = &rtwvif_target->conf->mac_addr;
2386 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2387
2388 reg1 = &rtwvif_ap->conf->bssid;
2389 reg2 = &rtwvif_target->conf->bssid;
2390 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2391
2392 reg1 = &rtwvif_ap->conf->bcn_ctrl;
2393 reg2 = &rtwvif_target->conf->bcn_ctrl;
2394 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1);
2395
2396 swap(rtwvif_target->port, rtwvif_ap->port);
2397 swap(rtwvif_target->conf, rtwvif_ap->conf);
2398
2399 rtw_fw_default_port(rtwdev, rtwvif_target);
2400}
2401
2402void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif)
2403{
2404 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2405 struct rtw_iter_port_switch_data iter_data;
2406
2407 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0)
2408 return;
2409
2410 iter_data.rtwdev = rtwdev;
2411 iter_data.rtwvif_ap = rtwvif;
2412 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data);
2413}
2414
2415static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif)
2416{
2417 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2418 bool *active = data;
2419
2420 if (*active)
2421 return;
2422
2423 if (vif->type != NL80211_IFTYPE_STATION)
2424 return;
2425
2426 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid))
2427 *active = true;
2428}
2429
2430bool rtw_core_check_sta_active(struct rtw_dev *rtwdev)
2431{
2432 bool sta_active = false;
2433
2434 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active);
2435
2436 return rtwdev->ap_active || sta_active;
2437}
2438
2439void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable)
2440{
2441 if (!rtwdev->ap_active)
2442 return;
2443
2444 if (enable) {
2445 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2446 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2447 } else {
2448 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2449 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2450 }
2451}
2452
2453MODULE_AUTHOR("Realtek Corporation");
2454MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
2455MODULE_LICENSE("Dual BSD/GPL");