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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH12K_DP_H
8#define ATH12K_DP_H
9
10#include "hal_rx.h"
11#include "hw.h"
12
13#define MAX_RXDMA_PER_PDEV 2
14
15struct ath12k_base;
16struct ath12k_peer;
17struct ath12k_dp;
18struct ath12k_vif;
19struct ath12k_link_vif;
20struct hal_tcl_status_ring;
21struct ath12k_ext_irq_grp;
22
23#define DP_MON_PURGE_TIMEOUT_MS 100
24#define DP_MON_SERVICE_BUDGET 128
25
26struct dp_srng {
27 u32 *vaddr_unaligned;
28 u32 *vaddr;
29 dma_addr_t paddr_unaligned;
30 dma_addr_t paddr;
31 int size;
32 u32 ring_id;
33};
34
35struct dp_rxdma_mon_ring {
36 struct dp_srng refill_buf_ring;
37 struct idr bufs_idr;
38 /* Protects bufs_idr */
39 spinlock_t idr_lock;
40 int bufs_max;
41};
42
43struct dp_rxdma_ring {
44 struct dp_srng refill_buf_ring;
45 int bufs_max;
46};
47
48#define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
49
50struct dp_tx_ring {
51 u8 tcl_data_ring_id;
52 struct dp_srng tcl_data_ring;
53 struct dp_srng tcl_comp_ring;
54 struct hal_wbm_completion_ring_tx *tx_status;
55 int tx_status_head;
56 int tx_status_tail;
57};
58
59struct ath12k_pdev_mon_stats {
60 u32 status_ppdu_state;
61 u32 status_ppdu_start;
62 u32 status_ppdu_end;
63 u32 status_ppdu_compl;
64 u32 status_ppdu_start_mis;
65 u32 status_ppdu_end_mis;
66 u32 status_ppdu_done;
67 u32 dest_ppdu_done;
68 u32 dest_mpdu_done;
69 u32 dest_mpdu_drop;
70 u32 dup_mon_linkdesc_cnt;
71 u32 dup_mon_buf_cnt;
72};
73
74struct dp_link_desc_bank {
75 void *vaddr_unaligned;
76 void *vaddr;
77 dma_addr_t paddr_unaligned;
78 dma_addr_t paddr;
79 u32 size;
80};
81
82/* Size to enforce scatter idle list mode */
83#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
84#define DP_LINK_DESC_BANKS_MAX 8
85
86#define DP_LINK_DESC_START 0x4000
87#define DP_LINK_DESC_SHIFT 3
88
89#define DP_LINK_DESC_COOKIE_SET(id, page) \
90 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
91
92#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
93
94#define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
95#define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
96#define DP_RX_DESC_COOKIE_MAX \
97 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
98#define DP_NOT_PPDU_ID_WRAP_AROUND 20000
99
100enum ath12k_dp_ppdu_state {
101 DP_PPDU_STATUS_START,
102 DP_PPDU_STATUS_DONE,
103};
104
105struct dp_mon_mpdu {
106 struct list_head list;
107 struct sk_buff *head;
108 struct sk_buff *tail;
109};
110
111#define DP_MON_MAX_STATUS_BUF 32
112
113struct ath12k_mon_data {
114 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
115 struct hal_rx_mon_ppdu_info mon_ppdu_info;
116
117 u32 mon_ppdu_status;
118 u32 mon_last_buf_cookie;
119 u64 mon_last_linkdesc_paddr;
120 u16 chan_noise_floor;
121
122 struct ath12k_pdev_mon_stats rx_mon_stats;
123 /* lock for monitor data */
124 spinlock_t mon_lock;
125 struct sk_buff_head rx_status_q;
126 struct dp_mon_mpdu *mon_mpdu;
127 struct list_head dp_rx_mon_mpdu_list;
128 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF];
129 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;
130 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;
131};
132
133struct ath12k_pdev_dp {
134 u32 mac_id;
135 atomic_t num_tx_pending;
136 wait_queue_head_t tx_empty_waitq;
137 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
138 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
139
140 struct ieee80211_rx_status rx_status;
141 struct ath12k_mon_data mon_data;
142};
143
144#define DP_NUM_CLIENTS_MAX 64
145#define DP_AVG_TIDS_PER_CLIENT 2
146#define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
147#define DP_AVG_MSDUS_PER_FLOW 128
148#define DP_AVG_FLOWS_PER_TID 2
149#define DP_AVG_MPDUS_PER_TID_MAX 128
150#define DP_AVG_MSDUS_PER_MPDU 4
151
152#define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
153
154#define DP_BA_WIN_SZ_MAX 1024
155
156#define DP_TCL_NUM_RING_MAX 4
157
158#define DP_IDLE_SCATTER_BUFS_MAX 16
159
160#define DP_WBM_RELEASE_RING_SIZE 64
161#define DP_TCL_DATA_RING_SIZE 512
162#define DP_TX_COMP_RING_SIZE 32768
163#define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
164#define DP_TCL_CMD_RING_SIZE 32
165#define DP_TCL_STATUS_RING_SIZE 32
166#define DP_REO_DST_RING_MAX 8
167#define DP_REO_DST_RING_SIZE 2048
168#define DP_REO_REINJECT_RING_SIZE 32
169#define DP_RX_RELEASE_RING_SIZE 1024
170#define DP_REO_EXCEPTION_RING_SIZE 128
171#define DP_REO_CMD_RING_SIZE 128
172#define DP_REO_STATUS_RING_SIZE 2048
173#define DP_RXDMA_BUF_RING_SIZE 4096
174#define DP_RX_MAC_BUF_RING_SIZE 2048
175#define DP_RXDMA_REFILL_RING_SIZE 2048
176#define DP_RXDMA_ERR_DST_RING_SIZE 1024
177#define DP_RXDMA_MON_STATUS_RING_SIZE 1024
178#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
179#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
180#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
181#define DP_TX_MONITOR_BUF_RING_SIZE 4096
182#define DP_TX_MONITOR_DEST_RING_SIZE 2048
183
184#define DP_TX_MONITOR_BUF_SIZE 2048
185#define DP_TX_MONITOR_BUF_SIZE_MIN 48
186#define DP_TX_MONITOR_BUF_SIZE_MAX 8192
187
188#define DP_RX_BUFFER_SIZE 2048
189#define DP_RX_BUFFER_SIZE_LITE 1024
190#define DP_RX_BUFFER_ALIGN_SIZE 128
191
192#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
193#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)
194
195#define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
196#define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
197
198#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
199#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
200#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
201
202#define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
203#define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10
204
205#define ATH12K_NUM_POOL_TX_DESC 32768
206
207/* TODO: revisit this count during testing */
208#define ATH12K_RX_DESC_COUNT (12288)
209
210#define ATH12K_PAGE_SIZE PAGE_SIZE
211
212/* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
213 * SPT pages which makes lower 12bits 0
214 */
215#define ATH12K_MAX_PPT_ENTRIES 1024
216
217/* Total 512 entries in a SPT, i.e 4K Page/8 */
218#define ATH12K_MAX_SPT_ENTRIES 512
219
220#define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)
221
222#define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \
223 ATH12K_MAX_SPT_ENTRIES)
224#define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)
225#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)
226
227#define ATH12K_TX_SPT_PAGE_OFFSET 0
228#define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES
229
230/* The SPT pages are divided for RX and TX, first block for RX
231 * and remaining for TX
232 */
233#define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES
234
235#define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA
236
237/* 4K aligned address have last 12 bits set to 0, this check is done
238 * so that two spt pages address can be stored per 8bytes
239 * of CMEM (PPT)
240 */
241#define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
242#define ATH12K_SPT_4K_ALIGN_OFFSET 12
243#define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
244
245/* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
246#define ATH12K_CMEM_ADDR_MSB 0x10
247
248/* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
249#define ATH12K_CC_SPT_MSB 8
250#define ATH12K_CC_PPT_MSB 19
251#define ATH12K_CC_PPT_SHIFT 9
252#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
253#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
254
255#define DP_REO_QREF_NUM GENMASK(31, 16)
256#define DP_MAX_PEER_ID 2047
257
258/* Total size of the LUT is based on 2K peers, each having reference
259 * for 17tids, note each entry is of type ath12k_reo_queue_ref
260 * hence total size is 2048 * 17 * 8 = 278528
261 */
262#define DP_REOQ_LUT_SIZE 278528
263
264/* Invalid TX Bank ID value */
265#define DP_INVALID_BANK_ID -1
266
267struct ath12k_dp_tx_bank_profile {
268 u8 is_configured;
269 u32 num_users;
270 u32 bank_config;
271};
272
273struct ath12k_hp_update_timer {
274 struct timer_list timer;
275 bool started;
276 bool init;
277 u32 tx_num;
278 u32 timer_tx_num;
279 u32 ring_id;
280 u32 interval;
281 struct ath12k_base *ab;
282};
283
284struct ath12k_rx_desc_info {
285 struct list_head list;
286 struct sk_buff *skb;
287 u32 cookie;
288 u32 magic;
289 u8 in_use : 1,
290 reserved : 7;
291};
292
293struct ath12k_tx_desc_info {
294 struct list_head list;
295 struct sk_buff *skb;
296 u32 desc_id; /* Cookie */
297 u8 mac_id;
298 u8 pool_id;
299};
300
301struct ath12k_spt_info {
302 dma_addr_t paddr;
303 u64 *vaddr;
304};
305
306struct ath12k_reo_queue_ref {
307 u32 info0;
308 u32 info1;
309} __packed;
310
311struct ath12k_reo_q_addr_lut {
312 dma_addr_t paddr;
313 u32 *vaddr;
314};
315
316struct ath12k_dp {
317 struct ath12k_base *ab;
318 u8 num_bank_profiles;
319 /* protects the access and update of bank_profiles */
320 spinlock_t tx_bank_lock;
321 struct ath12k_dp_tx_bank_profile *bank_profiles;
322 enum ath12k_htc_ep_id eid;
323 struct completion htt_tgt_version_received;
324 u8 htt_tgt_ver_major;
325 u8 htt_tgt_ver_minor;
326 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
327 enum hal_rx_buf_return_buf_manager idle_link_rbm;
328 struct dp_srng wbm_idle_ring;
329 struct dp_srng wbm_desc_rel_ring;
330 struct dp_srng reo_reinject_ring;
331 struct dp_srng rx_rel_ring;
332 struct dp_srng reo_except_ring;
333 struct dp_srng reo_cmd_ring;
334 struct dp_srng reo_status_ring;
335 enum ath12k_peer_metadata_version peer_metadata_ver;
336 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
337 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
338 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
339 struct list_head reo_cmd_list;
340 struct list_head reo_cmd_cache_flush_list;
341 u32 reo_cmd_cache_flush_count;
342
343 /* protects access to below fields,
344 * - reo_cmd_list
345 * - reo_cmd_cache_flush_list
346 * - reo_cmd_cache_flush_count
347 */
348 spinlock_t reo_cmd_lock;
349 struct ath12k_hp_update_timer reo_cmd_timer;
350 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
351 struct ath12k_spt_info *spt_info;
352 u32 num_spt_pages;
353 u32 rx_ppt_base;
354 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];
355 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];
356 struct list_head rx_desc_free_list;
357 /* protects the free desc list */
358 spinlock_t rx_desc_lock;
359
360 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
361 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
362 /* protects the free and used desc lists */
363 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
364
365 struct dp_rxdma_ring rx_refill_buf_ring;
366 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
367 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
368 struct dp_rxdma_mon_ring rxdma_mon_buf_ring;
369 struct dp_rxdma_mon_ring tx_mon_buf_ring;
370 struct ath12k_reo_q_addr_lut reoq_lut;
371};
372
373/* HTT definitions */
374
375#define HTT_TCL_META_DATA_TYPE BIT(0)
376#define HTT_TCL_META_DATA_VALID_HTT BIT(1)
377
378/* vdev meta data */
379#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
380#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
381#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
382
383/* peer meta data */
384#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
385
386/* HTT tx completion is overlaid in wbm_release_ring */
387#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)
388#define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)
389#define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)
390
391#define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)
392
393struct htt_tx_wbm_completion {
394 __le32 rsvd0[2];
395 __le32 info0;
396 __le32 info1;
397 __le32 info2;
398 __le32 info3;
399 __le32 info4;
400 __le32 rsvd1;
401
402} __packed;
403
404enum htt_h2t_msg_type {
405 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
406 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
407 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
408 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
409 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
410 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a,
411 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
412};
413
414#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
415
416struct htt_ver_req_cmd {
417 __le32 ver_reg_info;
418} __packed;
419
420enum htt_srng_ring_type {
421 HTT_HW_TO_SW_RING,
422 HTT_SW_TO_HW_RING,
423 HTT_SW_TO_SW_RING,
424};
425
426enum htt_srng_ring_id {
427 HTT_RXDMA_HOST_BUF_RING,
428 HTT_RXDMA_MONITOR_STATUS_RING,
429 HTT_RXDMA_MONITOR_BUF_RING,
430 HTT_RXDMA_MONITOR_DESC_RING,
431 HTT_RXDMA_MONITOR_DEST_RING,
432 HTT_HOST1_TO_FW_RXBUF_RING,
433 HTT_HOST2_TO_FW_RXBUF_RING,
434 HTT_RXDMA_NON_MONITOR_DEST_RING,
435 HTT_TX_MON_HOST2MON_BUF_RING,
436 HTT_TX_MON_MON2HOST_DEST_RING,
437};
438
439/* host -> target HTT_SRING_SETUP message
440 *
441 * After target is booted up, Host can send SRING setup message for
442 * each host facing LMAC SRING. Target setups up HW registers based
443 * on setup message and confirms back to Host if response_required is set.
444 * Host should wait for confirmation message before sending new SRING
445 * setup message
446 *
447 * The message would appear as follows:
448 *
449 * |31 24|23 20|19|18 16|15|14 8|7 0|
450 * |--------------- +-----------------+----------------+------------------|
451 * | ring_type | ring_id | pdev_id | msg_type |
452 * |----------------------------------------------------------------------|
453 * | ring_base_addr_lo |
454 * |----------------------------------------------------------------------|
455 * | ring_base_addr_hi |
456 * |----------------------------------------------------------------------|
457 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
458 * |----------------------------------------------------------------------|
459 * | ring_head_offset32_remote_addr_lo |
460 * |----------------------------------------------------------------------|
461 * | ring_head_offset32_remote_addr_hi |
462 * |----------------------------------------------------------------------|
463 * | ring_tail_offset32_remote_addr_lo |
464 * |----------------------------------------------------------------------|
465 * | ring_tail_offset32_remote_addr_hi |
466 * |----------------------------------------------------------------------|
467 * | ring_msi_addr_lo |
468 * |----------------------------------------------------------------------|
469 * | ring_msi_addr_hi |
470 * |----------------------------------------------------------------------|
471 * | ring_msi_data |
472 * |----------------------------------------------------------------------|
473 * | intr_timer_th |IM| intr_batch_counter_th |
474 * |----------------------------------------------------------------------|
475 * | reserved |RR|PTCF| intr_low_threshold |
476 * |----------------------------------------------------------------------|
477 * Where
478 * IM = sw_intr_mode
479 * RR = response_required
480 * PTCF = prefetch_timer_cfg
481 *
482 * The message is interpreted as follows:
483 * dword0 - b'0:7 - msg_type: This will be set to
484 * HTT_H2T_MSG_TYPE_SRING_SETUP
485 * b'8:15 - pdev_id:
486 * 0 (for rings at SOC/UMAC level),
487 * 1/2/3 mac id (for rings at LMAC level)
488 * b'16:23 - ring_id: identify which ring is to setup,
489 * more details can be got from enum htt_srng_ring_id
490 * b'24:31 - ring_type: identify type of host rings,
491 * more details can be got from enum htt_srng_ring_type
492 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
493 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
494 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
495 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
496 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
497 * SW_TO_HW_RING.
498 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
499 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
500 * Lower 32 bits of memory address of the remote variable
501 * storing the 4-byte word offset that identifies the head
502 * element within the ring.
503 * (The head offset variable has type u32.)
504 * Valid for HW_TO_SW and SW_TO_SW rings.
505 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
506 * Upper 32 bits of memory address of the remote variable
507 * storing the 4-byte word offset that identifies the head
508 * element within the ring.
509 * (The head offset variable has type u32.)
510 * Valid for HW_TO_SW and SW_TO_SW rings.
511 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
512 * Lower 32 bits of memory address of the remote variable
513 * storing the 4-byte word offset that identifies the tail
514 * element within the ring.
515 * (The tail offset variable has type u32.)
516 * Valid for HW_TO_SW and SW_TO_SW rings.
517 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
518 * Upper 32 bits of memory address of the remote variable
519 * storing the 4-byte word offset that identifies the tail
520 * element within the ring.
521 * (The tail offset variable has type u32.)
522 * Valid for HW_TO_SW and SW_TO_SW rings.
523 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
524 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
525 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
526 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
527 * dword10 - b'0:31 - ring_msi_data: MSI data
528 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
529 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
530 * dword11 - b'0:14 - intr_batch_counter_th:
531 * batch counter threshold is in units of 4-byte words.
532 * HW internally maintains and increments batch count.
533 * (see SRING spec for detail description).
534 * When batch count reaches threshold value, an interrupt
535 * is generated by HW.
536 * b'15 - sw_intr_mode:
537 * This configuration shall be static.
538 * Only programmed at power up.
539 * 0: generate pulse style sw interrupts
540 * 1: generate level style sw interrupts
541 * b'16:31 - intr_timer_th:
542 * The timer init value when timer is idle or is
543 * initialized to start downcounting.
544 * In 8us units (to cover a range of 0 to 524 ms)
545 * dword12 - b'0:15 - intr_low_threshold:
546 * Used only by Consumer ring to generate ring_sw_int_p.
547 * Ring entries low threshold water mark, that is used
548 * in combination with the interrupt timer as well as
549 * the clearing of the level interrupt.
550 * b'16:18 - prefetch_timer_cfg:
551 * Used only by Consumer ring to set timer mode to
552 * support Application prefetch handling.
553 * The external tail offset/pointer will be updated
554 * at following intervals:
555 * 3'b000: (Prefetch feature disabled; used only for debug)
556 * 3'b001: 1 usec
557 * 3'b010: 4 usec
558 * 3'b011: 8 usec (default)
559 * 3'b100: 16 usec
560 * Others: Reserved
561 * b'19 - response_required:
562 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
563 * b'20:31 - reserved: reserved for future use
564 */
565
566#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
567#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
568#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
569#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
570
571#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
572#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
573#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
574#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
575#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
576#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
577
578#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
579#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
580#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
581
582#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
583#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)
584#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
585
586struct htt_srng_setup_cmd {
587 __le32 info0;
588 __le32 ring_base_addr_lo;
589 __le32 ring_base_addr_hi;
590 __le32 info1;
591 __le32 ring_head_off32_remote_addr_lo;
592 __le32 ring_head_off32_remote_addr_hi;
593 __le32 ring_tail_off32_remote_addr_lo;
594 __le32 ring_tail_off32_remote_addr_hi;
595 __le32 ring_msi_addr_lo;
596 __le32 ring_msi_addr_hi;
597 __le32 msi_data;
598 __le32 intr_info;
599 __le32 info2;
600} __packed;
601
602/* host -> target FW PPDU_STATS config message
603 *
604 * @details
605 * The following field definitions describe the format of the HTT host
606 * to target FW for PPDU_STATS_CFG msg.
607 * The message allows the host to configure the PPDU_STATS_IND messages
608 * produced by the target.
609 *
610 * |31 24|23 16|15 8|7 0|
611 * |-----------------------------------------------------------|
612 * | REQ bit mask | pdev_mask | msg type |
613 * |-----------------------------------------------------------|
614 * Header fields:
615 * - MSG_TYPE
616 * Bits 7:0
617 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
618 * Value: 0x11
619 * - PDEV_MASK
620 * Bits 8:15
621 * Purpose: identifies which pdevs this PPDU stats configuration applies to
622 * Value: This is a overloaded field, refer to usage and interpretation of
623 * PDEV in interface document.
624 * Bit 8 : Reserved for SOC stats
625 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
626 * Indicates MACID_MASK in DBS
627 * - REQ_TLV_BIT_MASK
628 * Bits 16:31
629 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
630 * needs to be included in the target's PPDU_STATS_IND messages.
631 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
632 *
633 */
634
635struct htt_ppdu_stats_cfg_cmd {
636 __le32 msg;
637} __packed;
638
639#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
640#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8)
641#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
642
643enum htt_ppdu_stats_tag_type {
644 HTT_PPDU_STATS_TAG_COMMON,
645 HTT_PPDU_STATS_TAG_USR_COMMON,
646 HTT_PPDU_STATS_TAG_USR_RATE,
647 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
648 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
649 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
650 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
651 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
652 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
653 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
654 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
655 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
656 HTT_PPDU_STATS_TAG_INFO,
657 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
658
659 /* New TLV's are added above to this line */
660 HTT_PPDU_STATS_TAG_MAX,
661};
662
663#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
664 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
665 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
666 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
667 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
668 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
669 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
670 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
671
672#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
673 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
674 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
675 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
676 BIT(HTT_PPDU_STATS_TAG_INFO) | \
677 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
678 HTT_PPDU_STATS_TAG_DEFAULT)
679
680enum htt_stats_internal_ppdu_frametype {
681 HTT_STATS_PPDU_FTYPE_CTRL,
682 HTT_STATS_PPDU_FTYPE_DATA,
683 HTT_STATS_PPDU_FTYPE_BAR,
684 HTT_STATS_PPDU_FTYPE_MAX
685};
686
687/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
688 *
689 * details:
690 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
691 * configure RXDMA rings.
692 * The configuration is per ring based and includes both packet subtypes
693 * and PPDU/MPDU TLVs.
694 *
695 * The message would appear as follows:
696 *
697 * |31 26|25|24|23 16|15 8|7 0|
698 * |-----------------+----------------+----------------+---------------|
699 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
700 * |-------------------------------------------------------------------|
701 * | rsvd2 | ring_buffer_size |
702 * |-------------------------------------------------------------------|
703 * | packet_type_enable_flags_0 |
704 * |-------------------------------------------------------------------|
705 * | packet_type_enable_flags_1 |
706 * |-------------------------------------------------------------------|
707 * | packet_type_enable_flags_2 |
708 * |-------------------------------------------------------------------|
709 * | packet_type_enable_flags_3 |
710 * |-------------------------------------------------------------------|
711 * | tlv_filter_in_flags |
712 * |-------------------------------------------------------------------|
713 * Where:
714 * PS = pkt_swap
715 * SS = status_swap
716 * The message is interpreted as follows:
717 * dword0 - b'0:7 - msg_type: This will be set to
718 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
719 * b'8:15 - pdev_id:
720 * 0 (for rings at SOC/UMAC level),
721 * 1/2/3 mac id (for rings at LMAC level)
722 * b'16:23 - ring_id : Identify the ring to configure.
723 * More details can be got from enum htt_srng_ring_id
724 * b'24 - status_swap: 1 is to swap status TLV
725 * b'25 - pkt_swap: 1 is to swap packet TLV
726 * b'26:31 - rsvd1: reserved for future use
727 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
728 * in byte units.
729 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
730 * - b'16:31 - rsvd2: Reserved for future use
731 * dword2 - b'0:31 - packet_type_enable_flags_0:
732 * Enable MGMT packet from 0b0000 to 0b1001
733 * bits from low to high: FP, MD, MO - 3 bits
734 * FP: Filter_Pass
735 * MD: Monitor_Direct
736 * MO: Monitor_Other
737 * 10 mgmt subtypes * 3 bits -> 30 bits
738 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
739 * dword3 - b'0:31 - packet_type_enable_flags_1:
740 * Enable MGMT packet from 0b1010 to 0b1111
741 * bits from low to high: FP, MD, MO - 3 bits
742 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
743 * dword4 - b'0:31 - packet_type_enable_flags_2:
744 * Enable CTRL packet from 0b0000 to 0b1001
745 * bits from low to high: FP, MD, MO - 3 bits
746 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
747 * dword5 - b'0:31 - packet_type_enable_flags_3:
748 * Enable CTRL packet from 0b1010 to 0b1111,
749 * MCAST_DATA, UCAST_DATA, NULL_DATA
750 * bits from low to high: FP, MD, MO - 3 bits
751 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
752 * dword6 - b'0:31 - tlv_filter_in_flags:
753 * Filter in Attention/MPDU/PPDU/Header/User tlvs
754 * Refer to CFG_TLV_FILTER_IN_FLAG defs
755 */
756
757#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
758#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
759#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
760#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
761#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
762#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
763#define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26)
764
765#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)
766#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)
767#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)
768#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)
769#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)
770#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)
771#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)
772
773#define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23)
774#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)
775#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)
776#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)
777
778enum htt_rx_filter_tlv_flags {
779 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
780 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
781 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
782 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
783 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
784 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
785 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
786 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
787 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
788 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
789 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
790 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
791 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
792};
793
794enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
795 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
796 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
797 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
798 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
799 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
800 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
801 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
802 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
803 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
804 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
805 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
806 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
807 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
808 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
809 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
810 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
811 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
812 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
813 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
814 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
815 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
816 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
817 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
818 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
819 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
820 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
821 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
822 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
823 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
824 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
825};
826
827enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
828 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
829 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
830 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
831 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
832 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
833 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
834 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
835 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
836 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
837 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
838 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
839 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
840 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
841 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
842 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
843 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
844 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
845 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
846};
847
848enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
849 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
850 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
851 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
852 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
853 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
854 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
855 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
856 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
857 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
858 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
859 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
860 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
861 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
862 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
863 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
864 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
865 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
866 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
867 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
868 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
869 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
870 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
871 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
872 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
873 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
874 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
875 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
876 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
877 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
878 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
879};
880
881enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
882 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
883 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
884 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
885 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
886 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
887 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
889 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
890 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
892 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
893 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
894 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
895 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
896 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
897 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
898 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
899 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
900};
901
902enum htt_rx_data_pkt_filter_tlv_flasg3 {
903 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
904 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
905 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
906 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
907 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
908 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
909 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
910 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
911 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
912};
913
914#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
915 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
916 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
917 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
918 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
919 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
920 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
921 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
922 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
923 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
924
925#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
926 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
927 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
928 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
929 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
930 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
931 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
932 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
933 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
934 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
935
936#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
937 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
938 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
939 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
940 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
941 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
942 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
943 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
944 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
945 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
946
947#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
948 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
949 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
950 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
951 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
952
953#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
954 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
955 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
956 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
957 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
958
959#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
960 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
961 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
962 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
963 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
964
965#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
966 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
967 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
968
969#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
970 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
971 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
972
973#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
974 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
975 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
976
977#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
978 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
979 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
980 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
981 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
982 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
983
984#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
985 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
986 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
987 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
988 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
989 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
990
991#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
992 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
993 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
994 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
995 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
996 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
997
998#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
999 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1000 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1001
1002#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1003 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1004 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1005
1006#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1007 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1008 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1009
1010#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
1011 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
1012 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1013
1014#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
1015 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
1016 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1017
1018#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
1019 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
1020 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1021
1022#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
1023 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
1024 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1025
1026#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
1027 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
1028 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1029 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1030 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1031 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1032 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1033 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1034 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1035
1036#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
1037 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
1038 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1039 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1040 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1041 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1042 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1043 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1044 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1045
1046#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
1047
1048#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
1049
1050#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
1051
1052#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
1053
1054#define HTT_RX_MON_FILTER_TLV_FLAGS \
1055 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1056 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1057 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1058 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1059 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1060 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1061
1062#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
1063 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1064 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1065 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1066 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1067 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1068 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1069
1070#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
1071 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1072 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1073 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1074 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1075 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1076 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1077 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1078 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
1079
1080/* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
1081#define HTT_RX_TLV_FLAGS_RXDMA_RING \
1082 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1083 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1084 HTT_RX_FILTER_TLV_FLAGS_MSDU_END)
1085
1086#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1087#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1088
1089struct htt_rx_ring_selection_cfg_cmd {
1090 __le32 info0;
1091 __le32 info1;
1092 __le32 pkt_type_en_flags0;
1093 __le32 pkt_type_en_flags1;
1094 __le32 pkt_type_en_flags2;
1095 __le32 pkt_type_en_flags3;
1096 __le32 rx_filter_tlv;
1097 __le32 rx_packet_offset;
1098 __le32 rx_mpdu_offset;
1099 __le32 rx_msdu_offset;
1100 __le32 rx_attn_offset;
1101 __le32 info2;
1102 __le32 reserved[2];
1103 __le32 rx_mpdu_start_end_mask;
1104 __le32 rx_msdu_end_word_mask;
1105 __le32 info3;
1106} __packed;
1107
1108struct htt_rx_ring_tlv_filter {
1109 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
1110 u32 pkt_filter_flags0; /* MGMT */
1111 u32 pkt_filter_flags1; /* MGMT */
1112 u32 pkt_filter_flags2; /* CTRL */
1113 u32 pkt_filter_flags3; /* DATA */
1114 bool offset_valid;
1115 u16 rx_packet_offset;
1116 u16 rx_header_offset;
1117 u16 rx_mpdu_end_offset;
1118 u16 rx_mpdu_start_offset;
1119 u16 rx_msdu_end_offset;
1120 u16 rx_msdu_start_offset;
1121 u16 rx_attn_offset;
1122 u16 rx_mpdu_start_wmask;
1123 u16 rx_mpdu_end_wmask;
1124 u32 rx_msdu_end_wmask;
1125};
1126
1127#define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0
1128#define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1
1129#define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2
1130#define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3
1131
1132#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1133#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1134#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
1135#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
1136#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
1137
1138#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)
1139#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)
1140#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)
1141#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)
1142#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)
1143
1144#define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)
1145
1146struct htt_tx_ring_selection_cfg_cmd {
1147 __le32 info0;
1148 __le32 info1;
1149 __le32 info2;
1150 __le32 tlv_filter_mask_in0;
1151 __le32 tlv_filter_mask_in1;
1152 __le32 tlv_filter_mask_in2;
1153 __le32 tlv_filter_mask_in3;
1154 __le32 reserved[3];
1155} __packed;
1156
1157#define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)
1158#define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)
1159#define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)
1160
1161#define HTT_TX_MON_FILTER_HYBRID_MODE \
1162 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \
1163 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \
1164 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \
1165 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \
1166 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \
1167 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \
1168 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \
1169 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \
1170 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \
1171 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \
1172 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \
1173 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \
1174 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)
1175
1176struct htt_tx_ring_tlv_filter {
1177 u32 tx_mon_downstream_tlv_flags;
1178 u32 tx_mon_upstream_tlv_flags0;
1179 u32 tx_mon_upstream_tlv_flags1;
1180 u32 tx_mon_upstream_tlv_flags2;
1181 bool tx_mon_mgmt_filter;
1182 bool tx_mon_data_filter;
1183 bool tx_mon_ctrl_filter;
1184 u16 tx_mon_pkt_dma_len;
1185} __packed;
1186
1187enum htt_tx_mon_upstream_tlv_flags0 {
1188 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),
1189 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),
1190 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),
1191 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),
1192 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),
1193 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),
1194 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),
1195 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),
1196 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),
1197 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),
1198 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),
1199 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),
1200 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),
1201 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),
1202 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),
1203 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),
1204};
1205
1206#define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)
1207
1208/* HTT message target->host */
1209
1210enum htt_t2h_msg_type {
1211 HTT_T2H_MSG_TYPE_VERSION_CONF,
1212 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1213 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1214 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1215 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1216 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1217 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1218 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1219 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1220 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1221 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1222 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
1223 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b,
1224 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,
1225};
1226
1227#define HTT_TARGET_VERSION_MAJOR 3
1228
1229#define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1230#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1231#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1232
1233struct htt_t2h_version_conf_msg {
1234 __le32 version;
1235} __packed;
1236
1237#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1238#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1239#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1240#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1241#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1242#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1243#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1244
1245struct htt_t2h_peer_map_event {
1246 __le32 info;
1247 __le32 mac_addr_l32;
1248 __le32 info1;
1249 __le32 info2;
1250} __packed;
1251
1252#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1253#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1254#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1255 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1256#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1257#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1258
1259struct htt_t2h_peer_unmap_event {
1260 __le32 info;
1261 __le32 mac_addr_l32;
1262 __le32 info1;
1263} __packed;
1264
1265struct htt_resp_msg {
1266 union {
1267 struct htt_t2h_version_conf_msg version_msg;
1268 struct htt_t2h_peer_map_event peer_map_ev;
1269 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1270 };
1271} __packed;
1272
1273#define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\
1274 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))
1275#define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)
1276#define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)
1277#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)
1278#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)
1279#define HTT_VDEV_TXRX_STATS_COMMON_TLV 0
1280#define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1
1281
1282struct htt_t2h_vdev_txrx_stats_ind {
1283 __le32 vdev_id;
1284 __le32 rx_msdu_byte_cnt_lo;
1285 __le32 rx_msdu_byte_cnt_hi;
1286 __le32 rx_msdu_cnt_lo;
1287 __le32 rx_msdu_cnt_hi;
1288 __le32 tx_msdu_byte_cnt_lo;
1289 __le32 tx_msdu_byte_cnt_hi;
1290 __le32 tx_msdu_cnt_lo;
1291 __le32 tx_msdu_cnt_hi;
1292 __le32 tx_retry_cnt_lo;
1293 __le32 tx_retry_cnt_hi;
1294 __le32 tx_retry_byte_cnt_lo;
1295 __le32 tx_retry_byte_cnt_hi;
1296 __le32 tx_drop_cnt_lo;
1297 __le32 tx_drop_cnt_hi;
1298 __le32 tx_drop_byte_cnt_lo;
1299 __le32 tx_drop_byte_cnt_hi;
1300 __le32 msdu_ttl_cnt_lo;
1301 __le32 msdu_ttl_cnt_hi;
1302 __le32 msdu_ttl_byte_cnt_lo;
1303 __le32 msdu_ttl_byte_cnt_hi;
1304} __packed;
1305
1306struct htt_t2h_vdev_common_stats_tlv {
1307 __le32 soc_drop_count_lo;
1308 __le32 soc_drop_count_hi;
1309} __packed;
1310
1311/* ppdu stats
1312 *
1313 * @details
1314 * The following field definitions describe the format of the HTT target
1315 * to host ppdu stats indication message.
1316 *
1317 *
1318 * |31 16|15 12|11 10|9 8|7 0 |
1319 * |----------------------------------------------------------------------|
1320 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1321 * |----------------------------------------------------------------------|
1322 * | ppdu_id |
1323 * |----------------------------------------------------------------------|
1324 * | Timestamp in us |
1325 * |----------------------------------------------------------------------|
1326 * | reserved |
1327 * |----------------------------------------------------------------------|
1328 * | type-specific stats info |
1329 * | (see htt_ppdu_stats.h) |
1330 * |----------------------------------------------------------------------|
1331 * Header fields:
1332 * - MSG_TYPE
1333 * Bits 7:0
1334 * Purpose: Identifies this is a PPDU STATS indication
1335 * message.
1336 * Value: 0x1d
1337 * - mac_id
1338 * Bits 9:8
1339 * Purpose: mac_id of this ppdu_id
1340 * Value: 0-3
1341 * - pdev_id
1342 * Bits 11:10
1343 * Purpose: pdev_id of this ppdu_id
1344 * Value: 0-3
1345 * 0 (for rings at SOC level),
1346 * 1/2/3 PDEV -> 0/1/2
1347 * - payload_size
1348 * Bits 31:16
1349 * Purpose: total tlv size
1350 * Value: payload_size in bytes
1351 */
1352
1353#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1354#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1355
1356struct ath12k_htt_ppdu_stats_msg {
1357 __le32 info;
1358 __le32 ppdu_id;
1359 __le32 timestamp;
1360 __le32 rsvd;
1361 u8 data[];
1362} __packed;
1363
1364struct htt_tlv {
1365 __le32 header;
1366 u8 value[];
1367} __packed;
1368
1369#define HTT_TLV_TAG GENMASK(11, 0)
1370#define HTT_TLV_LEN GENMASK(23, 12)
1371
1372enum HTT_PPDU_STATS_BW {
1373 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1374 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1375 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1376 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1377 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1378 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1379 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1380};
1381
1382#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1383#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1384/* bw - HTT_PPDU_STATS_BW */
1385#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1386
1387struct htt_ppdu_stats_common {
1388 __le32 ppdu_id;
1389 __le16 sched_cmdid;
1390 u8 ring_id;
1391 u8 num_users;
1392 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1393 __le32 chain_mask;
1394 __le32 fes_duration_us; /* frame exchange sequence */
1395 __le32 ppdu_sch_eval_start_tstmp_us;
1396 __le32 ppdu_sch_end_tstmp_us;
1397 __le32 ppdu_start_tstmp_us;
1398 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1399 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1400 */
1401 __le16 phy_mode;
1402 __le16 bw_mhz;
1403} __packed;
1404
1405enum htt_ppdu_stats_gi {
1406 HTT_PPDU_STATS_SGI_0_8_US,
1407 HTT_PPDU_STATS_SGI_0_4_US,
1408 HTT_PPDU_STATS_SGI_1_6_US,
1409 HTT_PPDU_STATS_SGI_3_2_US,
1410};
1411
1412#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1413#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1414
1415enum HTT_PPDU_STATS_PPDU_TYPE {
1416 HTT_PPDU_STATS_PPDU_TYPE_SU,
1417 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
1418 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,
1419 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,
1420 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,
1421 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,
1422 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,
1423 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,
1424 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,
1425 HTT_PPDU_STATS_PPDU_TYPE_MAX
1426};
1427
1428#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1429#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1430
1431#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1432#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1433#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1434#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1435#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1436#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1437#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1438#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1439#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1440#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1441#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1442
1443#define HTT_USR_RATE_PREAMBLE(_val) \
1444 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)
1445#define HTT_USR_RATE_BW(_val) \
1446 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)
1447#define HTT_USR_RATE_NSS(_val) \
1448 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)
1449#define HTT_USR_RATE_MCS(_val) \
1450 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)
1451#define HTT_USR_RATE_GI(_val) \
1452 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)
1453#define HTT_USR_RATE_DCM(_val) \
1454 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)
1455
1456#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1457#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1458#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1459#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1460#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1461#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1462#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1463#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1464#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1465#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1466#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1467
1468struct htt_ppdu_stats_user_rate {
1469 u8 tid_num;
1470 u8 reserved0;
1471 __le16 sw_peer_id;
1472 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1473 __le16 ru_end;
1474 __le16 ru_start;
1475 __le16 resp_ru_end;
1476 __le16 resp_ru_start;
1477 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1478 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1479 /* Note: resp_rate_info is only valid for if resp_type is UL */
1480 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1481} __packed;
1482
1483#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1484#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1485#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1486#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1487#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1488#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1489
1490#define HTT_TX_INFO_IS_AMSDU(_flags) \
1491 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)
1492#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1493 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)
1494#define HTT_TX_INFO_RATECODE(_flags) \
1495 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)
1496#define HTT_TX_INFO_PEERID(_flags) \
1497 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)
1498
1499enum htt_ppdu_stats_usr_compln_status {
1500 HTT_PPDU_STATS_USER_STATUS_OK,
1501 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1502 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1503 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1504 HTT_PPDU_STATS_USER_STATUS_ABORT,
1505};
1506
1507#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1508#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1509#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1510#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1511
1512#define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1513 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)
1514#define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1515 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)
1516#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1517 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)
1518
1519struct htt_ppdu_stats_usr_cmpltn_cmn {
1520 u8 status;
1521 u8 tid_num;
1522 __le16 sw_peer_id;
1523 /* RSSI value of last ack packet (units = dB above noise floor) */
1524 __le32 ack_rssi;
1525 __le16 mpdu_tried;
1526 __le16 mpdu_success;
1527 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1528} __packed;
1529
1530#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1531#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1532#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1533
1534#define HTT_PPDU_STATS_NON_QOS_TID 16
1535
1536struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1537 __le32 ppdu_id;
1538 __le16 sw_peer_id;
1539 __le16 reserved0;
1540 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1541 __le16 current_seq;
1542 __le16 start_seq;
1543 __le32 success_bytes;
1544} __packed;
1545
1546struct htt_ppdu_user_stats {
1547 u16 peer_id;
1548 u16 delay_ba;
1549 u32 tlv_flags;
1550 bool is_valid_peer_id;
1551 struct htt_ppdu_stats_user_rate rate;
1552 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1553 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1554};
1555
1556#define HTT_PPDU_STATS_MAX_USERS 8
1557#define HTT_PPDU_DESC_MAX_DEPTH 16
1558
1559struct htt_ppdu_stats {
1560 struct htt_ppdu_stats_common common;
1561 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1562};
1563
1564struct htt_ppdu_stats_info {
1565 u32 tlv_bitmap;
1566 u32 ppdu_id;
1567 u32 frame_type;
1568 u32 frame_ctrl;
1569 u32 delay_ba;
1570 u32 bar_num_users;
1571 struct htt_ppdu_stats ppdu_stats;
1572 struct list_head list;
1573};
1574
1575/* @brief target -> host MLO offset indiciation message
1576 *
1577 * @details
1578 * The following field definitions describe the format of the HTT target
1579 * to host mlo offset indication message.
1580 *
1581 *
1582 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0|
1583 * |---------------------------------------------------------------------|
1584 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype|
1585 * |---------------------------------------------------------------------|
1586 * | sync_timestamp_lo_us |
1587 * |---------------------------------------------------------------------|
1588 * | sync_timestamp_hi_us |
1589 * |---------------------------------------------------------------------|
1590 * | mlo_offset_lo |
1591 * |---------------------------------------------------------------------|
1592 * | mlo_offset_hi |
1593 * |---------------------------------------------------------------------|
1594 * | mlo_offset_clcks |
1595 * |---------------------------------------------------------------------|
1596 * | rsvd2 | mlo_comp_clks |mlo_comp_us |
1597 * |---------------------------------------------------------------------|
1598 * | rsvd3 |mlo_comp_timer |
1599 * |---------------------------------------------------------------------|
1600 * Header fields
1601 * - MSG_TYPE
1602 * Bits 7:0
1603 * Purpose: Identifies this is a MLO offset indication msg
1604 * - PDEV_ID
1605 * Bits 9:8
1606 * Purpose: Pdev of this MLO offset
1607 * - CHIP_ID
1608 * Bits 12:10
1609 * Purpose: chip_id of this MLO offset
1610 * - MAC_FREQ
1611 * Bits 28:13
1612 * - SYNC_TIMESTAMP_LO_US
1613 * Purpose: clock frequency of the mac HW block in MHz
1614 * Bits: 31:0
1615 * Purpose: lower 32 bits of the WLAN global time stamp at which
1616 * last sync interrupt was received
1617 * - SYNC_TIMESTAMP_HI_US
1618 * Bits: 31:0
1619 * Purpose: upper 32 bits of WLAN global time stamp at which
1620 * last sync interrupt was received
1621 * - MLO_OFFSET_LO
1622 * Bits: 31:0
1623 * Purpose: lower 32 bits of the MLO offset in us
1624 * - MLO_OFFSET_HI
1625 * Bits: 31:0
1626 * Purpose: upper 32 bits of the MLO offset in us
1627 * - MLO_COMP_US
1628 * Bits: 15:0
1629 * Purpose: MLO time stamp compensation applied in us
1630 * - MLO_COMP_CLCKS
1631 * Bits: 25:16
1632 * Purpose: MLO time stamp compensation applied in clock ticks
1633 * - MLO_COMP_TIMER
1634 * Bits: 21:0
1635 * Purpose: Periodic timer at which compensation is applied
1636 */
1637
1638#define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)
1639#define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)
1640
1641struct ath12k_htt_mlo_offset_msg {
1642 __le32 info;
1643 __le32 sync_timestamp_lo_us;
1644 __le32 sync_timestamp_hi_us;
1645 __le32 mlo_offset_hi;
1646 __le32 mlo_offset_lo;
1647 __le32 mlo_offset_clks;
1648 __le32 mlo_comp_clks;
1649 __le32 mlo_comp_timer;
1650} __packed;
1651
1652/* @brief host -> target FW extended statistics retrieve
1653 *
1654 * @details
1655 * The following field definitions describe the format of the HTT host
1656 * to target FW extended stats retrieve message.
1657 * The message specifies the type of stats the host wants to retrieve.
1658 *
1659 * |31 24|23 16|15 8|7 0|
1660 * |-----------------------------------------------------------|
1661 * | reserved | stats type | pdev_mask | msg type |
1662 * |-----------------------------------------------------------|
1663 * | config param [0] |
1664 * |-----------------------------------------------------------|
1665 * | config param [1] |
1666 * |-----------------------------------------------------------|
1667 * | config param [2] |
1668 * |-----------------------------------------------------------|
1669 * | config param [3] |
1670 * |-----------------------------------------------------------|
1671 * | reserved |
1672 * |-----------------------------------------------------------|
1673 * | cookie LSBs |
1674 * |-----------------------------------------------------------|
1675 * | cookie MSBs |
1676 * |-----------------------------------------------------------|
1677 * Header fields:
1678 * - MSG_TYPE
1679 * Bits 7:0
1680 * Purpose: identifies this is a extended stats upload request message
1681 * Value: 0x10
1682 * - PDEV_MASK
1683 * Bits 8:15
1684 * Purpose: identifies the mask of PDEVs to retrieve stats from
1685 * Value: This is a overloaded field, refer to usage and interpretation of
1686 * PDEV in interface document.
1687 * Bit 8 : Reserved for SOC stats
1688 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1689 * Indicates MACID_MASK in DBS
1690 * - STATS_TYPE
1691 * Bits 23:16
1692 * Purpose: identifies which FW statistics to upload
1693 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1694 * - Reserved
1695 * Bits 31:24
1696 * - CONFIG_PARAM [0]
1697 * Bits 31:0
1698 * Purpose: give an opaque configuration value to the specified stats type
1699 * Value: stats-type specific configuration value
1700 * Refer to htt_stats.h for interpretation for each stats sub_type
1701 * - CONFIG_PARAM [1]
1702 * Bits 31:0
1703 * Purpose: give an opaque configuration value to the specified stats type
1704 * Value: stats-type specific configuration value
1705 * Refer to htt_stats.h for interpretation for each stats sub_type
1706 * - CONFIG_PARAM [2]
1707 * Bits 31:0
1708 * Purpose: give an opaque configuration value to the specified stats type
1709 * Value: stats-type specific configuration value
1710 * Refer to htt_stats.h for interpretation for each stats sub_type
1711 * - CONFIG_PARAM [3]
1712 * Bits 31:0
1713 * Purpose: give an opaque configuration value to the specified stats type
1714 * Value: stats-type specific configuration value
1715 * Refer to htt_stats.h for interpretation for each stats sub_type
1716 * - Reserved [31:0] for future use.
1717 * - COOKIE_LSBS
1718 * Bits 31:0
1719 * Purpose: Provide a mechanism to match a target->host stats confirmation
1720 * message with its preceding host->target stats request message.
1721 * Value: LSBs of the opaque cookie specified by the host-side requestor
1722 * - COOKIE_MSBS
1723 * Bits 31:0
1724 * Purpose: Provide a mechanism to match a target->host stats confirmation
1725 * message with its preceding host->target stats request message.
1726 * Value: MSBs of the opaque cookie specified by the host-side requestor
1727 */
1728
1729struct htt_ext_stats_cfg_hdr {
1730 u8 msg_type;
1731 u8 pdev_mask;
1732 u8 stats_type;
1733 u8 reserved;
1734} __packed;
1735
1736struct htt_ext_stats_cfg_cmd {
1737 struct htt_ext_stats_cfg_hdr hdr;
1738 __le32 cfg_param0;
1739 __le32 cfg_param1;
1740 __le32 cfg_param2;
1741 __le32 cfg_param3;
1742 __le32 reserved;
1743 __le32 cookie_lsb;
1744 __le32 cookie_msb;
1745} __packed;
1746
1747/* htt stats config default params */
1748#define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1749#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1750#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1751#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1752#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1753#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1754#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1755#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1756
1757/* HTT_DBG_EXT_STATS_PEER_INFO
1758 * PARAMS:
1759 * @config_param0:
1760 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1761 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1762 * [Bit31 : Bit16] sw_peer_id
1763 * @config_param1:
1764 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1765 * 0 bit htt_peer_stats_cmn_tlv
1766 * 1 bit htt_peer_details_tlv
1767 * 2 bit htt_tx_peer_rate_stats_tlv
1768 * 3 bit htt_rx_peer_rate_stats_tlv
1769 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1770 * 5 bit htt_rx_tid_stats_tlv
1771 * 6 bit htt_msdu_flow_stats_tlv
1772 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1773 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1774 * [Bit31 : Bit16] reserved
1775 */
1776#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1777#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1778
1779/* Used to set different configs to the specified stats type.*/
1780struct htt_ext_stats_cfg_params {
1781 u32 cfg0;
1782 u32 cfg1;
1783 u32 cfg2;
1784 u32 cfg3;
1785};
1786
1787enum vdev_stats_offload_timer_duration {
1788 ATH12K_STATS_TIMER_DUR_500MS = 1,
1789 ATH12K_STATS_TIMER_DUR_1SEC = 2,
1790 ATH12K_STATS_TIMER_DUR_2SEC = 3,
1791};
1792
1793static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1794{
1795 memcpy(addr, &addr_l32, 4);
1796 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1797}
1798
1799int ath12k_dp_service_srng(struct ath12k_base *ab,
1800 struct ath12k_ext_irq_grp *irq_grp,
1801 int budget);
1802int ath12k_dp_htt_connect(struct ath12k_dp *dp);
1803void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif);
1804void ath12k_dp_free(struct ath12k_base *ab);
1805int ath12k_dp_alloc(struct ath12k_base *ab);
1806void ath12k_dp_cc_config(struct ath12k_base *ab);
1807int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
1808void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab);
1809void ath12k_dp_pdev_free(struct ath12k_base *ab);
1810int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
1811 int mac_id, enum hal_ring_type ring_type);
1812int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
1813void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
1814void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
1815int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
1816 enum hal_ring_type type, int ring_num,
1817 int mac_id, int num_entries);
1818void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
1819 struct dp_link_desc_bank *desc_bank,
1820 u32 ring_type, struct dp_srng *ring);
1821int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
1822 struct dp_link_desc_bank *link_desc_banks,
1823 u32 ring_type, struct hal_srng *srng,
1824 u32 n_link_desc);
1825struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1826 u32 cookie);
1827struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1828 u32 desc_id);
1829bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab);
1830void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab);
1831#endif