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1/*
2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/kthread.h>
34#include <linux/slab.h>
35
36#include <linux/i2c/twl.h>
37
38#include "twl-core.h"
39
40/*
41 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
42 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
43 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
44 * SIH modules are more traditional IRQ components, which support per-IRQ
45 * enable/disable and trigger controls; they do most of the work.
46 *
47 * These chips are designed to support IRQ handling from two different
48 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
49 * and mask registers in the PIH and SIH modules.
50 *
51 * We set up IRQs starting at a platform-specified base, always starting
52 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
53 * base + 0 .. base + 7 PIH
54 * base + 8 .. base + 15 SIH for PWR_INT
55 * base + 16 .. base + 33 SIH for GPIO
56 */
57
58/* PIH register offsets */
59#define REG_PIH_ISR_P1 0x01
60#define REG_PIH_ISR_P2 0x02
61#define REG_PIH_SIR 0x03 /* for testing */
62
63
64/* Linux could (eventually) use either IRQ line */
65static int irq_line;
66
67struct sih {
68 char name[8];
69 u8 module; /* module id */
70 u8 control_offset; /* for SIH_CTRL */
71 bool set_cor;
72
73 u8 bits; /* valid in isr/imr */
74 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
75
76 u8 edr_offset;
77 u8 bytes_edr; /* bytelen of EDR */
78
79 u8 irq_lines; /* number of supported irq lines */
80
81 /* SIR ignored -- set interrupt, for testing only */
82 struct sih_irq_data {
83 u8 isr_offset;
84 u8 imr_offset;
85 } mask[2];
86 /* + 2 bytes padding */
87};
88
89static const struct sih *sih_modules;
90static int nr_sih_modules;
91
92#define SIH_INITIALIZER(modname, nbits) \
93 .module = TWL4030_MODULE_ ## modname, \
94 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
95 .bits = nbits, \
96 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
97 .edr_offset = TWL4030_ ## modname ## _EDR, \
98 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
99 .irq_lines = 2, \
100 .mask = { { \
101 .isr_offset = TWL4030_ ## modname ## _ISR1, \
102 .imr_offset = TWL4030_ ## modname ## _IMR1, \
103 }, \
104 { \
105 .isr_offset = TWL4030_ ## modname ## _ISR2, \
106 .imr_offset = TWL4030_ ## modname ## _IMR2, \
107 }, },
108
109/* register naming policies are inconsistent ... */
110#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
111#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
112#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
113
114
115/* Order in this table matches order in PIH_ISR. That is,
116 * BIT(n) in PIH_ISR is sih_modules[n].
117 */
118/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
119static const struct sih sih_modules_twl4030[6] = {
120 [0] = {
121 .name = "gpio",
122 .module = TWL4030_MODULE_GPIO,
123 .control_offset = REG_GPIO_SIH_CTRL,
124 .set_cor = true,
125 .bits = TWL4030_GPIO_MAX,
126 .bytes_ixr = 3,
127 /* Note: *all* of these IRQs default to no-trigger */
128 .edr_offset = REG_GPIO_EDR1,
129 .bytes_edr = 5,
130 .irq_lines = 2,
131 .mask = { {
132 .isr_offset = REG_GPIO_ISR1A,
133 .imr_offset = REG_GPIO_IMR1A,
134 }, {
135 .isr_offset = REG_GPIO_ISR1B,
136 .imr_offset = REG_GPIO_IMR1B,
137 }, },
138 },
139 [1] = {
140 .name = "keypad",
141 .set_cor = true,
142 SIH_INITIALIZER(KEYPAD_KEYP, 4)
143 },
144 [2] = {
145 .name = "bci",
146 .module = TWL4030_MODULE_INTERRUPTS,
147 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
148 .set_cor = true,
149 .bits = 12,
150 .bytes_ixr = 2,
151 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
152 /* Note: most of these IRQs default to no-trigger */
153 .bytes_edr = 3,
154 .irq_lines = 2,
155 .mask = { {
156 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
157 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
158 }, {
159 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
160 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
161 }, },
162 },
163 [3] = {
164 .name = "madc",
165 SIH_INITIALIZER(MADC, 4)
166 },
167 [4] = {
168 /* USB doesn't use the same SIH organization */
169 .name = "usb",
170 },
171 [5] = {
172 .name = "power",
173 .set_cor = true,
174 SIH_INITIALIZER(INT_PWR, 8)
175 },
176 /* there are no SIH modules #6 or #7 ... */
177};
178
179static const struct sih sih_modules_twl5031[8] = {
180 [0] = {
181 .name = "gpio",
182 .module = TWL4030_MODULE_GPIO,
183 .control_offset = REG_GPIO_SIH_CTRL,
184 .set_cor = true,
185 .bits = TWL4030_GPIO_MAX,
186 .bytes_ixr = 3,
187 /* Note: *all* of these IRQs default to no-trigger */
188 .edr_offset = REG_GPIO_EDR1,
189 .bytes_edr = 5,
190 .irq_lines = 2,
191 .mask = { {
192 .isr_offset = REG_GPIO_ISR1A,
193 .imr_offset = REG_GPIO_IMR1A,
194 }, {
195 .isr_offset = REG_GPIO_ISR1B,
196 .imr_offset = REG_GPIO_IMR1B,
197 }, },
198 },
199 [1] = {
200 .name = "keypad",
201 .set_cor = true,
202 SIH_INITIALIZER(KEYPAD_KEYP, 4)
203 },
204 [2] = {
205 .name = "bci",
206 .module = TWL5031_MODULE_INTERRUPTS,
207 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
208 .bits = 7,
209 .bytes_ixr = 1,
210 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
211 /* Note: most of these IRQs default to no-trigger */
212 .bytes_edr = 2,
213 .irq_lines = 2,
214 .mask = { {
215 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
216 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
217 }, {
218 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
219 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
220 }, },
221 },
222 [3] = {
223 .name = "madc",
224 SIH_INITIALIZER(MADC, 4)
225 },
226 [4] = {
227 /* USB doesn't use the same SIH organization */
228 .name = "usb",
229 },
230 [5] = {
231 .name = "power",
232 .set_cor = true,
233 SIH_INITIALIZER(INT_PWR, 8)
234 },
235 [6] = {
236 /*
237 * ECI/DBI doesn't use the same SIH organization.
238 * For example, it supports only one interrupt output line.
239 * That is, the interrupts are seen on both INT1 and INT2 lines.
240 */
241 .name = "eci_dbi",
242 .module = TWL5031_MODULE_ACCESSORY,
243 .bits = 9,
244 .bytes_ixr = 2,
245 .irq_lines = 1,
246 .mask = { {
247 .isr_offset = TWL5031_ACIIDR_LSB,
248 .imr_offset = TWL5031_ACIIMR_LSB,
249 }, },
250
251 },
252 [7] = {
253 /* Audio accessory */
254 .name = "audio",
255 .module = TWL5031_MODULE_ACCESSORY,
256 .control_offset = TWL5031_ACCSIHCTRL,
257 .bits = 2,
258 .bytes_ixr = 1,
259 .edr_offset = TWL5031_ACCEDR1,
260 /* Note: most of these IRQs default to no-trigger */
261 .bytes_edr = 1,
262 .irq_lines = 2,
263 .mask = { {
264 .isr_offset = TWL5031_ACCISR1,
265 .imr_offset = TWL5031_ACCIMR1,
266 }, {
267 .isr_offset = TWL5031_ACCISR2,
268 .imr_offset = TWL5031_ACCIMR2,
269 }, },
270 },
271};
272
273#undef TWL4030_MODULE_KEYPAD_KEYP
274#undef TWL4030_MODULE_INT_PWR
275#undef TWL4030_INT_PWR_EDR
276
277/*----------------------------------------------------------------------*/
278
279static unsigned twl4030_irq_base;
280
281static struct completion irq_event;
282
283/*
284 * This thread processes interrupts reported by the Primary Interrupt Handler.
285 */
286static int twl4030_irq_thread(void *data)
287{
288 long irq = (long)data;
289 static unsigned i2c_errors;
290 static const unsigned max_i2c_errors = 100;
291
292
293 current->flags |= PF_NOFREEZE;
294
295 while (!kthread_should_stop()) {
296 int ret;
297 int module_irq;
298 u8 pih_isr;
299
300 /* Wait for IRQ, then read PIH irq status (also blocking) */
301 wait_for_completion_interruptible(&irq_event);
302
303 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
304 REG_PIH_ISR_P1);
305 if (ret) {
306 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
307 ret);
308 if (++i2c_errors >= max_i2c_errors) {
309 printk(KERN_ERR "Maximum I2C error count"
310 " exceeded. Terminating %s.\n",
311 __func__);
312 break;
313 }
314 complete(&irq_event);
315 continue;
316 }
317
318 /* these handlers deal with the relevant SIH irq status */
319 local_irq_disable();
320 for (module_irq = twl4030_irq_base;
321 pih_isr;
322 pih_isr >>= 1, module_irq++) {
323 if (pih_isr & 0x1)
324 generic_handle_irq(module_irq);
325 }
326 local_irq_enable();
327
328 enable_irq(irq);
329 }
330
331 return 0;
332}
333
334/*
335 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
336 * This is a chained interrupt, so there is no desc->action method for it.
337 * Now we need to query the interrupt controller in the twl4030 to determine
338 * which module is generating the interrupt request. However, we can't do i2c
339 * transactions in interrupt context, so we must defer that work to a kernel
340 * thread. All we do here is acknowledge and mask the interrupt and wakeup
341 * the kernel thread.
342 */
343static irqreturn_t handle_twl4030_pih(int irq, void *devid)
344{
345 /* Acknowledge, clear *AND* mask the interrupt... */
346 disable_irq_nosync(irq);
347 complete(devid);
348 return IRQ_HANDLED;
349}
350/*----------------------------------------------------------------------*/
351
352/*
353 * twl4030_init_sih_modules() ... start from a known state where no
354 * IRQs will be coming in, and where we can quickly enable them then
355 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
356 *
357 * NOTE: we don't touch EDR registers here; they stay with hardware
358 * defaults or whatever the last value was. Note that when both EDR
359 * bits for an IRQ are clear, that's as if its IMR bit is set...
360 */
361static int twl4030_init_sih_modules(unsigned line)
362{
363 const struct sih *sih;
364 u8 buf[4];
365 int i;
366 int status;
367
368 /* line 0 == int1_n signal; line 1 == int2_n signal */
369 if (line > 1)
370 return -EINVAL;
371
372 irq_line = line;
373
374 /* disable all interrupts on our line */
375 memset(buf, 0xff, sizeof buf);
376 sih = sih_modules;
377 for (i = 0; i < nr_sih_modules; i++, sih++) {
378
379 /* skip USB -- it's funky */
380 if (!sih->bytes_ixr)
381 continue;
382
383 /* Not all the SIH modules support multiple interrupt lines */
384 if (sih->irq_lines <= line)
385 continue;
386
387 status = twl_i2c_write(sih->module, buf,
388 sih->mask[line].imr_offset, sih->bytes_ixr);
389 if (status < 0)
390 pr_err("twl4030: err %d initializing %s %s\n",
391 status, sih->name, "IMR");
392
393 /* Maybe disable "exclusive" mode; buffer second pending irq;
394 * set Clear-On-Read (COR) bit.
395 *
396 * NOTE that sometimes COR polarity is documented as being
397 * inverted: for MADC, COR=1 means "clear on write".
398 * And for PWR_INT it's not documented...
399 */
400 if (sih->set_cor) {
401 status = twl_i2c_write_u8(sih->module,
402 TWL4030_SIH_CTRL_COR_MASK,
403 sih->control_offset);
404 if (status < 0)
405 pr_err("twl4030: err %d initializing %s %s\n",
406 status, sih->name, "SIH_CTRL");
407 }
408 }
409
410 sih = sih_modules;
411 for (i = 0; i < nr_sih_modules; i++, sih++) {
412 u8 rxbuf[4];
413 int j;
414
415 /* skip USB */
416 if (!sih->bytes_ixr)
417 continue;
418
419 /* Not all the SIH modules support multiple interrupt lines */
420 if (sih->irq_lines <= line)
421 continue;
422
423 /* Clear pending interrupt status. Either the read was
424 * enough, or we need to write those bits. Repeat, in
425 * case an IRQ is pending (PENDDIS=0) ... that's not
426 * uncommon with PWR_INT.PWRON.
427 */
428 for (j = 0; j < 2; j++) {
429 status = twl_i2c_read(sih->module, rxbuf,
430 sih->mask[line].isr_offset, sih->bytes_ixr);
431 if (status < 0)
432 pr_err("twl4030: err %d initializing %s %s\n",
433 status, sih->name, "ISR");
434
435 if (!sih->set_cor)
436 status = twl_i2c_write(sih->module, buf,
437 sih->mask[line].isr_offset,
438 sih->bytes_ixr);
439 /* else COR=1 means read sufficed.
440 * (for most SIH modules...)
441 */
442 }
443 }
444
445 return 0;
446}
447
448static inline void activate_irq(int irq)
449{
450#ifdef CONFIG_ARM
451 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
452 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
453 */
454 set_irq_flags(irq, IRQF_VALID);
455#else
456 /* same effect on other architectures */
457 irq_set_noprobe(irq);
458#endif
459}
460
461/*----------------------------------------------------------------------*/
462
463static DEFINE_SPINLOCK(sih_agent_lock);
464
465static struct workqueue_struct *wq;
466
467struct sih_agent {
468 int irq_base;
469 const struct sih *sih;
470
471 u32 imr;
472 bool imr_change_pending;
473 struct work_struct mask_work;
474
475 u32 edge_change;
476 struct work_struct edge_work;
477};
478
479static void twl4030_sih_do_mask(struct work_struct *work)
480{
481 struct sih_agent *agent;
482 const struct sih *sih;
483 union {
484 u8 bytes[4];
485 u32 word;
486 } imr;
487 int status;
488
489 agent = container_of(work, struct sih_agent, mask_work);
490
491 /* see what work we have */
492 spin_lock_irq(&sih_agent_lock);
493 if (agent->imr_change_pending) {
494 sih = agent->sih;
495 /* byte[0] gets overwritten as we write ... */
496 imr.word = cpu_to_le32(agent->imr << 8);
497 agent->imr_change_pending = false;
498 } else
499 sih = NULL;
500 spin_unlock_irq(&sih_agent_lock);
501 if (!sih)
502 return;
503
504 /* write the whole mask ... simpler than subsetting it */
505 status = twl_i2c_write(sih->module, imr.bytes,
506 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
507 if (status)
508 pr_err("twl4030: %s, %s --> %d\n", __func__,
509 "write", status);
510}
511
512static void twl4030_sih_do_edge(struct work_struct *work)
513{
514 struct sih_agent *agent;
515 const struct sih *sih;
516 u8 bytes[6];
517 u32 edge_change;
518 int status;
519
520 agent = container_of(work, struct sih_agent, edge_work);
521
522 /* see what work we have */
523 spin_lock_irq(&sih_agent_lock);
524 edge_change = agent->edge_change;
525 agent->edge_change = 0;
526 sih = edge_change ? agent->sih : NULL;
527 spin_unlock_irq(&sih_agent_lock);
528 if (!sih)
529 return;
530
531 /* Read, reserving first byte for write scratch. Yes, this
532 * could be cached for some speedup ... but be careful about
533 * any processor on the other IRQ line, EDR registers are
534 * shared.
535 */
536 status = twl_i2c_read(sih->module, bytes + 1,
537 sih->edr_offset, sih->bytes_edr);
538 if (status) {
539 pr_err("twl4030: %s, %s --> %d\n", __func__,
540 "read", status);
541 return;
542 }
543
544 /* Modify only the bits we know must change */
545 while (edge_change) {
546 int i = fls(edge_change) - 1;
547 struct irq_data *idata = irq_get_irq_data(i + agent->irq_base);
548 int byte = 1 + (i >> 2);
549 int off = (i & 0x3) * 2;
550 unsigned int type;
551
552 bytes[byte] &= ~(0x03 << off);
553
554 type = irqd_get_trigger_type(idata);
555 if (type & IRQ_TYPE_EDGE_RISING)
556 bytes[byte] |= BIT(off + 1);
557 if (type & IRQ_TYPE_EDGE_FALLING)
558 bytes[byte] |= BIT(off + 0);
559
560 edge_change &= ~BIT(i);
561 }
562
563 /* Write */
564 status = twl_i2c_write(sih->module, bytes,
565 sih->edr_offset, sih->bytes_edr);
566 if (status)
567 pr_err("twl4030: %s, %s --> %d\n", __func__,
568 "write", status);
569}
570
571/*----------------------------------------------------------------------*/
572
573/*
574 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
575 * which can't perform the underlying I2C operations (because they sleep).
576 * So we must hand them off to a thread (workqueue) and cope with asynch
577 * completion, potentially including some re-ordering, of these requests.
578 */
579
580static void twl4030_sih_mask(struct irq_data *data)
581{
582 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
583 unsigned long flags;
584
585 spin_lock_irqsave(&sih_agent_lock, flags);
586 sih->imr |= BIT(data->irq - sih->irq_base);
587 sih->imr_change_pending = true;
588 queue_work(wq, &sih->mask_work);
589 spin_unlock_irqrestore(&sih_agent_lock, flags);
590}
591
592static void twl4030_sih_unmask(struct irq_data *data)
593{
594 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
595 unsigned long flags;
596
597 spin_lock_irqsave(&sih_agent_lock, flags);
598 sih->imr &= ~BIT(data->irq - sih->irq_base);
599 sih->imr_change_pending = true;
600 queue_work(wq, &sih->mask_work);
601 spin_unlock_irqrestore(&sih_agent_lock, flags);
602}
603
604static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
605{
606 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
607 unsigned long flags;
608
609 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
610 return -EINVAL;
611
612 spin_lock_irqsave(&sih_agent_lock, flags);
613 if (irqd_get_trigger_type(data) != trigger) {
614 sih->edge_change |= BIT(data->irq - sih->irq_base);
615 queue_work(wq, &sih->edge_work);
616 }
617 spin_unlock_irqrestore(&sih_agent_lock, flags);
618 return 0;
619}
620
621static struct irq_chip twl4030_sih_irq_chip = {
622 .name = "twl4030",
623 .irq_mask = twl4030_sih_mask,
624 .irq_unmask = twl4030_sih_unmask,
625 .irq_set_type = twl4030_sih_set_type,
626};
627
628/*----------------------------------------------------------------------*/
629
630static inline int sih_read_isr(const struct sih *sih)
631{
632 int status;
633 union {
634 u8 bytes[4];
635 u32 word;
636 } isr;
637
638 /* FIXME need retry-on-error ... */
639
640 isr.word = 0;
641 status = twl_i2c_read(sih->module, isr.bytes,
642 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
643
644 return (status < 0) ? status : le32_to_cpu(isr.word);
645}
646
647/*
648 * Generic handler for SIH interrupts ... we "know" this is called
649 * in task context, with IRQs enabled.
650 */
651static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
652{
653 struct sih_agent *agent = irq_get_handler_data(irq);
654 const struct sih *sih = agent->sih;
655 int isr;
656
657 /* reading ISR acks the IRQs, using clear-on-read mode */
658 local_irq_enable();
659 isr = sih_read_isr(sih);
660 local_irq_disable();
661
662 if (isr < 0) {
663 pr_err("twl4030: %s SIH, read ISR error %d\n",
664 sih->name, isr);
665 /* REVISIT: recover; eventually mask it all, etc */
666 return;
667 }
668
669 while (isr) {
670 irq = fls(isr);
671 irq--;
672 isr &= ~BIT(irq);
673
674 if (irq < sih->bits)
675 generic_handle_irq(agent->irq_base + irq);
676 else
677 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
678 sih->name, irq);
679 }
680}
681
682static unsigned twl4030_irq_next;
683
684/* returns the first IRQ used by this SIH bank,
685 * or negative errno
686 */
687int twl4030_sih_setup(int module)
688{
689 int sih_mod;
690 const struct sih *sih = NULL;
691 struct sih_agent *agent;
692 int i, irq;
693 int status = -EINVAL;
694 unsigned irq_base = twl4030_irq_next;
695
696 /* only support modules with standard clear-on-read for now */
697 for (sih_mod = 0, sih = sih_modules;
698 sih_mod < nr_sih_modules;
699 sih_mod++, sih++) {
700 if (sih->module == module && sih->set_cor) {
701 if (!WARN((irq_base + sih->bits) > NR_IRQS,
702 "irq %d for %s too big\n",
703 irq_base + sih->bits,
704 sih->name))
705 status = 0;
706 break;
707 }
708 }
709 if (status < 0)
710 return status;
711
712 agent = kzalloc(sizeof *agent, GFP_KERNEL);
713 if (!agent)
714 return -ENOMEM;
715
716 status = 0;
717
718 agent->irq_base = irq_base;
719 agent->sih = sih;
720 agent->imr = ~0;
721 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
722 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
723
724 for (i = 0; i < sih->bits; i++) {
725 irq = irq_base + i;
726
727 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
728 handle_edge_irq);
729 irq_set_chip_data(irq, agent);
730 activate_irq(irq);
731 }
732
733 status = irq_base;
734 twl4030_irq_next += i;
735
736 /* replace generic PIH handler (handle_simple_irq) */
737 irq = sih_mod + twl4030_irq_base;
738 irq_set_handler_data(irq, agent);
739 irq_set_chained_handler(irq, handle_twl4030_sih);
740
741 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
742 irq, irq_base, twl4030_irq_next - 1);
743
744 return status;
745}
746
747/* FIXME need a call to reverse twl4030_sih_setup() ... */
748
749
750/*----------------------------------------------------------------------*/
751
752/* FIXME pass in which interrupt line we'll use ... */
753#define twl_irq_line 0
754
755int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
756{
757 static struct irq_chip twl4030_irq_chip;
758
759 int status;
760 int i;
761 struct task_struct *task;
762
763 /*
764 * Mask and clear all TWL4030 interrupts since initially we do
765 * not have any TWL4030 module interrupt handlers present
766 */
767 status = twl4030_init_sih_modules(twl_irq_line);
768 if (status < 0)
769 return status;
770
771 wq = create_singlethread_workqueue("twl4030-irqchip");
772 if (!wq) {
773 pr_err("twl4030: workqueue FAIL\n");
774 return -ESRCH;
775 }
776
777 twl4030_irq_base = irq_base;
778
779 /* install an irq handler for each of the SIH modules;
780 * clone dummy irq_chip since PIH can't *do* anything
781 */
782 twl4030_irq_chip = dummy_irq_chip;
783 twl4030_irq_chip.name = "twl4030";
784
785 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
786
787 for (i = irq_base; i < irq_end; i++) {
788 irq_set_chip_and_handler(i, &twl4030_irq_chip,
789 handle_simple_irq);
790 activate_irq(i);
791 }
792 twl4030_irq_next = i;
793 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
794 irq_num, irq_base, twl4030_irq_next - 1);
795
796 /* ... and the PWR_INT module ... */
797 status = twl4030_sih_setup(TWL4030_MODULE_INT);
798 if (status < 0) {
799 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
800 goto fail;
801 }
802
803 /* install an irq handler to demultiplex the TWL4030 interrupt */
804
805
806 init_completion(&irq_event);
807
808 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED,
809 "TWL4030-PIH", &irq_event);
810 if (status < 0) {
811 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
812 goto fail_rqirq;
813 }
814
815 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num,
816 "twl4030-irq");
817 if (IS_ERR(task)) {
818 pr_err("twl4030: could not create irq %d thread!\n", irq_num);
819 status = PTR_ERR(task);
820 goto fail_kthread;
821 }
822 return status;
823fail_kthread:
824 free_irq(irq_num, &irq_event);
825fail_rqirq:
826 /* clean up twl4030_sih_setup */
827fail:
828 for (i = irq_base; i < irq_end; i++)
829 irq_set_chip_and_handler(i, NULL, NULL);
830 destroy_workqueue(wq);
831 wq = NULL;
832 return status;
833}
834
835int twl4030_exit_irq(void)
836{
837 /* FIXME undo twl_init_irq() */
838 if (twl4030_irq_base) {
839 pr_err("twl4030: can't yet clean up IRQs?\n");
840 return -ENOSYS;
841 }
842 return 0;
843}
844
845int twl4030_init_chip_irq(const char *chip)
846{
847 if (!strcmp(chip, "twl5031")) {
848 sih_modules = sih_modules_twl5031;
849 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
850 } else {
851 sih_modules = sih_modules_twl4030;
852 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
853 }
854
855 return 0;
856}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 *
5 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 *
7 * Modifications to defer interrupt handling to a kernel thread:
8 * Copyright (C) 2006 MontaVista Software, Inc.
9 *
10 * Based on tlv320aic23.c:
11 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 *
13 * Code cleanup and modifications to IRQ handler.
14 * by syed khasim <x0khasim@ti.com>
15 */
16
17#include <linux/device.h>
18#include <linux/export.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/irqdomain.h>
24#include <linux/mfd/twl.h>
25
26#include "twl-core.h"
27
28/*
29 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
30 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
31 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
32 * SIH modules are more traditional IRQ components, which support per-IRQ
33 * enable/disable and trigger controls; they do most of the work.
34 *
35 * These chips are designed to support IRQ handling from two different
36 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
37 * and mask registers in the PIH and SIH modules.
38 *
39 * We set up IRQs starting at a platform-specified base, always starting
40 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
41 * base + 0 .. base + 7 PIH
42 * base + 8 .. base + 15 SIH for PWR_INT
43 * base + 16 .. base + 33 SIH for GPIO
44 */
45#define TWL4030_CORE_NR_IRQS 8
46#define TWL4030_PWR_NR_IRQS 8
47
48/* PIH register offsets */
49#define REG_PIH_ISR_P1 0x01
50#define REG_PIH_ISR_P2 0x02
51#define REG_PIH_SIR 0x03 /* for testing */
52
53/* Linux could (eventually) use either IRQ line */
54static int irq_line;
55
56struct sih {
57 char name[8];
58 u8 module; /* module id */
59 u8 control_offset; /* for SIH_CTRL */
60 bool set_cor;
61
62 u8 bits; /* valid in isr/imr */
63 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
64
65 u8 edr_offset;
66 u8 bytes_edr; /* bytelen of EDR */
67
68 u8 irq_lines; /* number of supported irq lines */
69
70 /* SIR ignored -- set interrupt, for testing only */
71 struct sih_irq_data {
72 u8 isr_offset;
73 u8 imr_offset;
74 } mask[2];
75 /* + 2 bytes padding */
76};
77
78static const struct sih *sih_modules;
79static int nr_sih_modules;
80
81#define SIH_INITIALIZER(modname, nbits) \
82 .module = TWL4030_MODULE_ ## modname, \
83 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
84 .bits = nbits, \
85 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
86 .edr_offset = TWL4030_ ## modname ## _EDR, \
87 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
88 .irq_lines = 2, \
89 .mask = { { \
90 .isr_offset = TWL4030_ ## modname ## _ISR1, \
91 .imr_offset = TWL4030_ ## modname ## _IMR1, \
92 }, \
93 { \
94 .isr_offset = TWL4030_ ## modname ## _ISR2, \
95 .imr_offset = TWL4030_ ## modname ## _IMR2, \
96 }, },
97
98/* register naming policies are inconsistent ... */
99#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
100#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
101#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
102
103
104/*
105 * Order in this table matches order in PIH_ISR. That is,
106 * BIT(n) in PIH_ISR is sih_modules[n].
107 */
108/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
109static const struct sih sih_modules_twl4030[6] = {
110 [0] = {
111 .name = "gpio",
112 .module = TWL4030_MODULE_GPIO,
113 .control_offset = REG_GPIO_SIH_CTRL,
114 .set_cor = true,
115 .bits = TWL4030_GPIO_MAX,
116 .bytes_ixr = 3,
117 /* Note: *all* of these IRQs default to no-trigger */
118 .edr_offset = REG_GPIO_EDR1,
119 .bytes_edr = 5,
120 .irq_lines = 2,
121 .mask = { {
122 .isr_offset = REG_GPIO_ISR1A,
123 .imr_offset = REG_GPIO_IMR1A,
124 }, {
125 .isr_offset = REG_GPIO_ISR1B,
126 .imr_offset = REG_GPIO_IMR1B,
127 }, },
128 },
129 [1] = {
130 .name = "keypad",
131 .set_cor = true,
132 SIH_INITIALIZER(KEYPAD_KEYP, 4)
133 },
134 [2] = {
135 .name = "bci",
136 .module = TWL4030_MODULE_INTERRUPTS,
137 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
138 .set_cor = true,
139 .bits = 12,
140 .bytes_ixr = 2,
141 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
142 /* Note: most of these IRQs default to no-trigger */
143 .bytes_edr = 3,
144 .irq_lines = 2,
145 .mask = { {
146 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
147 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
148 }, {
149 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
150 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
151 }, },
152 },
153 [3] = {
154 .name = "madc",
155 SIH_INITIALIZER(MADC, 4)
156 },
157 [4] = {
158 /* USB doesn't use the same SIH organization */
159 .name = "usb",
160 },
161 [5] = {
162 .name = "power",
163 .set_cor = true,
164 SIH_INITIALIZER(INT_PWR, 8)
165 },
166 /* there are no SIH modules #6 or #7 ... */
167};
168
169static const struct sih sih_modules_twl5031[8] = {
170 [0] = {
171 .name = "gpio",
172 .module = TWL4030_MODULE_GPIO,
173 .control_offset = REG_GPIO_SIH_CTRL,
174 .set_cor = true,
175 .bits = TWL4030_GPIO_MAX,
176 .bytes_ixr = 3,
177 /* Note: *all* of these IRQs default to no-trigger */
178 .edr_offset = REG_GPIO_EDR1,
179 .bytes_edr = 5,
180 .irq_lines = 2,
181 .mask = { {
182 .isr_offset = REG_GPIO_ISR1A,
183 .imr_offset = REG_GPIO_IMR1A,
184 }, {
185 .isr_offset = REG_GPIO_ISR1B,
186 .imr_offset = REG_GPIO_IMR1B,
187 }, },
188 },
189 [1] = {
190 .name = "keypad",
191 .set_cor = true,
192 SIH_INITIALIZER(KEYPAD_KEYP, 4)
193 },
194 [2] = {
195 .name = "bci",
196 .module = TWL5031_MODULE_INTERRUPTS,
197 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
198 .bits = 7,
199 .bytes_ixr = 1,
200 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
201 /* Note: most of these IRQs default to no-trigger */
202 .bytes_edr = 2,
203 .irq_lines = 2,
204 .mask = { {
205 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
206 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
207 }, {
208 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
209 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
210 }, },
211 },
212 [3] = {
213 .name = "madc",
214 SIH_INITIALIZER(MADC, 4)
215 },
216 [4] = {
217 /* USB doesn't use the same SIH organization */
218 .name = "usb",
219 },
220 [5] = {
221 .name = "power",
222 .set_cor = true,
223 SIH_INITIALIZER(INT_PWR, 8)
224 },
225 [6] = {
226 /*
227 * ECI/DBI doesn't use the same SIH organization.
228 * For example, it supports only one interrupt output line.
229 * That is, the interrupts are seen on both INT1 and INT2 lines.
230 */
231 .name = "eci_dbi",
232 .module = TWL5031_MODULE_ACCESSORY,
233 .bits = 9,
234 .bytes_ixr = 2,
235 .irq_lines = 1,
236 .mask = { {
237 .isr_offset = TWL5031_ACIIDR_LSB,
238 .imr_offset = TWL5031_ACIIMR_LSB,
239 }, },
240
241 },
242 [7] = {
243 /* Audio accessory */
244 .name = "audio",
245 .module = TWL5031_MODULE_ACCESSORY,
246 .control_offset = TWL5031_ACCSIHCTRL,
247 .bits = 2,
248 .bytes_ixr = 1,
249 .edr_offset = TWL5031_ACCEDR1,
250 /* Note: most of these IRQs default to no-trigger */
251 .bytes_edr = 1,
252 .irq_lines = 2,
253 .mask = { {
254 .isr_offset = TWL5031_ACCISR1,
255 .imr_offset = TWL5031_ACCIMR1,
256 }, {
257 .isr_offset = TWL5031_ACCISR2,
258 .imr_offset = TWL5031_ACCIMR2,
259 }, },
260 },
261};
262
263#undef TWL4030_MODULE_KEYPAD_KEYP
264#undef TWL4030_MODULE_INT_PWR
265#undef TWL4030_INT_PWR_EDR
266
267/*----------------------------------------------------------------------*/
268
269static unsigned twl4030_irq_base;
270
271/*
272 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
273 * This is a chained interrupt, so there is no desc->action method for it.
274 * Now we need to query the interrupt controller in the twl4030 to determine
275 * which module is generating the interrupt request. However, we can't do i2c
276 * transactions in interrupt context, so we must defer that work to a kernel
277 * thread. All we do here is acknowledge and mask the interrupt and wakeup
278 * the kernel thread.
279 */
280static irqreturn_t handle_twl4030_pih(int irq, void *devid)
281{
282 irqreturn_t ret;
283 u8 pih_isr;
284
285 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
286 REG_PIH_ISR_P1);
287 if (ret) {
288 pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
289 return IRQ_NONE;
290 }
291
292 while (pih_isr) {
293 unsigned long pending = __ffs(pih_isr);
294 unsigned int irq;
295
296 pih_isr &= ~BIT(pending);
297 irq = pending + twl4030_irq_base;
298 handle_nested_irq(irq);
299 }
300
301 return IRQ_HANDLED;
302}
303
304/*----------------------------------------------------------------------*/
305
306/*
307 * twl4030_init_sih_modules() ... start from a known state where no
308 * IRQs will be coming in, and where we can quickly enable them then
309 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
310 *
311 * NOTE: we don't touch EDR registers here; they stay with hardware
312 * defaults or whatever the last value was. Note that when both EDR
313 * bits for an IRQ are clear, that's as if its IMR bit is set...
314 */
315static int twl4030_init_sih_modules(unsigned line)
316{
317 const struct sih *sih;
318 u8 buf[4];
319 int i;
320 int status;
321
322 /* line 0 == int1_n signal; line 1 == int2_n signal */
323 if (line > 1)
324 return -EINVAL;
325
326 irq_line = line;
327
328 /* disable all interrupts on our line */
329 memset(buf, 0xff, sizeof(buf));
330 sih = sih_modules;
331 for (i = 0; i < nr_sih_modules; i++, sih++) {
332 /* skip USB -- it's funky */
333 if (!sih->bytes_ixr)
334 continue;
335
336 /* Not all the SIH modules support multiple interrupt lines */
337 if (sih->irq_lines <= line)
338 continue;
339
340 status = twl_i2c_write(sih->module, buf,
341 sih->mask[line].imr_offset, sih->bytes_ixr);
342 if (status < 0)
343 pr_err("twl4030: err %d initializing %s %s\n",
344 status, sih->name, "IMR");
345
346 /*
347 * Maybe disable "exclusive" mode; buffer second pending irq;
348 * set Clear-On-Read (COR) bit.
349 *
350 * NOTE that sometimes COR polarity is documented as being
351 * inverted: for MADC, COR=1 means "clear on write".
352 * And for PWR_INT it's not documented...
353 */
354 if (sih->set_cor) {
355 status = twl_i2c_write_u8(sih->module,
356 TWL4030_SIH_CTRL_COR_MASK,
357 sih->control_offset);
358 if (status < 0)
359 pr_err("twl4030: err %d initializing %s %s\n",
360 status, sih->name, "SIH_CTRL");
361 }
362 }
363
364 sih = sih_modules;
365 for (i = 0; i < nr_sih_modules; i++, sih++) {
366 u8 rxbuf[4];
367 int j;
368
369 /* skip USB */
370 if (!sih->bytes_ixr)
371 continue;
372
373 /* Not all the SIH modules support multiple interrupt lines */
374 if (sih->irq_lines <= line)
375 continue;
376
377 /*
378 * Clear pending interrupt status. Either the read was
379 * enough, or we need to write those bits. Repeat, in
380 * case an IRQ is pending (PENDDIS=0) ... that's not
381 * uncommon with PWR_INT.PWRON.
382 */
383 for (j = 0; j < 2; j++) {
384 status = twl_i2c_read(sih->module, rxbuf,
385 sih->mask[line].isr_offset, sih->bytes_ixr);
386 if (status < 0)
387 pr_warn("twl4030: err %d initializing %s %s\n",
388 status, sih->name, "ISR");
389
390 if (!sih->set_cor) {
391 status = twl_i2c_write(sih->module, buf,
392 sih->mask[line].isr_offset,
393 sih->bytes_ixr);
394 if (status < 0)
395 pr_warn("twl4030: write failed: %d\n",
396 status);
397 }
398 /*
399 * else COR=1 means read sufficed.
400 * (for most SIH modules...)
401 */
402 }
403 }
404
405 return 0;
406}
407
408static inline void activate_irq(int irq)
409{
410 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
411}
412
413/*----------------------------------------------------------------------*/
414
415struct sih_agent {
416 int irq_base;
417 const struct sih *sih;
418
419 u32 imr;
420 bool imr_change_pending;
421
422 u32 edge_change;
423
424 struct mutex irq_lock;
425 char *irq_name;
426};
427
428/*----------------------------------------------------------------------*/
429
430/*
431 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
432 * which can't perform the underlying I2C operations (because they sleep).
433 * So we must hand them off to a thread (workqueue) and cope with asynch
434 * completion, potentially including some re-ordering, of these requests.
435 */
436
437static void twl4030_sih_mask(struct irq_data *data)
438{
439 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
440
441 agent->imr |= BIT(data->irq - agent->irq_base);
442 agent->imr_change_pending = true;
443}
444
445static void twl4030_sih_unmask(struct irq_data *data)
446{
447 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
448
449 agent->imr &= ~BIT(data->irq - agent->irq_base);
450 agent->imr_change_pending = true;
451}
452
453static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
454{
455 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
456
457 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
458 return -EINVAL;
459
460 if (irqd_get_trigger_type(data) != trigger)
461 agent->edge_change |= BIT(data->irq - agent->irq_base);
462
463 return 0;
464}
465
466static void twl4030_sih_bus_lock(struct irq_data *data)
467{
468 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
469
470 mutex_lock(&agent->irq_lock);
471}
472
473static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
474{
475 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
476 const struct sih *sih = agent->sih;
477 int status;
478
479 if (agent->imr_change_pending) {
480 union {
481 __le32 word;
482 u8 bytes[4];
483 } imr;
484
485 /* byte[0] gets overwritten as we write ... */
486 imr.word = cpu_to_le32(agent->imr);
487 agent->imr_change_pending = false;
488
489 /* write the whole mask ... simpler than subsetting it */
490 status = twl_i2c_write(sih->module, imr.bytes,
491 sih->mask[irq_line].imr_offset,
492 sih->bytes_ixr);
493 if (status)
494 pr_err("twl4030: %s, %s --> %d\n", __func__,
495 "write", status);
496 }
497
498 if (agent->edge_change) {
499 u32 edge_change;
500 u8 bytes[6];
501
502 edge_change = agent->edge_change;
503 agent->edge_change = 0;
504
505 /*
506 * Read, reserving first byte for write scratch. Yes, this
507 * could be cached for some speedup ... but be careful about
508 * any processor on the other IRQ line, EDR registers are
509 * shared.
510 */
511 status = twl_i2c_read(sih->module, bytes,
512 sih->edr_offset, sih->bytes_edr);
513 if (status) {
514 pr_err("twl4030: %s, %s --> %d\n", __func__,
515 "read", status);
516 return;
517 }
518
519 /* Modify only the bits we know must change */
520 while (edge_change) {
521 int i = fls(edge_change) - 1;
522 int byte = i >> 2;
523 int off = (i & 0x3) * 2;
524 unsigned int type;
525
526 bytes[byte] &= ~(0x03 << off);
527
528 type = irq_get_trigger_type(i + agent->irq_base);
529 if (type & IRQ_TYPE_EDGE_RISING)
530 bytes[byte] |= BIT(off + 1);
531 if (type & IRQ_TYPE_EDGE_FALLING)
532 bytes[byte] |= BIT(off + 0);
533
534 edge_change &= ~BIT(i);
535 }
536
537 /* Write */
538 status = twl_i2c_write(sih->module, bytes,
539 sih->edr_offset, sih->bytes_edr);
540 if (status)
541 pr_err("twl4030: %s, %s --> %d\n", __func__,
542 "write", status);
543 }
544
545 mutex_unlock(&agent->irq_lock);
546}
547
548static struct irq_chip twl4030_sih_irq_chip = {
549 .name = "twl4030",
550 .irq_mask = twl4030_sih_mask,
551 .irq_unmask = twl4030_sih_unmask,
552 .irq_set_type = twl4030_sih_set_type,
553 .irq_bus_lock = twl4030_sih_bus_lock,
554 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
555 .flags = IRQCHIP_SKIP_SET_WAKE,
556};
557
558/*----------------------------------------------------------------------*/
559
560static inline int sih_read_isr(const struct sih *sih)
561{
562 int status;
563 union {
564 u8 bytes[4];
565 __le32 word;
566 } isr;
567
568 /* FIXME need retry-on-error ... */
569
570 isr.word = 0;
571 status = twl_i2c_read(sih->module, isr.bytes,
572 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
573
574 return (status < 0) ? status : le32_to_cpu(isr.word);
575}
576
577/*
578 * Generic handler for SIH interrupts ... we "know" this is called
579 * in task context, with IRQs enabled.
580 */
581static irqreturn_t handle_twl4030_sih(int irq, void *data)
582{
583 struct sih_agent *agent = irq_get_handler_data(irq);
584 const struct sih *sih = agent->sih;
585 int isr;
586
587 /* reading ISR acks the IRQs, using clear-on-read mode */
588 isr = sih_read_isr(sih);
589
590 if (isr < 0) {
591 pr_err("twl4030: %s SIH, read ISR error %d\n",
592 sih->name, isr);
593 /* REVISIT: recover; eventually mask it all, etc */
594 return IRQ_HANDLED;
595 }
596
597 while (isr) {
598 irq = fls(isr);
599 irq--;
600 isr &= ~BIT(irq);
601
602 if (irq < sih->bits)
603 handle_nested_irq(agent->irq_base + irq);
604 else
605 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
606 sih->name, irq);
607 }
608 return IRQ_HANDLED;
609}
610
611/* returns the first IRQ used by this SIH bank, or negative errno */
612int twl4030_sih_setup(struct device *dev, int module, int irq_base)
613{
614 int sih_mod;
615 const struct sih *sih = NULL;
616 struct sih_agent *agent;
617 int i, irq;
618 int status = -EINVAL;
619
620 /* only support modules with standard clear-on-read for now */
621 for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
622 sih_mod++, sih++) {
623 if (sih->module == module && sih->set_cor) {
624 status = 0;
625 break;
626 }
627 }
628
629 if (status < 0) {
630 dev_err(dev, "module to setup SIH for not found\n");
631 return status;
632 }
633
634 agent = kzalloc(sizeof(*agent), GFP_KERNEL);
635 if (!agent)
636 return -ENOMEM;
637
638 agent->irq_base = irq_base;
639 agent->sih = sih;
640 agent->imr = ~0;
641 mutex_init(&agent->irq_lock);
642
643 for (i = 0; i < sih->bits; i++) {
644 irq = irq_base + i;
645
646 irq_set_chip_data(irq, agent);
647 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
648 handle_edge_irq);
649 irq_set_nested_thread(irq, 1);
650 activate_irq(irq);
651 }
652
653 /* replace generic PIH handler (handle_simple_irq) */
654 irq = sih_mod + twl4030_irq_base;
655 irq_set_handler_data(irq, agent);
656 agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
657 status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
658 IRQF_EARLY_RESUME | IRQF_ONESHOT,
659 agent->irq_name ?: sih->name, NULL);
660
661 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
662 irq, irq_base, irq_base + i - 1);
663
664 return status < 0 ? status : irq_base;
665}
666
667/* FIXME need a call to reverse twl4030_sih_setup() ... */
668
669/*----------------------------------------------------------------------*/
670
671/* FIXME pass in which interrupt line we'll use ... */
672#define twl_irq_line 0
673
674int twl4030_init_irq(struct device *dev, int irq_num)
675{
676 static struct irq_chip twl4030_irq_chip;
677 int status, i;
678 int irq_base, irq_end, nr_irqs;
679 struct device_node *node = dev->of_node;
680
681 /*
682 * TWL core and pwr interrupts must be contiguous because
683 * the hwirqs numbers are defined contiguously from 1 to 15.
684 * Create only one domain for both.
685 */
686 nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
687
688 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
689 if (irq_base < 0) {
690 dev_err(dev, "Fail to allocate IRQ descs\n");
691 return irq_base;
692 }
693
694 irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
695 &irq_domain_simple_ops, NULL);
696
697 irq_end = irq_base + TWL4030_CORE_NR_IRQS;
698
699 /*
700 * Mask and clear all TWL4030 interrupts since initially we do
701 * not have any TWL4030 module interrupt handlers present
702 */
703 status = twl4030_init_sih_modules(twl_irq_line);
704 if (status < 0)
705 return status;
706
707 twl4030_irq_base = irq_base;
708
709 /*
710 * Install an irq handler for each of the SIH modules;
711 * clone dummy irq_chip since PIH can't *do* anything
712 */
713 twl4030_irq_chip = dummy_irq_chip;
714 twl4030_irq_chip.name = "twl4030";
715
716 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
717
718 for (i = irq_base; i < irq_end; i++) {
719 irq_set_chip_and_handler(i, &twl4030_irq_chip,
720 handle_simple_irq);
721 irq_set_nested_thread(i, 1);
722 activate_irq(i);
723 }
724
725 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
726 irq_num, irq_base, irq_end);
727
728 /* ... and the PWR_INT module ... */
729 status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
730 if (status < 0) {
731 dev_err(dev, "sih_setup PWR INT --> %d\n", status);
732 goto fail;
733 }
734
735 /* install an irq handler to demultiplex the TWL4030 interrupt */
736 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
737 IRQF_ONESHOT,
738 "TWL4030-PIH", NULL);
739 if (status < 0) {
740 dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
741 goto fail_rqirq;
742 }
743 enable_irq_wake(irq_num);
744
745 return irq_base;
746fail_rqirq:
747 /* clean up twl4030_sih_setup */
748fail:
749 for (i = irq_base; i < irq_end; i++) {
750 irq_set_nested_thread(i, 0);
751 irq_set_chip_and_handler(i, NULL, NULL);
752 }
753
754 return status;
755}
756
757void twl4030_exit_irq(void)
758{
759 /* FIXME undo twl_init_irq() */
760 if (twl4030_irq_base)
761 pr_err("twl4030: can't yet clean up IRQs?\n");
762}
763
764int twl4030_init_chip_irq(const char *chip)
765{
766 if (!strcmp(chip, "twl5031")) {
767 sih_modules = sih_modules_twl5031;
768 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
769 } else {
770 sih_modules = sih_modules_twl4030;
771 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
772 }
773
774 return 0;
775}