1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4 */
  5
  6#include <linux/bitfield.h>
  7#include <linux/irq.h>
  8#include <linux/irqchip.h>
  9#include <linux/irqchip/chained_irq.h>
 10#include <linux/irqdomain.h>
 11#include <linux/module.h>
 12#include <linux/of.h>
 13#include <linux/of_address.h>
 14#include <linux/of_irq.h>
 15
 16/* FIC Registers */
 17#define AL_FIC_CAUSE		0x00
 18#define AL_FIC_SET_CAUSE	0x08
 19#define AL_FIC_MASK		0x10
 20#define AL_FIC_CONTROL		0x28
 21
 22#define CONTROL_TRIGGER_RISING	BIT(3)
 23#define CONTROL_MASK_MSI_X	BIT(5)
 24
 25#define NR_FIC_IRQS 32
 26
 27MODULE_AUTHOR("Talel Shenhar");
 28MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
 29
 30enum al_fic_state {
 31	AL_FIC_UNCONFIGURED = 0,
 32	AL_FIC_CONFIGURED_LEVEL,
 33	AL_FIC_CONFIGURED_RISING_EDGE,
 34};
 35
 36struct al_fic {
 37	void __iomem *base;
 38	struct irq_domain *domain;
 39	const char *name;
 40	unsigned int parent_irq;
 41	enum al_fic_state state;
 42};
 43
 44static void al_fic_set_trigger(struct al_fic *fic,
 45			       struct irq_chip_generic *gc,
 46			       enum al_fic_state new_state)
 47{
 48	irq_flow_handler_t handler;
 49	u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
 50
 51	if (new_state == AL_FIC_CONFIGURED_LEVEL) {
 52		handler = handle_level_irq;
 53		control &= ~CONTROL_TRIGGER_RISING;
 54	} else {
 55		handler = handle_edge_irq;
 56		control |= CONTROL_TRIGGER_RISING;
 57	}
 58	gc->chip_types->handler = handler;
 59	fic->state = new_state;
 60	writel_relaxed(control, fic->base + AL_FIC_CONTROL);
 61}
 62
 63static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
 64{
 65	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
 66	struct al_fic *fic = gc->private;
 67	enum al_fic_state new_state;
 68	int ret = 0;
 69
 70	irq_gc_lock(gc);
 71
 72	if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
 73	    ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
 74		pr_debug("fic doesn't support flow type %d\n", flow_type);
 75		ret = -EINVAL;
 76		goto err;
 77	}
 78
 79	new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
 80		AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
 81
 82	/*
 83	 * A given FIC instance can be either all level or all edge triggered.
 84	 * This is generally fixed depending on what pieces of HW it's wired up
 85	 * to.
 86	 *
 87	 * We configure it based on the sensitivity of the first source
 88	 * being setup, and reject any subsequent attempt at configuring it in a
 89	 * different way.
 90	 */
 91	if (fic->state == AL_FIC_UNCONFIGURED) {
 92		al_fic_set_trigger(fic, gc, new_state);
 93	} else if (fic->state != new_state) {
 94		pr_debug("fic %s state already configured to %d\n",
 95			 fic->name, fic->state);
 96		ret = -EINVAL;
 97		goto err;
 98	}
 99
100err:
101	irq_gc_unlock(gc);
102
103	return ret;
104}
105
106static void al_fic_irq_handler(struct irq_desc *desc)
107{
108	struct al_fic *fic = irq_desc_get_handler_data(desc);
109	struct irq_domain *domain = fic->domain;
110	struct irq_chip *irqchip = irq_desc_get_chip(desc);
111	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
112	unsigned long pending;
113	u32 hwirq;
114
115	chained_irq_enter(irqchip, desc);
116
117	pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
118	pending &= ~gc->mask_cache;
119
120	for_each_set_bit(hwirq, &pending, NR_FIC_IRQS)
121		generic_handle_domain_irq(domain, hwirq);
122
123	chained_irq_exit(irqchip, desc);
124}
125
126static int al_fic_irq_retrigger(struct irq_data *data)
127{
128	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
129	struct al_fic *fic = gc->private;
130
131	writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
132
133	return 1;
134}
135
136static int al_fic_register(struct device_node *node,
137			   struct al_fic *fic)
138{
139	struct irq_chip_generic *gc;
140	int ret;
141
142	fic->domain = irq_domain_add_linear(node,
143					    NR_FIC_IRQS,
144					    &irq_generic_chip_ops,
145					    fic);
146	if (!fic->domain) {
147		pr_err("fail to add irq domain\n");
148		return -ENOMEM;
149	}
150
151	ret = irq_alloc_domain_generic_chips(fic->domain,
152					     NR_FIC_IRQS,
153					     1, fic->name,
154					     handle_level_irq,
155					     0, 0, IRQ_GC_INIT_MASK_CACHE);
156	if (ret) {
157		pr_err("fail to allocate generic chip (%d)\n", ret);
158		goto err_domain_remove;
159	}
160
161	gc = irq_get_domain_generic_chip(fic->domain, 0);
162	gc->reg_base = fic->base;
163	gc->chip_types->regs.mask = AL_FIC_MASK;
164	gc->chip_types->regs.ack = AL_FIC_CAUSE;
165	gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
166	gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
167	gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
168	gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
169	gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
170	gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
171	gc->private = fic;
172
173	irq_set_chained_handler_and_data(fic->parent_irq,
174					 al_fic_irq_handler,
175					 fic);
176	return 0;
177
178err_domain_remove:
179	irq_domain_remove(fic->domain);
180
181	return ret;
182}
183
184/*
185 * al_fic_wire_init() - initialize and configure fic in wire mode
186 * @of_node: optional pointer to interrupt controller's device tree node.
187 * @base: mmio to fic register
188 * @name: name of the fic
189 * @parent_irq: interrupt of parent
190 *
191 * This API will configure the fic hardware to to work in wire mode.
192 * In wire mode, fic hardware is generating a wire ("wired") interrupt.
193 * Interrupt can be generated based on positive edge or level - configuration is
194 * to be determined based on connected hardware to this fic.
195 */
196static struct al_fic *al_fic_wire_init(struct device_node *node,
197				       void __iomem *base,
198				       const char *name,
199				       unsigned int parent_irq)
200{
201	struct al_fic *fic;
202	int ret;
203	u32 control = CONTROL_MASK_MSI_X;
204
205	fic = kzalloc(sizeof(*fic), GFP_KERNEL);
206	if (!fic)
207		return ERR_PTR(-ENOMEM);
208
209	fic->base = base;
210	fic->parent_irq = parent_irq;
211	fic->name = name;
212
213	/* mask out all interrupts */
214	writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
215
216	/* clear any pending interrupt */
217	writel_relaxed(0, fic->base + AL_FIC_CAUSE);
218
219	writel_relaxed(control, fic->base + AL_FIC_CONTROL);
220
221	ret = al_fic_register(node, fic);
222	if (ret) {
223		pr_err("fail to register irqchip\n");
224		goto err_free;
225	}
226
227	pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
228		 fic->name, parent_irq);
229
230	return fic;
231
232err_free:
233	kfree(fic);
234	return ERR_PTR(ret);
235}
236
237static int __init al_fic_init_dt(struct device_node *node,
238				 struct device_node *parent)
239{
240	int ret;
241	void __iomem *base;
242	unsigned int parent_irq;
243	struct al_fic *fic;
244
245	if (!parent) {
246		pr_err("%s: unsupported - device require a parent\n",
247		       node->name);
248		return -EINVAL;
249	}
250
251	base = of_iomap(node, 0);
252	if (!base) {
253		pr_err("%s: fail to map memory\n", node->name);
254		return -ENOMEM;
255	}
256
257	parent_irq = irq_of_parse_and_map(node, 0);
258	if (!parent_irq) {
259		pr_err("%s: fail to map irq\n", node->name);
260		ret = -EINVAL;
261		goto err_unmap;
262	}
263
264	fic = al_fic_wire_init(node,
265			       base,
266			       node->name,
267			       parent_irq);
268	if (IS_ERR(fic)) {
269		pr_err("%s: fail to initialize irqchip (%lu)\n",
270		       node->name,
271		       PTR_ERR(fic));
272		ret = PTR_ERR(fic);
273		goto err_irq_dispose;
274	}
275
276	return 0;
277
278err_irq_dispose:
279	irq_dispose_mapping(parent_irq);
280err_unmap:
281	iounmap(base);
282
283	return ret;
284}
285
286IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);