1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef _CORESIGHT_PRIV_H
  7#define _CORESIGHT_PRIV_H
  8
  9#include <linux/amba/bus.h>
 10#include <linux/bitops.h>
 11#include <linux/io.h>
 12#include <linux/coresight.h>
 13#include <linux/pm_runtime.h>
 14
 15extern struct mutex coresight_mutex;
 16extern const struct device_type coresight_dev_type[];
 17
 18/*
 19 * Coresight management registers (0xf00-0xfcc)
 20 * 0xfa0 - 0xfa4: Management	registers in PFTv1.0
 21 *		  Trace		registers in PFTv1.1
 22 */
 23#define CORESIGHT_ITCTRL	0xf00
 24#define CORESIGHT_CLAIMSET	0xfa0
 25#define CORESIGHT_CLAIMCLR	0xfa4
 26#define CORESIGHT_LAR		0xfb0
 27#define CORESIGHT_LSR		0xfb4
 28#define CORESIGHT_DEVARCH	0xfbc
 29#define CORESIGHT_AUTHSTATUS	0xfb8
 30#define CORESIGHT_DEVID		0xfc8
 31#define CORESIGHT_DEVTYPE	0xfcc
 32
 33
 34/*
 35 * Coresight device CLAIM protocol.
 36 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
 37 */
 38#define CORESIGHT_CLAIM_SELF_HOSTED	BIT(1)
 39
 40#define TIMEOUT_US		100
 41#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
 42
 43#define ETM_MODE_EXCL_KERN	BIT(30)
 44#define ETM_MODE_EXCL_USER	BIT(31)
 45struct cs_pair_attribute {
 46	struct device_attribute attr;
 47	u32 lo_off;
 48	u32 hi_off;
 49};
 50
 51struct cs_off_attribute {
 52	struct device_attribute attr;
 53	u32 off;
 54};
 55
 56extern ssize_t coresight_simple_show32(struct device *_dev,
 57				     struct device_attribute *attr, char *buf);
 58extern ssize_t coresight_simple_show_pair(struct device *_dev,
 59				     struct device_attribute *attr, char *buf);
 60
 61#define coresight_simple_reg32(name, offset)				\
 62	(&((struct cs_off_attribute[]) {				\
 63	   {								\
 64		__ATTR(name, 0444, coresight_simple_show32, NULL),	\
 65		offset							\
 66	   }								\
 67	})[0].attr.attr)
 68
 69#define coresight_simple_reg64(name, lo_off, hi_off)			\
 70	(&((struct cs_pair_attribute[]) {				\
 71	   {								\
 72		__ATTR(name, 0444, coresight_simple_show_pair, NULL),	\
 73		lo_off, hi_off						\
 74	   }								\
 75	})[0].attr.attr)
 76
 77extern const u32 coresight_barrier_pkt[4];
 78#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
 79
 80enum etm_addr_type {
 81	ETM_ADDR_TYPE_NONE,
 82	ETM_ADDR_TYPE_SINGLE,
 83	ETM_ADDR_TYPE_RANGE,
 84	ETM_ADDR_TYPE_START,
 85	ETM_ADDR_TYPE_STOP,
 86};
 87
 88/**
 89 * struct cs_buffer - keep track of a recording session' specifics
 90 * @cur:	index of the current buffer
 91 * @nr_pages:	max number of pages granted to us
 92 * @pid:	PID this cs_buffer belongs to
 93 * @offset:	offset within the current buffer
 94 * @data_size:	how much we collected in this run
 95 * @snapshot:	is this run in snapshot mode
 96 * @data_pages:	a handle the ring buffer
 97 */
 98struct cs_buffers {
 99	unsigned int		cur;
100	unsigned int		nr_pages;
101	pid_t			pid;
102	unsigned long		offset;
103	local_t			data_size;
104	bool			snapshot;
105	void			**data_pages;
106};
107
108static inline void coresight_insert_barrier_packet(void *buf)
109{
110	if (buf)
111		memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
112}
113
114static inline void CS_LOCK(void __iomem *addr)
115{
116	do {
117		/* Wait for things to settle */
118		mb();
119		writel_relaxed(0x0, addr + CORESIGHT_LAR);
120	} while (0);
121}
122
123static inline void CS_UNLOCK(void __iomem *addr)
124{
125	do {
126		writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
127		/* Make sure everyone has seen this */
128		mb();
129	} while (0);
130}
131
132void coresight_disable_path(struct list_head *path);
133int coresight_enable_path(struct list_head *path, enum cs_mode mode,
134			  void *sink_data);
135struct coresight_device *coresight_get_sink(struct list_head *path);
136struct coresight_device *coresight_get_sink_by_id(u32 id);
137struct coresight_device *
138coresight_find_default_sink(struct coresight_device *csdev);
139struct list_head *coresight_build_path(struct coresight_device *csdev,
140				       struct coresight_device *sink);
141void coresight_release_path(struct list_head *path);
142int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
143void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
144int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
145void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
146int coresight_make_links(struct coresight_device *orig,
147			 struct coresight_connection *conn,
148			 struct coresight_device *target);
149void coresight_remove_links(struct coresight_device *orig,
150			    struct coresight_connection *conn);
151u32 coresight_get_sink_id(struct coresight_device *csdev);
152
153#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
154extern int etm_readl_cp14(u32 off, unsigned int *val);
155extern int etm_writel_cp14(u32 off, u32 val);
156#else
157static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
158static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
159#endif
160
161struct cti_assoc_op {
162	void (*add)(struct coresight_device *csdev);
163	void (*remove)(struct coresight_device *csdev);
164};
165
166extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
167extern void coresight_remove_cti_ops(void);
168
169/*
170 * Macros and inline functions to handle CoreSight UCI data and driver
171 * private data in AMBA ID table entries, and extract data values.
172 */
173
174/* coresight AMBA ID, no UCI, no driver data: id table entry */
175#define CS_AMBA_ID(pid)			\
176	{				\
177		.id	= pid,		\
178		.mask	= 0x000fffff,	\
179	}
180
181/* coresight AMBA ID, UCI with driver data only: id table entry. */
182#define CS_AMBA_ID_DATA(pid, dval)				\
183	{							\
184		.id	= pid,					\
185		.mask	= 0x000fffff,				\
186		.data	=  (void *)&(struct amba_cs_uci_id)	\
187			{				\
188				.data = (void *)dval,	\
189			}				\
190	}
191
192/* coresight AMBA ID, full UCI structure: id table entry. */
193#define __CS_AMBA_UCI_ID(pid, m, uci_ptr)	\
194	{					\
195		.id	= pid,			\
196		.mask	= m,			\
197		.data	= (void *)uci_ptr	\
198	}
199#define CS_AMBA_UCI_ID(pid, uci)	__CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
200/*
201 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
202 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
203 * as a match value for blanket matching all devices in the given CoreSight
204 * device type and architecture.
205 */
206#define PIDR2_JEDEC			BIT(3)
207#define PID_PIDR2_JEDEC			(PIDR2_JEDEC << 16)
208/*
209 * Match all PIDs in a given CoreSight device type and architecture, defined
210 * by the uci.
211 */
212#define CS_AMBA_MATCH_ALL_UCI(uci)					\
213	__CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
214
215/* extract the data value from a UCI structure given amba_id pointer. */
216static inline void *coresight_get_uci_data(const struct amba_id *id)
217{
218	struct amba_cs_uci_id *uci_id = id->data;
219
220	if (!uci_id)
221		return NULL;
222
223	return uci_id->data;
224}
225
226static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
227{
228	while (table->mask) {
229		if ((pid & table->mask) == table->id)
230			return coresight_get_uci_data(table);
231		table++;
232	};
233	return NULL;
234}
235
236void coresight_release_platform_data(struct coresight_device *csdev,
237				     struct device *dev,
238				     struct coresight_platform_data *pdata);
239struct coresight_device *
240coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
241void coresight_add_helper(struct coresight_device *csdev,
242			  struct coresight_device *helper);
243
244void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
245struct coresight_device *coresight_get_percpu_sink(int cpu);
246void coresight_disable_source(struct coresight_device *csdev, void *data);
247
248#endif