1<?xml version="1.0" encoding="UTF-8"?>
  2<database xmlns="http://nouveau.freedesktop.org/"
  3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
  4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
  5<import file="freedreno_copyright.xml"/>
  6
  7<domain name="DSI_10nm_PHY_CMN" width="32">
  8	<reg32 offset="0x00000" name="REVISION_ID0"/>
  9	<reg32 offset="0x00004" name="REVISION_ID1"/>
 10	<reg32 offset="0x00008" name="REVISION_ID2"/>
 11	<reg32 offset="0x0000c" name="REVISION_ID3"/>
 12	<reg32 offset="0x00010" name="CLK_CFG0"/>
 13	<reg32 offset="0x00014" name="CLK_CFG1"/>
 14	<reg32 offset="0x00018" name="GLBL_CTRL"/>
 15	<reg32 offset="0x0001c" name="RBUF_CTRL"/>
 16	<reg32 offset="0x00020" name="VREG_CTRL"/>
 17	<reg32 offset="0x00024" name="CTRL_0"/>
 18	<reg32 offset="0x00028" name="CTRL_1"/>
 19	<reg32 offset="0x0002c" name="CTRL_2"/>
 20	<reg32 offset="0x00030" name="LANE_CFG0"/>
 21	<reg32 offset="0x00034" name="LANE_CFG1"/>
 22	<reg32 offset="0x00038" name="PLL_CNTRL"/>
 23	<reg32 offset="0x00098" name="LANE_CTRL0"/>
 24	<reg32 offset="0x0009c" name="LANE_CTRL1"/>
 25	<reg32 offset="0x000a0" name="LANE_CTRL2"/>
 26	<reg32 offset="0x000a4" name="LANE_CTRL3"/>
 27	<reg32 offset="0x000a8" name="LANE_CTRL4"/>
 28	<reg32 offset="0x000ac" name="TIMING_CTRL_0"/>
 29	<reg32 offset="0x000b0" name="TIMING_CTRL_1"/>
 30	<reg32 offset="0x000b4" name="TIMING_CTRL_2"/>
 31	<reg32 offset="0x000b8" name="TIMING_CTRL_3"/>
 32	<reg32 offset="0x000bc" name="TIMING_CTRL_4"/>
 33	<reg32 offset="0x000c0" name="TIMING_CTRL_5"/>
 34	<reg32 offset="0x000c4" name="TIMING_CTRL_6"/>
 35	<reg32 offset="0x000c8" name="TIMING_CTRL_7"/>
 36	<reg32 offset="0x000cc" name="TIMING_CTRL_8"/>
 37	<reg32 offset="0x000d0" name="TIMING_CTRL_9"/>
 38	<reg32 offset="0x000d4" name="TIMING_CTRL_10"/>
 39	<reg32 offset="0x000d8" name="TIMING_CTRL_11"/>
 40	<reg32 offset="0x000ec" name="PHY_STATUS"/>
 41	<reg32 offset="0x000f4" name="LANE_STATUS0"/>
 42	<reg32 offset="0x000f8" name="LANE_STATUS1"/>
 43</domain>
 44
 45<domain name="DSI_10nm_PHY" width="32">
 46	<array offset="0x00000" name="LN" length="5" stride="0x80">
 47		<reg32 offset="0x00" name="CFG0"/>
 48		<reg32 offset="0x04" name="CFG1"/>
 49		<reg32 offset="0x08" name="CFG2"/>
 50		<reg32 offset="0x0c" name="CFG3"/>
 51		<reg32 offset="0x10" name="TEST_DATAPATH"/>
 52		<reg32 offset="0x14" name="PIN_SWAP"/>
 53		<reg32 offset="0x18" name="HSTX_STR_CTRL"/>
 54		<reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>
 55		<reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>
 56		<reg32 offset="0x24" name="LPTX_STR_CTRL"/>
 57		<reg32 offset="0x28" name="LPRX_CTRL"/>
 58		<reg32 offset="0x2c" name="TX_DCTRL"/>
 59	</array>
 60</domain>
 61
 62<domain name="DSI_10nm_PHY_PLL" width="32">
 63	<reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
 64	<reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
 65	<reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
 66	<reg32 offset="0x001c" name="DSM_DIVIDER"/>
 67	<reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>
 68	<reg32 offset="0x0024" name="SYSTEM_MUXES"/>
 69	<reg32 offset="0x002c" name="CMODE"/>
 70	<reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>
 71	<reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>
 72	<reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>
 73	<reg32 offset="0x007c" name="PFILT"/>
 74	<reg32 offset="0x0080" name="IFILT"/>
 75	<reg32 offset="0x0094" name="OUTDIV"/>
 76	<reg32 offset="0x00a4" name="CORE_OVERRIDE"/>
 77	<reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>
 78	<reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>
 79	<reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>
 80	<reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>
 81	<reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>
 82	<reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>
 83	<reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>
 84	<reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>
 85	<reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>
 86	<reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>
 87	<reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>
 88	<reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>
 89	<reg32 offset="0x013c" name="SSC_CONTROL"/>
 90	<reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>
 91	<reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>
 92	<reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>
 93	<reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>
 94	<reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>
 95	<reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
 96	<reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>
 97	<reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>
 98	<reg32 offset="0x018c" name="CLOCK_INVERTERS"/>
 99	<reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>
100</domain>
101
102</database>