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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4 */
5
6#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
7
8#include <linux/types.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/phy/phy.h>
12#include <linux/phy/phy-dp.h>
13#include <linux/pm_opp.h>
14
15#include <drm/display/drm_dp_helper.h>
16#include <drm/drm_fixed.h>
17#include <drm/drm_print.h>
18
19#include "dp_reg.h"
20#include "dp_ctrl.h"
21#include "dp_link.h"
22
23#define DP_KHZ_TO_HZ 1000
24#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
25#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
26#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
27
28#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
29#define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
30
31#define MR_LINK_TRAINING1 0x8
32#define MR_LINK_SYMBOL_ERM 0x80
33#define MR_LINK_PRBS7 0x100
34#define MR_LINK_CUSTOM80 0x200
35#define MR_LINK_TRAINING4 0x40
36
37enum {
38 DP_TRAINING_NONE,
39 DP_TRAINING_1,
40 DP_TRAINING_2,
41};
42
43struct msm_dp_tu_calc_input {
44 u64 lclk; /* 162, 270, 540 and 810 */
45 u64 pclk_khz; /* in KHz */
46 u64 hactive; /* active h-width */
47 u64 hporch; /* bp + fp + pulse */
48 int nlanes; /* no.of.lanes */
49 int bpp; /* bits */
50 int pixel_enc; /* 444, 420, 422 */
51 int dsc_en; /* dsc on/off */
52 int async_en; /* async mode */
53 int fec_en; /* fec */
54 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
55 int num_of_dsc_slices; /* number of slices per line */
56};
57
58struct msm_dp_vc_tu_mapping_table {
59 u32 vic;
60 u8 lanes;
61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
62 u8 bpp;
63 u8 valid_boundary_link;
64 u16 delay_start_link;
65 bool boundary_moderation_en;
66 u8 valid_lower_boundary_link;
67 u8 upper_boundary_count;
68 u8 lower_boundary_count;
69 u8 tu_size_minus1;
70};
71
72struct msm_dp_ctrl_private {
73 struct msm_dp_ctrl msm_dp_ctrl;
74 struct drm_device *drm_dev;
75 struct device *dev;
76 struct drm_dp_aux *aux;
77 struct msm_dp_panel *panel;
78 struct msm_dp_link *link;
79 struct msm_dp_catalog *catalog;
80
81 struct phy *phy;
82
83 unsigned int num_core_clks;
84 struct clk_bulk_data *core_clks;
85
86 unsigned int num_link_clks;
87 struct clk_bulk_data *link_clks;
88
89 struct clk *pixel_clk;
90
91 union phy_configure_opts phy_opts;
92
93 struct completion idle_comp;
94 struct completion psr_op_comp;
95 struct completion video_comp;
96
97 bool core_clks_on;
98 bool link_clks_on;
99 bool stream_clks_on;
100};
101
102static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
103 struct msm_dp_link_info *link)
104{
105 u8 values[2];
106 int err;
107
108 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
109 values[1] = link->num_lanes;
110
111 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
112 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
113
114 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
115 if (err < 0)
116 return err;
117
118 return 0;
119}
120
121void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl)
122{
123 struct msm_dp_ctrl_private *ctrl;
124
125 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
126
127 reinit_completion(&ctrl->idle_comp);
128 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
129
130 if (!wait_for_completion_timeout(&ctrl->idle_comp,
131 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
132 pr_warn("PUSH_IDLE pattern timedout\n");
133
134 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
135}
136
137static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl)
138{
139 u32 config = 0, tbd;
140 const u8 *dpcd = ctrl->panel->dpcd;
141
142 /* Default-> LSCLK DIV: 1/4 LCLK */
143 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
144
145 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
146 config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */
147
148 /* Scrambler reset enable */
149 if (drm_dp_alternate_scrambler_reset_cap(dpcd))
150 config |= DP_CONFIGURATION_CTRL_ASSR;
151
152 tbd = msm_dp_link_get_test_bits_depth(ctrl->link,
153 ctrl->panel->msm_dp_mode.bpp);
154
155 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
156
157 /* Num of Lanes */
158 config |= ((ctrl->link->link_params.num_lanes - 1)
159 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
160
161 if (drm_dp_enhanced_frame_cap(dpcd))
162 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
163
164 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
165
166 /* sync clock & static Mvid */
167 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
168 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
169
170 if (ctrl->panel->psr_cap.version)
171 config |= DP_CONFIGURATION_CTRL_SEND_VSC;
172
173 msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
174}
175
176static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl)
177{
178 u32 cc, tb;
179
180 msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog);
181 msm_dp_catalog_setup_peripheral_flush(ctrl->catalog);
182
183 msm_dp_ctrl_config_ctrl(ctrl);
184
185 tb = msm_dp_link_get_test_bits_depth(ctrl->link,
186 ctrl->panel->msm_dp_mode.bpp);
187 cc = msm_dp_link_get_colorimetry_config(ctrl->link);
188 msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
189 msm_dp_panel_timing_cfg(ctrl->panel);
190}
191
192/*
193 * The structure and few functions present below are IP/Hardware
194 * specific implementation. Most of the implementation will not
195 * have coding comments
196 */
197struct tu_algo_data {
198 s64 lclk_fp;
199 s64 pclk_fp;
200 s64 lwidth;
201 s64 lwidth_fp;
202 s64 hbp_relative_to_pclk;
203 s64 hbp_relative_to_pclk_fp;
204 int nlanes;
205 int bpp;
206 int pixelEnc;
207 int dsc_en;
208 int async_en;
209 int bpc;
210
211 uint delay_start_link_extra_pixclk;
212 int extra_buffer_margin;
213 s64 ratio_fp;
214 s64 original_ratio_fp;
215
216 s64 err_fp;
217 s64 n_err_fp;
218 s64 n_n_err_fp;
219 int tu_size;
220 int tu_size_desired;
221 int tu_size_minus1;
222
223 int valid_boundary_link;
224 s64 resulting_valid_fp;
225 s64 total_valid_fp;
226 s64 effective_valid_fp;
227 s64 effective_valid_recorded_fp;
228 int n_tus;
229 int n_tus_per_lane;
230 int paired_tus;
231 int remainder_tus;
232 int remainder_tus_upper;
233 int remainder_tus_lower;
234 int extra_bytes;
235 int filler_size;
236 int delay_start_link;
237
238 int extra_pclk_cycles;
239 int extra_pclk_cycles_in_link_clk;
240 s64 ratio_by_tu_fp;
241 s64 average_valid2_fp;
242 int new_valid_boundary_link;
243 int remainder_symbols_exist;
244 int n_symbols;
245 s64 n_remainder_symbols_per_lane_fp;
246 s64 last_partial_tu_fp;
247 s64 TU_ratio_err_fp;
248
249 int n_tus_incl_last_incomplete_tu;
250 int extra_pclk_cycles_tmp;
251 int extra_pclk_cycles_in_link_clk_tmp;
252 int extra_required_bytes_new_tmp;
253 int filler_size_tmp;
254 int lower_filler_size_tmp;
255 int delay_start_link_tmp;
256
257 bool boundary_moderation_en;
258 int boundary_mod_lower_err;
259 int upper_boundary_count;
260 int lower_boundary_count;
261 int i_upper_boundary_count;
262 int i_lower_boundary_count;
263 int valid_lower_boundary_link;
264 int even_distribution_BF;
265 int even_distribution_legacy;
266 int even_distribution;
267 int min_hblank_violated;
268 s64 delay_start_time_fp;
269 s64 hbp_time_fp;
270 s64 hactive_time_fp;
271 s64 diff_abs_fp;
272
273 s64 ratio;
274};
275
276static int _tu_param_compare(s64 a, s64 b)
277{
278 u32 a_sign;
279 u32 b_sign;
280 s64 a_temp, b_temp, minus_1;
281
282 if (a == b)
283 return 0;
284
285 minus_1 = drm_fixp_from_fraction(-1, 1);
286
287 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
288
289 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
290
291 if (a_sign > b_sign)
292 return 2;
293 else if (b_sign > a_sign)
294 return 1;
295
296 if (!a_sign && !b_sign) { /* positive */
297 if (a > b)
298 return 1;
299 else
300 return 2;
301 } else { /* negative */
302 a_temp = drm_fixp_mul(a, minus_1);
303 b_temp = drm_fixp_mul(b, minus_1);
304
305 if (a_temp > b_temp)
306 return 2;
307 else
308 return 1;
309 }
310}
311
312static void msm_dp_panel_update_tu_timings(struct msm_dp_tu_calc_input *in,
313 struct tu_algo_data *tu)
314{
315 int nlanes = in->nlanes;
316 int dsc_num_slices = in->num_of_dsc_slices;
317 int dsc_num_bytes = 0;
318 int numerator;
319 s64 pclk_dsc_fp;
320 s64 dwidth_dsc_fp;
321 s64 hbp_dsc_fp;
322
323 int tot_num_eoc_symbols = 0;
324 int tot_num_hor_bytes = 0;
325 int tot_num_dummy_bytes = 0;
326 int dwidth_dsc_bytes = 0;
327 int eoc_bytes = 0;
328
329 s64 temp1_fp, temp2_fp, temp3_fp;
330
331 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
332 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
333 tu->lwidth = in->hactive;
334 tu->hbp_relative_to_pclk = in->hporch;
335 tu->nlanes = in->nlanes;
336 tu->bpp = in->bpp;
337 tu->pixelEnc = in->pixel_enc;
338 tu->dsc_en = in->dsc_en;
339 tu->async_en = in->async_en;
340 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
341 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
342
343 if (tu->pixelEnc == 420) {
344 temp1_fp = drm_fixp_from_fraction(2, 1);
345 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
346 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
347 tu->hbp_relative_to_pclk_fp =
348 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
349 }
350
351 if (tu->pixelEnc == 422) {
352 switch (tu->bpp) {
353 case 24:
354 tu->bpp = 16;
355 tu->bpc = 8;
356 break;
357 case 30:
358 tu->bpp = 20;
359 tu->bpc = 10;
360 break;
361 default:
362 tu->bpp = 16;
363 tu->bpc = 8;
364 break;
365 }
366 } else {
367 tu->bpc = tu->bpp/3;
368 }
369
370 if (!in->dsc_en)
371 goto fec_check;
372
373 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
374 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
375 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
376 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
377
378 temp1_fp = drm_fixp_from_fraction(8, 1);
379 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
380
381 numerator = drm_fixp2int(temp3_fp);
382
383 dsc_num_bytes = numerator / dsc_num_slices;
384 eoc_bytes = dsc_num_bytes % nlanes;
385 tot_num_eoc_symbols = nlanes * dsc_num_slices;
386 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
387 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
388
389 if (dsc_num_bytes == 0)
390 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
391
392 dwidth_dsc_bytes = (tot_num_hor_bytes +
393 tot_num_eoc_symbols +
394 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
395
396 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
397
398 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
399 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
400 pclk_dsc_fp = temp1_fp;
401
402 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
403 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
404 hbp_dsc_fp = temp2_fp;
405
406 /* output */
407 tu->pclk_fp = pclk_dsc_fp;
408 tu->lwidth_fp = dwidth_dsc_fp;
409 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
410
411fec_check:
412 if (in->fec_en) {
413 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
414 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
415 }
416}
417
418static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
419{
420 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
421 int compare_result_1, compare_result_2, compare_result_3;
422
423 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
424 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
425
426 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
427
428 temp = (tu->i_upper_boundary_count *
429 tu->new_valid_boundary_link +
430 tu->i_lower_boundary_count *
431 (tu->new_valid_boundary_link-1));
432 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
433 (tu->i_upper_boundary_count +
434 tu->i_lower_boundary_count));
435
436 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
437 temp2_fp = tu->lwidth_fp;
438 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
439 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
440 tu->n_tus = drm_fixp2int(temp2_fp);
441 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
442 tu->n_tus += 1;
443
444 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
445 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
446 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
447 temp2_fp = temp1_fp - temp2_fp;
448 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
449 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
450 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
451
452 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
453 tu->last_partial_tu_fp =
454 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
455 temp1_fp);
456
457 if (tu->n_remainder_symbols_per_lane_fp != 0)
458 tu->remainder_symbols_exist = 1;
459 else
460 tu->remainder_symbols_exist = 0;
461
462 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
463 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
464
465 tu->paired_tus = (int)((tu->n_tus_per_lane) /
466 (tu->i_upper_boundary_count +
467 tu->i_lower_boundary_count));
468
469 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
470 (tu->i_upper_boundary_count +
471 tu->i_lower_boundary_count);
472
473 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
474 tu->remainder_tus_upper = tu->i_upper_boundary_count;
475 tu->remainder_tus_lower = tu->remainder_tus -
476 tu->i_upper_boundary_count;
477 } else {
478 tu->remainder_tus_upper = tu->remainder_tus;
479 tu->remainder_tus_lower = 0;
480 }
481
482 temp = tu->paired_tus * (tu->i_upper_boundary_count *
483 tu->new_valid_boundary_link +
484 tu->i_lower_boundary_count *
485 (tu->new_valid_boundary_link - 1)) +
486 (tu->remainder_tus_upper *
487 tu->new_valid_boundary_link) +
488 (tu->remainder_tus_lower *
489 (tu->new_valid_boundary_link - 1));
490 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
491
492 if (tu->remainder_symbols_exist) {
493 temp1_fp = tu->total_valid_fp +
494 tu->n_remainder_symbols_per_lane_fp;
495 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
496 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
497 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
498 } else {
499 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
500 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
501 }
502 tu->effective_valid_fp = temp1_fp;
503
504 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
505 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
506 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
507
508 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
509 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
510 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
511
512 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
513
514 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
515 temp2_fp = tu->lwidth_fp;
516 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
517 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
518
519 if (temp2_fp)
520 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
521 else
522 tu->n_tus_incl_last_incomplete_tu = 0;
523
524 temp1 = 0;
525 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
526 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
527 temp1_fp = tu->average_valid2_fp - temp2_fp;
528 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
529 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
530
531 if (temp1_fp)
532 temp1 = drm_fixp2int_ceil(temp1_fp);
533
534 temp = tu->i_upper_boundary_count * tu->nlanes;
535 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
536 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
537 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
538 temp2_fp = temp1_fp - temp2_fp;
539 temp1_fp = drm_fixp_from_fraction(temp, 1);
540 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
541
542 if (temp2_fp)
543 temp2 = drm_fixp2int_ceil(temp2_fp);
544 else
545 temp2 = 0;
546 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
547
548 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
549 temp2_fp = drm_fixp_from_fraction(
550 tu->extra_required_bytes_new_tmp, 1);
551 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
552
553 if (temp1_fp)
554 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
555 else
556 tu->extra_pclk_cycles_tmp = 0;
557
558 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
559 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
560 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
561
562 if (temp1_fp)
563 tu->extra_pclk_cycles_in_link_clk_tmp =
564 drm_fixp2int_ceil(temp1_fp);
565 else
566 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
567
568 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
569
570 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
571
572 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
573 tu->lower_filler_size_tmp +
574 tu->extra_buffer_margin;
575
576 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
577 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
578
579 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
580 if (compare_result_1 == 2)
581 compare_result_1 = 1;
582 else
583 compare_result_1 = 0;
584
585 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
586 if (compare_result_2 == 2)
587 compare_result_2 = 1;
588 else
589 compare_result_2 = 0;
590
591 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
592 tu->delay_start_time_fp);
593 if (compare_result_3 == 2)
594 compare_result_3 = 0;
595 else
596 compare_result_3 = 1;
597
598 if (((tu->even_distribution == 1) ||
599 ((tu->even_distribution_BF == 0) &&
600 (tu->even_distribution_legacy == 0))) &&
601 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
602 compare_result_2 &&
603 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
604 (tu->new_valid_boundary_link - 1) > 0 &&
605 compare_result_3 &&
606 (tu->delay_start_link_tmp <= 1023)) {
607 tu->upper_boundary_count = tu->i_upper_boundary_count;
608 tu->lower_boundary_count = tu->i_lower_boundary_count;
609 tu->err_fp = tu->n_n_err_fp;
610 tu->boundary_moderation_en = true;
611 tu->tu_size_desired = tu->tu_size;
612 tu->valid_boundary_link = tu->new_valid_boundary_link;
613 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
614 tu->even_distribution_BF = 1;
615 tu->delay_start_link = tu->delay_start_link_tmp;
616 } else if (tu->boundary_mod_lower_err == 0) {
617 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
618 tu->diff_abs_fp);
619 if (compare_result_1 == 2)
620 tu->boundary_mod_lower_err = 1;
621 }
622}
623
624static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl,
625 struct msm_dp_tu_calc_input *in,
626 struct msm_dp_vc_tu_mapping_table *tu_table)
627{
628 struct tu_algo_data *tu;
629 int compare_result_1, compare_result_2;
630 u64 temp = 0;
631 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
632
633 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
634 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
635 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
636 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
637
638 u8 DP_BRUTE_FORCE = 1;
639 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
640 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
641 uint HBLANK_MARGIN = 4;
642
643 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
644 if (!tu)
645 return;
646
647 msm_dp_panel_update_tu_timings(in, tu);
648
649 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
650
651 temp1_fp = drm_fixp_from_fraction(4, 1);
652 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
653 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
654 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
655
656 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
657 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
658 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
659 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
660 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
661
662 tu->original_ratio_fp = tu->ratio_fp;
663 tu->boundary_moderation_en = false;
664 tu->upper_boundary_count = 0;
665 tu->lower_boundary_count = 0;
666 tu->i_upper_boundary_count = 0;
667 tu->i_lower_boundary_count = 0;
668 tu->valid_lower_boundary_link = 0;
669 tu->even_distribution_BF = 0;
670 tu->even_distribution_legacy = 0;
671 tu->even_distribution = 0;
672 tu->delay_start_time_fp = 0;
673
674 tu->err_fp = drm_fixp_from_fraction(1000, 1);
675 tu->n_err_fp = 0;
676 tu->n_n_err_fp = 0;
677
678 tu->ratio = drm_fixp2int(tu->ratio_fp);
679 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
680 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
681 if (temp2_fp != 0 &&
682 !tu->ratio && tu->dsc_en == 0) {
683 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
684 tu->ratio = drm_fixp2int(tu->ratio_fp);
685 if (tu->ratio)
686 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
687 }
688
689 if (tu->ratio > 1)
690 tu->ratio = 1;
691
692 if (tu->ratio == 1)
693 goto tu_size_calc;
694
695 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
696 if (!compare_result_1 || compare_result_1 == 1)
697 compare_result_1 = 1;
698 else
699 compare_result_1 = 0;
700
701 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
702 if (!compare_result_2 || compare_result_2 == 2)
703 compare_result_2 = 1;
704 else
705 compare_result_2 = 0;
706
707 if (tu->dsc_en && compare_result_1 && compare_result_2) {
708 HBLANK_MARGIN += 4;
709 drm_dbg_dp(ctrl->drm_dev,
710 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
711 }
712
713tu_size_calc:
714 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
715 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
716 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
717 temp = drm_fixp2int_ceil(temp2_fp);
718 temp1_fp = drm_fixp_from_fraction(temp, 1);
719 tu->n_err_fp = temp1_fp - temp2_fp;
720
721 if (tu->n_err_fp < tu->err_fp) {
722 tu->err_fp = tu->n_err_fp;
723 tu->tu_size_desired = tu->tu_size;
724 }
725 }
726
727 tu->tu_size_minus1 = tu->tu_size_desired - 1;
728
729 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
730 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
731 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
732
733 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
734 temp2_fp = tu->lwidth_fp;
735 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
736
737 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
738 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
739 tu->n_tus = drm_fixp2int(temp2_fp);
740 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
741 tu->n_tus += 1;
742
743 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
744
745 drm_dbg_dp(ctrl->drm_dev,
746 "n_sym = %d, num_of_tus = %d\n",
747 tu->valid_boundary_link, tu->n_tus);
748
749 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
750 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
751 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
752 temp2_fp = temp1_fp - temp2_fp;
753 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
754 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
755
756 temp = drm_fixp2int(temp2_fp);
757 if (temp && temp2_fp)
758 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
759 else
760 tu->extra_bytes = 0;
761
762 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
763 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
764 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
765
766 if (temp && temp1_fp)
767 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
768 else
769 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
770
771 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
772 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
773 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
774
775 if (temp1_fp)
776 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
777 else
778 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
779
780 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
781
782 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
783 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
784
785 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
786 tu->filler_size + tu->extra_buffer_margin;
787
788 tu->resulting_valid_fp =
789 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
790
791 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
792 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
793 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
794
795 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
796 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
797 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
798
799 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
800 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
801
802 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
803 tu->delay_start_time_fp);
804 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
805 tu->min_hblank_violated = 1;
806
807 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
808
809 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
810 tu->delay_start_time_fp);
811 if (compare_result_2 == 2)
812 tu->min_hblank_violated = 1;
813
814 tu->delay_start_time_fp = 0;
815
816 /* brute force */
817
818 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
819 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
820
821 temp = drm_fixp2int(tu->diff_abs_fp);
822 if (!temp && tu->diff_abs_fp <= 0xffff)
823 tu->diff_abs_fp = 0;
824
825 /* if(diff_abs < 0) diff_abs *= -1 */
826 if (tu->diff_abs_fp < 0)
827 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
828
829 tu->boundary_mod_lower_err = 0;
830 if ((tu->diff_abs_fp != 0 &&
831 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
832 (tu->even_distribution_legacy == 0) ||
833 (DP_BRUTE_FORCE == 1))) ||
834 (tu->min_hblank_violated == 1)) {
835 do {
836 tu->err_fp = drm_fixp_from_fraction(1000, 1);
837
838 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
839 temp2_fp = drm_fixp_from_fraction(
840 tu->delay_start_link_extra_pixclk, 1);
841 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
842
843 if (temp1_fp)
844 tu->extra_buffer_margin =
845 drm_fixp2int_ceil(temp1_fp);
846 else
847 tu->extra_buffer_margin = 0;
848
849 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
850 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
851
852 if (temp1_fp)
853 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
854 else
855 tu->n_symbols = 0;
856
857 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
858 for (tu->i_upper_boundary_count = 1;
859 tu->i_upper_boundary_count <= 15;
860 tu->i_upper_boundary_count++) {
861 for (tu->i_lower_boundary_count = 1;
862 tu->i_lower_boundary_count <= 15;
863 tu->i_lower_boundary_count++) {
864 _tu_valid_boundary_calc(tu);
865 }
866 }
867 }
868 tu->delay_start_link_extra_pixclk--;
869 } while (tu->boundary_moderation_en != true &&
870 tu->boundary_mod_lower_err == 1 &&
871 tu->delay_start_link_extra_pixclk != 0);
872
873 if (tu->boundary_moderation_en == true) {
874 temp1_fp = drm_fixp_from_fraction(
875 (tu->upper_boundary_count *
876 tu->valid_boundary_link +
877 tu->lower_boundary_count *
878 (tu->valid_boundary_link - 1)), 1);
879 temp2_fp = drm_fixp_from_fraction(
880 (tu->upper_boundary_count +
881 tu->lower_boundary_count), 1);
882 tu->resulting_valid_fp =
883 drm_fixp_div(temp1_fp, temp2_fp);
884
885 temp1_fp = drm_fixp_from_fraction(
886 tu->tu_size_desired, 1);
887 tu->ratio_by_tu_fp =
888 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
889
890 tu->valid_lower_boundary_link =
891 tu->valid_boundary_link - 1;
892
893 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
894 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
895 temp2_fp = drm_fixp_div(temp1_fp,
896 tu->resulting_valid_fp);
897 tu->n_tus = drm_fixp2int(temp2_fp);
898
899 tu->tu_size_minus1 = tu->tu_size_desired - 1;
900 tu->even_distribution_BF = 1;
901
902 temp1_fp =
903 drm_fixp_from_fraction(tu->tu_size_desired, 1);
904 temp2_fp =
905 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
906 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
907 }
908 }
909
910 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
911
912 if (temp2_fp)
913 temp = drm_fixp2int_ceil(temp2_fp);
914 else
915 temp = 0;
916
917 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
918 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
919 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
920 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
921 temp1_fp = drm_fixp_from_fraction(temp, 1);
922 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
923 temp = drm_fixp2int(temp2_fp);
924
925 if (tu->async_en)
926 tu->delay_start_link += (int)temp;
927
928 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
929 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
930
931 /* OUTPUTS */
932 tu_table->valid_boundary_link = tu->valid_boundary_link;
933 tu_table->delay_start_link = tu->delay_start_link;
934 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
935 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
936 tu_table->upper_boundary_count = tu->upper_boundary_count;
937 tu_table->lower_boundary_count = tu->lower_boundary_count;
938 tu_table->tu_size_minus1 = tu->tu_size_minus1;
939
940 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
941 tu_table->valid_boundary_link);
942 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
943 tu_table->delay_start_link);
944 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
945 tu_table->boundary_moderation_en);
946 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
947 tu_table->valid_lower_boundary_link);
948 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
949 tu_table->upper_boundary_count);
950 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
951 tu_table->lower_boundary_count);
952 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
953 tu_table->tu_size_minus1);
954
955 kfree(tu);
956}
957
958static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl,
959 struct msm_dp_vc_tu_mapping_table *tu_table)
960{
961 struct msm_dp_tu_calc_input in;
962 struct drm_display_mode *drm_mode;
963
964 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode;
965
966 in.lclk = ctrl->link->link_params.rate / 1000;
967 in.pclk_khz = drm_mode->clock;
968 in.hactive = drm_mode->hdisplay;
969 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
970 in.nlanes = ctrl->link->link_params.num_lanes;
971 in.bpp = ctrl->panel->msm_dp_mode.bpp;
972 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444;
973 in.dsc_en = 0;
974 in.async_en = 0;
975 in.fec_en = 0;
976 in.num_of_dsc_slices = 0;
977 in.compress_ratio = 100;
978
979 _dp_ctrl_calc_tu(ctrl, &in, tu_table);
980}
981
982static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl)
983{
984 u32 msm_dp_tu = 0x0;
985 u32 valid_boundary = 0x0;
986 u32 valid_boundary2 = 0x0;
987 struct msm_dp_vc_tu_mapping_table tu_calc_table;
988
989 msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
990
991 msm_dp_tu |= tu_calc_table.tu_size_minus1;
992 valid_boundary |= tu_calc_table.valid_boundary_link;
993 valid_boundary |= (tu_calc_table.delay_start_link << 16);
994
995 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
996 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
997 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
998
999 if (tu_calc_table.boundary_moderation_en)
1000 valid_boundary2 |= BIT(0);
1001
1002 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
1003 msm_dp_tu, valid_boundary, valid_boundary2);
1004
1005 msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
1006 msm_dp_tu, valid_boundary, valid_boundary2);
1007}
1008
1009static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl)
1010{
1011 int ret = 0;
1012
1013 if (!wait_for_completion_timeout(&ctrl->video_comp,
1014 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
1015 DRM_ERROR("wait4video timedout\n");
1016 ret = -ETIMEDOUT;
1017 }
1018 return ret;
1019}
1020
1021static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl,
1022 u8 v_level, u8 p_level)
1023{
1024 union phy_configure_opts *phy_opts = &ctrl->phy_opts;
1025
1026 /* TODO: Update for all lanes instead of just first one */
1027 phy_opts->dp.voltage[0] = v_level;
1028 phy_opts->dp.pre[0] = p_level;
1029 phy_opts->dp.set_voltages = 1;
1030 phy_configure(ctrl->phy, phy_opts);
1031 phy_opts->dp.set_voltages = 0;
1032
1033 return 0;
1034}
1035
1036static int msm_dp_ctrl_update_vx_px(struct msm_dp_ctrl_private *ctrl)
1037{
1038 struct msm_dp_link *link = ctrl->link;
1039 int ret = 0, lane, lane_cnt;
1040 u8 buf[4];
1041 u32 max_level_reached = 0;
1042 u32 voltage_swing_level = link->phy_params.v_level;
1043 u32 pre_emphasis_level = link->phy_params.p_level;
1044
1045 drm_dbg_dp(ctrl->drm_dev,
1046 "voltage level: %d emphasis level: %d\n",
1047 voltage_swing_level, pre_emphasis_level);
1048 ret = msm_dp_ctrl_set_vx_px(ctrl,
1049 voltage_swing_level, pre_emphasis_level);
1050
1051 if (ret)
1052 return ret;
1053
1054 if (voltage_swing_level >= DP_TRAIN_LEVEL_MAX) {
1055 drm_dbg_dp(ctrl->drm_dev,
1056 "max. voltage swing level reached %d\n",
1057 voltage_swing_level);
1058 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1059 }
1060
1061 if (pre_emphasis_level >= DP_TRAIN_LEVEL_MAX) {
1062 drm_dbg_dp(ctrl->drm_dev,
1063 "max. pre-emphasis level reached %d\n",
1064 pre_emphasis_level);
1065 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1066 }
1067
1068 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1069
1070 lane_cnt = ctrl->link->link_params.num_lanes;
1071 for (lane = 0; lane < lane_cnt; lane++)
1072 buf[lane] = voltage_swing_level | pre_emphasis_level
1073 | max_level_reached;
1074
1075 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1076 voltage_swing_level | pre_emphasis_level);
1077 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1078 buf, lane_cnt);
1079 if (ret == lane_cnt)
1080 ret = 0;
1081
1082 return ret;
1083}
1084
1085static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl,
1086 u8 pattern)
1087{
1088 u8 buf;
1089 int ret = 0;
1090
1091 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1092
1093 buf = pattern;
1094
1095 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1096 buf |= DP_LINK_SCRAMBLING_DISABLE;
1097
1098 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1099 return ret == 1;
1100}
1101
1102static int msm_dp_ctrl_read_link_status(struct msm_dp_ctrl_private *ctrl,
1103 u8 *link_status)
1104{
1105 int ret = 0, len;
1106
1107 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1108 if (len != DP_LINK_STATUS_SIZE) {
1109 DRM_ERROR("DP link status read failed, err: %d\n", len);
1110 ret = -EINVAL;
1111 }
1112
1113 return ret;
1114}
1115
1116static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl,
1117 int *training_step)
1118{
1119 int tries, old_v_level, ret = 0;
1120 u8 link_status[DP_LINK_STATUS_SIZE];
1121 int const maximum_retries = 4;
1122
1123 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1124
1125 *training_step = DP_TRAINING_1;
1126
1127 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1128 if (ret)
1129 return ret;
1130 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1131 DP_LINK_SCRAMBLING_DISABLE);
1132
1133 ret = msm_dp_ctrl_update_vx_px(ctrl);
1134 if (ret)
1135 return ret;
1136
1137 tries = 0;
1138 old_v_level = ctrl->link->phy_params.v_level;
1139 for (tries = 0; tries < maximum_retries; tries++) {
1140 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1141
1142 ret = msm_dp_ctrl_read_link_status(ctrl, link_status);
1143 if (ret)
1144 return ret;
1145
1146 if (drm_dp_clock_recovery_ok(link_status,
1147 ctrl->link->link_params.num_lanes)) {
1148 return 0;
1149 }
1150
1151 if (ctrl->link->phy_params.v_level >=
1152 DP_TRAIN_LEVEL_MAX) {
1153 DRM_ERROR_RATELIMITED("max v_level reached\n");
1154 return -EAGAIN;
1155 }
1156
1157 if (old_v_level != ctrl->link->phy_params.v_level) {
1158 tries = 0;
1159 old_v_level = ctrl->link->phy_params.v_level;
1160 }
1161
1162 msm_dp_link_adjust_levels(ctrl->link, link_status);
1163 ret = msm_dp_ctrl_update_vx_px(ctrl);
1164 if (ret)
1165 return ret;
1166 }
1167
1168 DRM_ERROR("max tries reached\n");
1169 return -ETIMEDOUT;
1170}
1171
1172static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl)
1173{
1174 int ret = 0;
1175
1176 switch (ctrl->link->link_params.rate) {
1177 case 810000:
1178 ctrl->link->link_params.rate = 540000;
1179 break;
1180 case 540000:
1181 ctrl->link->link_params.rate = 270000;
1182 break;
1183 case 270000:
1184 ctrl->link->link_params.rate = 162000;
1185 break;
1186 case 162000:
1187 default:
1188 ret = -EINVAL;
1189 break;
1190 }
1191
1192 if (!ret) {
1193 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1194 ctrl->link->link_params.rate);
1195 }
1196
1197 return ret;
1198}
1199
1200static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl)
1201{
1202
1203 if (ctrl->link->link_params.num_lanes == 1)
1204 return -1;
1205
1206 ctrl->link->link_params.num_lanes /= 2;
1207 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1208
1209 ctrl->link->phy_params.p_level = 0;
1210 ctrl->link->phy_params.v_level = 0;
1211
1212 return 0;
1213}
1214
1215static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl)
1216{
1217 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1218 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1219}
1220
1221static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl,
1222 int *training_step)
1223{
1224 int tries = 0, ret = 0;
1225 u8 pattern;
1226 u32 state_ctrl_bit;
1227 int const maximum_retries = 5;
1228 u8 link_status[DP_LINK_STATUS_SIZE];
1229
1230 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1231
1232 *training_step = DP_TRAINING_2;
1233
1234 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1235 pattern = DP_TRAINING_PATTERN_4;
1236 state_ctrl_bit = 4;
1237 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1238 pattern = DP_TRAINING_PATTERN_3;
1239 state_ctrl_bit = 3;
1240 } else {
1241 pattern = DP_TRAINING_PATTERN_2;
1242 state_ctrl_bit = 2;
1243 }
1244
1245 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1246 if (ret)
1247 return ret;
1248
1249 msm_dp_ctrl_train_pattern_set(ctrl, pattern);
1250
1251 for (tries = 0; tries <= maximum_retries; tries++) {
1252 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1253
1254 ret = msm_dp_ctrl_read_link_status(ctrl, link_status);
1255 if (ret)
1256 return ret;
1257
1258 if (drm_dp_channel_eq_ok(link_status,
1259 ctrl->link->link_params.num_lanes)) {
1260 return 0;
1261 }
1262
1263 msm_dp_link_adjust_levels(ctrl->link, link_status);
1264 ret = msm_dp_ctrl_update_vx_px(ctrl);
1265 if (ret)
1266 return ret;
1267
1268 }
1269
1270 return -ETIMEDOUT;
1271}
1272
1273static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl,
1274 int *training_step)
1275{
1276 int ret = 0;
1277 const u8 *dpcd = ctrl->panel->dpcd;
1278 u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
1279 u8 assr;
1280 struct msm_dp_link_info link_info = {0};
1281
1282 msm_dp_ctrl_config_ctrl(ctrl);
1283
1284 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1285 link_info.rate = ctrl->link->link_params.rate;
1286 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1287
1288 msm_dp_link_reset_phy_params_vx_px(ctrl->link);
1289
1290 msm_dp_aux_link_configure(ctrl->aux, &link_info);
1291
1292 if (drm_dp_max_downspread(dpcd))
1293 encoding[0] |= DP_SPREAD_AMP_0_5;
1294
1295 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
1296 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
1297
1298 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1299 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1300 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1301 &assr, 1);
1302 }
1303
1304 ret = msm_dp_ctrl_link_train_1(ctrl, training_step);
1305 if (ret) {
1306 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1307 goto end;
1308 }
1309
1310 /* print success info as this is a result of user initiated action */
1311 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1312
1313 ret = msm_dp_ctrl_link_train_2(ctrl, training_step);
1314 if (ret) {
1315 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1316 goto end;
1317 }
1318
1319 /* print success info as this is a result of user initiated action */
1320 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1321
1322end:
1323 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1324
1325 return ret;
1326}
1327
1328static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl,
1329 int *training_step)
1330{
1331 int ret = 0;
1332
1333 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1334
1335 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1336 return ret;
1337
1338 /*
1339 * As part of previous calls, DP controller state might have
1340 * transitioned to PUSH_IDLE. In order to start transmitting
1341 * a link training pattern, we have to first do soft reset.
1342 */
1343
1344 ret = msm_dp_ctrl_link_train(ctrl, training_step);
1345
1346 return ret;
1347}
1348
1349int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl)
1350{
1351 struct msm_dp_ctrl_private *ctrl;
1352 int ret = 0;
1353
1354 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1355
1356 if (ctrl->core_clks_on) {
1357 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n");
1358 return 0;
1359 }
1360
1361 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks);
1362 if (ret)
1363 return ret;
1364
1365 ctrl->core_clks_on = true;
1366
1367 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n");
1368 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1369 ctrl->stream_clks_on ? "on" : "off",
1370 ctrl->link_clks_on ? "on" : "off",
1371 ctrl->core_clks_on ? "on" : "off");
1372
1373 return 0;
1374}
1375
1376void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl)
1377{
1378 struct msm_dp_ctrl_private *ctrl;
1379
1380 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1381
1382 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks);
1383
1384 ctrl->core_clks_on = false;
1385
1386 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n");
1387 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1388 ctrl->stream_clks_on ? "on" : "off",
1389 ctrl->link_clks_on ? "on" : "off",
1390 ctrl->core_clks_on ? "on" : "off");
1391}
1392
1393static int msm_dp_ctrl_link_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl)
1394{
1395 struct msm_dp_ctrl_private *ctrl;
1396 int ret = 0;
1397
1398 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1399
1400 if (ctrl->link_clks_on) {
1401 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n");
1402 return 0;
1403 }
1404
1405 if (!ctrl->core_clks_on) {
1406 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n");
1407
1408 msm_dp_ctrl_core_clk_enable(msm_dp_ctrl);
1409 }
1410
1411 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks);
1412 if (ret)
1413 return ret;
1414
1415 ctrl->link_clks_on = true;
1416
1417 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n");
1418 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1419 ctrl->stream_clks_on ? "on" : "off",
1420 ctrl->link_clks_on ? "on" : "off",
1421 ctrl->core_clks_on ? "on" : "off");
1422
1423 return 0;
1424}
1425
1426static void msm_dp_ctrl_link_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl)
1427{
1428 struct msm_dp_ctrl_private *ctrl;
1429
1430 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1431
1432 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks);
1433
1434 ctrl->link_clks_on = false;
1435
1436 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n");
1437 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1438 ctrl->stream_clks_on ? "on" : "off",
1439 ctrl->link_clks_on ? "on" : "off",
1440 ctrl->core_clks_on ? "on" : "off");
1441}
1442
1443static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl)
1444{
1445 int ret = 0;
1446 struct phy *phy = ctrl->phy;
1447 const u8 *dpcd = ctrl->panel->dpcd;
1448
1449 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1450 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100;
1451 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd);
1452
1453 phy_configure(phy, &ctrl->phy_opts);
1454 phy_power_on(phy);
1455
1456 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
1457 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl);
1458 if (ret)
1459 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1460
1461 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
1462
1463 return ret;
1464}
1465
1466void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enable)
1467{
1468 struct msm_dp_ctrl_private *ctrl;
1469
1470 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1471
1472 msm_dp_catalog_ctrl_reset(ctrl->catalog);
1473
1474 /*
1475 * all dp controller programmable registers will not
1476 * be reset to default value after DP_SW_RESET
1477 * therefore interrupt mask bits have to be updated
1478 * to enable/disable interrupts
1479 */
1480 msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1481}
1482
1483void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl)
1484{
1485 u8 cfg;
1486 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl,
1487 struct msm_dp_ctrl_private, msm_dp_ctrl);
1488
1489 if (!ctrl->panel->psr_cap.version)
1490 return;
1491
1492 msm_dp_catalog_ctrl_config_psr(ctrl->catalog);
1493
1494 cfg = DP_PSR_ENABLE;
1495 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
1496}
1497
1498void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter)
1499{
1500 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl,
1501 struct msm_dp_ctrl_private, msm_dp_ctrl);
1502
1503 if (!ctrl->panel->psr_cap.version)
1504 return;
1505
1506 /*
1507 * When entering PSR,
1508 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT
1509 * 2. Turn off video
1510 * 3. Disable the mainlink
1511 *
1512 * When exiting PSR,
1513 * 1. Enable the mainlink
1514 * 2. Send the PSR exit SDP
1515 */
1516 if (enter) {
1517 reinit_completion(&ctrl->psr_op_comp);
1518 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true);
1519
1520 if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
1521 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
1522 DRM_ERROR("PSR_ENTRY timedout\n");
1523 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1524 return;
1525 }
1526
1527 msm_dp_ctrl_push_idle(msm_dp_ctrl);
1528 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1529
1530 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
1531 } else {
1532 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
1533
1534 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1535 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1536 msm_dp_ctrl_wait4video_ready(ctrl);
1537 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1538 }
1539}
1540
1541void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl)
1542{
1543 struct msm_dp_ctrl_private *ctrl;
1544 struct phy *phy;
1545
1546 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1547 phy = ctrl->phy;
1548
1549 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog);
1550 phy_init(phy);
1551
1552 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1553 phy, phy->init_count, phy->power_count);
1554}
1555
1556void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl)
1557{
1558 struct msm_dp_ctrl_private *ctrl;
1559 struct phy *phy;
1560
1561 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1562 phy = ctrl->phy;
1563
1564 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog);
1565 phy_exit(phy);
1566 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1567 phy, phy->init_count, phy->power_count);
1568}
1569
1570static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl)
1571{
1572 struct phy *phy = ctrl->phy;
1573 int ret = 0;
1574
1575 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1576 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1577 phy_configure(phy, &ctrl->phy_opts);
1578 /*
1579 * Disable and re-enable the mainlink clock since the
1580 * link clock might have been adjusted as part of the
1581 * link maintenance.
1582 */
1583 dev_pm_opp_set_rate(ctrl->dev, 0);
1584
1585 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
1586
1587 phy_power_off(phy);
1588 /* hw recommended delay before re-enabling clocks */
1589 msleep(20);
1590
1591 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
1592 if (ret) {
1593 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1594 return ret;
1595 }
1596
1597 return ret;
1598}
1599
1600static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl)
1601{
1602 struct phy *phy;
1603
1604 phy = ctrl->phy;
1605
1606 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1607
1608 msm_dp_catalog_ctrl_reset(ctrl->catalog);
1609
1610 dev_pm_opp_set_rate(ctrl->dev, 0);
1611 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
1612
1613 phy_power_off(phy);
1614
1615 /* aux channel down, reinit phy */
1616 phy_exit(phy);
1617 phy_init(phy);
1618
1619 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1620 phy, phy->init_count, phy->power_count);
1621 return 0;
1622}
1623
1624static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl)
1625{
1626 int ret = 0;
1627 int training_step = DP_TRAINING_NONE;
1628
1629 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl);
1630
1631 ctrl->link->phy_params.p_level = 0;
1632 ctrl->link->phy_params.v_level = 0;
1633
1634 ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step);
1635 if (ret)
1636 goto end;
1637
1638 msm_dp_ctrl_clear_training_pattern(ctrl);
1639
1640 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1641
1642 ret = msm_dp_ctrl_wait4video_ready(ctrl);
1643end:
1644 return ret;
1645}
1646
1647static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl)
1648{
1649 bool success = false;
1650 u32 pattern_sent = 0x0;
1651 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1652
1653 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1654
1655 if (msm_dp_ctrl_set_vx_px(ctrl,
1656 ctrl->link->phy_params.v_level,
1657 ctrl->link->phy_params.p_level)) {
1658 DRM_ERROR("Failed to set v/p levels\n");
1659 return false;
1660 }
1661 msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1662 msm_dp_ctrl_update_vx_px(ctrl);
1663 msm_dp_link_send_test_response(ctrl->link);
1664
1665 pattern_sent = msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1666
1667 switch (pattern_sent) {
1668 case MR_LINK_TRAINING1:
1669 success = (pattern_requested ==
1670 DP_PHY_TEST_PATTERN_D10_2);
1671 break;
1672 case MR_LINK_SYMBOL_ERM:
1673 success = ((pattern_requested ==
1674 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1675 (pattern_requested ==
1676 DP_PHY_TEST_PATTERN_CP2520));
1677 break;
1678 case MR_LINK_PRBS7:
1679 success = (pattern_requested ==
1680 DP_PHY_TEST_PATTERN_PRBS7);
1681 break;
1682 case MR_LINK_CUSTOM80:
1683 success = (pattern_requested ==
1684 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1685 break;
1686 case MR_LINK_TRAINING4:
1687 success = (pattern_requested ==
1688 DP_PHY_TEST_PATTERN_SEL_MASK);
1689 break;
1690 default:
1691 success = false;
1692 }
1693
1694 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
1695 success ? "success" : "failed", pattern_requested);
1696 return success;
1697}
1698
1699static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl)
1700{
1701 int ret;
1702 unsigned long pixel_rate;
1703
1704 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1705 drm_dbg_dp(ctrl->drm_dev,
1706 "no test pattern selected by sink\n");
1707 return 0;
1708 }
1709
1710 /*
1711 * The global reset will need DP link related clocks to be
1712 * running. Add the global reset just before disabling the
1713 * link clocks and core clocks.
1714 */
1715 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl);
1716
1717 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl);
1718 if (ret) {
1719 DRM_ERROR("failed to enable DP link controller\n");
1720 return ret;
1721 }
1722
1723 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock;
1724 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
1725 if (ret) {
1726 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
1727 return ret;
1728 }
1729
1730 if (ctrl->stream_clks_on) {
1731 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
1732 } else {
1733 ret = clk_prepare_enable(ctrl->pixel_clk);
1734 if (ret) {
1735 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1736 return ret;
1737 }
1738 ctrl->stream_clks_on = true;
1739 }
1740
1741 msm_dp_ctrl_send_phy_test_pattern(ctrl);
1742
1743 return 0;
1744}
1745
1746void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl)
1747{
1748 struct msm_dp_ctrl_private *ctrl;
1749 u32 sink_request = 0x0;
1750
1751 if (!msm_dp_ctrl) {
1752 DRM_ERROR("invalid input\n");
1753 return;
1754 }
1755
1756 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1757 sink_request = ctrl->link->sink_request;
1758
1759 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1760 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1761 if (msm_dp_ctrl_process_phy_test_request(ctrl)) {
1762 DRM_ERROR("process phy_test_req failed\n");
1763 return;
1764 }
1765 }
1766
1767 if (sink_request & DP_LINK_STATUS_UPDATED) {
1768 if (msm_dp_ctrl_link_maintenance(ctrl)) {
1769 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1770 return;
1771 }
1772 }
1773
1774 if (sink_request & DP_TEST_LINK_TRAINING) {
1775 msm_dp_link_send_test_response(ctrl->link);
1776 if (msm_dp_ctrl_link_maintenance(ctrl)) {
1777 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1778 return;
1779 }
1780 }
1781}
1782
1783static bool msm_dp_ctrl_clock_recovery_any_ok(
1784 const u8 link_status[DP_LINK_STATUS_SIZE],
1785 int lane_count)
1786{
1787 int reduced_cnt;
1788
1789 if (lane_count <= 1)
1790 return false;
1791
1792 /*
1793 * only interested in the lane number after reduced
1794 * lane_count = 4, then only interested in 2 lanes
1795 * lane_count = 2, then only interested in 1 lane
1796 */
1797 reduced_cnt = lane_count >> 1;
1798
1799 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1800}
1801
1802static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl)
1803{
1804 u8 link_status[DP_LINK_STATUS_SIZE];
1805 int num_lanes = ctrl->link->link_params.num_lanes;
1806
1807 msm_dp_ctrl_read_link_status(ctrl, link_status);
1808
1809 return drm_dp_channel_eq_ok(link_status, num_lanes);
1810}
1811
1812int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl)
1813{
1814 int rc = 0;
1815 struct msm_dp_ctrl_private *ctrl;
1816 u32 rate;
1817 int link_train_max_retries = 5;
1818 u32 const phy_cts_pixel_clk_khz = 148500;
1819 u8 link_status[DP_LINK_STATUS_SIZE];
1820 unsigned int training_step;
1821 unsigned long pixel_rate;
1822
1823 if (!msm_dp_ctrl)
1824 return -EINVAL;
1825
1826 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1827
1828 rate = ctrl->panel->link_info.rate;
1829 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock;
1830
1831 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl);
1832
1833 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1834 drm_dbg_dp(ctrl->drm_dev,
1835 "using phy test link parameters\n");
1836 if (!pixel_rate)
1837 pixel_rate = phy_cts_pixel_clk_khz;
1838 } else {
1839 ctrl->link->link_params.rate = rate;
1840 ctrl->link->link_params.num_lanes =
1841 ctrl->panel->link_info.num_lanes;
1842 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
1843 pixel_rate >>= 1;
1844 }
1845
1846 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1847 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
1848 pixel_rate);
1849
1850 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
1851 if (rc)
1852 return rc;
1853
1854 while (--link_train_max_retries) {
1855 training_step = DP_TRAINING_NONE;
1856 rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step);
1857 if (rc == 0) {
1858 /* training completed successfully */
1859 break;
1860 } else if (training_step == DP_TRAINING_1) {
1861 /* link train_1 failed */
1862 if (!msm_dp_catalog_link_is_connected(ctrl->catalog))
1863 break;
1864
1865 msm_dp_ctrl_read_link_status(ctrl, link_status);
1866
1867 rc = msm_dp_ctrl_link_rate_down_shift(ctrl);
1868 if (rc < 0) { /* already in RBR = 1.6G */
1869 if (msm_dp_ctrl_clock_recovery_any_ok(link_status,
1870 ctrl->link->link_params.num_lanes)) {
1871 /*
1872 * some lanes are ready,
1873 * reduce lane number
1874 */
1875 rc = msm_dp_ctrl_link_lane_down_shift(ctrl);
1876 if (rc < 0) { /* lane == 1 already */
1877 /* end with failure */
1878 break;
1879 }
1880 } else {
1881 /* end with failure */
1882 break; /* lane == 1 already */
1883 }
1884 }
1885 } else if (training_step == DP_TRAINING_2) {
1886 /* link train_2 failed */
1887 if (!msm_dp_catalog_link_is_connected(ctrl->catalog))
1888 break;
1889
1890 msm_dp_ctrl_read_link_status(ctrl, link_status);
1891
1892 if (!drm_dp_clock_recovery_ok(link_status,
1893 ctrl->link->link_params.num_lanes))
1894 rc = msm_dp_ctrl_link_rate_down_shift(ctrl);
1895 else
1896 rc = msm_dp_ctrl_link_lane_down_shift(ctrl);
1897
1898 if (rc < 0) {
1899 /* end with failure */
1900 break; /* lane == 1 already */
1901 }
1902
1903 /* stop link training before start re training */
1904 msm_dp_ctrl_clear_training_pattern(ctrl);
1905 }
1906
1907 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl);
1908 if (rc) {
1909 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc);
1910 break;
1911 }
1912 }
1913
1914 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1915 return rc;
1916
1917 if (rc == 0) { /* link train successfully */
1918 /*
1919 * do not stop train pattern here
1920 * stop link training at on_stream
1921 * to pass compliance test
1922 */
1923 } else {
1924 /*
1925 * link training failed
1926 * end txing train pattern here
1927 */
1928 msm_dp_ctrl_clear_training_pattern(ctrl);
1929
1930 msm_dp_ctrl_deinitialize_mainlink(ctrl);
1931 rc = -ECONNRESET;
1932 }
1933
1934 return rc;
1935}
1936
1937static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl)
1938{
1939 int training_step = DP_TRAINING_NONE;
1940
1941 return msm_dp_ctrl_setup_main_link(ctrl, &training_step);
1942}
1943
1944int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train)
1945{
1946 int ret = 0;
1947 bool mainlink_ready = false;
1948 struct msm_dp_ctrl_private *ctrl;
1949 unsigned long pixel_rate;
1950 unsigned long pixel_rate_orig;
1951
1952 if (!msm_dp_ctrl)
1953 return -EINVAL;
1954
1955 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1956
1957 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock;
1958
1959 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
1960 pixel_rate >>= 1;
1961
1962 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1963 ctrl->link->link_params.rate,
1964 ctrl->link->link_params.num_lanes, pixel_rate);
1965
1966 drm_dbg_dp(ctrl->drm_dev,
1967 "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n",
1968 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on);
1969
1970 if (!ctrl->link_clks_on) { /* link clk is off */
1971 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
1972 if (ret) {
1973 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1974 goto end;
1975 }
1976 }
1977
1978 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
1979 if (ret) {
1980 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
1981 goto end;
1982 }
1983
1984 if (ctrl->stream_clks_on) {
1985 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
1986 } else {
1987 ret = clk_prepare_enable(ctrl->pixel_clk);
1988 if (ret) {
1989 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1990 goto end;
1991 }
1992 ctrl->stream_clks_on = true;
1993 }
1994
1995 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl))
1996 msm_dp_ctrl_link_retrain(ctrl);
1997
1998 /* stop txing train pattern to end link training */
1999 msm_dp_ctrl_clear_training_pattern(ctrl);
2000
2001 /*
2002 * Set up transfer unit values and set controller state to send
2003 * video.
2004 */
2005 reinit_completion(&ctrl->video_comp);
2006
2007 msm_dp_ctrl_configure_source_params(ctrl);
2008
2009 msm_dp_catalog_ctrl_config_msa(ctrl->catalog,
2010 ctrl->link->link_params.rate,
2011 pixel_rate_orig,
2012 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420);
2013
2014 msm_dp_ctrl_setup_tr_unit(ctrl);
2015
2016 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
2017
2018 ret = msm_dp_ctrl_wait4video_ready(ctrl);
2019 if (ret)
2020 return ret;
2021
2022 mainlink_ready = msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
2023 drm_dbg_dp(ctrl->drm_dev,
2024 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
2025
2026end:
2027 return ret;
2028}
2029
2030void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl)
2031{
2032 struct msm_dp_ctrl_private *ctrl;
2033 struct phy *phy;
2034
2035 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2036 phy = ctrl->phy;
2037
2038 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog);
2039
2040 /* set dongle to D3 (power off) mode */
2041 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
2042
2043 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
2044
2045 if (ctrl->stream_clks_on) {
2046 clk_disable_unprepare(ctrl->pixel_clk);
2047 ctrl->stream_clks_on = false;
2048 }
2049
2050 dev_pm_opp_set_rate(ctrl->dev, 0);
2051 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2052
2053 phy_power_off(phy);
2054
2055 /* aux channel down, reinit phy */
2056 phy_exit(phy);
2057 phy_init(phy);
2058
2059 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2060 phy, phy->init_count, phy->power_count);
2061}
2062
2063void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl)
2064{
2065 struct msm_dp_ctrl_private *ctrl;
2066 struct phy *phy;
2067
2068 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2069 phy = ctrl->phy;
2070
2071 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
2072
2073 dev_pm_opp_set_rate(ctrl->dev, 0);
2074 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2075
2076 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
2077 phy, phy->init_count, phy->power_count);
2078
2079 phy_power_off(phy);
2080
2081 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
2082 phy, phy->init_count, phy->power_count);
2083}
2084
2085void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl)
2086{
2087 struct msm_dp_ctrl_private *ctrl;
2088 struct phy *phy;
2089
2090 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2091 phy = ctrl->phy;
2092
2093 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog);
2094
2095 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
2096
2097 msm_dp_catalog_ctrl_reset(ctrl->catalog);
2098
2099 if (ctrl->stream_clks_on) {
2100 clk_disable_unprepare(ctrl->pixel_clk);
2101 ctrl->stream_clks_on = false;
2102 }
2103
2104 dev_pm_opp_set_rate(ctrl->dev, 0);
2105 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2106
2107 phy_power_off(phy);
2108 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2109 phy, phy->init_count, phy->power_count);
2110}
2111
2112irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl)
2113{
2114 struct msm_dp_ctrl_private *ctrl;
2115 u32 isr;
2116 irqreturn_t ret = IRQ_NONE;
2117
2118 if (!msm_dp_ctrl)
2119 return IRQ_NONE;
2120
2121 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2122
2123 if (ctrl->panel->psr_cap.version) {
2124 isr = msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog);
2125
2126 if (isr)
2127 complete(&ctrl->psr_op_comp);
2128
2129 if (isr & PSR_EXIT_INT)
2130 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
2131
2132 if (isr & PSR_UPDATE_INT)
2133 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
2134
2135 if (isr & PSR_CAPTURE_INT)
2136 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
2137 }
2138
2139 isr = msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog);
2140
2141
2142 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2143 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2144 complete(&ctrl->video_comp);
2145 ret = IRQ_HANDLED;
2146 }
2147
2148 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2149 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2150 complete(&ctrl->idle_comp);
2151 ret = IRQ_HANDLED;
2152 }
2153
2154 return ret;
2155}
2156
2157static const char *core_clks[] = {
2158 "core_iface",
2159 "core_aux",
2160};
2161
2162static const char *ctrl_clks[] = {
2163 "ctrl_link",
2164 "ctrl_link_iface",
2165};
2166
2167static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl)
2168{
2169 struct msm_dp_ctrl_private *ctrl;
2170 struct device *dev;
2171 int i, rc;
2172
2173 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2174 dev = ctrl->dev;
2175
2176 ctrl->num_core_clks = ARRAY_SIZE(core_clks);
2177 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL);
2178 if (!ctrl->core_clks)
2179 return -ENOMEM;
2180
2181 for (i = 0; i < ctrl->num_core_clks; i++)
2182 ctrl->core_clks[i].id = core_clks[i];
2183
2184 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks);
2185 if (rc)
2186 return rc;
2187
2188 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks);
2189 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL);
2190 if (!ctrl->link_clks)
2191 return -ENOMEM;
2192
2193 for (i = 0; i < ctrl->num_link_clks; i++)
2194 ctrl->link_clks[i].id = ctrl_clks[i];
2195
2196 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks);
2197 if (rc)
2198 return rc;
2199
2200 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel");
2201 if (IS_ERR(ctrl->pixel_clk))
2202 return PTR_ERR(ctrl->pixel_clk);
2203
2204 return 0;
2205}
2206
2207struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link,
2208 struct msm_dp_panel *panel, struct drm_dp_aux *aux,
2209 struct msm_dp_catalog *catalog,
2210 struct phy *phy)
2211{
2212 struct msm_dp_ctrl_private *ctrl;
2213 int ret;
2214
2215 if (!dev || !panel || !aux ||
2216 !link || !catalog) {
2217 DRM_ERROR("invalid input\n");
2218 return ERR_PTR(-EINVAL);
2219 }
2220
2221 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2222 if (!ctrl) {
2223 DRM_ERROR("Mem allocation failure\n");
2224 return ERR_PTR(-ENOMEM);
2225 }
2226
2227 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
2228 if (ret) {
2229 dev_err(dev, "invalid DP OPP table in device tree\n");
2230 /* caller do PTR_ERR(opp_table) */
2231 return (struct msm_dp_ctrl *)ERR_PTR(ret);
2232 }
2233
2234 /* OPP table is optional */
2235 ret = devm_pm_opp_of_add_table(dev);
2236 if (ret)
2237 dev_err(dev, "failed to add DP OPP table\n");
2238
2239 init_completion(&ctrl->idle_comp);
2240 init_completion(&ctrl->psr_op_comp);
2241 init_completion(&ctrl->video_comp);
2242
2243 /* in parameters */
2244 ctrl->panel = panel;
2245 ctrl->aux = aux;
2246 ctrl->link = link;
2247 ctrl->catalog = catalog;
2248 ctrl->dev = dev;
2249 ctrl->phy = phy;
2250
2251 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl);
2252 if (ret) {
2253 dev_err(dev, "failed to init clocks\n");
2254 return ERR_PTR(ret);
2255 }
2256
2257 return &ctrl->msm_dp_ctrl;
2258}