1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 5 * Copyright (C) 2013 Red Hat
 6 * Author: Rob Clark <robdclark@gmail.com>
 7 */
 8
 9#ifndef __DPU_ENCODER_H__
10#define __DPU_ENCODER_H__
11
12#include <drm/drm_crtc.h>
13#include "dpu_hw_mdss.h"
14
15#define DPU_ENCODER_FRAME_EVENT_DONE			BIT(0)
16#define DPU_ENCODER_FRAME_EVENT_ERROR			BIT(1)
17#define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD		BIT(2)
18#define DPU_ENCODER_FRAME_EVENT_IDLE			BIT(3)
19
20#define IDLE_TIMEOUT	(66 - 16/2)
21
22#define MAX_H_TILES_PER_DISPLAY 2
23
24/**
25 * struct msm_display_info - defines display properties
26 * @intf_type:          INTF_ type
27 * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
28 * @h_tile_instance:    Controller instance used per tile. Number of elements is
29 *                      based on num_of_h_tiles
30 * @is_cmd_mode		Boolean to indicate if the CMD mode is requested
31 * @vsync_source:	Source of the TE signal for DSI CMD devices
32 */
33struct msm_display_info {
34	enum dpu_intf_type intf_type;
35	uint32_t num_of_h_tiles;
36	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
37	bool is_cmd_mode;
38	enum dpu_vsync_source vsync_source;
39};
40
41void dpu_encoder_assign_crtc(struct drm_encoder *encoder,
42			     struct drm_crtc *crtc);
43
44void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder,
45					struct drm_crtc *crtc, bool enable);
46
47void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
48
49void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
50
51void dpu_encoder_kickoff(struct drm_encoder *encoder);
52
53int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time);
54
55int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
56
57int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder);
58
59enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder);
60
61void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder);
62
63struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
64		int drm_enc_mode,
65		struct msm_display_info *disp_info);
66
67int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
68
69int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
70
71bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
72
73bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc);
74
75int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc);
76
77void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder);
78
79int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos);
80
81bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc);
82
83void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
84		struct drm_writeback_job *job);
85
86void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
87		struct drm_writeback_job *job);
88
89bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
90
91#endif /* __DPU_ENCODER_H__ */