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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9#include "adreno_gpu.h"
10#include "a6xx_gpu.h"
11#include "a6xx.xml.h"
12#include "a6xx_gmu.xml.h"
13
14static const struct adreno_reglist a612_hwcg[] = {
15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
61 {},
62};
63
64/* For a615 family (a615, a616, a618 and a619) */
65static const struct adreno_reglist a615_hwcg[] = {
66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
129 {},
130};
131
132static const struct adreno_reglist a620_hwcg[] = {
133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
134 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
135 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
136 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
137 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
138 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
139 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
140 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
141 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
142 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
143 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
144 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
145 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
146 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
147 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
148 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
149 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
150 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
151 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
152 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
153 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
154 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
155 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
156 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
157 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
158 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
159 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
160 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
161 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
162 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
163 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
164 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
165 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
166 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
167 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
168 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
169 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
170 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
171 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
172 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
173 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
174 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
175 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
176 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
177 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
178 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
179 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
180 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
181 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
182 {},
183};
184
185static const struct adreno_reglist a630_hwcg[] = {
186 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
187 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
188 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
189 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
190 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
191 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
192 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
193 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
194 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
195 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
196 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
197 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
198 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
199 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
200 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
201 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
202 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
203 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
204 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
205 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
206 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
207 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
208 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
209 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
210 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
211 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
212 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
213 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
214 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
215 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
216 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
217 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
218 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
219 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
220 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
221 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
222 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
223 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
224 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
225 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
226 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
227 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
228 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
229 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
230 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
231 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
232 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
233 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
234 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
235 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
236 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
237 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
238 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
239 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
240 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
241 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
242 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
243 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
244 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
245 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
246 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
247 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
248 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
249 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
250 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
251 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
252 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
253 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
254 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
255 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
256 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
257 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
258 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
259 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
260 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
261 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
262 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
263 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
264 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
265 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
266 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
267 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
268 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
269 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
270 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
271 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
272 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
273 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
274 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
275 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
276 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
277 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
278 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
279 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
280 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
281 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
282 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
283 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
284 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
285 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
286 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
287 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
291 {},
292};
293
294static const struct adreno_reglist a640_hwcg[] = {
295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
344 {},
345};
346
347static const struct adreno_reglist a650_hwcg[] = {
348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
397 {},
398};
399
400static const struct adreno_reglist a660_hwcg[] = {
401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
444 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
445 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
446 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
447 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
448 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
449 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
450 {},
451};
452
453static const struct adreno_reglist a690_hwcg[] = {
454 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
456 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
457 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
458 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
459 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
460 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
461 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
462 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
463 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
464 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
465 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
466 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
467 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
468 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
469 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
470 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
471 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
472 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
473 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
474 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
475 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
476 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
477 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
478 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
479 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
480 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
481 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
482 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
483 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
484 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
485 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
486 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
487 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
488 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
489 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
490 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
491 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
492 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
493 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
494 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
495 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
496 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
497 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
498 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
499 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
500 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
501 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
502 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
503 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
504 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
505 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
506 {}
507};
508
509/* For a615, a616, a618, a619, a630, a640 and a680 */
510static const u32 a630_protect_regs[] = {
511 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
512 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
513 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
514 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
515 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
516 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
517 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
518 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
519 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
520 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
521 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
522 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
523 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
524 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
525 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
526 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
527 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
528 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
529 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
530 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
531 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
532 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
533 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
534 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
535 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
536 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
537 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
538 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
539 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
540 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
541 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
542 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
543};
544DECLARE_ADRENO_PROTECT(a630_protect, 32);
545
546static const u32 a650_protect_regs[] = {
547 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
548 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
549 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
550 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
551 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
552 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
553 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
554 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
555 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
556 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
557 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
558 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
559 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
560 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
561 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
562 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
563 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
564 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
565 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
566 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
567 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
568 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
569 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
570 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
571 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
572 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
573 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
574 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
575 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
576 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
577 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
578 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
579 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
580 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
581 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
582 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
583 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
584 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
585 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
586};
587DECLARE_ADRENO_PROTECT(a650_protect, 48);
588
589/* These are for a635 and a660 */
590static const u32 a660_protect_regs[] = {
591 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
592 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
593 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
594 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
595 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
596 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
597 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
598 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
599 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
600 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
601 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
602 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
603 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
604 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
605 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
606 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
607 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
608 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
609 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
610 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
611 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
612 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
613 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
614 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
615 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
616 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
617 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
618 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
619 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
620 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
621 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
622 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
623 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
624 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
625 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
626 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
627 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
628 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
629 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
630 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
631 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
632};
633DECLARE_ADRENO_PROTECT(a660_protect, 48);
634
635/* These are for a690 */
636static const u32 a690_protect_regs[] = {
637 A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
638 A6XX_PROTECT_RDONLY(0x00501, 0x00001),
639 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
640 A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
641 A6XX_PROTECT_NORDWR(0x00510, 0x00000),
642 A6XX_PROTECT_NORDWR(0x00534, 0x00000),
643 A6XX_PROTECT_NORDWR(0x00800, 0x00082),
644 A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
645 A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
646 A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
647 A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
648 A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
649 A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
650 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
651 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
652 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
653 A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
654 A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
655 A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
656 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
657 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
658 A6XX_PROTECT_NORDWR(0x09624, 0x001db),
659 A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
660 A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
661 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
662 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
663 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
664 A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
665 A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
666 A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
667 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
668 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
669 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
670 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
671 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
672};
673DECLARE_ADRENO_PROTECT(a690_protect, 48);
674
675static const struct adreno_info a6xx_gpus[] = {
676 {
677 .chip_ids = ADRENO_CHIP_IDS(0x06010000),
678 .family = ADRENO_6XX_GEN1,
679 .revn = 610,
680 .fw = {
681 [ADRENO_FW_SQE] = "a630_sqe.fw",
682 },
683 .gmem = (SZ_128K + SZ_4K),
684 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
685 .init = a6xx_gpu_init,
686 .zapfw = "a610_zap.mdt",
687 .a6xx = &(const struct a6xx_info) {
688 .hwcg = a612_hwcg,
689 .protect = &a630_protect,
690 .gmu_cgc_mode = 0x00020202,
691 .prim_fifo_threshold = 0x00080000,
692 },
693 /*
694 * There are (at least) three SoCs implementing A610: SM6125
695 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
696 * not have speedbinning, as only a single SKU exists and we
697 * don't support khaje upstream yet. Hence, this matching
698 * table is only valid for bengal.
699 */
700 .speedbins = ADRENO_SPEEDBINS(
701 { 0, 0 },
702 { 206, 1 },
703 { 200, 2 },
704 { 157, 3 },
705 { 127, 4 },
706 ),
707 }, {
708 .chip_ids = ADRENO_CHIP_IDS(0x06010500),
709 .family = ADRENO_6XX_GEN1,
710 .revn = 615,
711 .fw = {
712 [ADRENO_FW_SQE] = "a630_sqe.fw",
713 [ADRENO_FW_GMU] = "a630_gmu.bin",
714 },
715 .gmem = SZ_512K,
716 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
717 .init = a6xx_gpu_init,
718 .zapfw = "a615_zap.mdt",
719 .a6xx = &(const struct a6xx_info) {
720 .hwcg = a615_hwcg,
721 .protect = &a630_protect,
722 .gmu_cgc_mode = 0x00000222,
723 .prim_fifo_threshold = 0x0018000,
724 },
725 .speedbins = ADRENO_SPEEDBINS(
726 /*
727 * The default speed bin (0) has the same values as
728 * speed bin 90 which goes up to 432 MHz.
729 */
730 { 0, 0 },
731 { 90, 0 },
732 { 105, 1 },
733 { 146, 2 },
734 { 163, 3 },
735 ),
736 }, {
737 .machine = "qcom,sm7150",
738 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
739 .family = ADRENO_6XX_GEN1,
740 .fw = {
741 [ADRENO_FW_SQE] = "a630_sqe.fw",
742 [ADRENO_FW_GMU] = "a630_gmu.bin",
743 },
744 .gmem = SZ_512K,
745 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
746 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
747 .init = a6xx_gpu_init,
748 .zapfw = "a615_zap.mbn",
749 .a6xx = &(const struct a6xx_info) {
750 .hwcg = a615_hwcg,
751 .protect = &a630_protect,
752 .gmu_cgc_mode = 0x00000222,
753 .prim_fifo_threshold = 0x00180000,
754 },
755 .speedbins = ADRENO_SPEEDBINS(
756 { 0, 0 },
757 { 128, 1 },
758 { 146, 2 },
759 { 167, 3 },
760 { 172, 4 },
761 ),
762 }, {
763 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
764 .family = ADRENO_6XX_GEN1,
765 .revn = 618,
766 .fw = {
767 [ADRENO_FW_SQE] = "a630_sqe.fw",
768 [ADRENO_FW_GMU] = "a630_gmu.bin",
769 },
770 .gmem = SZ_512K,
771 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
772 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
773 .init = a6xx_gpu_init,
774 .a6xx = &(const struct a6xx_info) {
775 .protect = &a630_protect,
776 .gmu_cgc_mode = 0x00000222,
777 .prim_fifo_threshold = 0x00180000,
778 },
779 .speedbins = ADRENO_SPEEDBINS(
780 { 0, 0 },
781 { 169, 1 },
782 { 174, 2 },
783 ),
784 }, {
785 .machine = "qcom,sm4350",
786 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
787 .family = ADRENO_6XX_GEN1,
788 .revn = 619,
789 .fw = {
790 [ADRENO_FW_SQE] = "a630_sqe.fw",
791 [ADRENO_FW_GMU] = "a619_gmu.bin",
792 },
793 .gmem = SZ_512K,
794 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
795 .init = a6xx_gpu_init,
796 .zapfw = "a615_zap.mdt",
797 .a6xx = &(const struct a6xx_info) {
798 .hwcg = a615_hwcg,
799 .protect = &a630_protect,
800 .gmu_cgc_mode = 0x00000222,
801 .prim_fifo_threshold = 0x00018000,
802 },
803 .speedbins = ADRENO_SPEEDBINS(
804 { 0, 0 },
805 { 138, 1 },
806 { 92, 2 },
807 ),
808 }, {
809 .machine = "qcom,sm6375",
810 .chip_ids = ADRENO_CHIP_IDS(0x06010901),
811 .family = ADRENO_6XX_GEN1,
812 .revn = 619,
813 .fw = {
814 [ADRENO_FW_SQE] = "a630_sqe.fw",
815 [ADRENO_FW_GMU] = "a619_gmu.bin",
816 },
817 .gmem = SZ_512K,
818 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
819 .init = a6xx_gpu_init,
820 .zapfw = "a615_zap.mdt",
821 .a6xx = &(const struct a6xx_info) {
822 .hwcg = a615_hwcg,
823 .protect = &a630_protect,
824 .gmu_cgc_mode = 0x00000222,
825 .prim_fifo_threshold = 0x00018000,
826 },
827 .speedbins = ADRENO_SPEEDBINS(
828 { 0, 0 },
829 { 190, 1 },
830 { 177, 2 },
831 ),
832 }, {
833 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
834 .family = ADRENO_6XX_GEN1,
835 .revn = 619,
836 .fw = {
837 [ADRENO_FW_SQE] = "a630_sqe.fw",
838 [ADRENO_FW_GMU] = "a619_gmu.bin",
839 },
840 .gmem = SZ_512K,
841 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
842 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
843 .init = a6xx_gpu_init,
844 .zapfw = "a615_zap.mdt",
845 .a6xx = &(const struct a6xx_info) {
846 .hwcg = a615_hwcg,
847 .protect = &a630_protect,
848 .gmu_cgc_mode = 0x00000222,
849 .prim_fifo_threshold = 0x00018000,
850 },
851 .speedbins = ADRENO_SPEEDBINS(
852 { 0, 0 },
853 { 120, 4 },
854 { 138, 3 },
855 { 169, 2 },
856 { 180, 1 },
857 ),
858 }, {
859 .chip_ids = ADRENO_CHIP_IDS(0x06020100),
860 .family = ADRENO_6XX_GEN3,
861 .fw = {
862 [ADRENO_FW_SQE] = "a650_sqe.fw",
863 [ADRENO_FW_GMU] = "a621_gmu.bin",
864 },
865 .gmem = SZ_512K,
866 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
867 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
868 ADRENO_QUIRK_HAS_HW_APRIV,
869 .init = a6xx_gpu_init,
870 .zapfw = "a620_zap.mbn",
871 .a6xx = &(const struct a6xx_info) {
872 .hwcg = a620_hwcg,
873 .protect = &a650_protect,
874 .gmu_cgc_mode = 0x00020200,
875 .prim_fifo_threshold = 0x00010000,
876 },
877 .address_space_size = SZ_16G,
878 .speedbins = ADRENO_SPEEDBINS(
879 { 0, 0 },
880 { 137, 1 },
881 ),
882 }, {
883 .chip_ids = ADRENO_CHIP_IDS(
884 0x06030001,
885 0x06030002
886 ),
887 .family = ADRENO_6XX_GEN1,
888 .revn = 630,
889 .fw = {
890 [ADRENO_FW_SQE] = "a630_sqe.fw",
891 [ADRENO_FW_GMU] = "a630_gmu.bin",
892 },
893 .gmem = SZ_1M,
894 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
895 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
896 .init = a6xx_gpu_init,
897 .zapfw = "a630_zap.mdt",
898 .a6xx = &(const struct a6xx_info) {
899 .hwcg = a630_hwcg,
900 .protect = &a630_protect,
901 .gmu_cgc_mode = 0x00020202,
902 .prim_fifo_threshold = 0x00180000,
903 },
904 }, {
905 .chip_ids = ADRENO_CHIP_IDS(0x06040001),
906 .family = ADRENO_6XX_GEN2,
907 .revn = 640,
908 .fw = {
909 [ADRENO_FW_SQE] = "a630_sqe.fw",
910 [ADRENO_FW_GMU] = "a640_gmu.bin",
911 },
912 .gmem = SZ_1M,
913 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
914 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
915 .init = a6xx_gpu_init,
916 .zapfw = "a640_zap.mdt",
917 .a6xx = &(const struct a6xx_info) {
918 .hwcg = a640_hwcg,
919 .protect = &a630_protect,
920 .gmu_cgc_mode = 0x00020202,
921 .prim_fifo_threshold = 0x00180000,
922 },
923 .speedbins = ADRENO_SPEEDBINS(
924 { 0, 0 },
925 { 1, 1 },
926 ),
927 }, {
928 .chip_ids = ADRENO_CHIP_IDS(0x06050002),
929 .family = ADRENO_6XX_GEN3,
930 .revn = 650,
931 .fw = {
932 [ADRENO_FW_SQE] = "a650_sqe.fw",
933 [ADRENO_FW_GMU] = "a650_gmu.bin",
934 },
935 .gmem = SZ_1M + SZ_128K,
936 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
937 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
938 ADRENO_QUIRK_HAS_HW_APRIV,
939 .init = a6xx_gpu_init,
940 .zapfw = "a650_zap.mdt",
941 .a6xx = &(const struct a6xx_info) {
942 .hwcg = a650_hwcg,
943 .protect = &a650_protect,
944 .gmu_cgc_mode = 0x00020202,
945 .prim_fifo_threshold = 0x00300200,
946 },
947 .address_space_size = SZ_16G,
948 .speedbins = ADRENO_SPEEDBINS(
949 { 0, 0 },
950 { 1, 1 },
951 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
952 { 3, 2 },
953 ),
954 }, {
955 .chip_ids = ADRENO_CHIP_IDS(0x06060001),
956 .family = ADRENO_6XX_GEN4,
957 .revn = 660,
958 .fw = {
959 [ADRENO_FW_SQE] = "a660_sqe.fw",
960 [ADRENO_FW_GMU] = "a660_gmu.bin",
961 },
962 .gmem = SZ_1M + SZ_512K,
963 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
964 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
965 ADRENO_QUIRK_HAS_HW_APRIV,
966 .init = a6xx_gpu_init,
967 .zapfw = "a660_zap.mdt",
968 .a6xx = &(const struct a6xx_info) {
969 .hwcg = a660_hwcg,
970 .protect = &a660_protect,
971 .gmu_cgc_mode = 0x00020000,
972 .prim_fifo_threshold = 0x00300200,
973 },
974 .address_space_size = SZ_16G,
975 }, {
976 .chip_ids = ADRENO_CHIP_IDS(0x06060300),
977 .family = ADRENO_6XX_GEN4,
978 .fw = {
979 [ADRENO_FW_SQE] = "a660_sqe.fw",
980 [ADRENO_FW_GMU] = "a663_gmu.bin",
981 },
982 .gmem = SZ_1M + SZ_512K,
983 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
984 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
985 ADRENO_QUIRK_HAS_HW_APRIV,
986 .init = a6xx_gpu_init,
987 .a6xx = &(const struct a6xx_info) {
988 .hwcg = a690_hwcg,
989 .protect = &a660_protect,
990 .gmu_cgc_mode = 0x00020200,
991 .prim_fifo_threshold = 0x00300200,
992 },
993 .address_space_size = SZ_16G,
994 }, {
995 .chip_ids = ADRENO_CHIP_IDS(0x06030500),
996 .family = ADRENO_6XX_GEN4,
997 .fw = {
998 [ADRENO_FW_SQE] = "a660_sqe.fw",
999 [ADRENO_FW_GMU] = "a660_gmu.bin",
1000 },
1001 .gmem = SZ_512K,
1002 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1003 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1004 ADRENO_QUIRK_HAS_HW_APRIV,
1005 .init = a6xx_gpu_init,
1006 .zapfw = "a660_zap.mbn",
1007 .a6xx = &(const struct a6xx_info) {
1008 .hwcg = a660_hwcg,
1009 .protect = &a660_protect,
1010 .gmu_cgc_mode = 0x00020202,
1011 .prim_fifo_threshold = 0x00200200,
1012 },
1013 .address_space_size = SZ_16G,
1014 .speedbins = ADRENO_SPEEDBINS(
1015 { 0, 0 },
1016 { 117, 0 },
1017 { 129, 4 },
1018 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
1019 { 190, 1 },
1020 ),
1021 }, {
1022 .chip_ids = ADRENO_CHIP_IDS(0x06080001),
1023 .family = ADRENO_6XX_GEN2,
1024 .revn = 680,
1025 .fw = {
1026 [ADRENO_FW_SQE] = "a630_sqe.fw",
1027 [ADRENO_FW_GMU] = "a640_gmu.bin",
1028 },
1029 .gmem = SZ_2M,
1030 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1031 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
1032 .init = a6xx_gpu_init,
1033 .zapfw = "a640_zap.mdt",
1034 .a6xx = &(const struct a6xx_info) {
1035 .hwcg = a640_hwcg,
1036 .protect = &a630_protect,
1037 .gmu_cgc_mode = 0x00020202,
1038 .prim_fifo_threshold = 0x00200200,
1039 },
1040 }, {
1041 .chip_ids = ADRENO_CHIP_IDS(0x06090000),
1042 .family = ADRENO_6XX_GEN4,
1043 .fw = {
1044 [ADRENO_FW_SQE] = "a660_sqe.fw",
1045 [ADRENO_FW_GMU] = "a660_gmu.bin",
1046 },
1047 .gmem = SZ_4M,
1048 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1049 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1050 ADRENO_QUIRK_HAS_HW_APRIV,
1051 .init = a6xx_gpu_init,
1052 .zapfw = "a690_zap.mdt",
1053 .a6xx = &(const struct a6xx_info) {
1054 .hwcg = a690_hwcg,
1055 .protect = &a690_protect,
1056 .gmu_cgc_mode = 0x00020200,
1057 .prim_fifo_threshold = 0x00800200,
1058 },
1059 .address_space_size = SZ_16G,
1060 }
1061};
1062DECLARE_ADRENO_GPULIST(a6xx);
1063
1064MODULE_FIRMWARE("qcom/a615_zap.mbn");
1065MODULE_FIRMWARE("qcom/a619_gmu.bin");
1066MODULE_FIRMWARE("qcom/a630_sqe.fw");
1067MODULE_FIRMWARE("qcom/a630_gmu.bin");
1068MODULE_FIRMWARE("qcom/a630_zap.mbn");
1069MODULE_FIRMWARE("qcom/a640_gmu.bin");
1070MODULE_FIRMWARE("qcom/a650_gmu.bin");
1071MODULE_FIRMWARE("qcom/a650_sqe.fw");
1072MODULE_FIRMWARE("qcom/a660_gmu.bin");
1073MODULE_FIRMWARE("qcom/a660_sqe.fw");
1074
1075static const struct adreno_reglist a702_hwcg[] = {
1076 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
1077 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
1078 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
1079 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1080 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
1081 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1082 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1083 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
1084 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1085 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1086 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1087 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1088 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1089 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1090 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1091 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1092 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1093 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
1094 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1095 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
1096 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
1097 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
1098 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1099 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
1100 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1101 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1102 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
1103 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1104 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1105 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1106 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1107 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1108 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1109 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1110 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1111 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1112 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1113 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1114 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1115 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1116 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1117 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1118 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1119 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1120 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1121 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1122 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
1123 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
1124 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
1125 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
1126 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
1127 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
1128 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
1129 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
1130 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
1131 {}
1132};
1133
1134static const struct adreno_reglist a730_hwcg[] = {
1135 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1136 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
1137 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1138 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1139 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1140 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1141 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1142 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1143 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1144 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1145 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1146 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1147 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1148 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1149 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1150 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1151 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1152 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1153 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1154 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1155 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1156 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1157 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1158 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1159 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1160 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1161 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1162 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1163 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1164 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1165 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1166 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1167 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1168 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1169 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1170 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1171 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1172 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1173 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1174 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1175 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1176 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1177 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1178 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1179 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1180 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
1181 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1182 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1183 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1184 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1185 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1186 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1187 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1188 {},
1189};
1190
1191static const struct adreno_reglist a740_hwcg[] = {
1192 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1193 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
1194 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
1195 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1196 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1197 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1198 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1199 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1200 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1201 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1202 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1203 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1204 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1205 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1206 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1207 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1208 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1209 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
1210 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
1211 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
1212 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1213 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1214 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1215 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1216 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1217 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1218 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1219 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1220 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1221 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1222 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1223 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1224 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
1225 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1226 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1227 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1228 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1229 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1230 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
1231 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1232 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
1233 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1234 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1235 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1236 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1237 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
1238 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
1239 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1240 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1241 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1242 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1243 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1244 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1245 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1246 {},
1247};
1248
1249static const u32 a730_protect_regs[] = {
1250 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1251 A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1252 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1253 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1254 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1255 A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1256 A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1257 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1258 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1259 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
1260 A6XX_PROTECT_NORDWR(0x008de, 0x0001),
1261 A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
1262 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1263 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1264 A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1265 A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1266 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1267 A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1268 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1269 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1270 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1271 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1272 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1273 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1274 A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1275 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1276 A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1277 A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1278 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1279 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1280 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1281 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1282 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1283 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1284 A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1285 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1286 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1287 A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1288 A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1289 A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1290 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1291 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1292 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1293 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1294 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1295 A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1296 /* CP_PROTECT_REG[45, 46] are left untouched! */
1297 0,
1298 0,
1299 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1300};
1301DECLARE_ADRENO_PROTECT(a730_protect, 48);
1302
1303static const uint32_t a7xx_pwrup_reglist_regs[] = {
1304 REG_A6XX_UCHE_TRAP_BASE,
1305 REG_A6XX_UCHE_TRAP_BASE + 1,
1306 REG_A6XX_UCHE_WRITE_THRU_BASE,
1307 REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
1308 REG_A6XX_UCHE_GMEM_RANGE_MIN,
1309 REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
1310 REG_A6XX_UCHE_GMEM_RANGE_MAX,
1311 REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
1312 REG_A6XX_UCHE_CACHE_WAYS,
1313 REG_A6XX_UCHE_MODE_CNTL,
1314 REG_A6XX_RB_NC_MODE_CNTL,
1315 REG_A6XX_RB_CMP_DBG_ECO_CNTL,
1316 REG_A7XX_GRAS_NC_MODE_CNTL,
1317 REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
1318 REG_A6XX_UCHE_GBIF_GX_CONFIG,
1319 REG_A6XX_UCHE_CLIENT_PF,
1320 REG_A6XX_TPL1_DBG_ECO_CNTL1,
1321};
1322
1323DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
1324
1325static const struct adreno_info a7xx_gpus[] = {
1326 {
1327 .chip_ids = ADRENO_CHIP_IDS(0x07000200),
1328 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
1329 .fw = {
1330 [ADRENO_FW_SQE] = "a702_sqe.fw",
1331 },
1332 .gmem = SZ_128K,
1333 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1334 .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
1335 .init = a6xx_gpu_init,
1336 .zapfw = "a702_zap.mbn",
1337 .a6xx = &(const struct a6xx_info) {
1338 .hwcg = a702_hwcg,
1339 .protect = &a650_protect,
1340 .gmu_cgc_mode = 0x00020202,
1341 .prim_fifo_threshold = 0x0000c000,
1342 },
1343 .speedbins = ADRENO_SPEEDBINS(
1344 { 0, 0 },
1345 { 236, 1 },
1346 { 178, 2 },
1347 { 142, 3 },
1348 ),
1349 }, {
1350 .chip_ids = ADRENO_CHIP_IDS(0x07030001),
1351 .family = ADRENO_7XX_GEN1,
1352 .fw = {
1353 [ADRENO_FW_SQE] = "a730_sqe.fw",
1354 [ADRENO_FW_GMU] = "gmu_gen70000.bin",
1355 },
1356 .gmem = SZ_2M,
1357 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1358 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1359 ADRENO_QUIRK_HAS_HW_APRIV |
1360 ADRENO_QUIRK_PREEMPTION,
1361 .init = a6xx_gpu_init,
1362 .zapfw = "a730_zap.mdt",
1363 .a6xx = &(const struct a6xx_info) {
1364 .hwcg = a730_hwcg,
1365 .protect = &a730_protect,
1366 .pwrup_reglist = &a7xx_pwrup_reglist,
1367 .gmu_cgc_mode = 0x00020000,
1368 },
1369 .address_space_size = SZ_16G,
1370 .preempt_record_size = 2860 * SZ_1K,
1371 }, {
1372 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
1373 .family = ADRENO_7XX_GEN2,
1374 .fw = {
1375 [ADRENO_FW_SQE] = "a740_sqe.fw",
1376 [ADRENO_FW_GMU] = "gmu_gen70200.bin",
1377 },
1378 .gmem = 3 * SZ_1M,
1379 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1380 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1381 ADRENO_QUIRK_HAS_HW_APRIV |
1382 ADRENO_QUIRK_PREEMPTION,
1383 .init = a6xx_gpu_init,
1384 .zapfw = "a740_zap.mdt",
1385 .a6xx = &(const struct a6xx_info) {
1386 .hwcg = a740_hwcg,
1387 .protect = &a730_protect,
1388 .pwrup_reglist = &a7xx_pwrup_reglist,
1389 .gmu_chipid = 0x7020100,
1390 .gmu_cgc_mode = 0x00020202,
1391 },
1392 .address_space_size = SZ_16G,
1393 .preempt_record_size = 4192 * SZ_1K,
1394 }, {
1395 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
1396 .family = ADRENO_7XX_GEN2,
1397 .fw = {
1398 [ADRENO_FW_SQE] = "gen70500_sqe.fw",
1399 [ADRENO_FW_GMU] = "gen70500_gmu.bin",
1400 },
1401 .gmem = 3 * SZ_1M,
1402 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1403 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1404 ADRENO_QUIRK_HAS_HW_APRIV |
1405 ADRENO_QUIRK_PREEMPTION,
1406 .init = a6xx_gpu_init,
1407 .a6xx = &(const struct a6xx_info) {
1408 .hwcg = a740_hwcg,
1409 .protect = &a730_protect,
1410 .pwrup_reglist = &a7xx_pwrup_reglist,
1411 .gmu_chipid = 0x7050001,
1412 .gmu_cgc_mode = 0x00020202,
1413 },
1414 .address_space_size = SZ_256G,
1415 .preempt_record_size = 4192 * SZ_1K,
1416 }, {
1417 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
1418 .family = ADRENO_7XX_GEN3,
1419 .fw = {
1420 [ADRENO_FW_SQE] = "gen70900_sqe.fw",
1421 [ADRENO_FW_GMU] = "gmu_gen70900.bin",
1422 },
1423 .gmem = 3 * SZ_1M,
1424 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1425 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1426 ADRENO_QUIRK_HAS_HW_APRIV |
1427 ADRENO_QUIRK_PREEMPTION,
1428 .init = a6xx_gpu_init,
1429 .zapfw = "gen70900_zap.mbn",
1430 .a6xx = &(const struct a6xx_info) {
1431 .protect = &a730_protect,
1432 .pwrup_reglist = &a7xx_pwrup_reglist,
1433 .gmu_chipid = 0x7090100,
1434 .gmu_cgc_mode = 0x00020202,
1435 },
1436 .address_space_size = SZ_16G,
1437 .preempt_record_size = 3572 * SZ_1K,
1438 }
1439};
1440DECLARE_ADRENO_GPULIST(a7xx);
1441
1442static inline __always_unused void __build_asserts(void)
1443{
1444 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
1445 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
1446 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
1447 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
1448 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
1449}