Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright © 2018-2020 Intel Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/module.h>
8#include <linux/of_graph.h>
9#include <linux/of_platform.h>
10#include <linux/of_reserved_mem.h>
11#include <linux/mfd/syscon.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_client_setup.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_fbdev_dma.h>
20#include <drm/drm_gem_dma_helper.h>
21#include <drm/drm_gem_framebuffer_helper.h>
22#include <drm/drm_module.h>
23#include <drm/drm_probe_helper.h>
24#include <drm/drm_vblank.h>
25
26#include "kmb_drv.h"
27#include "kmb_dsi.h"
28#include "kmb_regs.h"
29
30static int kmb_display_clk_enable(struct kmb_drm_private *kmb)
31{
32 int ret = 0;
33
34 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd);
35 if (ret) {
36 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret);
37 return ret;
38 }
39 DRM_INFO("SUCCESS : enabled LCD clocks\n");
40 return 0;
41}
42
43static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev)
44{
45 int ret = 0;
46 struct regmap *msscam;
47
48 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd");
49 if (IS_ERR(kmb->kmb_clk.clk_lcd)) {
50 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n");
51 return PTR_ERR(kmb->kmb_clk.clk_lcd);
52 }
53
54 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0");
55 if (IS_ERR(kmb->kmb_clk.clk_pll0)) {
56 drm_err(&kmb->drm, "clk_get() failed clk_pll0 ");
57 return PTR_ERR(kmb->kmb_clk.clk_pll0);
58 }
59 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000;
60 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz);
61
62 ret = kmb_dsi_clk_init(kmb->kmb_dsi);
63
64 /* Set LCD clock to 200 Mhz */
65 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK);
66 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) {
67 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n",
68 KMB_LCD_DEFAULT_CLK);
69 return -1;
70 }
71 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd));
72
73 ret = kmb_display_clk_enable(kmb);
74 if (ret)
75 return ret;
76
77 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
78 if (IS_ERR(msscam)) {
79 drm_err(&kmb->drm, "failed to get msscam syscon");
80 return -1;
81 }
82
83 /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
84 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff);
85 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff);
86 return 0;
87}
88
89static void kmb_display_clk_disable(struct kmb_drm_private *kmb)
90{
91 clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
92}
93
94static void __iomem *kmb_map_mmio(struct drm_device *drm,
95 struct platform_device *pdev,
96 char *name)
97{
98 struct resource *res;
99 void __iomem *mem;
100
101 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
102 if (!res) {
103 drm_err(drm, "failed to get resource for %s", name);
104 return ERR_PTR(-ENOMEM);
105 }
106 mem = devm_ioremap_resource(drm->dev, res);
107 if (IS_ERR(mem))
108 drm_err(drm, "failed to ioremap %s registers", name);
109 return mem;
110}
111
112static int kmb_hw_init(struct drm_device *drm, unsigned long flags)
113{
114 struct kmb_drm_private *kmb = to_kmb(drm);
115 struct platform_device *pdev = to_platform_device(drm->dev);
116 int irq_lcd;
117 int ret = 0;
118
119 /* Map LCD MMIO registers */
120 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd");
121 if (IS_ERR(kmb->lcd_mmio)) {
122 drm_err(&kmb->drm, "failed to map LCD registers\n");
123 return -ENOMEM;
124 }
125
126 /* Map MIPI MMIO registers */
127 ret = kmb_dsi_map_mmio(kmb->kmb_dsi);
128 if (ret)
129 return ret;
130
131 /* Enable display clocks */
132 kmb_initialize_clocks(kmb, &pdev->dev);
133
134 /* Register irqs here - section 17.3 in databook
135 * lists LCD at 79 and 82 for MIPI under MSS CPU -
136 * firmware has redirected 79 to A53 IRQ 33
137 */
138
139 /* Allocate LCD interrupt resources */
140 irq_lcd = platform_get_irq(pdev, 0);
141 if (irq_lcd < 0) {
142 ret = irq_lcd;
143 drm_err(&kmb->drm, "irq_lcd not found");
144 goto setup_fail;
145 }
146
147 /* Get the optional framebuffer memory resource */
148 ret = of_reserved_mem_device_init(drm->dev);
149 if (ret && ret != -ENODEV)
150 return ret;
151
152 spin_lock_init(&kmb->irq_lock);
153
154 kmb->irq_lcd = irq_lcd;
155
156 return 0;
157
158 setup_fail:
159 of_reserved_mem_device_release(drm->dev);
160
161 return ret;
162}
163
164static const struct drm_mode_config_funcs kmb_mode_config_funcs = {
165 .fb_create = drm_gem_fb_create,
166 .atomic_check = drm_atomic_helper_check,
167 .atomic_commit = drm_atomic_helper_commit,
168};
169
170static int kmb_setup_mode_config(struct drm_device *drm)
171{
172 int ret;
173 struct kmb_drm_private *kmb = to_kmb(drm);
174
175 ret = drmm_mode_config_init(drm);
176 if (ret)
177 return ret;
178 drm->mode_config.min_width = KMB_FB_MIN_WIDTH;
179 drm->mode_config.min_height = KMB_FB_MIN_HEIGHT;
180 drm->mode_config.max_width = KMB_FB_MAX_WIDTH;
181 drm->mode_config.max_height = KMB_FB_MAX_HEIGHT;
182 drm->mode_config.preferred_depth = 24;
183 drm->mode_config.funcs = &kmb_mode_config_funcs;
184
185 ret = kmb_setup_crtc(drm);
186 if (ret < 0) {
187 drm_err(drm, "failed to create crtc\n");
188 return ret;
189 }
190 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi);
191 /* Set the CRTC's port so that the encoder component can find it */
192 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0);
193 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
194 if (ret < 0) {
195 drm_err(drm, "failed to initialize vblank\n");
196 pm_runtime_disable(drm->dev);
197 return ret;
198 }
199
200 drm_mode_config_reset(drm);
201 return 0;
202}
203
204static irqreturn_t handle_lcd_irq(struct drm_device *dev)
205{
206 unsigned long status, val, val1;
207 int plane_id, dma0_state, dma1_state;
208 struct kmb_drm_private *kmb = to_kmb(dev);
209 u32 ctrl = 0;
210
211 status = kmb_read_lcd(kmb, LCD_INT_STATUS);
212
213 spin_lock(&kmb->irq_lock);
214 if (status & LCD_INT_EOF) {
215 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF);
216
217 /* When disabling/enabling LCD layers, the change takes effect
218 * immediately and does not wait for EOF (end of frame).
219 * When kmb_plane_atomic_disable is called, mark the plane as
220 * disabled but actually disable the plane when EOF irq is
221 * being handled.
222 */
223 for (plane_id = LAYER_0;
224 plane_id < KMB_MAX_PLANES; plane_id++) {
225 if (kmb->plane_status[plane_id].disable) {
226 kmb_clr_bitmask_lcd(kmb,
227 LCD_LAYERn_DMA_CFG
228 (plane_id),
229 LCD_DMA_LAYER_ENABLE);
230
231 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
232 kmb->plane_status[plane_id].ctrl);
233
234 ctrl = kmb_read_lcd(kmb, LCD_CONTROL);
235 if (!(ctrl & (LCD_CTRL_VL1_ENABLE |
236 LCD_CTRL_VL2_ENABLE |
237 LCD_CTRL_GL1_ENABLE |
238 LCD_CTRL_GL2_ENABLE))) {
239 /* If no LCD layers are using DMA,
240 * then disable DMA pipelined AXI read
241 * transactions.
242 */
243 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
244 LCD_CTRL_PIPELINE_DMA);
245 }
246
247 kmb->plane_status[plane_id].disable = false;
248 }
249 }
250 if (kmb->kmb_under_flow) {
251 /* DMA Recovery after underflow */
252 dma0_state = (kmb->layer_no == 0) ?
253 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE;
254 dma1_state = (kmb->layer_no == 0) ?
255 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE;
256
257 do {
258 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
259 val = kmb_read_lcd(kmb, dma0_state)
260 & LCD_DMA_STATE_ACTIVE;
261 val1 = kmb_read_lcd(kmb, dma1_state)
262 & LCD_DMA_STATE_ACTIVE;
263 } while ((val || val1));
264 /* disable dma */
265 kmb_clr_bitmask_lcd(kmb,
266 LCD_LAYERn_DMA_CFG(kmb->layer_no),
267 LCD_DMA_LAYER_ENABLE);
268 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
269 kmb->kmb_flush_done = 1;
270 kmb->kmb_under_flow = 0;
271 }
272 }
273
274 if (status & LCD_INT_LINE_CMP) {
275 /* clear line compare interrupt */
276 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
277 }
278
279 if (status & LCD_INT_VERT_COMP) {
280 /* Read VSTATUS */
281 val = kmb_read_lcd(kmb, LCD_VSTATUS);
282 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
283 switch (val) {
284 case LCD_VSTATUS_COMPARE_VSYNC:
285 /* Clear vertical compare interrupt */
286 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
287 if (kmb->kmb_flush_done) {
288 kmb_set_bitmask_lcd(kmb,
289 LCD_LAYERn_DMA_CFG
290 (kmb->layer_no),
291 LCD_DMA_LAYER_ENABLE);
292 kmb->kmb_flush_done = 0;
293 }
294 drm_crtc_handle_vblank(&kmb->crtc);
295 break;
296 case LCD_VSTATUS_COMPARE_BACKPORCH:
297 case LCD_VSTATUS_COMPARE_ACTIVE:
298 case LCD_VSTATUS_COMPARE_FRONT_PORCH:
299 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
300 break;
301 }
302 }
303 if (status & LCD_INT_DMA_ERR) {
304 val =
305 (status & LCD_INT_DMA_ERR &
306 kmb_read_lcd(kmb, LCD_INT_ENABLE));
307 /* LAYER0 - VL0 */
308 if (val & (LAYER0_DMA_FIFO_UNDERFLOW |
309 LAYER0_DMA_CB_FIFO_UNDERFLOW |
310 LAYER0_DMA_CR_FIFO_UNDERFLOW)) {
311 kmb->kmb_under_flow++;
312 drm_info(&kmb->drm,
313 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d",
314 val, kmb->kmb_under_flow);
315 /* disable underflow interrupt */
316 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
317 LAYER0_DMA_FIFO_UNDERFLOW |
318 LAYER0_DMA_CB_FIFO_UNDERFLOW |
319 LAYER0_DMA_CR_FIFO_UNDERFLOW);
320 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
321 LAYER0_DMA_CB_FIFO_UNDERFLOW |
322 LAYER0_DMA_FIFO_UNDERFLOW |
323 LAYER0_DMA_CR_FIFO_UNDERFLOW);
324 /* disable auto restart mode */
325 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0),
326 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
327
328 kmb->layer_no = 0;
329 }
330
331 if (val & LAYER0_DMA_FIFO_OVERFLOW)
332 drm_dbg(&kmb->drm,
333 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val);
334 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW)
335 drm_dbg(&kmb->drm,
336 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val);
337 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW)
338 drm_dbg(&kmb->drm,
339 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val);
340
341 /* LAYER1 - VL1 */
342 if (val & (LAYER1_DMA_FIFO_UNDERFLOW |
343 LAYER1_DMA_CB_FIFO_UNDERFLOW |
344 LAYER1_DMA_CR_FIFO_UNDERFLOW)) {
345 kmb->kmb_under_flow++;
346 drm_info(&kmb->drm,
347 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d",
348 val, kmb->kmb_under_flow);
349 /* disable underflow interrupt */
350 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
351 LAYER1_DMA_FIFO_UNDERFLOW |
352 LAYER1_DMA_CB_FIFO_UNDERFLOW |
353 LAYER1_DMA_CR_FIFO_UNDERFLOW);
354 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
355 LAYER1_DMA_CB_FIFO_UNDERFLOW |
356 LAYER1_DMA_FIFO_UNDERFLOW |
357 LAYER1_DMA_CR_FIFO_UNDERFLOW);
358 /* disable auto restart mode */
359 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1),
360 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
361 kmb->layer_no = 1;
362 }
363
364 /* LAYER1 - VL1 */
365 if (val & LAYER1_DMA_FIFO_OVERFLOW)
366 drm_dbg(&kmb->drm,
367 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val);
368 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW)
369 drm_dbg(&kmb->drm,
370 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val);
371 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW)
372 drm_dbg(&kmb->drm,
373 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val);
374
375 /* LAYER2 - GL0 */
376 if (val & LAYER2_DMA_FIFO_UNDERFLOW)
377 drm_dbg(&kmb->drm,
378 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val);
379 if (val & LAYER2_DMA_FIFO_OVERFLOW)
380 drm_dbg(&kmb->drm,
381 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val);
382
383 /* LAYER3 - GL1 */
384 if (val & LAYER3_DMA_FIFO_UNDERFLOW)
385 drm_dbg(&kmb->drm,
386 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
387 if (val & LAYER3_DMA_FIFO_OVERFLOW)
388 drm_dbg(&kmb->drm,
389 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
390 }
391
392 spin_unlock(&kmb->irq_lock);
393
394 if (status & LCD_INT_LAYER) {
395 /* Clear layer interrupts */
396 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER);
397 }
398
399 /* Clear all interrupts */
400 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1);
401 return IRQ_HANDLED;
402}
403
404/* IRQ handler */
405static irqreturn_t kmb_isr(int irq, void *arg)
406{
407 struct drm_device *dev = (struct drm_device *)arg;
408
409 handle_lcd_irq(dev);
410 return IRQ_HANDLED;
411}
412
413static void kmb_irq_reset(struct drm_device *drm)
414{
415 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF);
416 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0);
417}
418
419static int kmb_irq_install(struct drm_device *drm, unsigned int irq)
420{
421 if (irq == IRQ_NOTCONNECTED)
422 return -ENOTCONN;
423
424 kmb_irq_reset(drm);
425
426 return request_irq(irq, kmb_isr, 0, drm->driver->name, drm);
427}
428
429static void kmb_irq_uninstall(struct drm_device *drm)
430{
431 struct kmb_drm_private *kmb = to_kmb(drm);
432
433 kmb_irq_reset(drm);
434 free_irq(kmb->irq_lcd, drm);
435}
436
437DEFINE_DRM_GEM_DMA_FOPS(fops);
438
439static const struct drm_driver kmb_driver = {
440 .driver_features = DRIVER_GEM |
441 DRIVER_MODESET | DRIVER_ATOMIC,
442 /* GEM Operations */
443 .fops = &fops,
444 DRM_GEM_DMA_DRIVER_OPS_VMAP,
445 DRM_FBDEV_DMA_DRIVER_OPS,
446 .name = "kmb-drm",
447 .desc = "KEEMBAY DISPLAY DRIVER",
448 .date = DRIVER_DATE,
449 .major = DRIVER_MAJOR,
450 .minor = DRIVER_MINOR,
451};
452
453static void kmb_remove(struct platform_device *pdev)
454{
455 struct device *dev = &pdev->dev;
456 struct drm_device *drm = dev_get_drvdata(dev);
457 struct kmb_drm_private *kmb = to_kmb(drm);
458
459 drm_dev_unregister(drm);
460 drm_kms_helper_poll_fini(drm);
461 of_node_put(kmb->crtc.port);
462 kmb->crtc.port = NULL;
463 pm_runtime_get_sync(drm->dev);
464 kmb_irq_uninstall(drm);
465 pm_runtime_put_sync(drm->dev);
466 pm_runtime_disable(drm->dev);
467
468 of_reserved_mem_device_release(drm->dev);
469
470 /* Release clks */
471 kmb_display_clk_disable(kmb);
472
473 dev_set_drvdata(dev, NULL);
474
475 /* Unregister DSI host */
476 kmb_dsi_host_unregister(kmb->kmb_dsi);
477 drm_atomic_helper_shutdown(drm);
478}
479
480static int kmb_probe(struct platform_device *pdev)
481{
482 struct device *dev = get_device(&pdev->dev);
483 struct kmb_drm_private *kmb;
484 int ret = 0;
485 struct device_node *dsi_in;
486 struct device_node *dsi_node;
487 struct platform_device *dsi_pdev;
488
489 /* The bridge (ADV 7535) will return -EPROBE_DEFER until it
490 * has a mipi_dsi_host to register its device to. So, we
491 * first register the DSI host during probe time, and then return
492 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again
493 * and then the rest of the driver initialization can proceed
494 * afterwards and the bridge can be successfully attached.
495 */
496 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
497 if (!dsi_in) {
498 DRM_ERROR("Failed to get dsi_in node info from DT");
499 return -EINVAL;
500 }
501 dsi_node = of_graph_get_remote_port_parent(dsi_in);
502 if (!dsi_node) {
503 of_node_put(dsi_in);
504 DRM_ERROR("Failed to get dsi node from DT\n");
505 return -EINVAL;
506 }
507
508 dsi_pdev = of_find_device_by_node(dsi_node);
509 if (!dsi_pdev) {
510 of_node_put(dsi_in);
511 of_node_put(dsi_node);
512 DRM_ERROR("Failed to get dsi platform device\n");
513 return -EINVAL;
514 }
515
516 of_node_put(dsi_in);
517 of_node_put(dsi_node);
518 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev));
519
520 if (ret == -EPROBE_DEFER) {
521 return -EPROBE_DEFER;
522 } else if (ret) {
523 DRM_ERROR("probe failed to initialize DSI host bridge\n");
524 return ret;
525 }
526
527 /* Create DRM device */
528 kmb = devm_drm_dev_alloc(dev, &kmb_driver,
529 struct kmb_drm_private, drm);
530 if (IS_ERR(kmb))
531 return PTR_ERR(kmb);
532
533 dev_set_drvdata(dev, &kmb->drm);
534
535 /* Initialize MIPI DSI */
536 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev);
537 if (IS_ERR(kmb->kmb_dsi)) {
538 drm_err(&kmb->drm, "failed to initialize DSI\n");
539 ret = PTR_ERR(kmb->kmb_dsi);
540 goto err_free1;
541 }
542
543 kmb->kmb_dsi->dev = &dsi_pdev->dev;
544 kmb->kmb_dsi->pdev = dsi_pdev;
545 ret = kmb_hw_init(&kmb->drm, 0);
546 if (ret)
547 goto err_free1;
548
549 ret = kmb_setup_mode_config(&kmb->drm);
550 if (ret)
551 goto err_free;
552
553 ret = kmb_irq_install(&kmb->drm, kmb->irq_lcd);
554 if (ret < 0) {
555 drm_err(&kmb->drm, "failed to install IRQ handler\n");
556 goto err_irq;
557 }
558
559 drm_kms_helper_poll_init(&kmb->drm);
560
561 /* Register graphics device with the kernel */
562 ret = drm_dev_register(&kmb->drm, 0);
563 if (ret)
564 goto err_register;
565
566 drm_client_setup(&kmb->drm, NULL);
567
568 return 0;
569
570 err_register:
571 drm_kms_helper_poll_fini(&kmb->drm);
572 err_irq:
573 pm_runtime_disable(kmb->drm.dev);
574 err_free:
575 drm_crtc_cleanup(&kmb->crtc);
576 drm_mode_config_cleanup(&kmb->drm);
577 err_free1:
578 dev_set_drvdata(dev, NULL);
579 kmb_dsi_host_unregister(kmb->kmb_dsi);
580
581 return ret;
582}
583
584static const struct of_device_id kmb_of_match[] = {
585 {.compatible = "intel,keembay-display"},
586 {},
587};
588
589MODULE_DEVICE_TABLE(of, kmb_of_match);
590
591static int __maybe_unused kmb_pm_suspend(struct device *dev)
592{
593 struct drm_device *drm = dev_get_drvdata(dev);
594 struct kmb_drm_private *kmb = to_kmb(drm);
595
596 drm_kms_helper_poll_disable(drm);
597
598 kmb->state = drm_atomic_helper_suspend(drm);
599 if (IS_ERR(kmb->state)) {
600 drm_kms_helper_poll_enable(drm);
601 return PTR_ERR(kmb->state);
602 }
603
604 return 0;
605}
606
607static int __maybe_unused kmb_pm_resume(struct device *dev)
608{
609 struct drm_device *drm = dev_get_drvdata(dev);
610 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL;
611
612 if (!kmb)
613 return 0;
614
615 drm_atomic_helper_resume(drm, kmb->state);
616 drm_kms_helper_poll_enable(drm);
617
618 return 0;
619}
620
621static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume);
622
623static struct platform_driver kmb_platform_driver = {
624 .probe = kmb_probe,
625 .remove = kmb_remove,
626 .driver = {
627 .name = "kmb-drm",
628 .pm = &kmb_pm_ops,
629 .of_match_table = kmb_of_match,
630 },
631};
632
633drm_module_platform_driver(kmb_platform_driver);
634
635MODULE_AUTHOR("Intel Corporation");
636MODULE_DESCRIPTION("Keembay Display driver");
637MODULE_LICENSE("GPL v2");