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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX drm driver - Television Encoder (TVEv2)
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/regulator/consumer.h>
16#include <linux/videodev2.h>
17
18#include <video/imx-ipu-v3.h>
19
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_edid.h>
22#include <drm/drm_managed.h>
23#include <drm/drm_probe_helper.h>
24#include <drm/drm_simple_kms_helper.h>
25
26#include "imx-drm.h"
27
28#define TVE_COM_CONF_REG 0x00
29#define TVE_TVDAC0_CONT_REG 0x28
30#define TVE_TVDAC1_CONT_REG 0x2c
31#define TVE_TVDAC2_CONT_REG 0x30
32#define TVE_CD_CONT_REG 0x34
33#define TVE_INT_CONT_REG 0x64
34#define TVE_STAT_REG 0x68
35#define TVE_TST_MODE_REG 0x6c
36#define TVE_MV_CONT_REG 0xdc
37
38/* TVE_COM_CONF_REG */
39#define TVE_SYNC_CH_2_EN BIT(22)
40#define TVE_SYNC_CH_1_EN BIT(21)
41#define TVE_SYNC_CH_0_EN BIT(20)
42#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
43#define TVE_TV_OUT_DISABLE (0x0 << 12)
44#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
45#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
46#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
47#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
48#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
49#define TVE_TV_OUT_YPBPR (0x6 << 12)
50#define TVE_TV_OUT_RGB (0x7 << 12)
51#define TVE_TV_STAND_MASK (0xf << 8)
52#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
53#define TVE_P2I_CONV_EN BIT(7)
54#define TVE_INP_VIDEO_FORM BIT(6)
55#define TVE_INP_YCBCR_422 (0x0 << 6)
56#define TVE_INP_YCBCR_444 (0x1 << 6)
57#define TVE_DATA_SOURCE_MASK (0x3 << 4)
58#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
59#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
60#define TVE_DATA_SOURCE_EXT (0x2 << 4)
61#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
62#define TVE_IPU_CLK_EN_OFS 3
63#define TVE_IPU_CLK_EN BIT(3)
64#define TVE_DAC_SAMP_RATE_OFS 1
65#define TVE_DAC_SAMP_RATE_WIDTH 2
66#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
67#define TVE_DAC_FULL_RATE (0x0 << 1)
68#define TVE_DAC_DIV2_RATE (0x1 << 1)
69#define TVE_DAC_DIV4_RATE (0x2 << 1)
70#define TVE_EN BIT(0)
71
72/* TVE_TVDACx_CONT_REG */
73#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
74
75/* TVE_CD_CONT_REG */
76#define TVE_CD_CH_2_SM_EN BIT(22)
77#define TVE_CD_CH_1_SM_EN BIT(21)
78#define TVE_CD_CH_0_SM_EN BIT(20)
79#define TVE_CD_CH_2_LM_EN BIT(18)
80#define TVE_CD_CH_1_LM_EN BIT(17)
81#define TVE_CD_CH_0_LM_EN BIT(16)
82#define TVE_CD_CH_2_REF_LVL BIT(10)
83#define TVE_CD_CH_1_REF_LVL BIT(9)
84#define TVE_CD_CH_0_REF_LVL BIT(8)
85#define TVE_CD_EN BIT(0)
86
87/* TVE_INT_CONT_REG */
88#define TVE_FRAME_END_IEN BIT(13)
89#define TVE_CD_MON_END_IEN BIT(2)
90#define TVE_CD_SM_IEN BIT(1)
91#define TVE_CD_LM_IEN BIT(0)
92
93/* TVE_TST_MODE_REG */
94#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
95
96#define IMX_TVE_DAC_VOLTAGE 2750000
97
98enum {
99 TVE_MODE_TVOUT,
100 TVE_MODE_VGA,
101};
102
103struct imx_tve_encoder {
104 struct drm_connector connector;
105 struct drm_encoder encoder;
106 struct imx_tve *tve;
107};
108
109struct imx_tve {
110 struct device *dev;
111 int mode;
112 int di_hsync_pin;
113 int di_vsync_pin;
114
115 struct regmap *regmap;
116 struct regulator *dac_reg;
117 struct i2c_adapter *ddc;
118 struct clk *clk;
119 struct clk *di_sel_clk;
120 struct clk_hw clk_hw_di;
121 struct clk *di_clk;
122};
123
124static inline struct imx_tve *con_to_tve(struct drm_connector *c)
125{
126 return container_of(c, struct imx_tve_encoder, connector)->tve;
127}
128
129static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
130{
131 return container_of(e, struct imx_tve_encoder, encoder)->tve;
132}
133
134static void tve_enable(struct imx_tve *tve)
135{
136 clk_prepare_enable(tve->clk);
137 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
138
139 /* clear interrupt status register */
140 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
141
142 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
143 if (tve->mode == TVE_MODE_VGA)
144 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
145 else
146 regmap_write(tve->regmap, TVE_INT_CONT_REG,
147 TVE_CD_SM_IEN |
148 TVE_CD_LM_IEN |
149 TVE_CD_MON_END_IEN);
150}
151
152static void tve_disable(struct imx_tve *tve)
153{
154 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
155 clk_disable_unprepare(tve->clk);
156}
157
158static int tve_setup_tvout(struct imx_tve *tve)
159{
160 return -ENOTSUPP;
161}
162
163static int tve_setup_vga(struct imx_tve *tve)
164{
165 unsigned int mask;
166 unsigned int val;
167 int ret;
168
169 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
170 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
171 TVE_TVDAC_GAIN_MASK, 0x0a);
172 if (ret)
173 return ret;
174
175 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
176 TVE_TVDAC_GAIN_MASK, 0x0a);
177 if (ret)
178 return ret;
179
180 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
181 TVE_TVDAC_GAIN_MASK, 0x0a);
182 if (ret)
183 return ret;
184
185 /* set configuration register */
186 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
187 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
188 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
189 val |= TVE_TV_STAND_HD_1080P30 | 0;
190 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
191 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
192 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
193 if (ret)
194 return ret;
195
196 /* set test mode (as documented) */
197 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
198 TVE_TVDAC_TEST_MODE_MASK, 1);
199}
200
201static int imx_tve_connector_get_modes(struct drm_connector *connector)
202{
203 struct imx_tve *tve = con_to_tve(connector);
204 const struct drm_edid *drm_edid;
205 int ret;
206
207 if (!tve->ddc)
208 return 0;
209
210 drm_edid = drm_edid_read_ddc(connector, tve->ddc);
211 drm_edid_connector_update(connector, drm_edid);
212 ret = drm_edid_connector_add_modes(connector);
213 drm_edid_free(drm_edid);
214
215 return ret;
216}
217
218static enum drm_mode_status
219imx_tve_connector_mode_valid(struct drm_connector *connector,
220 struct drm_display_mode *mode)
221{
222 struct imx_tve *tve = con_to_tve(connector);
223 unsigned long rate;
224
225 /* pixel clock with 2x oversampling */
226 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
227 if (rate == mode->clock)
228 return MODE_OK;
229
230 /* pixel clock without oversampling */
231 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
232 if (rate == mode->clock)
233 return MODE_OK;
234
235 dev_warn(tve->dev, "ignoring mode %dx%d\n",
236 mode->hdisplay, mode->vdisplay);
237
238 return MODE_BAD;
239}
240
241static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
242 struct drm_display_mode *orig_mode,
243 struct drm_display_mode *mode)
244{
245 struct imx_tve *tve = enc_to_tve(encoder);
246 unsigned long rounded_rate;
247 unsigned long rate;
248 int div = 1;
249 int ret;
250
251 /*
252 * FIXME
253 * we should try 4k * mode->clock first,
254 * and enable 4x oversampling for lower resolutions
255 */
256 rate = 2000UL * mode->clock;
257 clk_set_rate(tve->clk, rate);
258 rounded_rate = clk_get_rate(tve->clk);
259 if (rounded_rate >= rate)
260 div = 2;
261 clk_set_rate(tve->di_clk, rounded_rate / div);
262
263 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
264 if (ret < 0) {
265 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
266 ret);
267 }
268
269 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
270 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
271
272 if (tve->mode == TVE_MODE_VGA)
273 ret = tve_setup_vga(tve);
274 else
275 ret = tve_setup_tvout(tve);
276 if (ret)
277 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
278}
279
280static void imx_tve_encoder_enable(struct drm_encoder *encoder)
281{
282 struct imx_tve *tve = enc_to_tve(encoder);
283
284 tve_enable(tve);
285}
286
287static void imx_tve_encoder_disable(struct drm_encoder *encoder)
288{
289 struct imx_tve *tve = enc_to_tve(encoder);
290
291 tve_disable(tve);
292}
293
294static int imx_tve_atomic_check(struct drm_encoder *encoder,
295 struct drm_crtc_state *crtc_state,
296 struct drm_connector_state *conn_state)
297{
298 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
299 struct imx_tve *tve = enc_to_tve(encoder);
300
301 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
302 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
303 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
304
305 return 0;
306}
307
308static void imx_tve_connector_destroy(struct drm_connector *connector)
309{
310 drm_connector_unregister(connector);
311 drm_connector_cleanup(connector);
312}
313
314static const struct drm_connector_funcs imx_tve_connector_funcs = {
315 .fill_modes = drm_helper_probe_single_connector_modes,
316 .destroy = imx_tve_connector_destroy,
317 .reset = drm_atomic_helper_connector_reset,
318 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
319 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
320};
321
322static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
323 .get_modes = imx_tve_connector_get_modes,
324 .mode_valid = imx_tve_connector_mode_valid,
325};
326
327static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
328 .mode_set = imx_tve_encoder_mode_set,
329 .enable = imx_tve_encoder_enable,
330 .disable = imx_tve_encoder_disable,
331 .atomic_check = imx_tve_atomic_check,
332};
333
334static irqreturn_t imx_tve_irq_handler(int irq, void *data)
335{
336 struct imx_tve *tve = data;
337 unsigned int val;
338
339 regmap_read(tve->regmap, TVE_STAT_REG, &val);
340
341 /* clear interrupt status register */
342 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
343
344 return IRQ_HANDLED;
345}
346
347static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
348 unsigned long parent_rate)
349{
350 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
351 unsigned int val;
352 int ret;
353
354 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
355 if (ret < 0)
356 return 0;
357
358 switch (val & TVE_DAC_SAMP_RATE_MASK) {
359 case TVE_DAC_DIV4_RATE:
360 return parent_rate / 4;
361 case TVE_DAC_DIV2_RATE:
362 return parent_rate / 2;
363 case TVE_DAC_FULL_RATE:
364 default:
365 return parent_rate;
366 }
367
368 return 0;
369}
370
371static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
372 unsigned long *prate)
373{
374 unsigned long div;
375
376 div = *prate / rate;
377 if (div >= 4)
378 return *prate / 4;
379 else if (div >= 2)
380 return *prate / 2;
381 return *prate;
382}
383
384static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
385 unsigned long parent_rate)
386{
387 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
388 unsigned long div;
389 u32 val;
390 int ret;
391
392 div = parent_rate / rate;
393 if (div >= 4)
394 val = TVE_DAC_DIV4_RATE;
395 else if (div >= 2)
396 val = TVE_DAC_DIV2_RATE;
397 else
398 val = TVE_DAC_FULL_RATE;
399
400 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
401 TVE_DAC_SAMP_RATE_MASK, val);
402
403 if (ret < 0) {
404 dev_err(tve->dev, "failed to set divider: %d\n", ret);
405 return ret;
406 }
407
408 return 0;
409}
410
411static const struct clk_ops clk_tve_di_ops = {
412 .round_rate = clk_tve_di_round_rate,
413 .set_rate = clk_tve_di_set_rate,
414 .recalc_rate = clk_tve_di_recalc_rate,
415};
416
417static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
418{
419 const char *tve_di_parent[1];
420 struct clk_init_data init = {
421 .name = "tve_di",
422 .ops = &clk_tve_di_ops,
423 .num_parents = 1,
424 .flags = 0,
425 };
426
427 tve_di_parent[0] = __clk_get_name(tve->clk);
428 init.parent_names = (const char **)&tve_di_parent;
429
430 tve->clk_hw_di.init = &init;
431 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
432 if (IS_ERR(tve->di_clk)) {
433 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
434 PTR_ERR(tve->di_clk));
435 return PTR_ERR(tve->di_clk);
436 }
437
438 return 0;
439}
440
441static void imx_tve_disable_regulator(void *data)
442{
443 struct imx_tve *tve = data;
444
445 regulator_disable(tve->dac_reg);
446}
447
448static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
449{
450 return (reg % 4 == 0) && (reg <= 0xdc);
451}
452
453static struct regmap_config tve_regmap_config = {
454 .reg_bits = 32,
455 .val_bits = 32,
456 .reg_stride = 4,
457
458 .readable_reg = imx_tve_readable_reg,
459
460 .fast_io = true,
461
462 .max_register = 0xdc,
463};
464
465static const char * const imx_tve_modes[] = {
466 [TVE_MODE_TVOUT] = "tvout",
467 [TVE_MODE_VGA] = "vga",
468};
469
470static int of_get_tve_mode(struct device_node *np)
471{
472 const char *bm;
473 int ret, i;
474
475 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
476 if (ret < 0)
477 return ret;
478
479 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
480 if (!strcasecmp(bm, imx_tve_modes[i]))
481 return i;
482
483 return -EINVAL;
484}
485
486static int imx_tve_bind(struct device *dev, struct device *master, void *data)
487{
488 struct drm_device *drm = data;
489 struct imx_tve *tve = dev_get_drvdata(dev);
490 struct imx_tve_encoder *tvee;
491 struct drm_encoder *encoder;
492 struct drm_connector *connector;
493 int encoder_type;
494 int ret;
495
496 encoder_type = tve->mode == TVE_MODE_VGA ?
497 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
498
499 tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
500 encoder_type);
501 if (IS_ERR(tvee))
502 return PTR_ERR(tvee);
503
504 tvee->tve = tve;
505 encoder = &tvee->encoder;
506 connector = &tvee->connector;
507
508 ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
509 if (ret)
510 return ret;
511
512 drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
513
514 drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
515 ret = drm_connector_init_with_ddc(drm, connector,
516 &imx_tve_connector_funcs,
517 DRM_MODE_CONNECTOR_VGA, tve->ddc);
518 if (ret)
519 return ret;
520
521 return drm_connector_attach_encoder(connector, encoder);
522}
523
524static const struct component_ops imx_tve_ops = {
525 .bind = imx_tve_bind,
526};
527
528static int imx_tve_probe(struct platform_device *pdev)
529{
530 struct device *dev = &pdev->dev;
531 struct device_node *np = dev->of_node;
532 struct device_node *ddc_node;
533 struct imx_tve *tve;
534 void __iomem *base;
535 unsigned int val;
536 int irq;
537 int ret;
538
539 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
540 if (!tve)
541 return -ENOMEM;
542
543 tve->dev = dev;
544
545 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
546 if (ddc_node) {
547 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
548 of_node_put(ddc_node);
549 }
550
551 tve->mode = of_get_tve_mode(np);
552 if (tve->mode != TVE_MODE_VGA) {
553 dev_err(dev, "only VGA mode supported, currently\n");
554 return -EINVAL;
555 }
556
557 if (tve->mode == TVE_MODE_VGA) {
558 ret = of_property_read_u32(np, "fsl,hsync-pin",
559 &tve->di_hsync_pin);
560
561 if (ret < 0) {
562 dev_err(dev, "failed to get hsync pin\n");
563 return ret;
564 }
565
566 ret = of_property_read_u32(np, "fsl,vsync-pin",
567 &tve->di_vsync_pin);
568
569 if (ret < 0) {
570 dev_err(dev, "failed to get vsync pin\n");
571 return ret;
572 }
573 }
574
575 base = devm_platform_ioremap_resource(pdev, 0);
576 if (IS_ERR(base))
577 return PTR_ERR(base);
578
579 tve_regmap_config.lock_arg = tve;
580 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
581 &tve_regmap_config);
582 if (IS_ERR(tve->regmap)) {
583 dev_err(dev, "failed to init regmap: %ld\n",
584 PTR_ERR(tve->regmap));
585 return PTR_ERR(tve->regmap);
586 }
587
588 irq = platform_get_irq(pdev, 0);
589 if (irq < 0)
590 return irq;
591
592 ret = devm_request_threaded_irq(dev, irq, NULL,
593 imx_tve_irq_handler, IRQF_ONESHOT,
594 "imx-tve", tve);
595 if (ret < 0) {
596 dev_err(dev, "failed to request irq: %d\n", ret);
597 return ret;
598 }
599
600 tve->dac_reg = devm_regulator_get(dev, "dac");
601 if (!IS_ERR(tve->dac_reg)) {
602 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
603 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
604 ret = regulator_enable(tve->dac_reg);
605 if (ret)
606 return ret;
607 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
608 if (ret)
609 return ret;
610 }
611
612 tve->clk = devm_clk_get(dev, "tve");
613 if (IS_ERR(tve->clk)) {
614 dev_err(dev, "failed to get high speed tve clock: %ld\n",
615 PTR_ERR(tve->clk));
616 return PTR_ERR(tve->clk);
617 }
618
619 /* this is the IPU DI clock input selector, can be parented to tve_di */
620 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
621 if (IS_ERR(tve->di_sel_clk)) {
622 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
623 PTR_ERR(tve->di_sel_clk));
624 return PTR_ERR(tve->di_sel_clk);
625 }
626
627 ret = tve_clk_init(tve, base);
628 if (ret < 0)
629 return ret;
630
631 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
632 if (ret < 0) {
633 dev_err(dev, "failed to read configuration register: %d\n",
634 ret);
635 return ret;
636 }
637 if (val != 0x00100000) {
638 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
639 return -ENODEV;
640 }
641
642 /* disable cable detection for VGA mode */
643 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
644 if (ret)
645 return ret;
646
647 platform_set_drvdata(pdev, tve);
648
649 return component_add(dev, &imx_tve_ops);
650}
651
652static void imx_tve_remove(struct platform_device *pdev)
653{
654 component_del(&pdev->dev, &imx_tve_ops);
655}
656
657static const struct of_device_id imx_tve_dt_ids[] = {
658 { .compatible = "fsl,imx53-tve", },
659 { /* sentinel */ }
660};
661MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
662
663static struct platform_driver imx_tve_driver = {
664 .probe = imx_tve_probe,
665 .remove = imx_tve_remove,
666 .driver = {
667 .of_match_table = imx_tve_dt_ids,
668 .name = "imx-tve",
669 },
670};
671
672module_platform_driver(imx_tve_driver);
673
674MODULE_DESCRIPTION("i.MX Television Encoder driver");
675MODULE_AUTHOR("Philipp Zabel, Pengutronix");
676MODULE_LICENSE("GPL");
677MODULE_ALIAS("platform:imx-tve");