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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
30/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
35 */
36#define INTEL_GMCH_CTRL 0x52
37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
38
39/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
42#define GC_CLOCK_CONTROL_MASK (0xf << 0)
43#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
47#define GCFGC2 0xda
48#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
53#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
72#define LBB 0xf4
73
74/* Graphics reset regs */
75#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
89#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3)
94
95/* VGA stuff */
96
97#define VGA_ST01_MDA 0x3ba
98#define VGA_ST01_CGA 0x3da
99
100#define VGA_MSR_WRITE 0x3c2
101#define VGA_MSR_READ 0x3cc
102#define VGA_MSR_MEM_EN (1<<1)
103#define VGA_MSR_CGA_MODE (1<<0)
104
105#define VGA_SR_INDEX 0x3c4
106#define VGA_SR_DATA 0x3c5
107
108#define VGA_AR_INDEX 0x3c0
109#define VGA_AR_VID_EN (1<<5)
110#define VGA_AR_DATA_WRITE 0x3c0
111#define VGA_AR_DATA_READ 0x3c1
112
113#define VGA_GR_INDEX 0x3ce
114#define VGA_GR_DATA 0x3cf
115/* GR05 */
116#define VGA_GR_MEM_READ_MODE_SHIFT 3
117#define VGA_GR_MEM_READ_MODE_PLANE 1
118/* GR06 */
119#define VGA_GR_MEM_MODE_MASK 0xc
120#define VGA_GR_MEM_MODE_SHIFT 2
121#define VGA_GR_MEM_A0000_AFFFF 0
122#define VGA_GR_MEM_A0000_BFFFF 1
123#define VGA_GR_MEM_B0000_B7FFF 2
124#define VGA_GR_MEM_B0000_BFFFF 3
125
126#define VGA_DACMASK 0x3c6
127#define VGA_DACRX 0x3c7
128#define VGA_DACWX 0x3c8
129#define VGA_DACDATA 0x3c9
130
131#define VGA_CR_INDEX_MDA 0x3b4
132#define VGA_CR_DATA_MDA 0x3b5
133#define VGA_CR_INDEX_CGA 0x3d4
134#define VGA_CR_DATA_CGA 0x3d5
135
136/*
137 * Memory interface instructions used by the kernel
138 */
139#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
140
141#define MI_NOOP MI_INSTR(0, 0)
142#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148#define MI_FLUSH MI_INSTR(0x04, 0)
149#define MI_READ_FLUSH (1 << 0)
150#define MI_EXE_FLUSH (1 << 1)
151#define MI_NO_WRITE_FLUSH (1 << 2)
152#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
155#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21)
163#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
164#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
165#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
166#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
167#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
168#define MI_MM_SPACE_GTT (1<<8)
169#define MI_MM_SPACE_PHYSICAL (0<<8)
170#define MI_SAVE_EXT_STATE_EN (1<<3)
171#define MI_RESTORE_EXT_STATE_EN (1<<2)
172#define MI_FORCE_RESTORE (1<<1)
173#define MI_RESTORE_INHIBIT (1<<0)
174#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
175#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
176#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
177#define MI_STORE_DWORD_INDEX_SHIFT 2
178/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
180 * simply ignores the register load under certain conditions.
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
183 */
184#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
185#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
186#define MI_INVALIDATE_TLB (1<<18)
187#define MI_INVALIDATE_BSD (1<<7)
188#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
189#define MI_BATCH_NON_SECURE (1)
190#define MI_BATCH_NON_SECURE_I965 (1<<8)
191#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
192#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
193#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
194#define MI_SEMAPHORE_UPDATE (1<<21)
195#define MI_SEMAPHORE_COMPARE (1<<20)
196#define MI_SEMAPHORE_REGISTER (1<<18)
197/*
198 * 3D instructions used by the kernel
199 */
200#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201
202#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
203#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
204#define SC_UPDATE_SCISSOR (0x1<<1)
205#define SC_ENABLE_MASK (0x1<<0)
206#define SC_ENABLE (0x1<<0)
207#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
208#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
209#define SCI_YMIN_MASK (0xffff<<16)
210#define SCI_XMIN_MASK (0xffff<<0)
211#define SCI_YMAX_MASK (0xffff<<16)
212#define SCI_XMAX_MASK (0xffff<<0)
213#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
214#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
215#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
216#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
217#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
218#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
219#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
220#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
221#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
222#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
223#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
224#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
225#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
226#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
227#define BLT_DEPTH_8 (0<<24)
228#define BLT_DEPTH_16_565 (1<<24)
229#define BLT_DEPTH_16_1555 (2<<24)
230#define BLT_DEPTH_32 (3<<24)
231#define BLT_ROP_GXCOPY (0xcc<<16)
232#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
233#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
234#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235#define ASYNC_FLIP (1<<22)
236#define DISPLAY_PLANE_A (0<<20)
237#define DISPLAY_PLANE_B (1<<20)
238#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
239#define PIPE_CONTROL_QW_WRITE (1<<14)
240#define PIPE_CONTROL_DEPTH_STALL (1<<13)
241#define PIPE_CONTROL_WC_FLUSH (1<<12)
242#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
243#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
244#define PIPE_CONTROL_ISP_DIS (1<<9)
245#define PIPE_CONTROL_NOTIFY (1<<8)
246#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
247#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
248
249
250/*
251 * Reset registers
252 */
253#define DEBUG_RESET_I830 0x6070
254#define DEBUG_RESET_FULL (1<<7)
255#define DEBUG_RESET_RENDER (1<<8)
256#define DEBUG_RESET_DISPLAY (1<<9)
257
258
259/*
260 * Fence registers
261 */
262#define FENCE_REG_830_0 0x2000
263#define FENCE_REG_945_8 0x3000
264#define I830_FENCE_START_MASK 0x07f80000
265#define I830_FENCE_TILING_Y_SHIFT 12
266#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
267#define I830_FENCE_PITCH_SHIFT 4
268#define I830_FENCE_REG_VALID (1<<0)
269#define I915_FENCE_MAX_PITCH_VAL 4
270#define I830_FENCE_MAX_PITCH_VAL 6
271#define I830_FENCE_MAX_SIZE_VAL (1<<8)
272
273#define I915_FENCE_START_MASK 0x0ff00000
274#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
275
276#define FENCE_REG_965_0 0x03000
277#define I965_FENCE_PITCH_SHIFT 2
278#define I965_FENCE_TILING_Y_SHIFT 1
279#define I965_FENCE_REG_VALID (1<<0)
280#define I965_FENCE_MAX_PITCH_VAL 0x0400
281
282#define FENCE_REG_SANDYBRIDGE_0 0x100000
283#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
284
285/*
286 * Instruction and interrupt control regs
287 */
288#define PGTBL_ER 0x02024
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define BLT_RING_BASE 0x22000
293#define RING_TAIL(base) ((base)+0x30)
294#define RING_HEAD(base) ((base)+0x34)
295#define RING_START(base) ((base)+0x38)
296#define RING_CTL(base) ((base)+0x3c)
297#define RING_SYNC_0(base) ((base)+0x40)
298#define RING_SYNC_1(base) ((base)+0x44)
299#define RING_MAX_IDLE(base) ((base)+0x54)
300#define RING_HWS_PGA(base) ((base)+0x80)
301#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
302#define RENDER_HWS_PGA_GEN7 (0x04080)
303#define BSD_HWS_PGA_GEN7 (0x04180)
304#define BLT_HWS_PGA_GEN7 (0x04280)
305#define RING_ACTHD(base) ((base)+0x74)
306#define RING_NOPID(base) ((base)+0x94)
307#define RING_IMR(base) ((base)+0xa8)
308#define TAIL_ADDR 0x001FFFF8
309#define HEAD_WRAP_COUNT 0xFFE00000
310#define HEAD_WRAP_ONE 0x00200000
311#define HEAD_ADDR 0x001FFFFC
312#define RING_NR_PAGES 0x001FF000
313#define RING_REPORT_MASK 0x00000006
314#define RING_REPORT_64K 0x00000002
315#define RING_REPORT_128K 0x00000004
316#define RING_NO_REPORT 0x00000000
317#define RING_VALID_MASK 0x00000001
318#define RING_VALID 0x00000001
319#define RING_INVALID 0x00000000
320#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
321#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
322#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
323#if 0
324#define PRB0_TAIL 0x02030
325#define PRB0_HEAD 0x02034
326#define PRB0_START 0x02038
327#define PRB0_CTL 0x0203c
328#define PRB1_TAIL 0x02040 /* 915+ only */
329#define PRB1_HEAD 0x02044 /* 915+ only */
330#define PRB1_START 0x02048 /* 915+ only */
331#define PRB1_CTL 0x0204c /* 915+ only */
332#endif
333#define IPEIR_I965 0x02064
334#define IPEHR_I965 0x02068
335#define INSTDONE_I965 0x0206c
336#define INSTPS 0x02070 /* 965+ only */
337#define INSTDONE1 0x0207c /* 965+ only */
338#define ACTHD_I965 0x02074
339#define HWS_PGA 0x02080
340#define HWS_ADDRESS_MASK 0xfffff000
341#define HWS_START_ADDRESS_SHIFT 4
342#define PWRCTXA 0x2088 /* 965GM+ only */
343#define PWRCTX_EN (1<<0)
344#define IPEIR 0x02088
345#define IPEHR 0x0208c
346#define INSTDONE 0x02090
347#define NOPID 0x02094
348#define HWSTAM 0x02098
349#define VCS_INSTDONE 0x1206C
350#define VCS_IPEIR 0x12064
351#define VCS_IPEHR 0x12068
352#define VCS_ACTHD 0x12074
353#define BCS_INSTDONE 0x2206C
354#define BCS_IPEIR 0x22064
355#define BCS_IPEHR 0x22068
356#define BCS_ACTHD 0x22074
357
358#define ERROR_GEN6 0x040a0
359
360/* GM45+ chicken bits -- debug workaround bits that may be required
361 * for various sorts of correct behavior. The top 16 bits of each are
362 * the enables for writing to the corresponding low bit.
363 */
364#define _3D_CHICKEN 0x02084
365#define _3D_CHICKEN2 0x0208c
366/* Disables pipelining of read flushes past the SF-WIZ interface.
367 * Required on all Ironlake steppings according to the B-Spec, but the
368 * particular danger of not doing so is not specified.
369 */
370# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
371#define _3D_CHICKEN3 0x02090
372
373#define MI_MODE 0x0209c
374# define VS_TIMER_DISPATCH (1 << 6)
375# define MI_FLUSH_ENABLE (1 << 11)
376
377#define GFX_MODE 0x02520
378#define GFX_MODE_GEN7 0x0229c
379#define GFX_RUN_LIST_ENABLE (1<<15)
380#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
381#define GFX_SURFACE_FAULT_ENABLE (1<<12)
382#define GFX_REPLAY_MODE (1<<11)
383#define GFX_PSMI_GRANULARITY (1<<10)
384#define GFX_PPGTT_ENABLE (1<<9)
385
386#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
387#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
388
389#define SCPD0 0x0209c /* 915+ only */
390#define IER 0x020a0
391#define IIR 0x020a4
392#define IMR 0x020a8
393#define ISR 0x020ac
394#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
395#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
396#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
397#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
398#define I915_HWB_OOM_INTERRUPT (1<<13)
399#define I915_SYNC_STATUS_INTERRUPT (1<<12)
400#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
401#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
402#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
403#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
404#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
405#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
406#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
407#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
408#define I915_DEBUG_INTERRUPT (1<<2)
409#define I915_USER_INTERRUPT (1<<1)
410#define I915_ASLE_INTERRUPT (1<<0)
411#define I915_BSD_USER_INTERRUPT (1<<25)
412#define EIR 0x020b0
413#define EMR 0x020b4
414#define ESR 0x020b8
415#define GM45_ERROR_PAGE_TABLE (1<<5)
416#define GM45_ERROR_MEM_PRIV (1<<4)
417#define I915_ERROR_PAGE_TABLE (1<<4)
418#define GM45_ERROR_CP_PRIV (1<<3)
419#define I915_ERROR_MEMORY_REFRESH (1<<1)
420#define I915_ERROR_INSTRUCTION (1<<0)
421#define INSTPM 0x020c0
422#define INSTPM_SELF_EN (1<<12) /* 915GM only */
423#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
424 will not assert AGPBUSY# and will only
425 be delivered when out of C3. */
426#define ACTHD 0x020c8
427#define FW_BLC 0x020d8
428#define FW_BLC2 0x020dc
429#define FW_BLC_SELF 0x020e0 /* 915+ only */
430#define FW_BLC_SELF_EN_MASK (1<<31)
431#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
432#define FW_BLC_SELF_EN (1<<15) /* 945 only */
433#define MM_BURST_LENGTH 0x00700000
434#define MM_FIFO_WATERMARK 0x0001F000
435#define LM_BURST_LENGTH 0x00000700
436#define LM_FIFO_WATERMARK 0x0000001F
437#define MI_ARB_STATE 0x020e4 /* 915+ only */
438#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
439
440/* Make render/texture TLB fetches lower priorty than associated data
441 * fetches. This is not turned on by default
442 */
443#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
444
445/* Isoch request wait on GTT enable (Display A/B/C streams).
446 * Make isoch requests stall on the TLB update. May cause
447 * display underruns (test mode only)
448 */
449#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
450
451/* Block grant count for isoch requests when block count is
452 * set to a finite value.
453 */
454#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
455#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
456#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
457#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
458#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
459
460/* Enable render writes to complete in C2/C3/C4 power states.
461 * If this isn't enabled, render writes are prevented in low
462 * power states. That seems bad to me.
463 */
464#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
465
466/* This acknowledges an async flip immediately instead
467 * of waiting for 2TLB fetches.
468 */
469#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
470
471/* Enables non-sequential data reads through arbiter
472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474
475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream
477 */
478#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
479
480/* Arbiter time slice for non-isoch streams */
481#define MI_ARB_TIME_SLICE_MASK (7 << 5)
482#define MI_ARB_TIME_SLICE_1 (0 << 5)
483#define MI_ARB_TIME_SLICE_2 (1 << 5)
484#define MI_ARB_TIME_SLICE_4 (2 << 5)
485#define MI_ARB_TIME_SLICE_6 (3 << 5)
486#define MI_ARB_TIME_SLICE_8 (4 << 5)
487#define MI_ARB_TIME_SLICE_10 (5 << 5)
488#define MI_ARB_TIME_SLICE_14 (6 << 5)
489#define MI_ARB_TIME_SLICE_16 (7 << 5)
490
491/* Low priority grace period page size */
492#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
493#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
494
495/* Disable display A/B trickle feed */
496#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
497
498/* Set display plane priority */
499#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
500#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
501
502#define CACHE_MODE_0 0x02120 /* 915+ only */
503#define CM0_MASK_SHIFT 16
504#define CM0_IZ_OPT_DISABLE (1<<6)
505#define CM0_ZR_OPT_DISABLE (1<<5)
506#define CM0_DEPTH_EVICT_DISABLE (1<<4)
507#define CM0_COLOR_EVICT_DISABLE (1<<3)
508#define CM0_DEPTH_WRITE_DISABLE (1<<1)
509#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
510#define BB_ADDR 0x02140 /* 8 bytes */
511#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
512#define ECOSKPD 0x021d0
513#define ECO_GATING_CX_ONLY (1<<3)
514#define ECO_FLIP_DONE (1<<0)
515
516/* GEN6 interrupt control */
517#define GEN6_RENDER_HWSTAM 0x2098
518#define GEN6_RENDER_IMR 0x20a8
519#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
520#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
521#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
522#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
523#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
524#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
525#define GEN6_RENDER_SYNC_STATUS (1 << 2)
526#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
527#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
528
529#define GEN6_BLITTER_HWSTAM 0x22098
530#define GEN6_BLITTER_IMR 0x220a8
531#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
532#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
533#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
534#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
535
536#define GEN6_BLITTER_ECOSKPD 0x221d0
537#define GEN6_BLITTER_LOCK_SHIFT 16
538#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
539
540#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
541#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
542#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
543#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
544#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
545
546#define GEN6_BSD_HWSTAM 0x12098
547#define GEN6_BSD_IMR 0x120a8
548#define GEN6_BSD_USER_INTERRUPT (1 << 12)
549
550#define GEN6_BSD_RNCID 0x12198
551
552/*
553 * Framebuffer compression (915+ only)
554 */
555
556#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
557#define FBC_LL_BASE 0x03204 /* 4k page aligned */
558#define FBC_CONTROL 0x03208
559#define FBC_CTL_EN (1<<31)
560#define FBC_CTL_PERIODIC (1<<30)
561#define FBC_CTL_INTERVAL_SHIFT (16)
562#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
563#define FBC_CTL_C3_IDLE (1<<13)
564#define FBC_CTL_STRIDE_SHIFT (5)
565#define FBC_CTL_FENCENO (1<<0)
566#define FBC_COMMAND 0x0320c
567#define FBC_CMD_COMPRESS (1<<0)
568#define FBC_STATUS 0x03210
569#define FBC_STAT_COMPRESSING (1<<31)
570#define FBC_STAT_COMPRESSED (1<<30)
571#define FBC_STAT_MODIFIED (1<<29)
572#define FBC_STAT_CURRENT_LINE (1<<0)
573#define FBC_CONTROL2 0x03214
574#define FBC_CTL_FENCE_DBL (0<<4)
575#define FBC_CTL_IDLE_IMM (0<<2)
576#define FBC_CTL_IDLE_FULL (1<<2)
577#define FBC_CTL_IDLE_LINE (2<<2)
578#define FBC_CTL_IDLE_DEBUG (3<<2)
579#define FBC_CTL_CPU_FENCE (1<<1)
580#define FBC_CTL_PLANEA (0<<0)
581#define FBC_CTL_PLANEB (1<<0)
582#define FBC_FENCE_OFF 0x0321b
583#define FBC_TAG 0x03300
584
585#define FBC_LL_SIZE (1536)
586
587/* Framebuffer compression for GM45+ */
588#define DPFC_CB_BASE 0x3200
589#define DPFC_CONTROL 0x3208
590#define DPFC_CTL_EN (1<<31)
591#define DPFC_CTL_PLANEA (0<<30)
592#define DPFC_CTL_PLANEB (1<<30)
593#define DPFC_CTL_FENCE_EN (1<<29)
594#define DPFC_CTL_PERSISTENT_MODE (1<<25)
595#define DPFC_SR_EN (1<<10)
596#define DPFC_CTL_LIMIT_1X (0<<6)
597#define DPFC_CTL_LIMIT_2X (1<<6)
598#define DPFC_CTL_LIMIT_4X (2<<6)
599#define DPFC_RECOMP_CTL 0x320c
600#define DPFC_RECOMP_STALL_EN (1<<27)
601#define DPFC_RECOMP_STALL_WM_SHIFT (16)
602#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
603#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
604#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
605#define DPFC_STATUS 0x3210
606#define DPFC_INVAL_SEG_SHIFT (16)
607#define DPFC_INVAL_SEG_MASK (0x07ff0000)
608#define DPFC_COMP_SEG_SHIFT (0)
609#define DPFC_COMP_SEG_MASK (0x000003ff)
610#define DPFC_STATUS2 0x3214
611#define DPFC_FENCE_YOFF 0x3218
612#define DPFC_CHICKEN 0x3224
613#define DPFC_HT_MODIFY (1<<31)
614
615/* Framebuffer compression for Ironlake */
616#define ILK_DPFC_CB_BASE 0x43200
617#define ILK_DPFC_CONTROL 0x43208
618/* The bit 28-8 is reserved */
619#define DPFC_RESERVED (0x1FFFFF00)
620#define ILK_DPFC_RECOMP_CTL 0x4320c
621#define ILK_DPFC_STATUS 0x43210
622#define ILK_DPFC_FENCE_YOFF 0x43218
623#define ILK_DPFC_CHICKEN 0x43224
624#define ILK_FBC_RT_BASE 0x2128
625#define ILK_FBC_RT_VALID (1<<0)
626
627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21)
630
631
632/*
633 * Framebuffer compression for Sandybridge
634 *
635 * The following two registers are of type GTTMMADR
636 */
637#define SNB_DPFC_CTL_SA 0x100100
638#define SNB_CPU_FENCE_ENABLE (1<<29)
639#define DPFC_CPU_FENCE_OFFSET 0x100104
640
641
642/*
643 * GPIO regs
644 */
645#define GPIOA 0x5010
646#define GPIOB 0x5014
647#define GPIOC 0x5018
648#define GPIOD 0x501c
649#define GPIOE 0x5020
650#define GPIOF 0x5024
651#define GPIOG 0x5028
652#define GPIOH 0x502c
653# define GPIO_CLOCK_DIR_MASK (1 << 0)
654# define GPIO_CLOCK_DIR_IN (0 << 1)
655# define GPIO_CLOCK_DIR_OUT (1 << 1)
656# define GPIO_CLOCK_VAL_MASK (1 << 2)
657# define GPIO_CLOCK_VAL_OUT (1 << 3)
658# define GPIO_CLOCK_VAL_IN (1 << 4)
659# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
660# define GPIO_DATA_DIR_MASK (1 << 8)
661# define GPIO_DATA_DIR_IN (0 << 9)
662# define GPIO_DATA_DIR_OUT (1 << 9)
663# define GPIO_DATA_VAL_MASK (1 << 10)
664# define GPIO_DATA_VAL_OUT (1 << 11)
665# define GPIO_DATA_VAL_IN (1 << 12)
666# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
667
668#define GMBUS0 0x5100 /* clock/port select */
669#define GMBUS_RATE_100KHZ (0<<8)
670#define GMBUS_RATE_50KHZ (1<<8)
671#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
672#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
673#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
674#define GMBUS_PORT_DISABLED 0
675#define GMBUS_PORT_SSC 1
676#define GMBUS_PORT_VGADDC 2
677#define GMBUS_PORT_PANEL 3
678#define GMBUS_PORT_DPC 4 /* HDMIC */
679#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
680 /* 6 reserved */
681#define GMBUS_PORT_DPD 7 /* HDMID */
682#define GMBUS_NUM_PORTS 8
683#define GMBUS1 0x5104 /* command/status */
684#define GMBUS_SW_CLR_INT (1<<31)
685#define GMBUS_SW_RDY (1<<30)
686#define GMBUS_ENT (1<<29) /* enable timeout */
687#define GMBUS_CYCLE_NONE (0<<25)
688#define GMBUS_CYCLE_WAIT (1<<25)
689#define GMBUS_CYCLE_INDEX (2<<25)
690#define GMBUS_CYCLE_STOP (4<<25)
691#define GMBUS_BYTE_COUNT_SHIFT 16
692#define GMBUS_SLAVE_INDEX_SHIFT 8
693#define GMBUS_SLAVE_ADDR_SHIFT 1
694#define GMBUS_SLAVE_READ (1<<0)
695#define GMBUS_SLAVE_WRITE (0<<0)
696#define GMBUS2 0x5108 /* status */
697#define GMBUS_INUSE (1<<15)
698#define GMBUS_HW_WAIT_PHASE (1<<14)
699#define GMBUS_STALL_TIMEOUT (1<<13)
700#define GMBUS_INT (1<<12)
701#define GMBUS_HW_RDY (1<<11)
702#define GMBUS_SATOER (1<<10)
703#define GMBUS_ACTIVE (1<<9)
704#define GMBUS3 0x510c /* data buffer bytes 3-0 */
705#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
706#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
707#define GMBUS_NAK_EN (1<<3)
708#define GMBUS_IDLE_EN (1<<2)
709#define GMBUS_HW_WAIT_EN (1<<1)
710#define GMBUS_HW_RDY_EN (1<<0)
711#define GMBUS5 0x5120 /* byte index */
712#define GMBUS_2BYTE_INDEX_EN (1<<31)
713
714/*
715 * Clock control & power management
716 */
717
718#define VGA0 0x6000
719#define VGA1 0x6004
720#define VGA_PD 0x6010
721#define VGA0_PD_P2_DIV_4 (1 << 7)
722#define VGA0_PD_P1_DIV_2 (1 << 5)
723#define VGA0_PD_P1_SHIFT 0
724#define VGA0_PD_P1_MASK (0x1f << 0)
725#define VGA1_PD_P2_DIV_4 (1 << 15)
726#define VGA1_PD_P1_DIV_2 (1 << 13)
727#define VGA1_PD_P1_SHIFT 8
728#define VGA1_PD_P1_MASK (0x1f << 8)
729#define _DPLL_A 0x06014
730#define _DPLL_B 0x06018
731#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
732#define DPLL_VCO_ENABLE (1 << 31)
733#define DPLL_DVO_HIGH_SPEED (1 << 30)
734#define DPLL_SYNCLOCK_ENABLE (1 << 29)
735#define DPLL_VGA_MODE_DIS (1 << 28)
736#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
737#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
738#define DPLL_MODE_MASK (3 << 26)
739#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
740#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
741#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
742#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
743#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
744#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
745#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
746
747#define SRX_INDEX 0x3c4
748#define SRX_DATA 0x3c5
749#define SR01 1
750#define SR01_SCREEN_OFF (1<<5)
751
752#define PPCR 0x61204
753#define PPCR_ON (1<<0)
754
755#define DVOB 0x61140
756#define DVOB_ON (1<<31)
757#define DVOC 0x61160
758#define DVOC_ON (1<<31)
759#define LVDS 0x61180
760#define LVDS_ON (1<<31)
761
762/* Scratch pad debug 0 reg:
763 */
764#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
765/*
766 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
767 * this field (only one bit may be set).
768 */
769#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
770#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
771#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
772/* i830, required in DVO non-gang */
773#define PLL_P2_DIVIDE_BY_4 (1 << 23)
774#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
775#define PLL_REF_INPUT_DREFCLK (0 << 13)
776#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
777#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
778#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
779#define PLL_REF_INPUT_MASK (3 << 13)
780#define PLL_LOAD_PULSE_PHASE_SHIFT 9
781/* Ironlake */
782# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
783# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
784# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
785# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
786# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
787
788/*
789 * Parallel to Serial Load Pulse phase selection.
790 * Selects the phase for the 10X DPLL clock for the PCIe
791 * digital display port. The range is 4 to 13; 10 or more
792 * is just a flip delay. The default is 6
793 */
794#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
795#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
796/*
797 * SDVO multiplier for 945G/GM. Not used on 965.
798 */
799#define SDVO_MULTIPLIER_MASK 0x000000ff
800#define SDVO_MULTIPLIER_SHIFT_HIRES 4
801#define SDVO_MULTIPLIER_SHIFT_VGA 0
802#define _DPLL_A_MD 0x0601c /* 965+ only */
803/*
804 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
805 *
806 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
807 */
808#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
809#define DPLL_MD_UDI_DIVIDER_SHIFT 24
810/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
811#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
812#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
813/*
814 * SDVO/UDI pixel multiplier.
815 *
816 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
817 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
818 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
819 * dummy bytes in the datastream at an increased clock rate, with both sides of
820 * the link knowing how many bytes are fill.
821 *
822 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
823 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
824 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
825 * through an SDVO command.
826 *
827 * This register field has values of multiplication factor minus 1, with
828 * a maximum multiplier of 5 for SDVO.
829 */
830#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
831#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
832/*
833 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
834 * This best be set to the default value (3) or the CRT won't work. No,
835 * I don't entirely understand what this does...
836 */
837#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
838#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
839#define _DPLL_B_MD 0x06020 /* 965+ only */
840#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
841#define _FPA0 0x06040
842#define _FPA1 0x06044
843#define _FPB0 0x06048
844#define _FPB1 0x0604c
845#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
846#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
847#define FP_N_DIV_MASK 0x003f0000
848#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
849#define FP_N_DIV_SHIFT 16
850#define FP_M1_DIV_MASK 0x00003f00
851#define FP_M1_DIV_SHIFT 8
852#define FP_M2_DIV_MASK 0x0000003f
853#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
854#define FP_M2_DIV_SHIFT 0
855#define DPLL_TEST 0x606c
856#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
857#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
858#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
859#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
860#define DPLLB_TEST_N_BYPASS (1 << 19)
861#define DPLLB_TEST_M_BYPASS (1 << 18)
862#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
863#define DPLLA_TEST_N_BYPASS (1 << 3)
864#define DPLLA_TEST_M_BYPASS (1 << 2)
865#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
866#define D_STATE 0x6104
867#define DSTATE_GFX_RESET_I830 (1<<6)
868#define DSTATE_PLL_D3_OFF (1<<3)
869#define DSTATE_GFX_CLOCK_GATING (1<<1)
870#define DSTATE_DOT_CLOCK_GATING (1<<0)
871#define DSPCLK_GATE_D 0x6200
872# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
873# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
874# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
875# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
876# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
877# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
878# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
879# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
880# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
881# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
882# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
883# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
884# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
885# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
886# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
887# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
888# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
889# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
890# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
891# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
892# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
893# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
894# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
895# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
896# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
897# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
898# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
899# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
900/**
901 * This bit must be set on the 830 to prevent hangs when turning off the
902 * overlay scaler.
903 */
904# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
905# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
906# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
907# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
908# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
909
910#define RENCLK_GATE_D1 0x6204
911# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
912# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
913# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
914# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
915# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
916# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
917# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
918# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
919# define MAG_CLOCK_GATE_DISABLE (1 << 5)
920/** This bit must be unset on 855,865 */
921# define MECI_CLOCK_GATE_DISABLE (1 << 4)
922# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
923# define MEC_CLOCK_GATE_DISABLE (1 << 2)
924# define MECO_CLOCK_GATE_DISABLE (1 << 1)
925/** This bit must be set on 855,865. */
926# define SV_CLOCK_GATE_DISABLE (1 << 0)
927# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
928# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
929# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
930# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
931# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
932# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
933# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
934# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
935# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
936# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
937# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
938# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
939# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
940# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
941# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
942# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
943# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
944
945# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
946/** This bit must always be set on 965G/965GM */
947# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
948# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
949# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
950# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
951# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
952# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
953/** This bit must always be set on 965G */
954# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
955# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
956# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
957# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
958# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
959# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
960# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
961# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
962# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
963# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
964# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
965# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
966# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
967# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
968# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
969# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
970# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
971# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
972# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
973
974#define RENCLK_GATE_D2 0x6208
975#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
976#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
977#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
978#define RAMCLK_GATE_D 0x6210 /* CRL only */
979#define DEUC 0x6214 /* CRL only */
980
981/*
982 * Palette regs
983 */
984
985#define _PALETTE_A 0x0a000
986#define _PALETTE_B 0x0a800
987#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
988
989/* MCH MMIO space */
990
991/*
992 * MCHBAR mirror.
993 *
994 * This mirrors the MCHBAR MMIO space whose location is determined by
995 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
996 * every way. It is not accessible from the CP register read instructions.
997 *
998 */
999#define MCHBAR_MIRROR_BASE 0x10000
1000
1001#define MCHBAR_MIRROR_BASE_SNB 0x140000
1002
1003/** 915-945 and GM965 MCH register controlling DRAM channel access */
1004#define DCC 0x10200
1005#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1006#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1007#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1008#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1009#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1010#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1011
1012/** Pineview MCH register contains DDR3 setting */
1013#define CSHRDDR3CTL 0x101a8
1014#define CSHRDDR3CTL_DDR3 (1 << 2)
1015
1016/** 965 MCH register controlling DRAM channel configuration */
1017#define C0DRB3 0x10206
1018#define C1DRB3 0x10606
1019
1020/* Clocking configuration register */
1021#define CLKCFG 0x10c00
1022#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1023#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1024#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1025#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1026#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1027#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1028/* Note, below two are guess */
1029#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1030#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1031#define CLKCFG_FSB_MASK (7 << 0)
1032#define CLKCFG_MEM_533 (1 << 4)
1033#define CLKCFG_MEM_667 (2 << 4)
1034#define CLKCFG_MEM_800 (3 << 4)
1035#define CLKCFG_MEM_MASK (7 << 4)
1036
1037#define TSC1 0x11001
1038#define TSE (1<<0)
1039#define TR1 0x11006
1040#define TSFS 0x11020
1041#define TSFS_SLOPE_MASK 0x0000ff00
1042#define TSFS_SLOPE_SHIFT 8
1043#define TSFS_INTR_MASK 0x000000ff
1044
1045#define CRSTANDVID 0x11100
1046#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1047#define PXVFREQ_PX_MASK 0x7f000000
1048#define PXVFREQ_PX_SHIFT 24
1049#define VIDFREQ_BASE 0x11110
1050#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1051#define VIDFREQ2 0x11114
1052#define VIDFREQ3 0x11118
1053#define VIDFREQ4 0x1111c
1054#define VIDFREQ_P0_MASK 0x1f000000
1055#define VIDFREQ_P0_SHIFT 24
1056#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1057#define VIDFREQ_P0_CSCLK_SHIFT 20
1058#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1059#define VIDFREQ_P0_CRCLK_SHIFT 16
1060#define VIDFREQ_P1_MASK 0x00001f00
1061#define VIDFREQ_P1_SHIFT 8
1062#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1063#define VIDFREQ_P1_CSCLK_SHIFT 4
1064#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1065#define INTTOEXT_BASE_ILK 0x11300
1066#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1067#define INTTOEXT_MAP3_SHIFT 24
1068#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1069#define INTTOEXT_MAP2_SHIFT 16
1070#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1071#define INTTOEXT_MAP1_SHIFT 8
1072#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1073#define INTTOEXT_MAP0_SHIFT 0
1074#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1075#define MEMSWCTL 0x11170 /* Ironlake only */
1076#define MEMCTL_CMD_MASK 0xe000
1077#define MEMCTL_CMD_SHIFT 13
1078#define MEMCTL_CMD_RCLK_OFF 0
1079#define MEMCTL_CMD_RCLK_ON 1
1080#define MEMCTL_CMD_CHFREQ 2
1081#define MEMCTL_CMD_CHVID 3
1082#define MEMCTL_CMD_VMMOFF 4
1083#define MEMCTL_CMD_VMMON 5
1084#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1085 when command complete */
1086#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1087#define MEMCTL_FREQ_SHIFT 8
1088#define MEMCTL_SFCAVM (1<<7)
1089#define MEMCTL_TGT_VID_MASK 0x007f
1090#define MEMIHYST 0x1117c
1091#define MEMINTREN 0x11180 /* 16 bits */
1092#define MEMINT_RSEXIT_EN (1<<8)
1093#define MEMINT_CX_SUPR_EN (1<<7)
1094#define MEMINT_CONT_BUSY_EN (1<<6)
1095#define MEMINT_AVG_BUSY_EN (1<<5)
1096#define MEMINT_EVAL_CHG_EN (1<<4)
1097#define MEMINT_MON_IDLE_EN (1<<3)
1098#define MEMINT_UP_EVAL_EN (1<<2)
1099#define MEMINT_DOWN_EVAL_EN (1<<1)
1100#define MEMINT_SW_CMD_EN (1<<0)
1101#define MEMINTRSTR 0x11182 /* 16 bits */
1102#define MEM_RSEXIT_MASK 0xc000
1103#define MEM_RSEXIT_SHIFT 14
1104#define MEM_CONT_BUSY_MASK 0x3000
1105#define MEM_CONT_BUSY_SHIFT 12
1106#define MEM_AVG_BUSY_MASK 0x0c00
1107#define MEM_AVG_BUSY_SHIFT 10
1108#define MEM_EVAL_CHG_MASK 0x0300
1109#define MEM_EVAL_BUSY_SHIFT 8
1110#define MEM_MON_IDLE_MASK 0x00c0
1111#define MEM_MON_IDLE_SHIFT 6
1112#define MEM_UP_EVAL_MASK 0x0030
1113#define MEM_UP_EVAL_SHIFT 4
1114#define MEM_DOWN_EVAL_MASK 0x000c
1115#define MEM_DOWN_EVAL_SHIFT 2
1116#define MEM_SW_CMD_MASK 0x0003
1117#define MEM_INT_STEER_GFX 0
1118#define MEM_INT_STEER_CMR 1
1119#define MEM_INT_STEER_SMI 2
1120#define MEM_INT_STEER_SCI 3
1121#define MEMINTRSTS 0x11184
1122#define MEMINT_RSEXIT (1<<7)
1123#define MEMINT_CONT_BUSY (1<<6)
1124#define MEMINT_AVG_BUSY (1<<5)
1125#define MEMINT_EVAL_CHG (1<<4)
1126#define MEMINT_MON_IDLE (1<<3)
1127#define MEMINT_UP_EVAL (1<<2)
1128#define MEMINT_DOWN_EVAL (1<<1)
1129#define MEMINT_SW_CMD (1<<0)
1130#define MEMMODECTL 0x11190
1131#define MEMMODE_BOOST_EN (1<<31)
1132#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1133#define MEMMODE_BOOST_FREQ_SHIFT 24
1134#define MEMMODE_IDLE_MODE_MASK 0x00030000
1135#define MEMMODE_IDLE_MODE_SHIFT 16
1136#define MEMMODE_IDLE_MODE_EVAL 0
1137#define MEMMODE_IDLE_MODE_CONT 1
1138#define MEMMODE_HWIDLE_EN (1<<15)
1139#define MEMMODE_SWMODE_EN (1<<14)
1140#define MEMMODE_RCLK_GATE (1<<13)
1141#define MEMMODE_HW_UPDATE (1<<12)
1142#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1143#define MEMMODE_FSTART_SHIFT 8
1144#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1145#define MEMMODE_FMAX_SHIFT 4
1146#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1147#define RCBMAXAVG 0x1119c
1148#define MEMSWCTL2 0x1119e /* Cantiga only */
1149#define SWMEMCMD_RENDER_OFF (0 << 13)
1150#define SWMEMCMD_RENDER_ON (1 << 13)
1151#define SWMEMCMD_SWFREQ (2 << 13)
1152#define SWMEMCMD_TARVID (3 << 13)
1153#define SWMEMCMD_VRM_OFF (4 << 13)
1154#define SWMEMCMD_VRM_ON (5 << 13)
1155#define CMDSTS (1<<12)
1156#define SFCAVM (1<<11)
1157#define SWFREQ_MASK 0x0380 /* P0-7 */
1158#define SWFREQ_SHIFT 7
1159#define TARVID_MASK 0x001f
1160#define MEMSTAT_CTG 0x111a0
1161#define RCBMINAVG 0x111a0
1162#define RCUPEI 0x111b0
1163#define RCDNEI 0x111b4
1164#define RSTDBYCTL 0x111b8
1165#define RS1EN (1<<31)
1166#define RS2EN (1<<30)
1167#define RS3EN (1<<29)
1168#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1169#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1170#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1171#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1172#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1173#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1174#define RSX_STATUS_MASK (7<<20)
1175#define RSX_STATUS_ON (0<<20)
1176#define RSX_STATUS_RC1 (1<<20)
1177#define RSX_STATUS_RC1E (2<<20)
1178#define RSX_STATUS_RS1 (3<<20)
1179#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1180#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1181#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1182#define RSX_STATUS_RSVD2 (7<<20)
1183#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1184#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1185#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1186#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1187#define RS1CONTSAV_MASK (3<<14)
1188#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1189#define RS1CONTSAV_RSVD (1<<14)
1190#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1191#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1192#define NORMSLEXLAT_MASK (3<<12)
1193#define SLOW_RS123 (0<<12)
1194#define SLOW_RS23 (1<<12)
1195#define SLOW_RS3 (2<<12)
1196#define NORMAL_RS123 (3<<12)
1197#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1198#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1199#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1200#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1201#define RS_CSTATE_MASK (3<<4)
1202#define RS_CSTATE_C367_RS1 (0<<4)
1203#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1204#define RS_CSTATE_RSVD (2<<4)
1205#define RS_CSTATE_C367_RS2 (3<<4)
1206#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1207#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1208#define VIDCTL 0x111c0
1209#define VIDSTS 0x111c8
1210#define VIDSTART 0x111cc /* 8 bits */
1211#define MEMSTAT_ILK 0x111f8
1212#define MEMSTAT_VID_MASK 0x7f00
1213#define MEMSTAT_VID_SHIFT 8
1214#define MEMSTAT_PSTATE_MASK 0x00f8
1215#define MEMSTAT_PSTATE_SHIFT 3
1216#define MEMSTAT_MON_ACTV (1<<2)
1217#define MEMSTAT_SRC_CTL_MASK 0x0003
1218#define MEMSTAT_SRC_CTL_CORE 0
1219#define MEMSTAT_SRC_CTL_TRB 1
1220#define MEMSTAT_SRC_CTL_THM 2
1221#define MEMSTAT_SRC_CTL_STDBY 3
1222#define RCPREVBSYTUPAVG 0x113b8
1223#define RCPREVBSYTDNAVG 0x113bc
1224#define PMMISC 0x11214
1225#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1226#define SDEW 0x1124c
1227#define CSIEW0 0x11250
1228#define CSIEW1 0x11254
1229#define CSIEW2 0x11258
1230#define PEW 0x1125c
1231#define DEW 0x11270
1232#define MCHAFE 0x112c0
1233#define CSIEC 0x112e0
1234#define DMIEC 0x112e4
1235#define DDREC 0x112e8
1236#define PEG0EC 0x112ec
1237#define PEG1EC 0x112f0
1238#define GFXEC 0x112f4
1239#define RPPREVBSYTUPAVG 0x113b8
1240#define RPPREVBSYTDNAVG 0x113bc
1241#define ECR 0x11600
1242#define ECR_GPFE (1<<31)
1243#define ECR_IMONE (1<<30)
1244#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1245#define OGW0 0x11608
1246#define OGW1 0x1160c
1247#define EG0 0x11610
1248#define EG1 0x11614
1249#define EG2 0x11618
1250#define EG3 0x1161c
1251#define EG4 0x11620
1252#define EG5 0x11624
1253#define EG6 0x11628
1254#define EG7 0x1162c
1255#define PXW 0x11664
1256#define PXWL 0x11680
1257#define LCFUSE02 0x116c0
1258#define LCFUSE_HIV_MASK 0x000000ff
1259#define CSIPLL0 0x12c10
1260#define DDRMPLL1 0X12c20
1261#define PEG_BAND_GAP_DATA 0x14d68
1262
1263#define GEN6_GT_PERF_STATUS 0x145948
1264#define GEN6_RP_STATE_LIMITS 0x145994
1265#define GEN6_RP_STATE_CAP 0x145998
1266
1267/*
1268 * Logical Context regs
1269 */
1270#define CCID 0x2180
1271#define CCID_EN (1<<0)
1272/*
1273 * Overlay regs
1274 */
1275
1276#define OVADD 0x30000
1277#define DOVSTA 0x30008
1278#define OC_BUF (0x3<<20)
1279#define OGAMC5 0x30010
1280#define OGAMC4 0x30014
1281#define OGAMC3 0x30018
1282#define OGAMC2 0x3001c
1283#define OGAMC1 0x30020
1284#define OGAMC0 0x30024
1285
1286/*
1287 * Display engine regs
1288 */
1289
1290/* Pipe A timing regs */
1291#define _HTOTAL_A 0x60000
1292#define _HBLANK_A 0x60004
1293#define _HSYNC_A 0x60008
1294#define _VTOTAL_A 0x6000c
1295#define _VBLANK_A 0x60010
1296#define _VSYNC_A 0x60014
1297#define _PIPEASRC 0x6001c
1298#define _BCLRPAT_A 0x60020
1299
1300/* Pipe B timing regs */
1301#define _HTOTAL_B 0x61000
1302#define _HBLANK_B 0x61004
1303#define _HSYNC_B 0x61008
1304#define _VTOTAL_B 0x6100c
1305#define _VBLANK_B 0x61010
1306#define _VSYNC_B 0x61014
1307#define _PIPEBSRC 0x6101c
1308#define _BCLRPAT_B 0x61020
1309
1310#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1311#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1312#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1313#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1314#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1315#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1316#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1317
1318/* VGA port control */
1319#define ADPA 0x61100
1320#define ADPA_DAC_ENABLE (1<<31)
1321#define ADPA_DAC_DISABLE 0
1322#define ADPA_PIPE_SELECT_MASK (1<<30)
1323#define ADPA_PIPE_A_SELECT 0
1324#define ADPA_PIPE_B_SELECT (1<<30)
1325#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1327#define ADPA_SETS_HVPOLARITY 0
1328#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1329#define ADPA_VSYNC_CNTL_ENABLE 0
1330#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1331#define ADPA_HSYNC_CNTL_ENABLE 0
1332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1333#define ADPA_VSYNC_ACTIVE_LOW 0
1334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1335#define ADPA_HSYNC_ACTIVE_LOW 0
1336#define ADPA_DPMS_MASK (~(3<<10))
1337#define ADPA_DPMS_ON (0<<10)
1338#define ADPA_DPMS_SUSPEND (1<<10)
1339#define ADPA_DPMS_STANDBY (2<<10)
1340#define ADPA_DPMS_OFF (3<<10)
1341
1342
1343/* Hotplug control (945+ only) */
1344#define PORT_HOTPLUG_EN 0x61110
1345#define HDMIB_HOTPLUG_INT_EN (1 << 29)
1346#define DPB_HOTPLUG_INT_EN (1 << 29)
1347#define HDMIC_HOTPLUG_INT_EN (1 << 28)
1348#define DPC_HOTPLUG_INT_EN (1 << 28)
1349#define HDMID_HOTPLUG_INT_EN (1 << 27)
1350#define DPD_HOTPLUG_INT_EN (1 << 27)
1351#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1352#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1353#define TV_HOTPLUG_INT_EN (1 << 18)
1354#define CRT_HOTPLUG_INT_EN (1 << 9)
1355#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1356#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1357/* must use period 64 on GM45 according to docs */
1358#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1359#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1360#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1361#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1362#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1363#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1364#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1365#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1366#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1367#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1368#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1369#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1370
1371#define PORT_HOTPLUG_STAT 0x61114
1372#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1373#define DPB_HOTPLUG_INT_STATUS (1 << 29)
1374#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1375#define DPC_HOTPLUG_INT_STATUS (1 << 28)
1376#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1377#define DPD_HOTPLUG_INT_STATUS (1 << 27)
1378#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1379#define TV_HOTPLUG_INT_STATUS (1 << 10)
1380#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1381#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1382#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1383#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1384#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1385#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1386
1387/* SDVO port control */
1388#define SDVOB 0x61140
1389#define SDVOC 0x61160
1390#define SDVO_ENABLE (1 << 31)
1391#define SDVO_PIPE_B_SELECT (1 << 30)
1392#define SDVO_STALL_SELECT (1 << 29)
1393#define SDVO_INTERRUPT_ENABLE (1 << 26)
1394/**
1395 * 915G/GM SDVO pixel multiplier.
1396 *
1397 * Programmed value is multiplier - 1, up to 5x.
1398 *
1399 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1400 */
1401#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1402#define SDVO_PORT_MULTIPLY_SHIFT 23
1403#define SDVO_PHASE_SELECT_MASK (15 << 19)
1404#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1405#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1406#define SDVOC_GANG_MODE (1 << 16)
1407#define SDVO_ENCODING_SDVO (0x0 << 10)
1408#define SDVO_ENCODING_HDMI (0x2 << 10)
1409/** Requird for HDMI operation */
1410#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1411#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1412#define SDVO_BORDER_ENABLE (1 << 7)
1413#define SDVO_AUDIO_ENABLE (1 << 6)
1414/** New with 965, default is to be set */
1415#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1416/** New with 965, default is to be set */
1417#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1418#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1419#define SDVO_DETECTED (1 << 2)
1420/* Bits to be preserved when writing */
1421#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1422#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1423
1424/* DVO port control */
1425#define DVOA 0x61120
1426#define DVOB 0x61140
1427#define DVOC 0x61160
1428#define DVO_ENABLE (1 << 31)
1429#define DVO_PIPE_B_SELECT (1 << 30)
1430#define DVO_PIPE_STALL_UNUSED (0 << 28)
1431#define DVO_PIPE_STALL (1 << 28)
1432#define DVO_PIPE_STALL_TV (2 << 28)
1433#define DVO_PIPE_STALL_MASK (3 << 28)
1434#define DVO_USE_VGA_SYNC (1 << 15)
1435#define DVO_DATA_ORDER_I740 (0 << 14)
1436#define DVO_DATA_ORDER_FP (1 << 14)
1437#define DVO_VSYNC_DISABLE (1 << 11)
1438#define DVO_HSYNC_DISABLE (1 << 10)
1439#define DVO_VSYNC_TRISTATE (1 << 9)
1440#define DVO_HSYNC_TRISTATE (1 << 8)
1441#define DVO_BORDER_ENABLE (1 << 7)
1442#define DVO_DATA_ORDER_GBRG (1 << 6)
1443#define DVO_DATA_ORDER_RGGB (0 << 6)
1444#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1445#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1446#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1447#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1448#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1449#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1450#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1451#define DVO_PRESERVE_MASK (0x7<<24)
1452#define DVOA_SRCDIM 0x61124
1453#define DVOB_SRCDIM 0x61144
1454#define DVOC_SRCDIM 0x61164
1455#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1456#define DVO_SRCDIM_VERTICAL_SHIFT 0
1457
1458/* LVDS port control */
1459#define LVDS 0x61180
1460/*
1461 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1462 * the DPLL semantics change when the LVDS is assigned to that pipe.
1463 */
1464#define LVDS_PORT_EN (1 << 31)
1465/* Selects pipe B for LVDS data. Must be set on pre-965. */
1466#define LVDS_PIPEB_SELECT (1 << 30)
1467#define LVDS_PIPE_MASK (1 << 30)
1468#define LVDS_PIPE(pipe) ((pipe) << 30)
1469/* LVDS dithering flag on 965/g4x platform */
1470#define LVDS_ENABLE_DITHER (1 << 25)
1471/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1472#define LVDS_VSYNC_POLARITY (1 << 21)
1473#define LVDS_HSYNC_POLARITY (1 << 20)
1474
1475/* Enable border for unscaled (or aspect-scaled) display */
1476#define LVDS_BORDER_ENABLE (1 << 15)
1477/*
1478 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1479 * pixel.
1480 */
1481#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1482#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1483#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1484/*
1485 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1486 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1487 * on.
1488 */
1489#define LVDS_A3_POWER_MASK (3 << 6)
1490#define LVDS_A3_POWER_DOWN (0 << 6)
1491#define LVDS_A3_POWER_UP (3 << 6)
1492/*
1493 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1494 * is set.
1495 */
1496#define LVDS_CLKB_POWER_MASK (3 << 4)
1497#define LVDS_CLKB_POWER_DOWN (0 << 4)
1498#define LVDS_CLKB_POWER_UP (3 << 4)
1499/*
1500 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1501 * setting for whether we are in dual-channel mode. The B3 pair will
1502 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1503 */
1504#define LVDS_B0B3_POWER_MASK (3 << 2)
1505#define LVDS_B0B3_POWER_DOWN (0 << 2)
1506#define LVDS_B0B3_POWER_UP (3 << 2)
1507
1508/* Video Data Island Packet control */
1509#define VIDEO_DIP_DATA 0x61178
1510#define VIDEO_DIP_CTL 0x61170
1511#define VIDEO_DIP_ENABLE (1 << 31)
1512#define VIDEO_DIP_PORT_B (1 << 29)
1513#define VIDEO_DIP_PORT_C (2 << 29)
1514#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1515#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1516#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1517#define VIDEO_DIP_SELECT_AVI (0 << 19)
1518#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1519#define VIDEO_DIP_SELECT_SPD (3 << 19)
1520#define VIDEO_DIP_SELECT_MASK (3 << 19)
1521#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1522#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1523#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1524
1525/* Panel power sequencing */
1526#define PP_STATUS 0x61200
1527#define PP_ON (1 << 31)
1528/*
1529 * Indicates that all dependencies of the panel are on:
1530 *
1531 * - PLL enabled
1532 * - pipe enabled
1533 * - LVDS/DVOB/DVOC on
1534 */
1535#define PP_READY (1 << 30)
1536#define PP_SEQUENCE_NONE (0 << 28)
1537#define PP_SEQUENCE_ON (1 << 28)
1538#define PP_SEQUENCE_OFF (2 << 28)
1539#define PP_SEQUENCE_MASK 0x30000000
1540#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1541#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1542#define PP_SEQUENCE_STATE_MASK 0x0000000f
1543#define PP_CONTROL 0x61204
1544#define POWER_TARGET_ON (1 << 0)
1545#define PP_ON_DELAYS 0x61208
1546#define PP_OFF_DELAYS 0x6120c
1547#define PP_DIVISOR 0x61210
1548
1549/* Panel fitting */
1550#define PFIT_CONTROL 0x61230
1551#define PFIT_ENABLE (1 << 31)
1552#define PFIT_PIPE_MASK (3 << 29)
1553#define PFIT_PIPE_SHIFT 29
1554#define VERT_INTERP_DISABLE (0 << 10)
1555#define VERT_INTERP_BILINEAR (1 << 10)
1556#define VERT_INTERP_MASK (3 << 10)
1557#define VERT_AUTO_SCALE (1 << 9)
1558#define HORIZ_INTERP_DISABLE (0 << 6)
1559#define HORIZ_INTERP_BILINEAR (1 << 6)
1560#define HORIZ_INTERP_MASK (3 << 6)
1561#define HORIZ_AUTO_SCALE (1 << 5)
1562#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1563#define PFIT_FILTER_FUZZY (0 << 24)
1564#define PFIT_SCALING_AUTO (0 << 26)
1565#define PFIT_SCALING_PROGRAMMED (1 << 26)
1566#define PFIT_SCALING_PILLAR (2 << 26)
1567#define PFIT_SCALING_LETTER (3 << 26)
1568#define PFIT_PGM_RATIOS 0x61234
1569#define PFIT_VERT_SCALE_MASK 0xfff00000
1570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1571/* Pre-965 */
1572#define PFIT_VERT_SCALE_SHIFT 20
1573#define PFIT_VERT_SCALE_MASK 0xfff00000
1574#define PFIT_HORIZ_SCALE_SHIFT 4
1575#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1576/* 965+ */
1577#define PFIT_VERT_SCALE_SHIFT_965 16
1578#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1579#define PFIT_HORIZ_SCALE_SHIFT_965 0
1580#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1581
1582#define PFIT_AUTO_RATIOS 0x61238
1583
1584/* Backlight control */
1585#define BLC_PWM_CTL 0x61254
1586#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1587#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1588#define BLM_COMBINATION_MODE (1 << 30)
1589/*
1590 * This is the most significant 15 bits of the number of backlight cycles in a
1591 * complete cycle of the modulated backlight control.
1592 *
1593 * The actual value is this field multiplied by two.
1594 */
1595#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1596#define BLM_LEGACY_MODE (1 << 16)
1597/*
1598 * This is the number of cycles out of the backlight modulation cycle for which
1599 * the backlight is on.
1600 *
1601 * This field must be no greater than the number of cycles in the complete
1602 * backlight modulation cycle.
1603 */
1604#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1605#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1606
1607#define BLC_HIST_CTL 0x61260
1608
1609/* TV port control */
1610#define TV_CTL 0x68000
1611/** Enables the TV encoder */
1612# define TV_ENC_ENABLE (1 << 31)
1613/** Sources the TV encoder input from pipe B instead of A. */
1614# define TV_ENC_PIPEB_SELECT (1 << 30)
1615/** Outputs composite video (DAC A only) */
1616# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1617/** Outputs SVideo video (DAC B/C) */
1618# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1619/** Outputs Component video (DAC A/B/C) */
1620# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1621/** Outputs Composite and SVideo (DAC A/B/C) */
1622# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1623# define TV_TRILEVEL_SYNC (1 << 21)
1624/** Enables slow sync generation (945GM only) */
1625# define TV_SLOW_SYNC (1 << 20)
1626/** Selects 4x oversampling for 480i and 576p */
1627# define TV_OVERSAMPLE_4X (0 << 18)
1628/** Selects 2x oversampling for 720p and 1080i */
1629# define TV_OVERSAMPLE_2X (1 << 18)
1630/** Selects no oversampling for 1080p */
1631# define TV_OVERSAMPLE_NONE (2 << 18)
1632/** Selects 8x oversampling */
1633# define TV_OVERSAMPLE_8X (3 << 18)
1634/** Selects progressive mode rather than interlaced */
1635# define TV_PROGRESSIVE (1 << 17)
1636/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1637# define TV_PAL_BURST (1 << 16)
1638/** Field for setting delay of Y compared to C */
1639# define TV_YC_SKEW_MASK (7 << 12)
1640/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1641# define TV_ENC_SDP_FIX (1 << 11)
1642/**
1643 * Enables a fix for the 915GM only.
1644 *
1645 * Not sure what it does.
1646 */
1647# define TV_ENC_C0_FIX (1 << 10)
1648/** Bits that must be preserved by software */
1649# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1650# define TV_FUSE_STATE_MASK (3 << 4)
1651/** Read-only state that reports all features enabled */
1652# define TV_FUSE_STATE_ENABLED (0 << 4)
1653/** Read-only state that reports that Macrovision is disabled in hardware*/
1654# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1655/** Read-only state that reports that TV-out is disabled in hardware. */
1656# define TV_FUSE_STATE_DISABLED (2 << 4)
1657/** Normal operation */
1658# define TV_TEST_MODE_NORMAL (0 << 0)
1659/** Encoder test pattern 1 - combo pattern */
1660# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1661/** Encoder test pattern 2 - full screen vertical 75% color bars */
1662# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1663/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1664# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1665/** Encoder test pattern 4 - random noise */
1666# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1667/** Encoder test pattern 5 - linear color ramps */
1668# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1669/**
1670 * This test mode forces the DACs to 50% of full output.
1671 *
1672 * This is used for load detection in combination with TVDAC_SENSE_MASK
1673 */
1674# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1675# define TV_TEST_MODE_MASK (7 << 0)
1676
1677#define TV_DAC 0x68004
1678# define TV_DAC_SAVE 0x00ffff00
1679/**
1680 * Reports that DAC state change logic has reported change (RO).
1681 *
1682 * This gets cleared when TV_DAC_STATE_EN is cleared
1683*/
1684# define TVDAC_STATE_CHG (1 << 31)
1685# define TVDAC_SENSE_MASK (7 << 28)
1686/** Reports that DAC A voltage is above the detect threshold */
1687# define TVDAC_A_SENSE (1 << 30)
1688/** Reports that DAC B voltage is above the detect threshold */
1689# define TVDAC_B_SENSE (1 << 29)
1690/** Reports that DAC C voltage is above the detect threshold */
1691# define TVDAC_C_SENSE (1 << 28)
1692/**
1693 * Enables DAC state detection logic, for load-based TV detection.
1694 *
1695 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1696 * to off, for load detection to work.
1697 */
1698# define TVDAC_STATE_CHG_EN (1 << 27)
1699/** Sets the DAC A sense value to high */
1700# define TVDAC_A_SENSE_CTL (1 << 26)
1701/** Sets the DAC B sense value to high */
1702# define TVDAC_B_SENSE_CTL (1 << 25)
1703/** Sets the DAC C sense value to high */
1704# define TVDAC_C_SENSE_CTL (1 << 24)
1705/** Overrides the ENC_ENABLE and DAC voltage levels */
1706# define DAC_CTL_OVERRIDE (1 << 7)
1707/** Sets the slew rate. Must be preserved in software */
1708# define ENC_TVDAC_SLEW_FAST (1 << 6)
1709# define DAC_A_1_3_V (0 << 4)
1710# define DAC_A_1_1_V (1 << 4)
1711# define DAC_A_0_7_V (2 << 4)
1712# define DAC_A_MASK (3 << 4)
1713# define DAC_B_1_3_V (0 << 2)
1714# define DAC_B_1_1_V (1 << 2)
1715# define DAC_B_0_7_V (2 << 2)
1716# define DAC_B_MASK (3 << 2)
1717# define DAC_C_1_3_V (0 << 0)
1718# define DAC_C_1_1_V (1 << 0)
1719# define DAC_C_0_7_V (2 << 0)
1720# define DAC_C_MASK (3 << 0)
1721
1722/**
1723 * CSC coefficients are stored in a floating point format with 9 bits of
1724 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1725 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1726 * -1 (0x3) being the only legal negative value.
1727 */
1728#define TV_CSC_Y 0x68010
1729# define TV_RY_MASK 0x07ff0000
1730# define TV_RY_SHIFT 16
1731# define TV_GY_MASK 0x00000fff
1732# define TV_GY_SHIFT 0
1733
1734#define TV_CSC_Y2 0x68014
1735# define TV_BY_MASK 0x07ff0000
1736# define TV_BY_SHIFT 16
1737/**
1738 * Y attenuation for component video.
1739 *
1740 * Stored in 1.9 fixed point.
1741 */
1742# define TV_AY_MASK 0x000003ff
1743# define TV_AY_SHIFT 0
1744
1745#define TV_CSC_U 0x68018
1746# define TV_RU_MASK 0x07ff0000
1747# define TV_RU_SHIFT 16
1748# define TV_GU_MASK 0x000007ff
1749# define TV_GU_SHIFT 0
1750
1751#define TV_CSC_U2 0x6801c
1752# define TV_BU_MASK 0x07ff0000
1753# define TV_BU_SHIFT 16
1754/**
1755 * U attenuation for component video.
1756 *
1757 * Stored in 1.9 fixed point.
1758 */
1759# define TV_AU_MASK 0x000003ff
1760# define TV_AU_SHIFT 0
1761
1762#define TV_CSC_V 0x68020
1763# define TV_RV_MASK 0x0fff0000
1764# define TV_RV_SHIFT 16
1765# define TV_GV_MASK 0x000007ff
1766# define TV_GV_SHIFT 0
1767
1768#define TV_CSC_V2 0x68024
1769# define TV_BV_MASK 0x07ff0000
1770# define TV_BV_SHIFT 16
1771/**
1772 * V attenuation for component video.
1773 *
1774 * Stored in 1.9 fixed point.
1775 */
1776# define TV_AV_MASK 0x000007ff
1777# define TV_AV_SHIFT 0
1778
1779#define TV_CLR_KNOBS 0x68028
1780/** 2s-complement brightness adjustment */
1781# define TV_BRIGHTNESS_MASK 0xff000000
1782# define TV_BRIGHTNESS_SHIFT 24
1783/** Contrast adjustment, as a 2.6 unsigned floating point number */
1784# define TV_CONTRAST_MASK 0x00ff0000
1785# define TV_CONTRAST_SHIFT 16
1786/** Saturation adjustment, as a 2.6 unsigned floating point number */
1787# define TV_SATURATION_MASK 0x0000ff00
1788# define TV_SATURATION_SHIFT 8
1789/** Hue adjustment, as an integer phase angle in degrees */
1790# define TV_HUE_MASK 0x000000ff
1791# define TV_HUE_SHIFT 0
1792
1793#define TV_CLR_LEVEL 0x6802c
1794/** Controls the DAC level for black */
1795# define TV_BLACK_LEVEL_MASK 0x01ff0000
1796# define TV_BLACK_LEVEL_SHIFT 16
1797/** Controls the DAC level for blanking */
1798# define TV_BLANK_LEVEL_MASK 0x000001ff
1799# define TV_BLANK_LEVEL_SHIFT 0
1800
1801#define TV_H_CTL_1 0x68030
1802/** Number of pixels in the hsync. */
1803# define TV_HSYNC_END_MASK 0x1fff0000
1804# define TV_HSYNC_END_SHIFT 16
1805/** Total number of pixels minus one in the line (display and blanking). */
1806# define TV_HTOTAL_MASK 0x00001fff
1807# define TV_HTOTAL_SHIFT 0
1808
1809#define TV_H_CTL_2 0x68034
1810/** Enables the colorburst (needed for non-component color) */
1811# define TV_BURST_ENA (1 << 31)
1812/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1813# define TV_HBURST_START_SHIFT 16
1814# define TV_HBURST_START_MASK 0x1fff0000
1815/** Length of the colorburst */
1816# define TV_HBURST_LEN_SHIFT 0
1817# define TV_HBURST_LEN_MASK 0x0001fff
1818
1819#define TV_H_CTL_3 0x68038
1820/** End of hblank, measured in pixels minus one from start of hsync */
1821# define TV_HBLANK_END_SHIFT 16
1822# define TV_HBLANK_END_MASK 0x1fff0000
1823/** Start of hblank, measured in pixels minus one from start of hsync */
1824# define TV_HBLANK_START_SHIFT 0
1825# define TV_HBLANK_START_MASK 0x0001fff
1826
1827#define TV_V_CTL_1 0x6803c
1828/** XXX */
1829# define TV_NBR_END_SHIFT 16
1830# define TV_NBR_END_MASK 0x07ff0000
1831/** XXX */
1832# define TV_VI_END_F1_SHIFT 8
1833# define TV_VI_END_F1_MASK 0x00003f00
1834/** XXX */
1835# define TV_VI_END_F2_SHIFT 0
1836# define TV_VI_END_F2_MASK 0x0000003f
1837
1838#define TV_V_CTL_2 0x68040
1839/** Length of vsync, in half lines */
1840# define TV_VSYNC_LEN_MASK 0x07ff0000
1841# define TV_VSYNC_LEN_SHIFT 16
1842/** Offset of the start of vsync in field 1, measured in one less than the
1843 * number of half lines.
1844 */
1845# define TV_VSYNC_START_F1_MASK 0x00007f00
1846# define TV_VSYNC_START_F1_SHIFT 8
1847/**
1848 * Offset of the start of vsync in field 2, measured in one less than the
1849 * number of half lines.
1850 */
1851# define TV_VSYNC_START_F2_MASK 0x0000007f
1852# define TV_VSYNC_START_F2_SHIFT 0
1853
1854#define TV_V_CTL_3 0x68044
1855/** Enables generation of the equalization signal */
1856# define TV_EQUAL_ENA (1 << 31)
1857/** Length of vsync, in half lines */
1858# define TV_VEQ_LEN_MASK 0x007f0000
1859# define TV_VEQ_LEN_SHIFT 16
1860/** Offset of the start of equalization in field 1, measured in one less than
1861 * the number of half lines.
1862 */
1863# define TV_VEQ_START_F1_MASK 0x0007f00
1864# define TV_VEQ_START_F1_SHIFT 8
1865/**
1866 * Offset of the start of equalization in field 2, measured in one less than
1867 * the number of half lines.
1868 */
1869# define TV_VEQ_START_F2_MASK 0x000007f
1870# define TV_VEQ_START_F2_SHIFT 0
1871
1872#define TV_V_CTL_4 0x68048
1873/**
1874 * Offset to start of vertical colorburst, measured in one less than the
1875 * number of lines from vertical start.
1876 */
1877# define TV_VBURST_START_F1_MASK 0x003f0000
1878# define TV_VBURST_START_F1_SHIFT 16
1879/**
1880 * Offset to the end of vertical colorburst, measured in one less than the
1881 * number of lines from the start of NBR.
1882 */
1883# define TV_VBURST_END_F1_MASK 0x000000ff
1884# define TV_VBURST_END_F1_SHIFT 0
1885
1886#define TV_V_CTL_5 0x6804c
1887/**
1888 * Offset to start of vertical colorburst, measured in one less than the
1889 * number of lines from vertical start.
1890 */
1891# define TV_VBURST_START_F2_MASK 0x003f0000
1892# define TV_VBURST_START_F2_SHIFT 16
1893/**
1894 * Offset to the end of vertical colorburst, measured in one less than the
1895 * number of lines from the start of NBR.
1896 */
1897# define TV_VBURST_END_F2_MASK 0x000000ff
1898# define TV_VBURST_END_F2_SHIFT 0
1899
1900#define TV_V_CTL_6 0x68050
1901/**
1902 * Offset to start of vertical colorburst, measured in one less than the
1903 * number of lines from vertical start.
1904 */
1905# define TV_VBURST_START_F3_MASK 0x003f0000
1906# define TV_VBURST_START_F3_SHIFT 16
1907/**
1908 * Offset to the end of vertical colorburst, measured in one less than the
1909 * number of lines from the start of NBR.
1910 */
1911# define TV_VBURST_END_F3_MASK 0x000000ff
1912# define TV_VBURST_END_F3_SHIFT 0
1913
1914#define TV_V_CTL_7 0x68054
1915/**
1916 * Offset to start of vertical colorburst, measured in one less than the
1917 * number of lines from vertical start.
1918 */
1919# define TV_VBURST_START_F4_MASK 0x003f0000
1920# define TV_VBURST_START_F4_SHIFT 16
1921/**
1922 * Offset to the end of vertical colorburst, measured in one less than the
1923 * number of lines from the start of NBR.
1924 */
1925# define TV_VBURST_END_F4_MASK 0x000000ff
1926# define TV_VBURST_END_F4_SHIFT 0
1927
1928#define TV_SC_CTL_1 0x68060
1929/** Turns on the first subcarrier phase generation DDA */
1930# define TV_SC_DDA1_EN (1 << 31)
1931/** Turns on the first subcarrier phase generation DDA */
1932# define TV_SC_DDA2_EN (1 << 30)
1933/** Turns on the first subcarrier phase generation DDA */
1934# define TV_SC_DDA3_EN (1 << 29)
1935/** Sets the subcarrier DDA to reset frequency every other field */
1936# define TV_SC_RESET_EVERY_2 (0 << 24)
1937/** Sets the subcarrier DDA to reset frequency every fourth field */
1938# define TV_SC_RESET_EVERY_4 (1 << 24)
1939/** Sets the subcarrier DDA to reset frequency every eighth field */
1940# define TV_SC_RESET_EVERY_8 (2 << 24)
1941/** Sets the subcarrier DDA to never reset the frequency */
1942# define TV_SC_RESET_NEVER (3 << 24)
1943/** Sets the peak amplitude of the colorburst.*/
1944# define TV_BURST_LEVEL_MASK 0x00ff0000
1945# define TV_BURST_LEVEL_SHIFT 16
1946/** Sets the increment of the first subcarrier phase generation DDA */
1947# define TV_SCDDA1_INC_MASK 0x00000fff
1948# define TV_SCDDA1_INC_SHIFT 0
1949
1950#define TV_SC_CTL_2 0x68064
1951/** Sets the rollover for the second subcarrier phase generation DDA */
1952# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1953# define TV_SCDDA2_SIZE_SHIFT 16
1954/** Sets the increent of the second subcarrier phase generation DDA */
1955# define TV_SCDDA2_INC_MASK 0x00007fff
1956# define TV_SCDDA2_INC_SHIFT 0
1957
1958#define TV_SC_CTL_3 0x68068
1959/** Sets the rollover for the third subcarrier phase generation DDA */
1960# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1961# define TV_SCDDA3_SIZE_SHIFT 16
1962/** Sets the increent of the third subcarrier phase generation DDA */
1963# define TV_SCDDA3_INC_MASK 0x00007fff
1964# define TV_SCDDA3_INC_SHIFT 0
1965
1966#define TV_WIN_POS 0x68070
1967/** X coordinate of the display from the start of horizontal active */
1968# define TV_XPOS_MASK 0x1fff0000
1969# define TV_XPOS_SHIFT 16
1970/** Y coordinate of the display from the start of vertical active (NBR) */
1971# define TV_YPOS_MASK 0x00000fff
1972# define TV_YPOS_SHIFT 0
1973
1974#define TV_WIN_SIZE 0x68074
1975/** Horizontal size of the display window, measured in pixels*/
1976# define TV_XSIZE_MASK 0x1fff0000
1977# define TV_XSIZE_SHIFT 16
1978/**
1979 * Vertical size of the display window, measured in pixels.
1980 *
1981 * Must be even for interlaced modes.
1982 */
1983# define TV_YSIZE_MASK 0x00000fff
1984# define TV_YSIZE_SHIFT 0
1985
1986#define TV_FILTER_CTL_1 0x68080
1987/**
1988 * Enables automatic scaling calculation.
1989 *
1990 * If set, the rest of the registers are ignored, and the calculated values can
1991 * be read back from the register.
1992 */
1993# define TV_AUTO_SCALE (1 << 31)
1994/**
1995 * Disables the vertical filter.
1996 *
1997 * This is required on modes more than 1024 pixels wide */
1998# define TV_V_FILTER_BYPASS (1 << 29)
1999/** Enables adaptive vertical filtering */
2000# define TV_VADAPT (1 << 28)
2001# define TV_VADAPT_MODE_MASK (3 << 26)
2002/** Selects the least adaptive vertical filtering mode */
2003# define TV_VADAPT_MODE_LEAST (0 << 26)
2004/** Selects the moderately adaptive vertical filtering mode */
2005# define TV_VADAPT_MODE_MODERATE (1 << 26)
2006/** Selects the most adaptive vertical filtering mode */
2007# define TV_VADAPT_MODE_MOST (3 << 26)
2008/**
2009 * Sets the horizontal scaling factor.
2010 *
2011 * This should be the fractional part of the horizontal scaling factor divided
2012 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2013 *
2014 * (src width - 1) / ((oversample * dest width) - 1)
2015 */
2016# define TV_HSCALE_FRAC_MASK 0x00003fff
2017# define TV_HSCALE_FRAC_SHIFT 0
2018
2019#define TV_FILTER_CTL_2 0x68084
2020/**
2021 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2022 *
2023 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2024 */
2025# define TV_VSCALE_INT_MASK 0x00038000
2026# define TV_VSCALE_INT_SHIFT 15
2027/**
2028 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2029 *
2030 * \sa TV_VSCALE_INT_MASK
2031 */
2032# define TV_VSCALE_FRAC_MASK 0x00007fff
2033# define TV_VSCALE_FRAC_SHIFT 0
2034
2035#define TV_FILTER_CTL_3 0x68088
2036/**
2037 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2038 *
2039 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2040 *
2041 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2042 */
2043# define TV_VSCALE_IP_INT_MASK 0x00038000
2044# define TV_VSCALE_IP_INT_SHIFT 15
2045/**
2046 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2047 *
2048 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2049 *
2050 * \sa TV_VSCALE_IP_INT_MASK
2051 */
2052# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2053# define TV_VSCALE_IP_FRAC_SHIFT 0
2054
2055#define TV_CC_CONTROL 0x68090
2056# define TV_CC_ENABLE (1 << 31)
2057/**
2058 * Specifies which field to send the CC data in.
2059 *
2060 * CC data is usually sent in field 0.
2061 */
2062# define TV_CC_FID_MASK (1 << 27)
2063# define TV_CC_FID_SHIFT 27
2064/** Sets the horizontal position of the CC data. Usually 135. */
2065# define TV_CC_HOFF_MASK 0x03ff0000
2066# define TV_CC_HOFF_SHIFT 16
2067/** Sets the vertical position of the CC data. Usually 21 */
2068# define TV_CC_LINE_MASK 0x0000003f
2069# define TV_CC_LINE_SHIFT 0
2070
2071#define TV_CC_DATA 0x68094
2072# define TV_CC_RDY (1 << 31)
2073/** Second word of CC data to be transmitted. */
2074# define TV_CC_DATA_2_MASK 0x007f0000
2075# define TV_CC_DATA_2_SHIFT 16
2076/** First word of CC data to be transmitted. */
2077# define TV_CC_DATA_1_MASK 0x0000007f
2078# define TV_CC_DATA_1_SHIFT 0
2079
2080#define TV_H_LUMA_0 0x68100
2081#define TV_H_LUMA_59 0x681ec
2082#define TV_H_CHROMA_0 0x68200
2083#define TV_H_CHROMA_59 0x682ec
2084#define TV_V_LUMA_0 0x68300
2085#define TV_V_LUMA_42 0x683a8
2086#define TV_V_CHROMA_0 0x68400
2087#define TV_V_CHROMA_42 0x684a8
2088
2089/* Display Port */
2090#define DP_A 0x64000 /* eDP */
2091#define DP_B 0x64100
2092#define DP_C 0x64200
2093#define DP_D 0x64300
2094
2095#define DP_PORT_EN (1 << 31)
2096#define DP_PIPEB_SELECT (1 << 30)
2097#define DP_PIPE_MASK (1 << 30)
2098
2099/* Link training mode - select a suitable mode for each stage */
2100#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2101#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2102#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2103#define DP_LINK_TRAIN_OFF (3 << 28)
2104#define DP_LINK_TRAIN_MASK (3 << 28)
2105#define DP_LINK_TRAIN_SHIFT 28
2106
2107/* CPT Link training mode */
2108#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2109#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2110#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2111#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2112#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2113#define DP_LINK_TRAIN_SHIFT_CPT 8
2114
2115/* Signal voltages. These are mostly controlled by the other end */
2116#define DP_VOLTAGE_0_4 (0 << 25)
2117#define DP_VOLTAGE_0_6 (1 << 25)
2118#define DP_VOLTAGE_0_8 (2 << 25)
2119#define DP_VOLTAGE_1_2 (3 << 25)
2120#define DP_VOLTAGE_MASK (7 << 25)
2121#define DP_VOLTAGE_SHIFT 25
2122
2123/* Signal pre-emphasis levels, like voltages, the other end tells us what
2124 * they want
2125 */
2126#define DP_PRE_EMPHASIS_0 (0 << 22)
2127#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2128#define DP_PRE_EMPHASIS_6 (2 << 22)
2129#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2130#define DP_PRE_EMPHASIS_MASK (7 << 22)
2131#define DP_PRE_EMPHASIS_SHIFT 22
2132
2133/* How many wires to use. I guess 3 was too hard */
2134#define DP_PORT_WIDTH_1 (0 << 19)
2135#define DP_PORT_WIDTH_2 (1 << 19)
2136#define DP_PORT_WIDTH_4 (3 << 19)
2137#define DP_PORT_WIDTH_MASK (7 << 19)
2138
2139/* Mystic DPCD version 1.1 special mode */
2140#define DP_ENHANCED_FRAMING (1 << 18)
2141
2142/* eDP */
2143#define DP_PLL_FREQ_270MHZ (0 << 16)
2144#define DP_PLL_FREQ_160MHZ (1 << 16)
2145#define DP_PLL_FREQ_MASK (3 << 16)
2146
2147/** locked once port is enabled */
2148#define DP_PORT_REVERSAL (1 << 15)
2149
2150/* eDP */
2151#define DP_PLL_ENABLE (1 << 14)
2152
2153/** sends the clock on lane 15 of the PEG for debug */
2154#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2155
2156#define DP_SCRAMBLING_DISABLE (1 << 12)
2157#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2158
2159/** limit RGB values to avoid confusing TVs */
2160#define DP_COLOR_RANGE_16_235 (1 << 8)
2161
2162/** Turn on the audio link */
2163#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2164
2165/** vs and hs sync polarity */
2166#define DP_SYNC_VS_HIGH (1 << 4)
2167#define DP_SYNC_HS_HIGH (1 << 3)
2168
2169/** A fantasy */
2170#define DP_DETECTED (1 << 2)
2171
2172/** The aux channel provides a way to talk to the
2173 * signal sink for DDC etc. Max packet size supported
2174 * is 20 bytes in each direction, hence the 5 fixed
2175 * data registers
2176 */
2177#define DPA_AUX_CH_CTL 0x64010
2178#define DPA_AUX_CH_DATA1 0x64014
2179#define DPA_AUX_CH_DATA2 0x64018
2180#define DPA_AUX_CH_DATA3 0x6401c
2181#define DPA_AUX_CH_DATA4 0x64020
2182#define DPA_AUX_CH_DATA5 0x64024
2183
2184#define DPB_AUX_CH_CTL 0x64110
2185#define DPB_AUX_CH_DATA1 0x64114
2186#define DPB_AUX_CH_DATA2 0x64118
2187#define DPB_AUX_CH_DATA3 0x6411c
2188#define DPB_AUX_CH_DATA4 0x64120
2189#define DPB_AUX_CH_DATA5 0x64124
2190
2191#define DPC_AUX_CH_CTL 0x64210
2192#define DPC_AUX_CH_DATA1 0x64214
2193#define DPC_AUX_CH_DATA2 0x64218
2194#define DPC_AUX_CH_DATA3 0x6421c
2195#define DPC_AUX_CH_DATA4 0x64220
2196#define DPC_AUX_CH_DATA5 0x64224
2197
2198#define DPD_AUX_CH_CTL 0x64310
2199#define DPD_AUX_CH_DATA1 0x64314
2200#define DPD_AUX_CH_DATA2 0x64318
2201#define DPD_AUX_CH_DATA3 0x6431c
2202#define DPD_AUX_CH_DATA4 0x64320
2203#define DPD_AUX_CH_DATA5 0x64324
2204
2205#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2206#define DP_AUX_CH_CTL_DONE (1 << 30)
2207#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2208#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2209#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2210#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2211#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2212#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2213#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2214#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2215#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2216#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2217#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2218#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2219#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2220#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2221#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2222#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2223#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2224#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2225#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2226
2227/*
2228 * Computing GMCH M and N values for the Display Port link
2229 *
2230 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2231 *
2232 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2233 *
2234 * The GMCH value is used internally
2235 *
2236 * bytes_per_pixel is the number of bytes coming out of the plane,
2237 * which is after the LUTs, so we want the bytes for our color format.
2238 * For our current usage, this is always 3, one byte for R, G and B.
2239 */
2240#define _PIPEA_GMCH_DATA_M 0x70050
2241#define _PIPEB_GMCH_DATA_M 0x71050
2242
2243/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2244#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2245#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2246
2247#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2248
2249#define _PIPEA_GMCH_DATA_N 0x70054
2250#define _PIPEB_GMCH_DATA_N 0x71054
2251#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2252
2253/*
2254 * Computing Link M and N values for the Display Port link
2255 *
2256 * Link M / N = pixel_clock / ls_clk
2257 *
2258 * (the DP spec calls pixel_clock the 'strm_clk')
2259 *
2260 * The Link value is transmitted in the Main Stream
2261 * Attributes and VB-ID.
2262 */
2263
2264#define _PIPEA_DP_LINK_M 0x70060
2265#define _PIPEB_DP_LINK_M 0x71060
2266#define PIPEA_DP_LINK_M_MASK (0xffffff)
2267
2268#define _PIPEA_DP_LINK_N 0x70064
2269#define _PIPEB_DP_LINK_N 0x71064
2270#define PIPEA_DP_LINK_N_MASK (0xffffff)
2271
2272#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2273#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2274#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2275#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2276
2277/* Display & cursor control */
2278
2279/* Pipe A */
2280#define _PIPEADSL 0x70000
2281#define DSL_LINEMASK 0x00000fff
2282#define _PIPEACONF 0x70008
2283#define PIPECONF_ENABLE (1<<31)
2284#define PIPECONF_DISABLE 0
2285#define PIPECONF_DOUBLE_WIDE (1<<30)
2286#define I965_PIPECONF_ACTIVE (1<<30)
2287#define PIPECONF_SINGLE_WIDE 0
2288#define PIPECONF_PIPE_UNLOCKED 0
2289#define PIPECONF_PIPE_LOCKED (1<<25)
2290#define PIPECONF_PALETTE 0
2291#define PIPECONF_GAMMA (1<<24)
2292#define PIPECONF_FORCE_BORDER (1<<25)
2293#define PIPECONF_PROGRESSIVE (0 << 21)
2294#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2295#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2296#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2297#define PIPECONF_BPP_MASK (0x000000e0)
2298#define PIPECONF_BPP_8 (0<<5)
2299#define PIPECONF_BPP_10 (1<<5)
2300#define PIPECONF_BPP_6 (2<<5)
2301#define PIPECONF_BPP_12 (3<<5)
2302#define PIPECONF_DITHER_EN (1<<4)
2303#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2304#define PIPECONF_DITHER_TYPE_SP (0<<2)
2305#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2306#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2307#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2308#define _PIPEASTAT 0x70024
2309#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2310#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2311#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2312#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2313#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2314#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2315#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2316#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2317#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2318#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2319#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2320#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2321#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2322#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2323#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2324#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2325#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2326#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2327#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2328#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2329#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2330#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2331#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2332#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2333#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2334#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2335#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2336#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2337#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2338#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2339#define PIPE_8BPC (0 << 5)
2340#define PIPE_10BPC (1 << 5)
2341#define PIPE_6BPC (2 << 5)
2342#define PIPE_12BPC (3 << 5)
2343
2344#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2345#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2346#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2347#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2348#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2349#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2350
2351#define DSPARB 0x70030
2352#define DSPARB_CSTART_MASK (0x7f << 7)
2353#define DSPARB_CSTART_SHIFT 7
2354#define DSPARB_BSTART_MASK (0x7f)
2355#define DSPARB_BSTART_SHIFT 0
2356#define DSPARB_BEND_SHIFT 9 /* on 855 */
2357#define DSPARB_AEND_SHIFT 0
2358
2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8
2365#define DSPFW_PLANEB_MASK (0x7f<<8)
2366#define DSPFW_PLANEA_MASK (0x7f)
2367#define DSPFW2 0x70038
2368#define DSPFW_CURSORA_MASK 0x00003f00
2369#define DSPFW_CURSORA_SHIFT 8
2370#define DSPFW_PLANEC_MASK (0x7f)
2371#define DSPFW3 0x7003c
2372#define DSPFW_HPLL_SR_EN (1<<31)
2373#define DSPFW_CURSOR_SR_SHIFT 24
2374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
2375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2376#define DSPFW_HPLL_CURSOR_SHIFT 16
2377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2378#define DSPFW_HPLL_SR_MASK (0x1ff)
2379
2380/* FIFO watermark sizes etc */
2381#define G4X_FIFO_LINE_SIZE 64
2382#define I915_FIFO_LINE_SIZE 64
2383#define I830_FIFO_LINE_SIZE 32
2384
2385#define G4X_FIFO_SIZE 127
2386#define I965_FIFO_SIZE 512
2387#define I945_FIFO_SIZE 127
2388#define I915_FIFO_SIZE 95
2389#define I855GM_FIFO_SIZE 127 /* In cachelines */
2390#define I830_FIFO_SIZE 95
2391
2392#define G4X_MAX_WM 0x3f
2393#define I915_MAX_WM 0x3f
2394
2395#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2396#define PINEVIEW_FIFO_LINE_SIZE 64
2397#define PINEVIEW_MAX_WM 0x1ff
2398#define PINEVIEW_DFT_WM 0x3f
2399#define PINEVIEW_DFT_HPLLOFF_WM 0
2400#define PINEVIEW_GUARD_WM 10
2401#define PINEVIEW_CURSOR_FIFO 64
2402#define PINEVIEW_CURSOR_MAX_WM 0x3f
2403#define PINEVIEW_CURSOR_DFT_WM 0
2404#define PINEVIEW_CURSOR_GUARD_WM 5
2405
2406#define I965_CURSOR_FIFO 64
2407#define I965_CURSOR_MAX_WM 32
2408#define I965_CURSOR_DFT_WM 8
2409
2410/* define the Watermark register on Ironlake */
2411#define WM0_PIPEA_ILK 0x45100
2412#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2413#define WM0_PIPE_PLANE_SHIFT 16
2414#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2415#define WM0_PIPE_SPRITE_SHIFT 8
2416#define WM0_PIPE_CURSOR_MASK (0x1f)
2417
2418#define WM0_PIPEB_ILK 0x45104
2419#define WM1_LP_ILK 0x45108
2420#define WM1_LP_SR_EN (1<<31)
2421#define WM1_LP_LATENCY_SHIFT 24
2422#define WM1_LP_LATENCY_MASK (0x7f<<24)
2423#define WM1_LP_FBC_MASK (0xf<<20)
2424#define WM1_LP_FBC_SHIFT 20
2425#define WM1_LP_SR_MASK (0x1ff<<8)
2426#define WM1_LP_SR_SHIFT 8
2427#define WM1_LP_CURSOR_MASK (0x3f)
2428#define WM2_LP_ILK 0x4510c
2429#define WM2_LP_EN (1<<31)
2430#define WM3_LP_ILK 0x45110
2431#define WM3_LP_EN (1<<31)
2432#define WM1S_LP_ILK 0x45120
2433#define WM1S_LP_EN (1<<31)
2434
2435/* Memory latency timer register */
2436#define MLTR_ILK 0x11222
2437#define MLTR_WM1_SHIFT 0
2438#define MLTR_WM2_SHIFT 8
2439/* the unit of memory self-refresh latency time is 0.5us */
2440#define ILK_SRLT_MASK 0x3f
2441#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2442#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2443#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2444
2445/* define the fifo size on Ironlake */
2446#define ILK_DISPLAY_FIFO 128
2447#define ILK_DISPLAY_MAXWM 64
2448#define ILK_DISPLAY_DFTWM 8
2449#define ILK_CURSOR_FIFO 32
2450#define ILK_CURSOR_MAXWM 16
2451#define ILK_CURSOR_DFTWM 8
2452
2453#define ILK_DISPLAY_SR_FIFO 512
2454#define ILK_DISPLAY_MAX_SRWM 0x1ff
2455#define ILK_DISPLAY_DFT_SRWM 0x3f
2456#define ILK_CURSOR_SR_FIFO 64
2457#define ILK_CURSOR_MAX_SRWM 0x3f
2458#define ILK_CURSOR_DFT_SRWM 8
2459
2460#define ILK_FIFO_LINE_SIZE 64
2461
2462/* define the WM info on Sandybridge */
2463#define SNB_DISPLAY_FIFO 128
2464#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2465#define SNB_DISPLAY_DFTWM 8
2466#define SNB_CURSOR_FIFO 32
2467#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2468#define SNB_CURSOR_DFTWM 8
2469
2470#define SNB_DISPLAY_SR_FIFO 512
2471#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2472#define SNB_DISPLAY_DFT_SRWM 0x3f
2473#define SNB_CURSOR_SR_FIFO 64
2474#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2475#define SNB_CURSOR_DFT_SRWM 8
2476
2477#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2478
2479#define SNB_FIFO_LINE_SIZE 64
2480
2481
2482/* the address where we get all kinds of latency value */
2483#define SSKPD 0x5d10
2484#define SSKPD_WM_MASK 0x3f
2485#define SSKPD_WM0_SHIFT 0
2486#define SSKPD_WM1_SHIFT 8
2487#define SSKPD_WM2_SHIFT 16
2488#define SSKPD_WM3_SHIFT 24
2489
2490#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2491#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2492#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2493#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2494#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2495
2496/*
2497 * The two pipe frame counter registers are not synchronized, so
2498 * reading a stable value is somewhat tricky. The following code
2499 * should work:
2500 *
2501 * do {
2502 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2503 * PIPE_FRAME_HIGH_SHIFT;
2504 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2505 * PIPE_FRAME_LOW_SHIFT);
2506 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2507 * PIPE_FRAME_HIGH_SHIFT);
2508 * } while (high1 != high2);
2509 * frame = (high1 << 8) | low1;
2510 */
2511#define _PIPEAFRAMEHIGH 0x70040
2512#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2513#define PIPE_FRAME_HIGH_SHIFT 0
2514#define _PIPEAFRAMEPIXEL 0x70044
2515#define PIPE_FRAME_LOW_MASK 0xff000000
2516#define PIPE_FRAME_LOW_SHIFT 24
2517#define PIPE_PIXEL_MASK 0x00ffffff
2518#define PIPE_PIXEL_SHIFT 0
2519/* GM45+ just has to be different */
2520#define _PIPEA_FRMCOUNT_GM45 0x70040
2521#define _PIPEA_FLIPCOUNT_GM45 0x70044
2522#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2523
2524/* Cursor A & B regs */
2525#define _CURACNTR 0x70080
2526/* Old style CUR*CNTR flags (desktop 8xx) */
2527#define CURSOR_ENABLE 0x80000000
2528#define CURSOR_GAMMA_ENABLE 0x40000000
2529#define CURSOR_STRIDE_MASK 0x30000000
2530#define CURSOR_FORMAT_SHIFT 24
2531#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2532#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2533#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2534#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2535#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2536#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2537/* New style CUR*CNTR flags */
2538#define CURSOR_MODE 0x27
2539#define CURSOR_MODE_DISABLE 0x00
2540#define CURSOR_MODE_64_32B_AX 0x07
2541#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2542#define MCURSOR_PIPE_SELECT (1 << 28)
2543#define MCURSOR_PIPE_A 0x00
2544#define MCURSOR_PIPE_B (1 << 28)
2545#define MCURSOR_GAMMA_ENABLE (1 << 26)
2546#define _CURABASE 0x70084
2547#define _CURAPOS 0x70088
2548#define CURSOR_POS_MASK 0x007FF
2549#define CURSOR_POS_SIGN 0x8000
2550#define CURSOR_X_SHIFT 0
2551#define CURSOR_Y_SHIFT 16
2552#define CURSIZE 0x700a0
2553#define _CURBCNTR 0x700c0
2554#define _CURBBASE 0x700c4
2555#define _CURBPOS 0x700c8
2556
2557#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2558#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2559#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2560
2561/* Display A control */
2562#define _DSPACNTR 0x70180
2563#define DISPLAY_PLANE_ENABLE (1<<31)
2564#define DISPLAY_PLANE_DISABLE 0
2565#define DISPPLANE_GAMMA_ENABLE (1<<30)
2566#define DISPPLANE_GAMMA_DISABLE 0
2567#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2568#define DISPPLANE_8BPP (0x2<<26)
2569#define DISPPLANE_15_16BPP (0x4<<26)
2570#define DISPPLANE_16BPP (0x5<<26)
2571#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2572#define DISPPLANE_32BPP (0x7<<26)
2573#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2574#define DISPPLANE_STEREO_ENABLE (1<<25)
2575#define DISPPLANE_STEREO_DISABLE 0
2576#define DISPPLANE_SEL_PIPE_SHIFT 24
2577#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2578#define DISPPLANE_SEL_PIPE_A 0
2579#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2580#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2581#define DISPPLANE_SRC_KEY_DISABLE 0
2582#define DISPPLANE_LINE_DOUBLE (1<<20)
2583#define DISPPLANE_NO_LINE_DOUBLE 0
2584#define DISPPLANE_STEREO_POLARITY_FIRST 0
2585#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2586#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2587#define DISPPLANE_TILED (1<<10)
2588#define _DSPAADDR 0x70184
2589#define _DSPASTRIDE 0x70188
2590#define _DSPAPOS 0x7018C /* reserved */
2591#define _DSPASIZE 0x70190
2592#define _DSPASURF 0x7019C /* 965+ only */
2593#define _DSPATILEOFF 0x701A4 /* 965+ only */
2594
2595#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2596#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2597#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2598#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2599#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2600#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2601#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2602
2603/* VBIOS flags */
2604#define SWF00 0x71410
2605#define SWF01 0x71414
2606#define SWF02 0x71418
2607#define SWF03 0x7141c
2608#define SWF04 0x71420
2609#define SWF05 0x71424
2610#define SWF06 0x71428
2611#define SWF10 0x70410
2612#define SWF11 0x70414
2613#define SWF14 0x71420
2614#define SWF30 0x72414
2615#define SWF31 0x72418
2616#define SWF32 0x7241c
2617
2618/* Pipe B */
2619#define _PIPEBDSL 0x71000
2620#define _PIPEBCONF 0x71008
2621#define _PIPEBSTAT 0x71024
2622#define _PIPEBFRAMEHIGH 0x71040
2623#define _PIPEBFRAMEPIXEL 0x71044
2624#define _PIPEB_FRMCOUNT_GM45 0x71040
2625#define _PIPEB_FLIPCOUNT_GM45 0x71044
2626
2627
2628/* Display B control */
2629#define _DSPBCNTR 0x71180
2630#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2631#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2632#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2633#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2634#define _DSPBADDR 0x71184
2635#define _DSPBSTRIDE 0x71188
2636#define _DSPBPOS 0x7118C
2637#define _DSPBSIZE 0x71190
2638#define _DSPBSURF 0x7119C
2639#define _DSPBTILEOFF 0x711A4
2640
2641/* VBIOS regs */
2642#define VGACNTRL 0x71400
2643# define VGA_DISP_DISABLE (1 << 31)
2644# define VGA_2X_MODE (1 << 30)
2645# define VGA_PIPE_B_SELECT (1 << 29)
2646
2647/* Ironlake */
2648
2649#define CPU_VGACNTRL 0x41000
2650
2651#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2652#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2653#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2654#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2655#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2656#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2657#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2658#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2659#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2660
2661/* refresh rate hardware control */
2662#define RR_HW_CTL 0x45300
2663#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2664#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2665
2666#define FDI_PLL_BIOS_0 0x46000
2667#define FDI_PLL_FB_CLOCK_MASK 0xff
2668#define FDI_PLL_BIOS_1 0x46004
2669#define FDI_PLL_BIOS_2 0x46008
2670#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2671#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2672#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2673
2674#define PCH_DSPCLK_GATE_D 0x42020
2675# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2676# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2677# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2678# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2679
2680#define PCH_3DCGDIS0 0x46020
2681# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2682# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2683
2684#define PCH_3DCGDIS1 0x46024
2685# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2686
2687#define FDI_PLL_FREQ_CTL 0x46030
2688#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2689#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2690#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2691
2692
2693#define _PIPEA_DATA_M1 0x60030
2694#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2695#define TU_SIZE_MASK 0x7e000000
2696#define PIPE_DATA_M1_OFFSET 0
2697#define _PIPEA_DATA_N1 0x60034
2698#define PIPE_DATA_N1_OFFSET 0
2699
2700#define _PIPEA_DATA_M2 0x60038
2701#define PIPE_DATA_M2_OFFSET 0
2702#define _PIPEA_DATA_N2 0x6003c
2703#define PIPE_DATA_N2_OFFSET 0
2704
2705#define _PIPEA_LINK_M1 0x60040
2706#define PIPE_LINK_M1_OFFSET 0
2707#define _PIPEA_LINK_N1 0x60044
2708#define PIPE_LINK_N1_OFFSET 0
2709
2710#define _PIPEA_LINK_M2 0x60048
2711#define PIPE_LINK_M2_OFFSET 0
2712#define _PIPEA_LINK_N2 0x6004c
2713#define PIPE_LINK_N2_OFFSET 0
2714
2715/* PIPEB timing regs are same start from 0x61000 */
2716
2717#define _PIPEB_DATA_M1 0x61030
2718#define _PIPEB_DATA_N1 0x61034
2719
2720#define _PIPEB_DATA_M2 0x61038
2721#define _PIPEB_DATA_N2 0x6103c
2722
2723#define _PIPEB_LINK_M1 0x61040
2724#define _PIPEB_LINK_N1 0x61044
2725
2726#define _PIPEB_LINK_M2 0x61048
2727#define _PIPEB_LINK_N2 0x6104c
2728
2729#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2730#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2731#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2732#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2733#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2734#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2735#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2736#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2737
2738/* CPU panel fitter */
2739/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2740#define _PFA_CTL_1 0x68080
2741#define _PFB_CTL_1 0x68880
2742#define PF_ENABLE (1<<31)
2743#define PF_FILTER_MASK (3<<23)
2744#define PF_FILTER_PROGRAMMED (0<<23)
2745#define PF_FILTER_MED_3x3 (1<<23)
2746#define PF_FILTER_EDGE_ENHANCE (2<<23)
2747#define PF_FILTER_EDGE_SOFTEN (3<<23)
2748#define _PFA_WIN_SZ 0x68074
2749#define _PFB_WIN_SZ 0x68874
2750#define _PFA_WIN_POS 0x68070
2751#define _PFB_WIN_POS 0x68870
2752#define _PFA_VSCALE 0x68084
2753#define _PFB_VSCALE 0x68884
2754#define _PFA_HSCALE 0x68090
2755#define _PFB_HSCALE 0x68890
2756
2757#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2758#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2759#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2760#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2761#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2762
2763/* legacy palette */
2764#define _LGC_PALETTE_A 0x4a000
2765#define _LGC_PALETTE_B 0x4a800
2766#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2767
2768/* interrupts */
2769#define DE_MASTER_IRQ_CONTROL (1 << 31)
2770#define DE_SPRITEB_FLIP_DONE (1 << 29)
2771#define DE_SPRITEA_FLIP_DONE (1 << 28)
2772#define DE_PLANEB_FLIP_DONE (1 << 27)
2773#define DE_PLANEA_FLIP_DONE (1 << 26)
2774#define DE_PCU_EVENT (1 << 25)
2775#define DE_GTT_FAULT (1 << 24)
2776#define DE_POISON (1 << 23)
2777#define DE_PERFORM_COUNTER (1 << 22)
2778#define DE_PCH_EVENT (1 << 21)
2779#define DE_AUX_CHANNEL_A (1 << 20)
2780#define DE_DP_A_HOTPLUG (1 << 19)
2781#define DE_GSE (1 << 18)
2782#define DE_PIPEB_VBLANK (1 << 15)
2783#define DE_PIPEB_EVEN_FIELD (1 << 14)
2784#define DE_PIPEB_ODD_FIELD (1 << 13)
2785#define DE_PIPEB_LINE_COMPARE (1 << 12)
2786#define DE_PIPEB_VSYNC (1 << 11)
2787#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2788#define DE_PIPEA_VBLANK (1 << 7)
2789#define DE_PIPEA_EVEN_FIELD (1 << 6)
2790#define DE_PIPEA_ODD_FIELD (1 << 5)
2791#define DE_PIPEA_LINE_COMPARE (1 << 4)
2792#define DE_PIPEA_VSYNC (1 << 3)
2793#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2794
2795/* More Ivybridge lolz */
2796#define DE_ERR_DEBUG_IVB (1<<30)
2797#define DE_GSE_IVB (1<<29)
2798#define DE_PCH_EVENT_IVB (1<<28)
2799#define DE_DP_A_HOTPLUG_IVB (1<<27)
2800#define DE_AUX_CHANNEL_A_IVB (1<<26)
2801#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2802#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2803#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2804#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2805#define DE_PIPEB_VBLANK_IVB (1<<5)
2806#define DE_PIPEA_VBLANK_IVB (1<<0)
2807
2808#define DEISR 0x44000
2809#define DEIMR 0x44004
2810#define DEIIR 0x44008
2811#define DEIER 0x4400c
2812
2813/* GT interrupt */
2814#define GT_PIPE_NOTIFY (1 << 4)
2815#define GT_SYNC_STATUS (1 << 2)
2816#define GT_USER_INTERRUPT (1 << 0)
2817#define GT_BSD_USER_INTERRUPT (1 << 5)
2818#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2819#define GT_BLT_USER_INTERRUPT (1 << 22)
2820
2821#define GTISR 0x44010
2822#define GTIMR 0x44014
2823#define GTIIR 0x44018
2824#define GTIER 0x4401c
2825
2826#define ILK_DISPLAY_CHICKEN2 0x42004
2827/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2828#define ILK_ELPIN_409_SELECT (1 << 25)
2829#define ILK_DPARB_GATE (1<<22)
2830#define ILK_VSDPFD_FULL (1<<21)
2831#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2832#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2833#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2834#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2835#define ILK_HDCP_DISABLE (1<<25)
2836#define ILK_eDP_A_DISABLE (1<<24)
2837#define ILK_DESKTOP (1<<23)
2838#define ILK_DSPCLK_GATE 0x42020
2839#define IVB_VRHUNIT_CLK_GATE (1<<28)
2840#define ILK_DPARB_CLK_GATE (1<<5)
2841#define ILK_DPFD_CLK_GATE (1<<7)
2842
2843/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2844#define ILK_CLK_FBC (1<<7)
2845#define ILK_DPFC_DIS1 (1<<8)
2846#define ILK_DPFC_DIS2 (1<<9)
2847
2848#define DISP_ARB_CTL 0x45000
2849#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2850#define DISP_FBC_WM_DIS (1<<15)
2851
2852/* PCH */
2853
2854/* south display engine interrupt */
2855#define SDE_AUDIO_POWER_D (1 << 27)
2856#define SDE_AUDIO_POWER_C (1 << 26)
2857#define SDE_AUDIO_POWER_B (1 << 25)
2858#define SDE_AUDIO_POWER_SHIFT (25)
2859#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2860#define SDE_GMBUS (1 << 24)
2861#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2862#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2863#define SDE_AUDIO_HDCP_MASK (3 << 22)
2864#define SDE_AUDIO_TRANSB (1 << 21)
2865#define SDE_AUDIO_TRANSA (1 << 20)
2866#define SDE_AUDIO_TRANS_MASK (3 << 20)
2867#define SDE_POISON (1 << 19)
2868/* 18 reserved */
2869#define SDE_FDI_RXB (1 << 17)
2870#define SDE_FDI_RXA (1 << 16)
2871#define SDE_FDI_MASK (3 << 16)
2872#define SDE_AUXD (1 << 15)
2873#define SDE_AUXC (1 << 14)
2874#define SDE_AUXB (1 << 13)
2875#define SDE_AUX_MASK (7 << 13)
2876/* 12 reserved */
2877#define SDE_CRT_HOTPLUG (1 << 11)
2878#define SDE_PORTD_HOTPLUG (1 << 10)
2879#define SDE_PORTC_HOTPLUG (1 << 9)
2880#define SDE_PORTB_HOTPLUG (1 << 8)
2881#define SDE_SDVOB_HOTPLUG (1 << 6)
2882#define SDE_HOTPLUG_MASK (0xf << 8)
2883#define SDE_TRANSB_CRC_DONE (1 << 5)
2884#define SDE_TRANSB_CRC_ERR (1 << 4)
2885#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2886#define SDE_TRANSA_CRC_DONE (1 << 2)
2887#define SDE_TRANSA_CRC_ERR (1 << 1)
2888#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2889#define SDE_TRANS_MASK (0x3f)
2890/* CPT */
2891#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2895#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2896 SDE_PORTD_HOTPLUG_CPT | \
2897 SDE_PORTC_HOTPLUG_CPT | \
2898 SDE_PORTB_HOTPLUG_CPT)
2899
2900#define SDEISR 0xc4000
2901#define SDEIMR 0xc4004
2902#define SDEIIR 0xc4008
2903#define SDEIER 0xc400c
2904
2905/* digital port hotplug */
2906#define PCH_PORT_HOTPLUG 0xc4030
2907#define PORTD_HOTPLUG_ENABLE (1 << 20)
2908#define PORTD_PULSE_DURATION_2ms (0)
2909#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2910#define PORTD_PULSE_DURATION_6ms (2 << 18)
2911#define PORTD_PULSE_DURATION_100ms (3 << 18)
2912#define PORTD_HOTPLUG_NO_DETECT (0)
2913#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2914#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2915#define PORTC_HOTPLUG_ENABLE (1 << 12)
2916#define PORTC_PULSE_DURATION_2ms (0)
2917#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2918#define PORTC_PULSE_DURATION_6ms (2 << 10)
2919#define PORTC_PULSE_DURATION_100ms (3 << 10)
2920#define PORTC_HOTPLUG_NO_DETECT (0)
2921#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2922#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2923#define PORTB_HOTPLUG_ENABLE (1 << 4)
2924#define PORTB_PULSE_DURATION_2ms (0)
2925#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2926#define PORTB_PULSE_DURATION_6ms (2 << 2)
2927#define PORTB_PULSE_DURATION_100ms (3 << 2)
2928#define PORTB_HOTPLUG_NO_DETECT (0)
2929#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2930#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2931
2932#define PCH_GPIOA 0xc5010
2933#define PCH_GPIOB 0xc5014
2934#define PCH_GPIOC 0xc5018
2935#define PCH_GPIOD 0xc501c
2936#define PCH_GPIOE 0xc5020
2937#define PCH_GPIOF 0xc5024
2938
2939#define PCH_GMBUS0 0xc5100
2940#define PCH_GMBUS1 0xc5104
2941#define PCH_GMBUS2 0xc5108
2942#define PCH_GMBUS3 0xc510c
2943#define PCH_GMBUS4 0xc5110
2944#define PCH_GMBUS5 0xc5120
2945
2946#define _PCH_DPLL_A 0xc6014
2947#define _PCH_DPLL_B 0xc6018
2948#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2949
2950#define _PCH_FPA0 0xc6040
2951#define FP_CB_TUNE (0x3<<22)
2952#define _PCH_FPA1 0xc6044
2953#define _PCH_FPB0 0xc6048
2954#define _PCH_FPB1 0xc604c
2955#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2956#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2957
2958#define PCH_DPLL_TEST 0xc606c
2959
2960#define PCH_DREF_CONTROL 0xC6200
2961#define DREF_CONTROL_MASK 0x7fc3
2962#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2963#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2964#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2965#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2966#define DREF_SSC_SOURCE_DISABLE (0<<11)
2967#define DREF_SSC_SOURCE_ENABLE (2<<11)
2968#define DREF_SSC_SOURCE_MASK (3<<11)
2969#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2970#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2971#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2972#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2973#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2974#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2975#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2976#define DREF_SSC4_DOWNSPREAD (0<<6)
2977#define DREF_SSC4_CENTERSPREAD (1<<6)
2978#define DREF_SSC1_DISABLE (0<<1)
2979#define DREF_SSC1_ENABLE (1<<1)
2980#define DREF_SSC4_DISABLE (0)
2981#define DREF_SSC4_ENABLE (1)
2982
2983#define PCH_RAWCLK_FREQ 0xc6204
2984#define FDL_TP1_TIMER_SHIFT 12
2985#define FDL_TP1_TIMER_MASK (3<<12)
2986#define FDL_TP2_TIMER_SHIFT 10
2987#define FDL_TP2_TIMER_MASK (3<<10)
2988#define RAWCLK_FREQ_MASK 0x3ff
2989
2990#define PCH_DPLL_TMR_CFG 0xc6208
2991
2992#define PCH_SSC4_PARMS 0xc6210
2993#define PCH_SSC4_AUX_PARMS 0xc6214
2994
2995#define PCH_DPLL_SEL 0xc7000
2996#define TRANSA_DPLL_ENABLE (1<<3)
2997#define TRANSA_DPLLB_SEL (1<<0)
2998#define TRANSA_DPLLA_SEL 0
2999#define TRANSB_DPLL_ENABLE (1<<7)
3000#define TRANSB_DPLLB_SEL (1<<4)
3001#define TRANSB_DPLLA_SEL (0)
3002#define TRANSC_DPLL_ENABLE (1<<11)
3003#define TRANSC_DPLLB_SEL (1<<8)
3004#define TRANSC_DPLLA_SEL (0)
3005
3006/* transcoder */
3007
3008#define _TRANS_HTOTAL_A 0xe0000
3009#define TRANS_HTOTAL_SHIFT 16
3010#define TRANS_HACTIVE_SHIFT 0
3011#define _TRANS_HBLANK_A 0xe0004
3012#define TRANS_HBLANK_END_SHIFT 16
3013#define TRANS_HBLANK_START_SHIFT 0
3014#define _TRANS_HSYNC_A 0xe0008
3015#define TRANS_HSYNC_END_SHIFT 16
3016#define TRANS_HSYNC_START_SHIFT 0
3017#define _TRANS_VTOTAL_A 0xe000c
3018#define TRANS_VTOTAL_SHIFT 16
3019#define TRANS_VACTIVE_SHIFT 0
3020#define _TRANS_VBLANK_A 0xe0010
3021#define TRANS_VBLANK_END_SHIFT 16
3022#define TRANS_VBLANK_START_SHIFT 0
3023#define _TRANS_VSYNC_A 0xe0014
3024#define TRANS_VSYNC_END_SHIFT 16
3025#define TRANS_VSYNC_START_SHIFT 0
3026
3027#define _TRANSA_DATA_M1 0xe0030
3028#define _TRANSA_DATA_N1 0xe0034
3029#define _TRANSA_DATA_M2 0xe0038
3030#define _TRANSA_DATA_N2 0xe003c
3031#define _TRANSA_DP_LINK_M1 0xe0040
3032#define _TRANSA_DP_LINK_N1 0xe0044
3033#define _TRANSA_DP_LINK_M2 0xe0048
3034#define _TRANSA_DP_LINK_N2 0xe004c
3035
3036/* Per-transcoder DIP controls */
3037
3038#define _VIDEO_DIP_CTL_A 0xe0200
3039#define _VIDEO_DIP_DATA_A 0xe0208
3040#define _VIDEO_DIP_GCP_A 0xe0210
3041
3042#define _VIDEO_DIP_CTL_B 0xe1200
3043#define _VIDEO_DIP_DATA_B 0xe1208
3044#define _VIDEO_DIP_GCP_B 0xe1210
3045
3046#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3047#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3048#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3049
3050#define _TRANS_HTOTAL_B 0xe1000
3051#define _TRANS_HBLANK_B 0xe1004
3052#define _TRANS_HSYNC_B 0xe1008
3053#define _TRANS_VTOTAL_B 0xe100c
3054#define _TRANS_VBLANK_B 0xe1010
3055#define _TRANS_VSYNC_B 0xe1014
3056
3057#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3058#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3059#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3060#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3061#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3062#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3063
3064#define _TRANSB_DATA_M1 0xe1030
3065#define _TRANSB_DATA_N1 0xe1034
3066#define _TRANSB_DATA_M2 0xe1038
3067#define _TRANSB_DATA_N2 0xe103c
3068#define _TRANSB_DP_LINK_M1 0xe1040
3069#define _TRANSB_DP_LINK_N1 0xe1044
3070#define _TRANSB_DP_LINK_M2 0xe1048
3071#define _TRANSB_DP_LINK_N2 0xe104c
3072
3073#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3074#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3075#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3076#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3077#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3078#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3079#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3080#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3081
3082#define _TRANSACONF 0xf0008
3083#define _TRANSBCONF 0xf1008
3084#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3085#define TRANS_DISABLE (0<<31)
3086#define TRANS_ENABLE (1<<31)
3087#define TRANS_STATE_MASK (1<<30)
3088#define TRANS_STATE_DISABLE (0<<30)
3089#define TRANS_STATE_ENABLE (1<<30)
3090#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3091#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3092#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3093#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3094#define TRANS_DP_AUDIO_ONLY (1<<26)
3095#define TRANS_DP_VIDEO_AUDIO (0<<26)
3096#define TRANS_PROGRESSIVE (0<<21)
3097#define TRANS_8BPC (0<<5)
3098#define TRANS_10BPC (1<<5)
3099#define TRANS_6BPC (2<<5)
3100#define TRANS_12BPC (3<<5)
3101
3102#define _TRANSA_CHICKEN2 0xf0064
3103#define _TRANSB_CHICKEN2 0xf1064
3104#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3105#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3106
3107#define SOUTH_CHICKEN1 0xc2000
3108#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3109#define FDIA_PHASE_SYNC_SHIFT_EN 18
3110#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3111#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3112#define SOUTH_CHICKEN2 0xc2004
3113#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3114
3115#define _FDI_RXA_CHICKEN 0xc200c
3116#define _FDI_RXB_CHICKEN 0xc2010
3117#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3118#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3119#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3120
3121#define SOUTH_DSPCLK_GATE_D 0xc2020
3122#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3123
3124/* CPU: FDI_TX */
3125#define _FDI_TXA_CTL 0x60100
3126#define _FDI_TXB_CTL 0x61100
3127#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3128#define FDI_TX_DISABLE (0<<31)
3129#define FDI_TX_ENABLE (1<<31)
3130#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3131#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3133#define FDI_LINK_TRAIN_NONE (3<<28)
3134#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3135#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3136#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3137#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3138#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3139#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3140#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3141#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3142/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3143 SNB has different settings. */
3144/* SNB A-stepping */
3145#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3146#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3147#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3148#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3149/* SNB B-stepping */
3150#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3151#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3152#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3153#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3154#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3155#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3156#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3157#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3158#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3159#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3160/* Ironlake: hardwired to 1 */
3161#define FDI_TX_PLL_ENABLE (1<<14)
3162
3163/* Ivybridge has different bits for lolz */
3164#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3165#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3166#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3167#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3168
3169/* both Tx and Rx */
3170#define FDI_LINK_TRAIN_AUTO (1<<10)
3171#define FDI_SCRAMBLING_ENABLE (0<<7)
3172#define FDI_SCRAMBLING_DISABLE (1<<7)
3173
3174/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3175#define _FDI_RXA_CTL 0xf000c
3176#define _FDI_RXB_CTL 0xf100c
3177#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3178#define FDI_RX_ENABLE (1<<31)
3179/* train, dp width same as FDI_TX */
3180#define FDI_FS_ERRC_ENABLE (1<<27)
3181#define FDI_FE_ERRC_ENABLE (1<<26)
3182#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3183#define FDI_8BPC (0<<16)
3184#define FDI_10BPC (1<<16)
3185#define FDI_6BPC (2<<16)
3186#define FDI_12BPC (3<<16)
3187#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3188#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3189#define FDI_RX_PLL_ENABLE (1<<13)
3190#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3191#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3192#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3193#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3194#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3195#define FDI_PCDCLK (1<<4)
3196/* CPT */
3197#define FDI_AUTO_TRAINING (1<<10)
3198#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3199#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3200#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3201#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3202#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3203
3204#define _FDI_RXA_MISC 0xf0010
3205#define _FDI_RXB_MISC 0xf1010
3206#define _FDI_RXA_TUSIZE1 0xf0030
3207#define _FDI_RXA_TUSIZE2 0xf0038
3208#define _FDI_RXB_TUSIZE1 0xf1030
3209#define _FDI_RXB_TUSIZE2 0xf1038
3210#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3211#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3212#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3213
3214/* FDI_RX interrupt register format */
3215#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3216#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3217#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3218#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3219#define FDI_RX_FS_CODE_ERR (1<<6)
3220#define FDI_RX_FE_CODE_ERR (1<<5)
3221#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3222#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3223#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3224#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3225#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3226
3227#define _FDI_RXA_IIR 0xf0014
3228#define _FDI_RXA_IMR 0xf0018
3229#define _FDI_RXB_IIR 0xf1014
3230#define _FDI_RXB_IMR 0xf1018
3231#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3232#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3233
3234#define FDI_PLL_CTL_1 0xfe000
3235#define FDI_PLL_CTL_2 0xfe004
3236
3237/* CRT */
3238#define PCH_ADPA 0xe1100
3239#define ADPA_TRANS_SELECT_MASK (1<<30)
3240#define ADPA_TRANS_A_SELECT 0
3241#define ADPA_TRANS_B_SELECT (1<<30)
3242#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3243#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3244#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3245#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3246#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3247#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3248#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3249#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3250#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3251#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3252#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3253#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3254#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3255#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3256#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3257#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3258#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3259#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3260#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3261
3262/* or SDVOB */
3263#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30)
3267#define TRANSCODER(pipe) ((pipe) << 30)
3268#define TRANSCODER_MASK (1 << 30)
3269#define COLOR_FORMAT_8bpc (0)
3270#define COLOR_FORMAT_12bpc (3 << 26)
3271#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3272#define SDVO_ENCODING (0)
3273#define TMDS_ENCODING (2 << 10)
3274#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3275/* CPT */
3276#define HDMI_MODE_SELECT (1 << 9)
3277#define DVI_MODE_SELECT (0)
3278#define SDVOB_BORDER_ENABLE (1 << 7)
3279#define AUDIO_ENABLE (1 << 6)
3280#define VSYNC_ACTIVE_HIGH (1 << 4)
3281#define HSYNC_ACTIVE_HIGH (1 << 3)
3282#define PORT_DETECTED (1 << 2)
3283
3284/* PCH SDVOB multiplex with HDMIB */
3285#define PCH_SDVOB HDMIB
3286
3287#define HDMIC 0xe1150
3288#define HDMID 0xe1160
3289
3290#define PCH_LVDS 0xe1180
3291#define LVDS_DETECTED (1 << 1)
3292
3293#define BLC_PWM_CPU_CTL2 0x48250
3294#define PWM_ENABLE (1 << 31)
3295#define PWM_PIPE_A (0 << 29)
3296#define PWM_PIPE_B (1 << 29)
3297#define BLC_PWM_CPU_CTL 0x48254
3298
3299#define BLC_PWM_PCH_CTL1 0xc8250
3300#define PWM_PCH_ENABLE (1 << 31)
3301#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3302#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3303#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3304#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3305
3306#define BLC_PWM_PCH_CTL2 0xc8254
3307
3308#define PCH_PP_STATUS 0xc7200
3309#define PCH_PP_CONTROL 0xc7204
3310#define PANEL_UNLOCK_REGS (0xabcd << 16)
3311#define EDP_FORCE_VDD (1 << 3)
3312#define EDP_BLC_ENABLE (1 << 2)
3313#define PANEL_POWER_RESET (1 << 1)
3314#define PANEL_POWER_OFF (0 << 0)
3315#define PANEL_POWER_ON (1 << 0)
3316#define PCH_PP_ON_DELAYS 0xc7208
3317#define EDP_PANEL (1 << 30)
3318#define PCH_PP_OFF_DELAYS 0xc720c
3319#define PCH_PP_DIVISOR 0xc7210
3320
3321#define PCH_DP_B 0xe4100
3322#define PCH_DPB_AUX_CH_CTL 0xe4110
3323#define PCH_DPB_AUX_CH_DATA1 0xe4114
3324#define PCH_DPB_AUX_CH_DATA2 0xe4118
3325#define PCH_DPB_AUX_CH_DATA3 0xe411c
3326#define PCH_DPB_AUX_CH_DATA4 0xe4120
3327#define PCH_DPB_AUX_CH_DATA5 0xe4124
3328
3329#define PCH_DP_C 0xe4200
3330#define PCH_DPC_AUX_CH_CTL 0xe4210
3331#define PCH_DPC_AUX_CH_DATA1 0xe4214
3332#define PCH_DPC_AUX_CH_DATA2 0xe4218
3333#define PCH_DPC_AUX_CH_DATA3 0xe421c
3334#define PCH_DPC_AUX_CH_DATA4 0xe4220
3335#define PCH_DPC_AUX_CH_DATA5 0xe4224
3336
3337#define PCH_DP_D 0xe4300
3338#define PCH_DPD_AUX_CH_CTL 0xe4310
3339#define PCH_DPD_AUX_CH_DATA1 0xe4314
3340#define PCH_DPD_AUX_CH_DATA2 0xe4318
3341#define PCH_DPD_AUX_CH_DATA3 0xe431c
3342#define PCH_DPD_AUX_CH_DATA4 0xe4320
3343#define PCH_DPD_AUX_CH_DATA5 0xe4324
3344
3345/* CPT */
3346#define PORT_TRANS_A_SEL_CPT 0
3347#define PORT_TRANS_B_SEL_CPT (1<<29)
3348#define PORT_TRANS_C_SEL_CPT (2<<29)
3349#define PORT_TRANS_SEL_MASK (3<<29)
3350#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3351
3352#define TRANS_DP_CTL_A 0xe0300
3353#define TRANS_DP_CTL_B 0xe1300
3354#define TRANS_DP_CTL_C 0xe2300
3355#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3356#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3357#define TRANS_DP_PORT_SEL_B (0<<29)
3358#define TRANS_DP_PORT_SEL_C (1<<29)
3359#define TRANS_DP_PORT_SEL_D (2<<29)
3360#define TRANS_DP_PORT_SEL_NONE (3<<29)
3361#define TRANS_DP_PORT_SEL_MASK (3<<29)
3362#define TRANS_DP_AUDIO_ONLY (1<<26)
3363#define TRANS_DP_ENH_FRAMING (1<<18)
3364#define TRANS_DP_8BPC (0<<9)
3365#define TRANS_DP_10BPC (1<<9)
3366#define TRANS_DP_6BPC (2<<9)
3367#define TRANS_DP_12BPC (3<<9)
3368#define TRANS_DP_BPC_MASK (3<<9)
3369#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3370#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3371#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3372#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3373#define TRANS_DP_SYNC_MASK (3<<3)
3374
3375/* SNB eDP training params */
3376/* SNB A-stepping */
3377#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3378#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3379#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3380#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3381/* SNB B-stepping */
3382#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3383#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3384#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3385#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3386#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3387#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3388
3389#define FORCEWAKE 0xA18C
3390#define FORCEWAKE_ACK 0x130090
3391
3392#define GT_FIFO_FREE_ENTRIES 0x120008
3393#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3394
3395#define GEN6_RPNSWREQ 0xA008
3396#define GEN6_TURBO_DISABLE (1<<31)
3397#define GEN6_FREQUENCY(x) ((x)<<25)
3398#define GEN6_OFFSET(x) ((x)<<19)
3399#define GEN6_AGGRESSIVE_TURBO (0<<15)
3400#define GEN6_RC_VIDEO_FREQ 0xA00C
3401#define GEN6_RC_CONTROL 0xA090
3402#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3403#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3404#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3405#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3406#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3407#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3408#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3409#define GEN6_RP_DOWN_TIMEOUT 0xA010
3410#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3411#define GEN6_RPSTAT1 0xA01C
3412#define GEN6_CAGF_SHIFT 8
3413#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3414#define GEN6_RP_CONTROL 0xA024
3415#define GEN6_RP_MEDIA_TURBO (1<<11)
3416#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3417#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3418#define GEN6_RP_ENABLE (1<<7)
3419#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3420#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3421#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3422#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3423#define GEN6_RP_UP_THRESHOLD 0xA02C
3424#define GEN6_RP_DOWN_THRESHOLD 0xA030
3425#define GEN6_RP_CUR_UP_EI 0xA050
3426#define GEN6_CURICONT_MASK 0xffffff
3427#define GEN6_RP_CUR_UP 0xA054
3428#define GEN6_CURBSYTAVG_MASK 0xffffff
3429#define GEN6_RP_PREV_UP 0xA058
3430#define GEN6_RP_CUR_DOWN_EI 0xA05C
3431#define GEN6_CURIAVG_MASK 0xffffff
3432#define GEN6_RP_CUR_DOWN 0xA060
3433#define GEN6_RP_PREV_DOWN 0xA064
3434#define GEN6_RP_UP_EI 0xA068
3435#define GEN6_RP_DOWN_EI 0xA06C
3436#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3437#define GEN6_RC_STATE 0xA094
3438#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3439#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3440#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3441#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3442#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3443#define GEN6_RC_SLEEP 0xA0B0
3444#define GEN6_RC1e_THRESHOLD 0xA0B4
3445#define GEN6_RC6_THRESHOLD 0xA0B8
3446#define GEN6_RC6p_THRESHOLD 0xA0BC
3447#define GEN6_RC6pp_THRESHOLD 0xA0C0
3448#define GEN6_PMINTRMSK 0xA168
3449
3450#define GEN6_PMISR 0x44020
3451#define GEN6_PMIMR 0x44024 /* rps_lock */
3452#define GEN6_PMIIR 0x44028
3453#define GEN6_PMIER 0x4402C
3454#define GEN6_PM_MBOX_EVENT (1<<25)
3455#define GEN6_PM_THERMAL_EVENT (1<<24)
3456#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3457#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3458#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3459#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3461#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3462 GEN6_PM_RP_DOWN_THRESHOLD | \
3463 GEN6_PM_RP_DOWN_TIMEOUT)
3464
3465#define GEN6_PCODE_MAILBOX 0x138124
3466#define GEN6_PCODE_READY (1<<31)
3467#define GEN6_READ_OC_PARAMS 0xc
3468#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3469#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3470#define GEN6_PCODE_DATA 0x138128
3471#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3472
3473#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include "i915_reg_defs.h"
29#include "display/intel_display_reg_defs.h"
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119#define GU_CNTL_PROTECTED _MMIO(0x10100C)
120#define DEPRESENT REG_BIT(9)
121
122#define GU_CNTL _MMIO(0x101010)
123#define LMEM_INIT REG_BIT(7)
124#define DRIVERFLR REG_BIT(31)
125#define GU_DEBUG _MMIO(0x101018)
126#define DRIVERFLR_STATUS REG_BIT(31)
127
128#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
131#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
132#define GEN6_STOLEN_RESERVED_1M (0 << 4)
133#define GEN6_STOLEN_RESERVED_512K (1 << 4)
134#define GEN6_STOLEN_RESERVED_256K (2 << 4)
135#define GEN6_STOLEN_RESERVED_128K (3 << 4)
136#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
137#define GEN7_STOLEN_RESERVED_1M (0 << 5)
138#define GEN7_STOLEN_RESERVED_256K (1 << 5)
139#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
140#define GEN8_STOLEN_RESERVED_1M (0 << 7)
141#define GEN8_STOLEN_RESERVED_2M (1 << 7)
142#define GEN8_STOLEN_RESERVED_4M (2 << 7)
143#define GEN8_STOLEN_RESERVED_8M (3 << 7)
144#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
146
147#define _VGA_MSR_WRITE _MMIO(0x3c2)
148
149#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
151#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
152
153/*
154 * Reset registers
155 */
156#define DEBUG_RESET_I830 _MMIO(0x6070)
157#define DEBUG_RESET_FULL (1 << 7)
158#define DEBUG_RESET_RENDER (1 << 8)
159#define DEBUG_RESET_DISPLAY (1 << 9)
160
161/*
162 * IOSF sideband
163 */
164#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
165#define IOSF_DEVFN_SHIFT 24
166#define IOSF_OPCODE_SHIFT 16
167#define IOSF_PORT_SHIFT 8
168#define IOSF_BYTE_ENABLES_SHIFT 4
169#define IOSF_BAR_SHIFT 1
170#define IOSF_SB_BUSY (1 << 0)
171#define IOSF_PORT_BUNIT 0x03
172#define IOSF_PORT_PUNIT 0x04
173#define IOSF_PORT_NC 0x11
174#define IOSF_PORT_DPIO 0x12
175#define IOSF_PORT_GPIO_NC 0x13
176#define IOSF_PORT_CCK 0x14
177#define IOSF_PORT_DPIO_2 0x1a
178#define IOSF_PORT_FLISDSI 0x1b
179#define IOSF_PORT_GPIO_SC 0x48
180#define IOSF_PORT_GPIO_SUS 0xa8
181#define IOSF_PORT_CCU 0xa9
182#define CHV_IOSF_PORT_GPIO_N 0x13
183#define CHV_IOSF_PORT_GPIO_SE 0x48
184#define CHV_IOSF_PORT_GPIO_E 0xa8
185#define CHV_IOSF_PORT_GPIO_SW 0xb2
186#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
188
189/* DPIO registers */
190#define DPIO_DEVFN 0
191
192#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
193#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
194#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
195#define DPIO_SFR_BYPASS (1 << 1)
196#define DPIO_CMNRST (1 << 0)
197
198#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
199#define MIPIO_RST_CTRL (1 << 2)
200
201#define _BXT_PHY_CTL_DDI_A 0x64C00
202#define _BXT_PHY_CTL_DDI_B 0x64C10
203#define _BXT_PHY_CTL_DDI_C 0x64C20
204#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
205#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
206#define BXT_PHY_LANE_ENABLED (1 << 8)
207#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
208 _BXT_PHY_CTL_DDI_B)
209
210#define _PHY_CTL_FAMILY_DDI 0x64C90
211#define _PHY_CTL_FAMILY_EDP 0x64C80
212#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
213#define COMMON_RESET_DIS (1 << 31)
214#define BXT_PHY_CTL_FAMILY(phy) \
215 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
216 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
217 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
218
219/* UAIMI scratch pad register 1 */
220#define UAIMI_SPR1 _MMIO(0x4F074)
221/* SKL VccIO mask */
222#define SKL_VCCIO_MASK 0x1
223/* SKL balance leg register */
224#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
225/* I_boost values */
226#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
227#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
228/* Balance leg disable bits */
229#define BALANCE_LEG_DISABLE_SHIFT 23
230#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
231
232/*
233 * Fence registers
234 * [0-7] @ 0x2000 gen2,gen3
235 * [8-15] @ 0x3000 945,g33,pnv
236 *
237 * [0-15] @ 0x3000 gen4,gen5
238 *
239 * [0-15] @ 0x100000 gen6,vlv,chv
240 * [0-31] @ 0x100000 gen7+
241 */
242#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
243#define I830_FENCE_START_MASK 0x07f80000
244#define I830_FENCE_TILING_Y_SHIFT 12
245#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
246#define I830_FENCE_PITCH_SHIFT 4
247#define I830_FENCE_REG_VALID (1 << 0)
248#define I915_FENCE_MAX_PITCH_VAL 4
249#define I830_FENCE_MAX_PITCH_VAL 6
250#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
251
252#define I915_FENCE_START_MASK 0x0ff00000
253#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
254
255#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
256#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
257#define I965_FENCE_PITCH_SHIFT 2
258#define I965_FENCE_TILING_Y_SHIFT 1
259#define I965_FENCE_REG_VALID (1 << 0)
260#define I965_FENCE_MAX_PITCH_VAL 0x0400
261
262#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
263#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
264#define GEN6_FENCE_PITCH_SHIFT 32
265#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
266
267
268/* control register for cpu gtt access */
269#define TILECTL _MMIO(0x101000)
270#define TILECTL_SWZCTL (1 << 0)
271#define TILECTL_TLBPF (1 << 1)
272#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
273#define TILECTL_BACKSNOOP_DIS (1 << 3)
274
275/*
276 * Instruction and interrupt control regs
277 */
278#define PGTBL_CTL _MMIO(0x02020)
279#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
280#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
281#define PGTBL_ER _MMIO(0x02024)
282#define PRB0_BASE (0x2030 - 0x30)
283#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
284#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
285#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
286#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
287#define SRB2_BASE (0x2120 - 0x30) /* 830 */
288#define SRB3_BASE (0x2130 - 0x30) /* 830 */
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define GEN8_BSD2_RING_BASE 0x1c000
293#define GEN11_BSD_RING_BASE 0x1c0000
294#define GEN11_BSD2_RING_BASE 0x1c4000
295#define GEN11_BSD3_RING_BASE 0x1d0000
296#define GEN11_BSD4_RING_BASE 0x1d4000
297#define XEHP_BSD5_RING_BASE 0x1e0000
298#define XEHP_BSD6_RING_BASE 0x1e4000
299#define XEHP_BSD7_RING_BASE 0x1f0000
300#define XEHP_BSD8_RING_BASE 0x1f4000
301#define VEBOX_RING_BASE 0x1a000
302#define GEN11_VEBOX_RING_BASE 0x1c8000
303#define GEN11_VEBOX2_RING_BASE 0x1d8000
304#define XEHP_VEBOX3_RING_BASE 0x1e8000
305#define XEHP_VEBOX4_RING_BASE 0x1f8000
306#define MTL_GSC_RING_BASE 0x11a000
307#define GEN12_COMPUTE0_RING_BASE 0x1a000
308#define GEN12_COMPUTE1_RING_BASE 0x1c000
309#define GEN12_COMPUTE2_RING_BASE 0x1e000
310#define GEN12_COMPUTE3_RING_BASE 0x26000
311#define BLT_RING_BASE 0x22000
312#define XEHPC_BCS1_RING_BASE 0x3e0000
313#define XEHPC_BCS2_RING_BASE 0x3e2000
314#define XEHPC_BCS3_RING_BASE 0x3e4000
315#define XEHPC_BCS4_RING_BASE 0x3e6000
316#define XEHPC_BCS5_RING_BASE 0x3e8000
317#define XEHPC_BCS6_RING_BASE 0x3ea000
318#define XEHPC_BCS7_RING_BASE 0x3ec000
319#define XEHPC_BCS8_RING_BASE 0x3ee000
320#define DG1_GSC_HECI1_BASE 0x00258000
321#define DG1_GSC_HECI2_BASE 0x00259000
322#define DG2_GSC_HECI1_BASE 0x00373000
323#define DG2_GSC_HECI2_BASE 0x00374000
324#define MTL_GSC_HECI1_BASE 0x00116000
325#define MTL_GSC_HECI2_BASE 0x00117000
326
327#define HECI_H_CSR(base) _MMIO((base) + 0x4)
328#define HECI_H_CSR_IE REG_BIT(0)
329#define HECI_H_CSR_IS REG_BIT(1)
330#define HECI_H_CSR_IG REG_BIT(2)
331#define HECI_H_CSR_RDY REG_BIT(3)
332#define HECI_H_CSR_RST REG_BIT(4)
333
334#define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
335#define HECI_H_GS1_ER_PREP REG_BIT(0)
336
337/*
338 * The FWSTS register values are FW defined and can be different between
339 * HECI1 and HECI2
340 */
341#define HECI_FWSTS1 0xc40
342#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
343#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
344#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
345#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
346#define HECI_FWSTS2 0xc48
347#define HECI_FWSTS3 0xc60
348#define HECI_FWSTS4 0xc64
349#define HECI_FWSTS5 0xc68
350#define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19)
351#define HECI_FWSTS6 0xc6c
352
353/* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
354#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
355 HECI_FWSTS1, \
356 HECI_FWSTS2, \
357 HECI_FWSTS3, \
358 HECI_FWSTS4, \
359 HECI_FWSTS5, \
360 HECI_FWSTS6))
361
362#define HSW_GTT_CACHE_EN _MMIO(0x4024)
363#define GTT_CACHE_EN_ALL 0xF0007FFF
364#define GEN7_WR_WATERMARK _MMIO(0x4028)
365#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
366#define ARB_MODE _MMIO(0x4030)
367#define ARB_MODE_SWIZZLE_SNB (1 << 4)
368#define ARB_MODE_SWIZZLE_IVB (1 << 5)
369#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
370#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
371/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
372#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
373#define GEN7_LRA_LIMITS_REG_NUM 13
374#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
375#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
376
377#define GEN7_ERR_INT _MMIO(0x44040)
378#define ERR_INT_POISON (1 << 31)
379#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
380#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
381#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
382#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
383#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
384#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
385#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
386#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
387#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
388
389#define FPGA_DBG _MMIO(0x42300)
390#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
391
392#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
393#define CLAIM_ER_CLR REG_BIT(31)
394#define CLAIM_ER_OVERFLOW REG_BIT(16)
395#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
396
397#define DERRMR _MMIO(0x44050)
398/* Note that HBLANK events are reserved on bdw+ */
399#define DERRMR_PIPEA_SCANLINE (1 << 0)
400#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
401#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
402#define DERRMR_PIPEA_VBLANK (1 << 3)
403#define DERRMR_PIPEA_HBLANK (1 << 5)
404#define DERRMR_PIPEB_SCANLINE (1 << 8)
405#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
406#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
407#define DERRMR_PIPEB_VBLANK (1 << 11)
408#define DERRMR_PIPEB_HBLANK (1 << 13)
409/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
410#define DERRMR_PIPEC_SCANLINE (1 << 14)
411#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
412#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
413#define DERRMR_PIPEC_VBLANK (1 << 21)
414#define DERRMR_PIPEC_HBLANK (1 << 22)
415
416#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
417#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
418#define SCPD0 _MMIO(0x209c) /* 915+ only */
419#define SCPD_FBC_IGNORE_3D (1 << 6)
420#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
421#define GEN2_IER _MMIO(0x20a0)
422#define GEN2_IIR _MMIO(0x20a4)
423#define GEN2_IMR _MMIO(0x20a8)
424#define GEN2_ISR _MMIO(0x20ac)
425
426#define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
427 GEN2_IER, \
428 GEN2_IIR)
429
430#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
431#define GINT_DIS (1 << 22)
432#define GCFG_DIS (1 << 8)
433#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
434#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
435#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
436#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
437#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
438#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
439#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
440#define VLV_PCBR_ADDR_SHIFT 12
441
442#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
443 VLV_IER, \
444 VLV_IIR)
445
446#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
447#define EIR _MMIO(0x20b0)
448#define EMR _MMIO(0x20b4)
449#define ESR _MMIO(0x20b8)
450#define GM45_ERROR_PAGE_TABLE (1 << 5)
451#define GM45_ERROR_MEM_PRIV (1 << 4)
452#define I915_ERROR_PAGE_TABLE (1 << 4)
453#define GM45_ERROR_CP_PRIV (1 << 3)
454#define I915_ERROR_MEMORY_REFRESH (1 << 1)
455#define I915_ERROR_INSTRUCTION (1 << 0)
456#define INSTPM _MMIO(0x20c0)
457#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
458#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
459 will not assert AGPBUSY# and will only
460 be delivered when out of C3. */
461#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
462#define INSTPM_TLB_INVALIDATE (1 << 9)
463#define INSTPM_SYNC_FLUSH (1 << 5)
464#define MEM_MODE _MMIO(0x20cc)
465#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
466#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
467#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
468#define FW_BLC _MMIO(0x20d8)
469#define FW_BLC2 _MMIO(0x20dc)
470#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
471#define FW_BLC_SELF_EN_MASK (1 << 31)
472#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
473#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
474#define MM_BURST_LENGTH 0x00700000
475#define MM_FIFO_WATERMARK 0x0001F000
476#define LM_BURST_LENGTH 0x00000700
477#define LM_FIFO_WATERMARK 0x0000001F
478#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
479
480#define _MBUS_ABOX0_CTL 0x45038
481#define _MBUS_ABOX1_CTL 0x45048
482#define _MBUS_ABOX2_CTL 0x4504C
483#define MBUS_ABOX_CTL(x) \
484 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
485 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
486 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
487
488#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
489#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
490#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
491#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
492#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
493#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
494#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
495#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
496
497/* Make render/texture TLB fetches lower priorty than associated data
498 * fetches. This is not turned on by default
499 */
500#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
501
502/* Isoch request wait on GTT enable (Display A/B/C streams).
503 * Make isoch requests stall on the TLB update. May cause
504 * display underruns (test mode only)
505 */
506#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
507
508/* Block grant count for isoch requests when block count is
509 * set to a finite value.
510 */
511#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
512#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
513#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
514#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
515#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
516
517/* Enable render writes to complete in C2/C3/C4 power states.
518 * If this isn't enabled, render writes are prevented in low
519 * power states. That seems bad to me.
520 */
521#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
522
523/* This acknowledges an async flip immediately instead
524 * of waiting for 2TLB fetches.
525 */
526#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
527
528/* Enables non-sequential data reads through arbiter
529 */
530#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
531
532/* Disable FSB snooping of cacheable write cycles from binner/render
533 * command stream
534 */
535#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
536
537/* Arbiter time slice for non-isoch streams */
538#define MI_ARB_TIME_SLICE_MASK (7 << 5)
539#define MI_ARB_TIME_SLICE_1 (0 << 5)
540#define MI_ARB_TIME_SLICE_2 (1 << 5)
541#define MI_ARB_TIME_SLICE_4 (2 << 5)
542#define MI_ARB_TIME_SLICE_6 (3 << 5)
543#define MI_ARB_TIME_SLICE_8 (4 << 5)
544#define MI_ARB_TIME_SLICE_10 (5 << 5)
545#define MI_ARB_TIME_SLICE_14 (6 << 5)
546#define MI_ARB_TIME_SLICE_16 (7 << 5)
547
548/* Low priority grace period page size */
549#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
550#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
551
552/* Disable display A/B trickle feed */
553#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
554
555/* Set display plane priority */
556#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
557#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
558
559#define MI_STATE _MMIO(0x20e4) /* gen2 only */
560#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
561#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
562
563/* On modern GEN architectures interrupt control consists of two sets
564 * of registers. The first set pertains to the ring generating the
565 * interrupt. The second control is for the functional block generating the
566 * interrupt. These are PM, GT, DE, etc.
567 *
568 * Luckily *knocks on wood* all the ring interrupt bits match up with the
569 * GT interrupt bits, so we don't need to duplicate the defines.
570 *
571 * These defines should cover us well from SNB->HSW with minor exceptions
572 * it can also work on ILK.
573 */
574#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
575#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
576#define GT_BLT_USER_INTERRUPT (1 << 22)
577#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
578#define GT_BSD_USER_INTERRUPT (1 << 12)
579#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
580#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
581#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
582#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
583#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
584#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
585#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
586#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
587#define GT_RENDER_USER_INTERRUPT (1 << 0)
588
589#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
590#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
591
592#define GT_PARITY_ERROR(dev_priv) \
593 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
594 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
595
596/* These are all the "old" interrupts */
597#define ILK_BSD_USER_INTERRUPT (1 << 5)
598
599#define I915_PM_INTERRUPT (1 << 31)
600#define I915_ISP_INTERRUPT (1 << 22)
601#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
602#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
603#define I915_MIPIC_INTERRUPT (1 << 19)
604#define I915_MIPIA_INTERRUPT (1 << 18)
605#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
606#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
607#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
608#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
609#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
610#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
611#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
612#define I915_HWB_OOM_INTERRUPT (1 << 13)
613#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
614#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
615#define I915_MISC_INTERRUPT (1 << 11)
616#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
617#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
618#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
619#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
620#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
621#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
622#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
623#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
624#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
625#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
626#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
627#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
628#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
629#define I915_DEBUG_INTERRUPT (1 << 2)
630#define I915_WINVALID_INTERRUPT (1 << 1)
631#define I915_USER_INTERRUPT (1 << 1)
632#define I915_ASLE_INTERRUPT (1 << 0)
633#define I915_BSD_USER_INTERRUPT (1 << 25)
634
635#define GEN6_BSD_RNCID _MMIO(0x12198)
636
637#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
638#define GEN7_FF_SCHED_MASK 0x0077070
639#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
640#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
641#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
642#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
643#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
644#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
645#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
646#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
647#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
648#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
649#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
650#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
651#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
652#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
653#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
654
655#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
656#define ILK_FBCQ_DIS REG_BIT(22)
657#define ILK_PABSTRETCH_DIS REG_BIT(21)
658#define ILK_SABSTRETCH_DIS REG_BIT(20)
659#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
660#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
661#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
662#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
663#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
664#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
665#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
666#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
667#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
668#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
669
670#define IPS_CTL _MMIO(0x43408)
671#define IPS_ENABLE REG_BIT(31)
672#define IPS_FALSE_COLOR REG_BIT(4)
673
674/*
675 * Clock control & power management
676 */
677#define _DPLL_A 0x6014
678#define _DPLL_B 0x6018
679#define _CHV_DPLL_C 0x6030
680#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
681 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
682
683#define VGA0 _MMIO(0x6000)
684#define VGA1 _MMIO(0x6004)
685#define VGA_PD _MMIO(0x6010)
686#define VGA0_PD_P2_DIV_4 (1 << 7)
687#define VGA0_PD_P1_DIV_2 (1 << 5)
688#define VGA0_PD_P1_SHIFT 0
689#define VGA0_PD_P1_MASK (0x1f << 0)
690#define VGA1_PD_P2_DIV_4 (1 << 15)
691#define VGA1_PD_P1_DIV_2 (1 << 13)
692#define VGA1_PD_P1_SHIFT 8
693#define VGA1_PD_P1_MASK (0x1f << 8)
694#define DPLL_VCO_ENABLE (1 << 31)
695#define DPLL_SDVO_HIGH_SPEED (1 << 30)
696#define DPLL_DVO_2X_MODE (1 << 30)
697#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
698#define DPLL_SYNCLOCK_ENABLE (1 << 29)
699#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
700#define DPLL_VGA_MODE_DIS (1 << 28)
701#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
702#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
703#define DPLL_MODE_MASK (3 << 26)
704#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
705#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
706#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
707#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
708#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
709#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
710#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
711#define DPLL_LOCK_VLV (1 << 15)
712#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
713#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
714#define DPLL_SSC_REF_CLK_CHV (1 << 13)
715#define DPLL_PORTC_READY_MASK (0xf << 4)
716#define DPLL_PORTB_READY_MASK (0xf)
717
718#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
719
720/* Additional CHV pll/phy registers */
721#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
722#define DPLL_PORTD_READY_MASK (0xf)
723#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
724#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
725#define PHY_LDO_DELAY_0NS 0x0
726#define PHY_LDO_DELAY_200NS 0x1
727#define PHY_LDO_DELAY_600NS 0x2
728#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
729#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
730#define PHY_CH_SU_PSR 0x1
731#define PHY_CH_DEEP_PSR 0x7
732#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
733#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
734#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
735#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
736#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
737#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
738
739/*
740 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
741 * this field (only one bit may be set).
742 */
743#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
744#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
745#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
746/* i830, required in DVO non-gang */
747#define PLL_P2_DIVIDE_BY_4 (1 << 23)
748#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
749#define PLL_REF_INPUT_DREFCLK (0 << 13)
750#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
751#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
752#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
753#define PLL_REF_INPUT_MASK (3 << 13)
754#define PLL_LOAD_PULSE_PHASE_SHIFT 9
755/* Ironlake */
756# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
757# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
758# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
759# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
760# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
761
762/*
763 * Parallel to Serial Load Pulse phase selection.
764 * Selects the phase for the 10X DPLL clock for the PCIe
765 * digital display port. The range is 4 to 13; 10 or more
766 * is just a flip delay. The default is 6
767 */
768#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
769#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
770/*
771 * SDVO multiplier for 945G/GM. Not used on 965.
772 */
773#define SDVO_MULTIPLIER_MASK 0x000000ff
774#define SDVO_MULTIPLIER_SHIFT_HIRES 4
775#define SDVO_MULTIPLIER_SHIFT_VGA 0
776
777#define _DPLL_A_MD 0x601c
778#define _DPLL_B_MD 0x6020
779#define _CHV_DPLL_C_MD 0x603c
780#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
781 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
782
783/*
784 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
785 *
786 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
787 */
788#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
789#define DPLL_MD_UDI_DIVIDER_SHIFT 24
790/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
791#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
792#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
793/*
794 * SDVO/UDI pixel multiplier.
795 *
796 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
797 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
798 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
799 * dummy bytes in the datastream at an increased clock rate, with both sides of
800 * the link knowing how many bytes are fill.
801 *
802 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
803 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
804 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
805 * through an SDVO command.
806 *
807 * This register field has values of multiplication factor minus 1, with
808 * a maximum multiplier of 5 for SDVO.
809 */
810#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
811#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
812/*
813 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
814 * This best be set to the default value (3) or the CRT won't work. No,
815 * I don't entirely understand what this does...
816 */
817#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
818#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
819
820#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
821
822#define _FPA0 0x6040
823#define _FPA1 0x6044
824#define _FPB0 0x6048
825#define _FPB1 0x604c
826#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
827#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
828#define FP_N_DIV_MASK 0x003f0000
829#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
830#define FP_N_DIV_SHIFT 16
831#define FP_M1_DIV_MASK 0x00003f00
832#define FP_M1_DIV_SHIFT 8
833#define FP_M2_DIV_MASK 0x0000003f
834#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
835#define FP_M2_DIV_SHIFT 0
836#define DPLL_TEST _MMIO(0x606c)
837#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
838#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
839#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
840#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
841#define DPLLB_TEST_N_BYPASS (1 << 19)
842#define DPLLB_TEST_M_BYPASS (1 << 18)
843#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
844#define DPLLA_TEST_N_BYPASS (1 << 3)
845#define DPLLA_TEST_M_BYPASS (1 << 2)
846#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
847#define D_STATE _MMIO(0x6104)
848#define DSTATE_GFX_RESET_I830 (1 << 6)
849#define DSTATE_PLL_D3_OFF (1 << 3)
850#define DSTATE_GFX_CLOCK_GATING (1 << 1)
851#define DSTATE_DOT_CLOCK_GATING (1 << 0)
852#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
853# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
854# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
855# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
856# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
857# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
858# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
859# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
860# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
861# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
862# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
863# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
864# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
865# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
866# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
867# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
868# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
869# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
870# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
871# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
872# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
873# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
874# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
875# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
876# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
877# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
878# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
879# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
880# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
881# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
882/*
883 * This bit must be set on the 830 to prevent hangs when turning off the
884 * overlay scaler.
885 */
886# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
887# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
888# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
889# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
890# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
891
892#define RENCLK_GATE_D1 _MMIO(0x6204)
893# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
894# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
895# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
896# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
897# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
898# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
899# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
900# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
901# define MAG_CLOCK_GATE_DISABLE (1 << 5)
902/* This bit must be unset on 855,865 */
903# define MECI_CLOCK_GATE_DISABLE (1 << 4)
904# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
905# define MEC_CLOCK_GATE_DISABLE (1 << 2)
906# define MECO_CLOCK_GATE_DISABLE (1 << 1)
907/* This bit must be set on 855,865. */
908# define SV_CLOCK_GATE_DISABLE (1 << 0)
909# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
910# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
911# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
912# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
913# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
914# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
915# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
916# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
917# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
918# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
919# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
920# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
921# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
922# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
923# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
924# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
925# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
926
927# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
928/* This bit must always be set on 965G/965GM */
929# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
930# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
931# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
932# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
933# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
934# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
935/* This bit must always be set on 965G */
936# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
937# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
938# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
939# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
940# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
941# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
942# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
943# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
944# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
945# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
946# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
947# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
948# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
949# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
950# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
951# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
952# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
953# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
954# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
955
956#define RENCLK_GATE_D2 _MMIO(0x6208)
957#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
958#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
959#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
960
961#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
962#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
963
964#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
965#define DEUC _MMIO(0x6214) /* CRL only */
966
967#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
968#define FW_CSPWRDWNEN (1 << 15)
969
970#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
971
972#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
973#define CDCLK_FREQ_SHIFT 4
974#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
975#define CZCLK_FREQ_MASK 0xf
976
977#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
978#define PFI_CREDIT_63 (9 << 28) /* chv only */
979#define PFI_CREDIT_31 (8 << 28) /* chv only */
980#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
981#define PFI_CREDIT_RESEND (1 << 27)
982#define VGA_FAST_MODE_DISABLE (1 << 14)
983
984#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
985
986#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
987
988#define BXT_RP_STATE_CAP _MMIO(0x138170)
989#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
990
991#define MTL_RP_STATE_CAP _MMIO(0x138000)
992#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
993#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
994#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
995
996#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
997#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
998#define MTL_RPE_MASK REG_GENMASK(8, 0)
999
1000#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1001#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1002#define PROCHOT_MASK REG_BIT(0)
1003#define THERMAL_LIMIT_MASK REG_BIT(1)
1004#define RATL_MASK REG_BIT(5)
1005#define VR_THERMALERT_MASK REG_BIT(6)
1006#define VR_TDC_MASK REG_BIT(7)
1007#define POWER_LIMIT_4_MASK REG_BIT(8)
1008#define POWER_LIMIT_1_MASK REG_BIT(10)
1009#define POWER_LIMIT_2_MASK REG_BIT(11)
1010#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1011#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1012
1013#define CHV_CLK_CTL1 _MMIO(0x101100)
1014#define VLV_CLK_CTL2 _MMIO(0x101104)
1015#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1016
1017/*
1018 * Overlay regs
1019 */
1020
1021#define OVADD _MMIO(0x30000)
1022#define DOVSTA _MMIO(0x30008)
1023#define OC_BUF (0x3 << 20)
1024#define OGAMC5 _MMIO(0x30010)
1025#define OGAMC4 _MMIO(0x30014)
1026#define OGAMC3 _MMIO(0x30018)
1027#define OGAMC2 _MMIO(0x3001c)
1028#define OGAMC1 _MMIO(0x30020)
1029#define OGAMC0 _MMIO(0x30024)
1030
1031/*
1032 * GEN9 clock gating regs
1033 */
1034#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1035#define DARBF_GATING_DIS REG_BIT(27)
1036#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
1037#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
1038#define PWM2_GATING_DIS REG_BIT(14)
1039#define PWM1_GATING_DIS REG_BIT(13)
1040
1041#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1042#define TGL_VRH_GATING_DIS REG_BIT(31)
1043#define DPT_GATING_DIS REG_BIT(22)
1044
1045#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1046#define BXT_GMBUS_GATING_DIS (1 << 14)
1047
1048#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1049#define DPCE_GATING_DIS REG_BIT(17)
1050
1051#define _CLKGATE_DIS_PSL_A 0x46520
1052#define _CLKGATE_DIS_PSL_B 0x46524
1053#define _CLKGATE_DIS_PSL_C 0x46528
1054#define DUPS1_GATING_DIS (1 << 15)
1055#define DUPS2_GATING_DIS (1 << 19)
1056#define DUPS3_GATING_DIS (1 << 23)
1057#define CURSOR_GATING_DIS REG_BIT(28)
1058#define DPF_GATING_DIS (1 << 10)
1059#define DPF_RAM_GATING_DIS (1 << 9)
1060#define DPFR_GATING_DIS (1 << 8)
1061
1062#define CLKGATE_DIS_PSL(pipe) \
1063 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1064
1065#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1066#define _CLKGATE_DIS_PSL_EXT_B 0x46550
1067#define PIPEDMC_GATING_DIS REG_BIT(12)
1068
1069#define CLKGATE_DIS_PSL_EXT(pipe) \
1070 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1071
1072/* DDI Buffer Control */
1073#define _DDI_CLK_VALFREQ_A 0x64030
1074#define _DDI_CLK_VALFREQ_B 0x64130
1075#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
1076
1077/*
1078 * Display engine regs
1079 */
1080
1081/* Pipe/transcoder A timing regs */
1082#define _TRANS_HTOTAL_A 0x60000
1083#define _TRANS_HTOTAL_B 0x61000
1084#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
1085#define HTOTAL_MASK REG_GENMASK(31, 16)
1086#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
1087#define HACTIVE_MASK REG_GENMASK(15, 0)
1088#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
1089
1090#define _TRANS_HBLANK_A 0x60004
1091#define _TRANS_HBLANK_B 0x61004
1092#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
1093#define HBLANK_END_MASK REG_GENMASK(31, 16)
1094#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
1095#define HBLANK_START_MASK REG_GENMASK(15, 0)
1096#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
1097
1098#define _TRANS_HSYNC_A 0x60008
1099#define _TRANS_HSYNC_B 0x61008
1100#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
1101#define HSYNC_END_MASK REG_GENMASK(31, 16)
1102#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
1103#define HSYNC_START_MASK REG_GENMASK(15, 0)
1104#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
1105
1106#define _TRANS_VTOTAL_A 0x6000c
1107#define _TRANS_VTOTAL_B 0x6100c
1108#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
1109#define VTOTAL_MASK REG_GENMASK(31, 16)
1110#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
1111#define VACTIVE_MASK REG_GENMASK(15, 0)
1112#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
1113
1114#define _TRANS_VBLANK_A 0x60010
1115#define _TRANS_VBLANK_B 0x61010
1116#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
1117#define VBLANK_END_MASK REG_GENMASK(31, 16)
1118#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
1119#define VBLANK_START_MASK REG_GENMASK(15, 0)
1120#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
1121
1122#define _TRANS_VSYNC_A 0x60014
1123#define _TRANS_VSYNC_B 0x61014
1124#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
1125#define VSYNC_END_MASK REG_GENMASK(31, 16)
1126#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
1127#define VSYNC_START_MASK REG_GENMASK(15, 0)
1128#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
1129
1130#define _PIPEASRC 0x6001c
1131#define _PIPEBSRC 0x6101c
1132#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
1133#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1134#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1135#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1136#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1137
1138#define _BCLRPAT_A 0x60020
1139#define _BCLRPAT_B 0x61020
1140#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
1141
1142#define _TRANS_VSYNCSHIFT_A 0x60028
1143#define _TRANS_VSYNCSHIFT_B 0x61028
1144#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
1145
1146#define _TRANS_MULT_A 0x6002c
1147#define _TRANS_MULT_B 0x6102c
1148#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
1149
1150/* VGA port control */
1151#define ADPA _MMIO(0x61100)
1152#define PCH_ADPA _MMIO(0xe1100)
1153#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
1154#define ADPA_DAC_ENABLE (1 << 31)
1155#define ADPA_DAC_DISABLE 0
1156#define ADPA_PIPE_SEL_SHIFT 30
1157#define ADPA_PIPE_SEL_MASK (1 << 30)
1158#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
1159#define ADPA_PIPE_SEL_SHIFT_CPT 29
1160#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
1161#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
1162#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1163#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
1164#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
1165#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
1166#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
1167#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
1168#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
1169#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
1170#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
1171#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
1172#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
1173#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
1174#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
1175#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
1176#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
1177#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
1178#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
1179#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
1180#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
1181#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
1182#define ADPA_SETS_HVPOLARITY 0
1183#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
1184#define ADPA_VSYNC_CNTL_ENABLE 0
1185#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
1186#define ADPA_HSYNC_CNTL_ENABLE 0
1187#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
1188#define ADPA_VSYNC_ACTIVE_LOW 0
1189#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
1190#define ADPA_HSYNC_ACTIVE_LOW 0
1191#define ADPA_DPMS_MASK (~(3 << 10))
1192#define ADPA_DPMS_ON (0 << 10)
1193#define ADPA_DPMS_SUSPEND (1 << 10)
1194#define ADPA_DPMS_STANDBY (2 << 10)
1195#define ADPA_DPMS_OFF (3 << 10)
1196
1197/* Hotplug control (945+ only) */
1198#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
1199#define PORTB_HOTPLUG_INT_EN (1 << 29)
1200#define PORTC_HOTPLUG_INT_EN (1 << 28)
1201#define PORTD_HOTPLUG_INT_EN (1 << 27)
1202#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1203#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1204#define TV_HOTPLUG_INT_EN (1 << 18)
1205#define CRT_HOTPLUG_INT_EN (1 << 9)
1206#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
1207 PORTC_HOTPLUG_INT_EN | \
1208 PORTD_HOTPLUG_INT_EN | \
1209 SDVOC_HOTPLUG_INT_EN | \
1210 SDVOB_HOTPLUG_INT_EN | \
1211 CRT_HOTPLUG_INT_EN)
1212#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1213#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1214/* must use period 64 on GM45 according to docs */
1215#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1216#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1217#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1218#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1219#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1220#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1221#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1222#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1223#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1224#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1225#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1226#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1227
1228#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
1229/* HDMI/DP bits are g4x+ */
1230#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
1231#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
1232#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
1233#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
1234#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
1235#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
1236#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
1237#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
1238#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
1239#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
1240#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
1241#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
1242/* CRT/TV common between gen3+ */
1243#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1244#define TV_HOTPLUG_INT_STATUS (1 << 10)
1245#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1246#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1247#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1248#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1249#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
1250#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
1251#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
1252#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
1253
1254/* SDVO is different across gen3/4 */
1255#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1256#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1257/*
1258 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
1259 * since reality corrobates that they're the same as on gen3. But keep these
1260 * bits here (and the comment!) to help any other lost wanderers back onto the
1261 * right tracks.
1262 */
1263#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1264#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1265#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1266#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1267#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
1268 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1269 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1270 PORTB_HOTPLUG_INT_STATUS | \
1271 PORTC_HOTPLUG_INT_STATUS | \
1272 PORTD_HOTPLUG_INT_STATUS)
1273
1274#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
1275 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1276 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1277 PORTB_HOTPLUG_INT_STATUS | \
1278 PORTC_HOTPLUG_INT_STATUS | \
1279 PORTD_HOTPLUG_INT_STATUS)
1280
1281/* SDVO and HDMI port control.
1282 * The same register may be used for SDVO or HDMI */
1283#define _GEN3_SDVOB 0x61140
1284#define _GEN3_SDVOC 0x61160
1285#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
1286#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
1287#define GEN4_HDMIB GEN3_SDVOB
1288#define GEN4_HDMIC GEN3_SDVOC
1289#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
1290#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
1291#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
1292#define PCH_SDVOB _MMIO(0xe1140)
1293#define PCH_HDMIB PCH_SDVOB
1294#define PCH_HDMIC _MMIO(0xe1150)
1295#define PCH_HDMID _MMIO(0xe1160)
1296
1297#define PORT_DFT_I9XX _MMIO(0x61150)
1298#define DC_BALANCE_RESET (1 << 25)
1299#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
1300#define DC_BALANCE_RESET_VLV (1 << 31)
1301#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
1302#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
1303#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
1304#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
1305
1306/* Gen 3 SDVO bits: */
1307#define SDVO_ENABLE (1 << 31)
1308#define SDVO_PIPE_SEL_SHIFT 30
1309#define SDVO_PIPE_SEL_MASK (1 << 30)
1310#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
1311#define SDVO_STALL_SELECT (1 << 29)
1312#define SDVO_INTERRUPT_ENABLE (1 << 26)
1313/*
1314 * 915G/GM SDVO pixel multiplier.
1315 * Programmed value is multiplier - 1, up to 5x.
1316 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1317 */
1318#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1319#define SDVO_PORT_MULTIPLY_SHIFT 23
1320#define SDVO_PHASE_SELECT_MASK (15 << 19)
1321#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1322#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1323#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
1324#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
1325#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
1326#define SDVO_DETECTED (1 << 2)
1327/* Bits to be preserved when writing */
1328#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
1329 SDVO_INTERRUPT_ENABLE)
1330#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
1331
1332/* Gen 4 SDVO/HDMI bits: */
1333#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
1334#define SDVO_COLOR_FORMAT_MASK (7 << 26)
1335#define SDVO_ENCODING_SDVO (0 << 10)
1336#define SDVO_ENCODING_HDMI (2 << 10)
1337#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
1338#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1339#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
1340#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
1341/* VSYNC/HSYNC bits new with 965, default is to be set */
1342#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1343#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1344
1345/* Gen 5 (IBX) SDVO/HDMI bits: */
1346#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
1347#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
1348
1349/* Gen 6 (CPT) SDVO/HDMI bits: */
1350#define SDVO_PIPE_SEL_SHIFT_CPT 29
1351#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
1352#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
1353
1354/* CHV SDVO/HDMI bits: */
1355#define SDVO_PIPE_SEL_SHIFT_CHV 24
1356#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
1357#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
1358
1359/* Video Data Island Packet control */
1360#define VIDEO_DIP_DATA _MMIO(0x61178)
1361/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
1362 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1363 * of the infoframe structure specified by CEA-861. */
1364#define VIDEO_DIP_DATA_SIZE 32
1365#define VIDEO_DIP_ASYNC_DATA_SIZE 36
1366#define VIDEO_DIP_GMP_DATA_SIZE 36
1367#define VIDEO_DIP_VSC_DATA_SIZE 36
1368#define VIDEO_DIP_PPS_DATA_SIZE 132
1369#define VIDEO_DIP_CTL _MMIO(0x61170)
1370/* Pre HSW: */
1371#define VIDEO_DIP_ENABLE (1 << 31)
1372#define VIDEO_DIP_PORT(port) ((port) << 29)
1373#define VIDEO_DIP_PORT_MASK (3 << 29)
1374#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
1375#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1376#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1377#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
1378#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1379#define VIDEO_DIP_SELECT_AVI (0 << 19)
1380#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1381#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
1382#define VIDEO_DIP_SELECT_SPD (3 << 19)
1383#define VIDEO_DIP_SELECT_MASK (3 << 19)
1384#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1385#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1386#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1387#define VIDEO_DIP_FREQ_MASK (3 << 16)
1388/* HSW and later: */
1389#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
1390#define PSR_VSC_BIT_7_SET (1 << 27)
1391#define VSC_SELECT_MASK (0x3 << 25)
1392#define VSC_SELECT_SHIFT 25
1393#define VSC_DIP_HW_HEA_DATA (0 << 25)
1394#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
1395#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
1396#define VSC_DIP_SW_HEA_DATA (3 << 25)
1397#define VDIP_ENABLE_PPS (1 << 24)
1398#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
1399#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
1400#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
1401#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
1402#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
1403#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1404/* ADL and later: */
1405#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
1406
1407/* Panel fitting */
1408#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
1409#define PFIT_ENABLE REG_BIT(31)
1410#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
1411#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
1412#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
1413#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
1414#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
1415#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
1416#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
1417#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
1418#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
1419#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
1420#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
1421#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
1422#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
1423#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
1424#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
1425#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
1426#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
1427#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
1428
1429#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
1430#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
1431#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
1432#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
1433#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
1434#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
1435#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
1436
1437#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
1438
1439#define PCH_GTC_CTL _MMIO(0xe7000)
1440#define PCH_GTC_ENABLE (1 << 31)
1441
1442/* Display Port */
1443#define DP_A _MMIO(0x64000) /* eDP */
1444#define DP_B _MMIO(0x64100)
1445#define DP_C _MMIO(0x64200)
1446#define DP_D _MMIO(0x64300)
1447#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
1448#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
1449#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
1450#define DP_PORT_EN (1 << 31)
1451#define DP_PIPE_SEL_SHIFT 30
1452#define DP_PIPE_SEL_MASK (1 << 30)
1453#define DP_PIPE_SEL(pipe) ((pipe) << 30)
1454#define DP_PIPE_SEL_SHIFT_IVB 29
1455#define DP_PIPE_SEL_MASK_IVB (3 << 29)
1456#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
1457#define DP_PIPE_SEL_SHIFT_CHV 16
1458#define DP_PIPE_SEL_MASK_CHV (3 << 16)
1459#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
1460
1461/* Link training mode - select a suitable mode for each stage */
1462#define DP_LINK_TRAIN_PAT_1 (0 << 28)
1463#define DP_LINK_TRAIN_PAT_2 (1 << 28)
1464#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1465#define DP_LINK_TRAIN_OFF (3 << 28)
1466#define DP_LINK_TRAIN_MASK (3 << 28)
1467#define DP_LINK_TRAIN_SHIFT 28
1468
1469/* CPT Link training mode */
1470#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1471#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
1472#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
1473#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
1474#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
1475#define DP_LINK_TRAIN_SHIFT_CPT 8
1476
1477/* Signal voltages. These are mostly controlled by the other end */
1478#define DP_VOLTAGE_0_4 (0 << 25)
1479#define DP_VOLTAGE_0_6 (1 << 25)
1480#define DP_VOLTAGE_0_8 (2 << 25)
1481#define DP_VOLTAGE_1_2 (3 << 25)
1482#define DP_VOLTAGE_MASK (7 << 25)
1483#define DP_VOLTAGE_SHIFT 25
1484
1485/* Signal pre-emphasis levels, like voltages, the other end tells us what
1486 * they want
1487 */
1488#define DP_PRE_EMPHASIS_0 (0 << 22)
1489#define DP_PRE_EMPHASIS_3_5 (1 << 22)
1490#define DP_PRE_EMPHASIS_6 (2 << 22)
1491#define DP_PRE_EMPHASIS_9_5 (3 << 22)
1492#define DP_PRE_EMPHASIS_MASK (7 << 22)
1493#define DP_PRE_EMPHASIS_SHIFT 22
1494
1495/* How many wires to use. I guess 3 was too hard */
1496#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
1497#define DP_PORT_WIDTH_MASK (7 << 19)
1498#define DP_PORT_WIDTH_SHIFT 19
1499
1500/* Mystic DPCD version 1.1 special mode */
1501#define DP_ENHANCED_FRAMING (1 << 18)
1502
1503/* eDP */
1504#define DP_PLL_FREQ_270MHZ (0 << 16)
1505#define DP_PLL_FREQ_162MHZ (1 << 16)
1506#define DP_PLL_FREQ_MASK (3 << 16)
1507
1508/* locked once port is enabled */
1509#define DP_PORT_REVERSAL (1 << 15)
1510
1511/* eDP */
1512#define DP_PLL_ENABLE (1 << 14)
1513
1514/* sends the clock on lane 15 of the PEG for debug */
1515#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1516
1517#define DP_SCRAMBLING_DISABLE (1 << 12)
1518#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1519
1520/* limit RGB values to avoid confusing TVs */
1521#define DP_COLOR_RANGE_16_235 (1 << 8)
1522
1523/* Turn on the audio link */
1524#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1525
1526/* vs and hs sync polarity */
1527#define DP_SYNC_VS_HIGH (1 << 4)
1528#define DP_SYNC_HS_HIGH (1 << 3)
1529
1530/* A fantasy */
1531#define DP_DETECTED (1 << 2)
1532
1533/*
1534 * Computing GMCH M and N values for the Display Port link
1535 *
1536 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1537 *
1538 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1539 *
1540 * The GMCH value is used internally
1541 *
1542 * bytes_per_pixel is the number of bytes coming out of the plane,
1543 * which is after the LUTs, so we want the bytes for our color format.
1544 * For our current usage, this is always 3, one byte for R, G and B.
1545 */
1546#define _PIPEA_DATA_M_G4X 0x70050
1547#define _PIPEB_DATA_M_G4X 0x71050
1548#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
1549/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1550#define TU_SIZE_MASK REG_GENMASK(30, 25)
1551#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
1552#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
1553#define DATA_LINK_N_MAX (0x800000)
1554
1555#define _PIPEA_DATA_N_G4X 0x70054
1556#define _PIPEB_DATA_N_G4X 0x71054
1557#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
1558
1559/*
1560 * Computing Link M and N values for the Display Port link
1561 *
1562 * Link M / N = pixel_clock / ls_clk
1563 *
1564 * (the DP spec calls pixel_clock the 'strm_clk')
1565 *
1566 * The Link value is transmitted in the Main Stream
1567 * Attributes and VB-ID.
1568 */
1569#define _PIPEA_LINK_M_G4X 0x70060
1570#define _PIPEB_LINK_M_G4X 0x71060
1571#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
1572
1573#define _PIPEA_LINK_N_G4X 0x70064
1574#define _PIPEB_LINK_N_G4X 0x71064
1575#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
1576
1577/* Pipe A */
1578#define _PIPEADSL 0x70000
1579#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
1580#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
1581#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
1582
1583#define _TRANSACONF 0x70008
1584#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
1585#define TRANSCONF_ENABLE REG_BIT(31)
1586#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
1587#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
1588#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
1589#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
1590#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1591#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
1592#define TRANSCONF_FORCE_BORDER REG_BIT(25)
1593#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
1594#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
1595#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
1596#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
1597#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
1598#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
1599#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
1600#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
1601#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
1602#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
1603#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
1604#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
1605#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
1606/*
1607 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
1608 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
1609 */
1610#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
1611#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
1612#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
1613#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
1614#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
1615#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
1616#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
1617#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
1618#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
1619#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
1620#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
1621#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
1622#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
1623#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
1624#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
1625#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
1626#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
1627#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
1628#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
1629#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
1630#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
1631#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
1632#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
1633#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
1634#define TRANSCONF_DITHER_EN REG_BIT(4)
1635#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1636#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
1637#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
1638#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
1639#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
1640#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
1641#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
1642
1643#define _PIPEASTAT 0x70024
1644#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
1645#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
1646#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
1647#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
1648#define PIPE_CRC_DONE_ENABLE (1UL << 28)
1649#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
1650#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
1651#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
1652#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
1653#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
1654#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
1655#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
1656#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
1657#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
1658#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
1659#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
1660#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
1661#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
1662#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
1663#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
1664#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
1665#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
1666#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
1667#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
1668#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
1669#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
1670#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
1671#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
1672#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
1673#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
1674#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
1675#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
1676#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
1677#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
1678#define PIPE_DPST_EVENT_STATUS (1UL << 7)
1679#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
1680#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
1681#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
1682#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
1683#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
1684#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
1685#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
1686#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
1687#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
1688#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
1689#define PIPE_HBLANK_INT_STATUS (1UL << 0)
1690#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
1691#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
1692#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
1693
1694#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
1695#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
1696#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
1697
1698#define _PIPE_MISC_A 0x70030
1699#define _PIPE_MISC_B 0x71030
1700#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
1701#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
1702#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
1703#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
1704#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
1705#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
1706#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
1707#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
1708#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
1709#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
1710#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
1711/*
1712 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
1713 * valid values of: 6, 8, 10 BPC.
1714 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
1715 * 6, 8, 10, 12 BPC.
1716 */
1717#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
1718#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
1719#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
1720#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
1721#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
1722#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
1723#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1724#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
1725#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
1726#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
1727#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
1728
1729#define _PIPE_MISC2_A 0x7002C
1730#define _PIPE_MISC2_B 0x7102C
1731#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
1732#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
1733#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
1734#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
1735#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1736#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
1737
1738#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1739#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
1740#define PIPEB_HLINE_INT_EN REG_BIT(28)
1741#define PIPEB_VBLANK_INT_EN REG_BIT(27)
1742#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
1743#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
1744#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
1745#define PIPE_PSR_INT_EN REG_BIT(22)
1746#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
1747#define PIPEA_HLINE_INT_EN REG_BIT(20)
1748#define PIPEA_VBLANK_INT_EN REG_BIT(19)
1749#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
1750#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
1751#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
1752#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
1753#define PIPEC_HLINE_INT_EN REG_BIT(12)
1754#define PIPEC_VBLANK_INT_EN REG_BIT(11)
1755#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
1756#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
1757#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
1758
1759#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
1760#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
1761#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
1762#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
1763#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
1764#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
1765#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
1766#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
1767#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
1768#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
1769#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
1770#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
1771#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
1772#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
1773#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
1774#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
1775#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
1776#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
1777#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
1778#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
1779#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
1780#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
1781#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
1782#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
1783#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
1784#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
1785#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
1786#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
1787#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
1788
1789#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
1790#define DSPARB_CSTART_MASK (0x7f << 7)
1791#define DSPARB_CSTART_SHIFT 7
1792#define DSPARB_BSTART_MASK (0x7f)
1793#define DSPARB_BSTART_SHIFT 0
1794#define DSPARB_BEND_SHIFT 9 /* on 855 */
1795#define DSPARB_AEND_SHIFT 0
1796#define DSPARB_SPRITEA_SHIFT_VLV 0
1797#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
1798#define DSPARB_SPRITEB_SHIFT_VLV 8
1799#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
1800#define DSPARB_SPRITEC_SHIFT_VLV 16
1801#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
1802#define DSPARB_SPRITED_SHIFT_VLV 24
1803#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
1804#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
1805#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
1806#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
1807#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
1808#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
1809#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
1810#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
1811#define DSPARB_SPRITED_HI_SHIFT_VLV 12
1812#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
1813#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
1814#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
1815#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
1816#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
1817#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
1818#define DSPARB_SPRITEE_SHIFT_VLV 0
1819#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
1820#define DSPARB_SPRITEF_SHIFT_VLV 8
1821#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
1822
1823/* pnv/gen4/g4x/vlv/chv */
1824#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
1825#define DSPFW_SR_SHIFT 23
1826#define DSPFW_SR_MASK (0x1ff << 23)
1827#define DSPFW_CURSORB_SHIFT 16
1828#define DSPFW_CURSORB_MASK (0x3f << 16)
1829#define DSPFW_PLANEB_SHIFT 8
1830#define DSPFW_PLANEB_MASK (0x7f << 8)
1831#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
1832#define DSPFW_PLANEA_SHIFT 0
1833#define DSPFW_PLANEA_MASK (0x7f << 0)
1834#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
1835#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
1836#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
1837#define DSPFW_FBC_SR_SHIFT 28
1838#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
1839#define DSPFW_FBC_HPLL_SR_SHIFT 24
1840#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
1841#define DSPFW_SPRITEB_SHIFT (16)
1842#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
1843#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
1844#define DSPFW_CURSORA_SHIFT 8
1845#define DSPFW_CURSORA_MASK (0x3f << 8)
1846#define DSPFW_PLANEC_OLD_SHIFT 0
1847#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
1848#define DSPFW_SPRITEA_SHIFT 0
1849#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
1850#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
1851#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
1852#define DSPFW_HPLL_SR_EN (1 << 31)
1853#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
1854#define DSPFW_CURSOR_SR_SHIFT 24
1855#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
1856#define DSPFW_HPLL_CURSOR_SHIFT 16
1857#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
1858#define DSPFW_HPLL_SR_SHIFT 0
1859#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
1860
1861/* vlv/chv */
1862#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
1863#define DSPFW_SPRITEB_WM1_SHIFT 16
1864#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
1865#define DSPFW_CURSORA_WM1_SHIFT 8
1866#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
1867#define DSPFW_SPRITEA_WM1_SHIFT 0
1868#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
1869#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
1870#define DSPFW_PLANEB_WM1_SHIFT 24
1871#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
1872#define DSPFW_PLANEA_WM1_SHIFT 16
1873#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
1874#define DSPFW_CURSORB_WM1_SHIFT 8
1875#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
1876#define DSPFW_CURSOR_SR_WM1_SHIFT 0
1877#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
1878#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
1879#define DSPFW_SR_WM1_SHIFT 0
1880#define DSPFW_SR_WM1_MASK (0x1ff << 0)
1881#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
1882#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
1883#define DSPFW_SPRITED_WM1_SHIFT 24
1884#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
1885#define DSPFW_SPRITED_SHIFT 16
1886#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
1887#define DSPFW_SPRITEC_WM1_SHIFT 8
1888#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
1889#define DSPFW_SPRITEC_SHIFT 0
1890#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
1891#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
1892#define DSPFW_SPRITEF_WM1_SHIFT 24
1893#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
1894#define DSPFW_SPRITEF_SHIFT 16
1895#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
1896#define DSPFW_SPRITEE_WM1_SHIFT 8
1897#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
1898#define DSPFW_SPRITEE_SHIFT 0
1899#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
1900#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
1901#define DSPFW_PLANEC_WM1_SHIFT 24
1902#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
1903#define DSPFW_PLANEC_SHIFT 16
1904#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
1905#define DSPFW_CURSORC_WM1_SHIFT 8
1906#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
1907#define DSPFW_CURSORC_SHIFT 0
1908#define DSPFW_CURSORC_MASK (0x3f << 0)
1909
1910/* vlv/chv high order bits */
1911#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
1912#define DSPFW_SR_HI_SHIFT 24
1913#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1914#define DSPFW_SPRITEF_HI_SHIFT 23
1915#define DSPFW_SPRITEF_HI_MASK (1 << 23)
1916#define DSPFW_SPRITEE_HI_SHIFT 22
1917#define DSPFW_SPRITEE_HI_MASK (1 << 22)
1918#define DSPFW_PLANEC_HI_SHIFT 21
1919#define DSPFW_PLANEC_HI_MASK (1 << 21)
1920#define DSPFW_SPRITED_HI_SHIFT 20
1921#define DSPFW_SPRITED_HI_MASK (1 << 20)
1922#define DSPFW_SPRITEC_HI_SHIFT 16
1923#define DSPFW_SPRITEC_HI_MASK (1 << 16)
1924#define DSPFW_PLANEB_HI_SHIFT 12
1925#define DSPFW_PLANEB_HI_MASK (1 << 12)
1926#define DSPFW_SPRITEB_HI_SHIFT 8
1927#define DSPFW_SPRITEB_HI_MASK (1 << 8)
1928#define DSPFW_SPRITEA_HI_SHIFT 4
1929#define DSPFW_SPRITEA_HI_MASK (1 << 4)
1930#define DSPFW_PLANEA_HI_SHIFT 0
1931#define DSPFW_PLANEA_HI_MASK (1 << 0)
1932#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
1933#define DSPFW_SR_WM1_HI_SHIFT 24
1934#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1935#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
1936#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
1937#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
1938#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
1939#define DSPFW_PLANEC_WM1_HI_SHIFT 21
1940#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
1941#define DSPFW_SPRITED_WM1_HI_SHIFT 20
1942#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
1943#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
1944#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
1945#define DSPFW_PLANEB_WM1_HI_SHIFT 12
1946#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
1947#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
1948#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
1949#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
1950#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
1951#define DSPFW_PLANEA_WM1_HI_SHIFT 0
1952#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
1953
1954/* drain latency register values*/
1955#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1956#define DDL_CURSOR_SHIFT 24
1957#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
1958#define DDL_PLANE_SHIFT 0
1959#define DDL_PRECISION_HIGH (1 << 7)
1960#define DDL_PRECISION_LOW (0 << 7)
1961#define DRAIN_LATENCY_MASK 0x7f
1962
1963#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1964#define CBR_PND_DEADLINE_DISABLE (1 << 31)
1965#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
1966
1967#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
1968#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
1969
1970/* FIFO watermark sizes etc */
1971#define G4X_FIFO_LINE_SIZE 64
1972#define I915_FIFO_LINE_SIZE 64
1973#define I830_FIFO_LINE_SIZE 32
1974
1975#define VALLEYVIEW_FIFO_SIZE 255
1976#define G4X_FIFO_SIZE 127
1977#define I965_FIFO_SIZE 512
1978#define I945_FIFO_SIZE 127
1979#define I915_FIFO_SIZE 95
1980#define I855GM_FIFO_SIZE 127 /* In cachelines */
1981#define I830_FIFO_SIZE 95
1982
1983#define VALLEYVIEW_MAX_WM 0xff
1984#define G4X_MAX_WM 0x3f
1985#define I915_MAX_WM 0x3f
1986
1987#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
1988#define PINEVIEW_FIFO_LINE_SIZE 64
1989#define PINEVIEW_MAX_WM 0x1ff
1990#define PINEVIEW_DFT_WM 0x3f
1991#define PINEVIEW_DFT_HPLLOFF_WM 0
1992#define PINEVIEW_GUARD_WM 10
1993#define PINEVIEW_CURSOR_FIFO 64
1994#define PINEVIEW_CURSOR_MAX_WM 0x3f
1995#define PINEVIEW_CURSOR_DFT_WM 0
1996#define PINEVIEW_CURSOR_GUARD_WM 5
1997
1998#define VALLEYVIEW_CURSOR_MAX_WM 64
1999#define I965_CURSOR_FIFO 64
2000#define I965_CURSOR_MAX_WM 32
2001#define I965_CURSOR_DFT_WM 8
2002
2003/* define the Watermark register on Ironlake */
2004#define _WM0_PIPEA_ILK 0x45100
2005#define _WM0_PIPEB_ILK 0x45104
2006#define _WM0_PIPEC_IVB 0x45200
2007#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
2008 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
2009#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
2010#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
2011#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2012#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
2013#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
2014#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
2015#define WM1_LP_ILK _MMIO(0x45108)
2016#define WM2_LP_ILK _MMIO(0x4510c)
2017#define WM3_LP_ILK _MMIO(0x45110)
2018#define WM_LP_ENABLE REG_BIT(31)
2019#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
2020#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
2021#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
2022#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
2023#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2024#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
2025#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
2026#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
2027#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
2028#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
2029#define WM1S_LP_ILK _MMIO(0x45120)
2030#define WM2S_LP_IVB _MMIO(0x45124)
2031#define WM3S_LP_IVB _MMIO(0x45128)
2032#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
2033#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
2034#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
2035
2036/*
2037 * The two pipe frame counter registers are not synchronized, so
2038 * reading a stable value is somewhat tricky. The following code
2039 * should work:
2040 *
2041 * do {
2042 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2043 * PIPE_FRAME_HIGH_SHIFT;
2044 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2045 * PIPE_FRAME_LOW_SHIFT);
2046 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2047 * PIPE_FRAME_HIGH_SHIFT);
2048 * } while (high1 != high2);
2049 * frame = (high1 << 8) | low1;
2050 */
2051#define _PIPEAFRAMEHIGH 0x70040
2052#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
2053#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2054#define PIPE_FRAME_HIGH_SHIFT 0
2055
2056#define _PIPEAFRAMEPIXEL 0x70044
2057#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
2058#define PIPE_FRAME_LOW_MASK 0xff000000
2059#define PIPE_FRAME_LOW_SHIFT 24
2060#define PIPE_PIXEL_MASK 0x00ffffff
2061#define PIPE_PIXEL_SHIFT 0
2062
2063/* GM45+ just has to be different */
2064#define _PIPEA_FRMCOUNT_G4X 0x70040
2065#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
2066
2067#define _PIPEA_FLIPCOUNT_G4X 0x70044
2068#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
2069
2070/* CHV pipe B blender */
2071#define _CHV_BLEND_A 0x60a00
2072#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
2073#define CHV_BLEND_MASK REG_GENMASK(31, 30)
2074#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
2075#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
2076#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
2077
2078#define _CHV_CANVAS_A 0x60a04
2079#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
2080#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
2081#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
2082#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
2083
2084/* Display/Sprite base address macros */
2085#define DISP_BASEADDR_MASK (0xfffff000)
2086#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
2087#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
2088
2089/*
2090 * VBIOS flags
2091 * gen2:
2092 * [00:06] alm,mgm
2093 * [10:16] all
2094 * [30:32] alm,mgm
2095 * gen3+:
2096 * [00:0f] all
2097 * [10:1f] all
2098 * [30:32] all
2099 */
2100#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
2101#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
2102#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
2103#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
2104
2105/* VBIOS regs */
2106#define VGACNTRL _MMIO(0x71400)
2107# define VGA_DISP_DISABLE (1 << 31)
2108# define VGA_2X_MODE (1 << 30)
2109# define VGA_PIPE_B_SELECT (1 << 29)
2110
2111#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
2112
2113/* Ironlake */
2114
2115#define CPU_VGACNTRL _MMIO(0x41000)
2116
2117#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
2118#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2119#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
2120#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
2121#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
2122#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
2123#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
2124#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
2125#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
2126#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
2127#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
2128
2129/* refresh rate hardware control */
2130#define RR_HW_CTL _MMIO(0x45300)
2131#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2132#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2133
2134#define PCH_3DCGDIS0 _MMIO(0x46020)
2135# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2136# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2137
2138#define PCH_3DCGDIS1 _MMIO(0x46024)
2139# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2140
2141#define _PIPEA_DATA_M1 0x60030
2142#define _PIPEB_DATA_M1 0x61030
2143#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
2144
2145#define _PIPEA_DATA_N1 0x60034
2146#define _PIPEB_DATA_N1 0x61034
2147#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
2148
2149#define _PIPEA_DATA_M2 0x60038
2150#define _PIPEB_DATA_M2 0x61038
2151#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
2152
2153#define _PIPEA_DATA_N2 0x6003c
2154#define _PIPEB_DATA_N2 0x6103c
2155#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
2156
2157#define _PIPEA_LINK_M1 0x60040
2158#define _PIPEB_LINK_M1 0x61040
2159#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
2160
2161#define _PIPEA_LINK_N1 0x60044
2162#define _PIPEB_LINK_N1 0x61044
2163#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
2164
2165#define _PIPEA_LINK_M2 0x60048
2166#define _PIPEB_LINK_M2 0x61048
2167#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
2168
2169#define _PIPEA_LINK_N2 0x6004c
2170#define _PIPEB_LINK_N2 0x6104c
2171#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
2172
2173/* CPU panel fitter */
2174/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2175#define _PFA_CTL_1 0x68080
2176#define _PFB_CTL_1 0x68880
2177#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2178#define PF_ENABLE REG_BIT(31)
2179#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
2180#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
2181#define PF_FILTER_MASK REG_GENMASK(24, 23)
2182#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
2183#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
2184#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
2185#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
2186
2187#define _PFA_WIN_SZ 0x68074
2188#define _PFB_WIN_SZ 0x68874
2189#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2190#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2191#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
2192#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2193#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
2194
2195#define _PFA_WIN_POS 0x68070
2196#define _PFB_WIN_POS 0x68870
2197#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2198#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
2199#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
2200#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
2201#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
2202
2203#define _PFA_VSCALE 0x68084
2204#define _PFB_VSCALE 0x68884
2205#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2206
2207#define _PFA_HSCALE 0x68090
2208#define _PFB_HSCALE 0x68890
2209#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2210
2211/*
2212 * Skylake scalers
2213 */
2214#define _ID(id, a, b) _PICK_EVEN(id, a, b)
2215#define _PS_1A_CTRL 0x68180
2216#define _PS_2A_CTRL 0x68280
2217#define _PS_1B_CTRL 0x68980
2218#define _PS_2B_CTRL 0x68A80
2219#define _PS_1C_CTRL 0x69180
2220#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
2221 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
2222 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
2223#define PS_SCALER_EN REG_BIT(31)
2224#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
2225#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
2226#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
2227#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
2228#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
2229#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
2230#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
2231#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
2232#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
2233#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
2234#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
2235#define PS_BINDING_MASK REG_GENMASK(27, 25)
2236#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
2237#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
2238#define PS_FILTER_MASK REG_GENMASK(24, 23)
2239#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
2240#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
2241#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
2242#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
2243#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
2244#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
2245#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
2246#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
2247#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
2248#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
2249#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
2250#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
2251#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
2252#define PS_PWRUP_PROGRESS REG_BIT(17)
2253#define PS_V_FILTER_BYPASS REG_BIT(8)
2254#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
2255#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
2256#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
2257#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
2258#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
2259#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2260#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
2261#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
2262#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
2263#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
2264#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
2265#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
2266#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
2267#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
2268#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
2269
2270#define _PS_PWR_GATE_1A 0x68160
2271#define _PS_PWR_GATE_2A 0x68260
2272#define _PS_PWR_GATE_1B 0x68960
2273#define _PS_PWR_GATE_2B 0x68A60
2274#define _PS_PWR_GATE_1C 0x69160
2275#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
2276 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
2277 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
2278#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
2279#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
2280#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
2281#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
2282#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
2283#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
2284#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
2285#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
2286#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
2287#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
2288#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
2289
2290#define _PS_WIN_POS_1A 0x68170
2291#define _PS_WIN_POS_2A 0x68270
2292#define _PS_WIN_POS_1B 0x68970
2293#define _PS_WIN_POS_2B 0x68A70
2294#define _PS_WIN_POS_1C 0x69170
2295#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
2296 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
2297 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
2298#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
2299#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
2300#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
2301#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
2302
2303#define _PS_WIN_SZ_1A 0x68174
2304#define _PS_WIN_SZ_2A 0x68274
2305#define _PS_WIN_SZ_1B 0x68974
2306#define _PS_WIN_SZ_2B 0x68A74
2307#define _PS_WIN_SZ_1C 0x69174
2308#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
2309 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
2310 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
2311#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2312#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
2313#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2314#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
2315
2316#define _PS_VSCALE_1A 0x68184
2317#define _PS_VSCALE_2A 0x68284
2318#define _PS_VSCALE_1B 0x68984
2319#define _PS_VSCALE_2B 0x68A84
2320#define _PS_VSCALE_1C 0x69184
2321#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
2322 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
2323 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
2324
2325#define _PS_HSCALE_1A 0x68190
2326#define _PS_HSCALE_2A 0x68290
2327#define _PS_HSCALE_1B 0x68990
2328#define _PS_HSCALE_2B 0x68A90
2329#define _PS_HSCALE_1C 0x69190
2330#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
2331 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
2332 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
2333
2334#define _PS_VPHASE_1A 0x68188
2335#define _PS_VPHASE_2A 0x68288
2336#define _PS_VPHASE_1B 0x68988
2337#define _PS_VPHASE_2B 0x68A88
2338#define _PS_VPHASE_1C 0x69188
2339#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
2340 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
2341 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
2342#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
2343#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
2344#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
2345#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
2346#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
2347#define PS_PHASE_TRIP (1 << 0)
2348
2349#define _PS_HPHASE_1A 0x68194
2350#define _PS_HPHASE_2A 0x68294
2351#define _PS_HPHASE_1B 0x68994
2352#define _PS_HPHASE_2B 0x68A94
2353#define _PS_HPHASE_1C 0x69194
2354#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
2355 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
2356 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
2357
2358#define _PS_ECC_STAT_1A 0x681D0
2359#define _PS_ECC_STAT_2A 0x682D0
2360#define _PS_ECC_STAT_1B 0x689D0
2361#define _PS_ECC_STAT_2B 0x68AD0
2362#define _PS_ECC_STAT_1C 0x691D0
2363#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
2364 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
2365 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
2366
2367#define _PS_COEF_SET0_INDEX_1A 0x68198
2368#define _PS_COEF_SET0_INDEX_2A 0x68298
2369#define _PS_COEF_SET0_INDEX_1B 0x68998
2370#define _PS_COEF_SET0_INDEX_2B 0x68A98
2371#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
2372 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
2373 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
2374#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
2375
2376#define _PS_COEF_SET0_DATA_1A 0x6819C
2377#define _PS_COEF_SET0_DATA_2A 0x6829C
2378#define _PS_COEF_SET0_DATA_1B 0x6899C
2379#define _PS_COEF_SET0_DATA_2B 0x68A9C
2380#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
2381 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
2382 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
2383
2384/* Display Internal Timeout Register */
2385#define RM_TIMEOUT _MMIO(0x42060)
2386#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
2387#define MMIO_TIMEOUT_US(us) ((us) << 0)
2388
2389/* interrupts */
2390#define DE_MASTER_IRQ_CONTROL (1 << 31)
2391#define DE_SPRITEB_FLIP_DONE (1 << 29)
2392#define DE_SPRITEA_FLIP_DONE (1 << 28)
2393#define DE_PLANEB_FLIP_DONE (1 << 27)
2394#define DE_PLANEA_FLIP_DONE (1 << 26)
2395#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
2396#define DE_PCU_EVENT (1 << 25)
2397#define DE_GTT_FAULT (1 << 24)
2398#define DE_POISON (1 << 23)
2399#define DE_PERFORM_COUNTER (1 << 22)
2400#define DE_PCH_EVENT (1 << 21)
2401#define DE_AUX_CHANNEL_A (1 << 20)
2402#define DE_DP_A_HOTPLUG (1 << 19)
2403#define DE_GSE (1 << 18)
2404#define DE_PIPEB_VBLANK (1 << 15)
2405#define DE_PIPEB_EVEN_FIELD (1 << 14)
2406#define DE_PIPEB_ODD_FIELD (1 << 13)
2407#define DE_PIPEB_LINE_COMPARE (1 << 12)
2408#define DE_PIPEB_VSYNC (1 << 11)
2409#define DE_PIPEB_CRC_DONE (1 << 10)
2410#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2411#define DE_PIPEA_VBLANK (1 << 7)
2412#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
2413#define DE_PIPEA_EVEN_FIELD (1 << 6)
2414#define DE_PIPEA_ODD_FIELD (1 << 5)
2415#define DE_PIPEA_LINE_COMPARE (1 << 4)
2416#define DE_PIPEA_VSYNC (1 << 3)
2417#define DE_PIPEA_CRC_DONE (1 << 2)
2418#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
2419#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2420#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
2421
2422/* More Ivybridge lolz */
2423#define DE_ERR_INT_IVB (1 << 30)
2424#define DE_GSE_IVB (1 << 29)
2425#define DE_PCH_EVENT_IVB (1 << 28)
2426#define DE_DP_A_HOTPLUG_IVB (1 << 27)
2427#define DE_AUX_CHANNEL_A_IVB (1 << 26)
2428#define DE_EDP_PSR_INT_HSW (1 << 19)
2429#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
2430#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
2431#define DE_PIPEC_VBLANK_IVB (1 << 10)
2432#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
2433#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
2434#define DE_PIPEB_VBLANK_IVB (1 << 5)
2435#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
2436#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
2437#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
2438#define DE_PIPEA_VBLANK_IVB (1 << 0)
2439#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
2440
2441#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
2442#define MASTER_INTERRUPT_ENABLE (1 << 31)
2443
2444#define DEISR _MMIO(0x44000)
2445#define DEIMR _MMIO(0x44004)
2446#define DEIIR _MMIO(0x44008)
2447#define DEIER _MMIO(0x4400c)
2448
2449#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
2450 DEIER, \
2451 DEIIR)
2452
2453#define GTISR _MMIO(0x44010)
2454#define GTIMR _MMIO(0x44014)
2455#define GTIIR _MMIO(0x44018)
2456#define GTIER _MMIO(0x4401c)
2457
2458#define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \
2459 GTIER, \
2460 GTIIR)
2461
2462#define GEN8_MASTER_IRQ _MMIO(0x44200)
2463#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
2464#define GEN8_PCU_IRQ (1 << 30)
2465#define GEN8_DE_PCH_IRQ (1 << 23)
2466#define GEN8_DE_MISC_IRQ (1 << 22)
2467#define GEN8_DE_PORT_IRQ (1 << 20)
2468#define GEN8_DE_PIPE_C_IRQ (1 << 18)
2469#define GEN8_DE_PIPE_B_IRQ (1 << 17)
2470#define GEN8_DE_PIPE_A_IRQ (1 << 16)
2471#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
2472#define GEN8_GT_VECS_IRQ (1 << 6)
2473#define GEN8_GT_GUC_IRQ (1 << 5)
2474#define GEN8_GT_PM_IRQ (1 << 4)
2475#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
2476#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
2477#define GEN8_GT_BCS_IRQ (1 << 1)
2478#define GEN8_GT_RCS_IRQ (1 << 0)
2479
2480#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
2481
2482#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
2483#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
2484#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
2485#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
2486
2487#define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \
2488 GEN8_GT_IER(which), \
2489 GEN8_GT_IIR(which))
2490
2491#define GEN8_RCS_IRQ_SHIFT 0
2492#define GEN8_BCS_IRQ_SHIFT 16
2493#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
2494#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
2495#define GEN8_VECS_IRQ_SHIFT 0
2496#define GEN8_WD_IRQ_SHIFT 16
2497
2498#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
2499#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
2500#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
2501#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
2502#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
2503#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
2504#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
2505#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2506#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2507#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
2508#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2509#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2510#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
2511#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
2512#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
2513#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
2514#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
2515#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
2516#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
2517#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
2518#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
2519#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
2520#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
2521#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
2522#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
2523#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
2524#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
2525#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
2526#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
2527#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
2528#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
2529#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
2530#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
2531#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
2532#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
2533#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
2534#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
2535 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
2536#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
2537#define GEN8_PIPE_VSYNC REG_BIT(1)
2538#define GEN8_PIPE_VBLANK REG_BIT(0)
2539
2540#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
2541 GEN8_DE_PIPE_IER(pipe), \
2542 GEN8_DE_PIPE_IIR(pipe))
2543
2544#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
2545#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
2546
2547#define GEN8_DE_PORT_ISR _MMIO(0x44440)
2548#define GEN8_DE_PORT_IMR _MMIO(0x44444)
2549#define GEN8_DE_PORT_IIR _MMIO(0x44448)
2550#define GEN8_DE_PORT_IER _MMIO(0x4444c)
2551#define DSI1_NON_TE (1 << 31)
2552#define DSI0_NON_TE (1 << 30)
2553#define ICL_AUX_CHANNEL_E (1 << 29)
2554#define ICL_AUX_CHANNEL_F (1 << 28)
2555#define GEN9_AUX_CHANNEL_D (1 << 27)
2556#define GEN9_AUX_CHANNEL_C (1 << 26)
2557#define GEN9_AUX_CHANNEL_B (1 << 25)
2558#define DSI1_TE (1 << 24)
2559#define DSI0_TE (1 << 23)
2560#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
2561#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
2562 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
2563 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
2564#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
2565#define BXT_DE_PORT_GMBUS (1 << 1)
2566#define GEN8_AUX_CHANNEL_A (1 << 0)
2567#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
2568#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
2569#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
2570#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
2571#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
2572#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
2573#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
2574#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
2575#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
2576#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
2577#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
2578
2579#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
2580 GEN8_DE_PORT_IER, \
2581 GEN8_DE_PORT_IIR)
2582
2583#define GEN8_DE_MISC_ISR _MMIO(0x44460)
2584#define GEN8_DE_MISC_IMR _MMIO(0x44464)
2585#define GEN8_DE_MISC_IIR _MMIO(0x44468)
2586#define GEN8_DE_MISC_IER _MMIO(0x4446c)
2587#define XELPDP_RM_TIMEOUT REG_BIT(29)
2588#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
2589#define GEN8_DE_MISC_GSE REG_BIT(27)
2590#define GEN8_DE_EDP_PSR REG_BIT(19)
2591#define XELPDP_PMDEMAND_RSP REG_BIT(3)
2592#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
2593
2594#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
2595 GEN8_DE_MISC_IER, \
2596 GEN8_DE_MISC_IIR)
2597
2598#define GEN8_PCU_ISR _MMIO(0x444e0)
2599#define GEN8_PCU_IMR _MMIO(0x444e4)
2600#define GEN8_PCU_IIR _MMIO(0x444e8)
2601#define GEN8_PCU_IER _MMIO(0x444ec)
2602
2603#define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \
2604 GEN8_PCU_IER, \
2605 GEN8_PCU_IIR)
2606
2607#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
2608#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
2609#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
2610#define GEN11_GU_MISC_IER _MMIO(0x444fc)
2611#define GEN11_GU_MISC_GSE (1 << 27)
2612
2613#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
2614 GEN11_GU_MISC_IER, \
2615 GEN11_GU_MISC_IIR)
2616
2617#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
2618#define GEN11_MASTER_IRQ (1 << 31)
2619#define GEN11_PCU_IRQ (1 << 30)
2620#define GEN11_GU_MISC_IRQ (1 << 29)
2621#define GEN11_DISPLAY_IRQ (1 << 16)
2622#define GEN11_GT_DW_IRQ(x) (1 << (x))
2623#define GEN11_GT_DW1_IRQ (1 << 1)
2624#define GEN11_GT_DW0_IRQ (1 << 0)
2625
2626#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
2627#define DG1_MSTR_IRQ REG_BIT(31)
2628#define DG1_MSTR_TILE(t) REG_BIT(t)
2629
2630#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
2631#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
2632#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
2633#define GEN11_DE_PCH_IRQ (1 << 23)
2634#define GEN11_DE_MISC_IRQ (1 << 22)
2635#define GEN11_DE_HPD_IRQ (1 << 21)
2636#define GEN11_DE_PORT_IRQ (1 << 20)
2637#define GEN11_DE_PIPE_C (1 << 18)
2638#define GEN11_DE_PIPE_B (1 << 17)
2639#define GEN11_DE_PIPE_A (1 << 16)
2640
2641#define GEN11_DE_HPD_ISR _MMIO(0x44470)
2642#define GEN11_DE_HPD_IMR _MMIO(0x44474)
2643#define GEN11_DE_HPD_IIR _MMIO(0x44478)
2644#define GEN11_DE_HPD_IER _MMIO(0x4447c)
2645#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2646#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
2647 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
2648 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
2649 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
2650 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
2651 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
2652#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2653#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
2654 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
2655 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
2656 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
2657 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
2658 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
2659
2660#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
2661 GEN11_DE_HPD_IER, \
2662 GEN11_DE_HPD_IIR)
2663
2664#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
2665#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
2666#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
2667#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
2668#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
2669#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
2670
2671#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
2672#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
2673#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
2674#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
2675#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2676#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
2677#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
2678#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
2679#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
2680#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
2681#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2682#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
2683
2684#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \
2685 PICAINTERRUPT_IER, \
2686 PICAINTERRUPT_IIR)
2687
2688#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
2689#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
2690#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
2691#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
2692#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
2693#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
2694#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
2695
2696#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
2697#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
2698#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
2699#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
2700#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
2701#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
2702#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
2703#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
2704
2705#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
2706#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
2707#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
2708#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
2709#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
2710
2711#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
2712#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
2713
2714#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
2715/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2716#define ILK_ELPIN_409_SELECT REG_BIT(25)
2717#define ILK_DPARB_GATE REG_BIT(22)
2718#define ILK_VSDPFD_FULL REG_BIT(21)
2719
2720#define FUSE_STRAP _MMIO(0x42014)
2721#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
2722#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
2723#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
2724#define IVB_PIPE_C_DISABLE REG_BIT(28)
2725#define ILK_HDCP_DISABLE REG_BIT(25)
2726#define ILK_eDP_A_DISABLE REG_BIT(24)
2727#define HSW_CDCLK_LIMIT REG_BIT(24)
2728#define ILK_DESKTOP REG_BIT(23)
2729#define HSW_CPU_SSC_ENABLE REG_BIT(21)
2730
2731#define FUSE_STRAP3 _MMIO(0x42020)
2732#define HSW_REF_CLK_SELECT REG_BIT(1)
2733
2734#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
2735#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
2736#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
2737#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
2738#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
2739#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
2740
2741#define IVB_CHICKEN3 _MMIO(0x4200c)
2742#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
2743#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
2744
2745#define CHICKEN_PAR1_1 _MMIO(0x42080)
2746#define IGNORE_KVMR_PIPE_A REG_BIT(23)
2747#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
2748#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
2749#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
2750#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
2751#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
2752#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
2753#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
2754
2755#define CHICKEN_PAR2_1 _MMIO(0x42090)
2756#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
2757
2758#define CHICKEN_MISC_2 _MMIO(0x42084)
2759#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
2760#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
2761#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
2762#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
2763#define GLK_CL2_PWR_DOWN REG_BIT(12)
2764#define GLK_CL1_PWR_DOWN REG_BIT(11)
2765#define GLK_CL0_PWR_DOWN REG_BIT(10)
2766
2767#define CHICKEN_MISC_3 _MMIO(0x42088)
2768#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2769#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2770#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2771
2772#define CHICKEN_MISC_4 _MMIO(0x4208c)
2773#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
2774#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
2775#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
2776
2777#define _CHICKEN_PIPESL_1_A 0x420b0
2778#define _CHICKEN_PIPESL_1_B 0x420b4
2779#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
2780#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
2781#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
2782#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
2783#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
2784#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
2785#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
2786#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
2787#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
2788#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
2789#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
2790#define HSW_FBCQ_DIS REG_BIT(22)
2791#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
2792#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
2793#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
2794#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
2795#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
2796#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
2797#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
2798#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
2799
2800#define _CHICKEN_TRANS_A 0x420c0
2801#define _CHICKEN_TRANS_B 0x420c4
2802#define _CHICKEN_TRANS_C 0x420c8
2803#define _CHICKEN_TRANS_EDP 0x420cc
2804#define _CHICKEN_TRANS_D 0x420d8
2805#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
2806 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
2807 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
2808 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
2809 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
2810 [TRANSCODER_D] = _CHICKEN_TRANS_D))
2811#define _MTL_CHICKEN_TRANS_A 0x604e0
2812#define _MTL_CHICKEN_TRANS_B 0x614e0
2813#define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
2814 _MTL_CHICKEN_TRANS_A, \
2815 _MTL_CHICKEN_TRANS_B)
2816#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
2817#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
2818#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
2819#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
2820#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
2821#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
2822#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
2823#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
2824#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
2825#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
2826#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
2827#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
2828#define DP_FEC_BS_JITTER_WA REG_BIT(15)
2829#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
2830#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
2831#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
2832
2833#define DISP_ARB_CTL _MMIO(0x45000)
2834#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
2835#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
2836#define DISP_FBC_WM_DIS REG_BIT(15)
2837
2838#define DISP_ARB_CTL2 _MMIO(0x45004)
2839#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
2840#define DISP_IPC_ENABLE REG_BIT(3)
2841
2842#define GEN7_MSG_CTL _MMIO(0x45010)
2843#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
2844#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
2845
2846#define _BW_BUDDY0_CTL 0x45130
2847#define _BW_BUDDY1_CTL 0x45140
2848#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
2849 _BW_BUDDY0_CTL, \
2850 _BW_BUDDY1_CTL))
2851#define BW_BUDDY_DISABLE REG_BIT(31)
2852#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
2853#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
2854
2855#define _BW_BUDDY0_PAGE_MASK 0x45134
2856#define _BW_BUDDY1_PAGE_MASK 0x45144
2857#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
2858 _BW_BUDDY0_PAGE_MASK, \
2859 _BW_BUDDY1_PAGE_MASK))
2860
2861#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
2862#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
2863#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
2864
2865#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
2866#define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
2867#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
2868#define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
2869#define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
2870#define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
2871#define ICL_DELAY_PMRSP REG_BIT(22)
2872#define DISABLE_FLR_SRC REG_BIT(15)
2873#define MASK_WAKEMEM REG_BIT(13)
2874#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
2875
2876#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
2877#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
2878#define DCPR_MASK_LPMODE REG_BIT(26)
2879#define DCPR_SEND_RESP_IMM REG_BIT(25)
2880#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
2881
2882#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
2883#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
2884
2885#define SKL_DFSM _MMIO(0x51000)
2886#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
2887#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
2888#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
2889#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
2890#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
2891#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
2892#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
2893#define ICL_DFSM_DMC_DISABLE (1 << 23)
2894#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
2895#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
2896#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
2897#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
2898#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
2899#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
2900
2901#define XE2LPD_DE_CAP _MMIO(0x41100)
2902#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
2903#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
2904#define XE2LPD_DE_CAP_DSC_REMOVED 1
2905#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
2906#define XE2LPD_DE_CAP_SCALER_SINGLE 1
2907
2908#define SKL_DSSM _MMIO(0x51004)
2909#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
2910#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
2911#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
2912#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
2913
2914#define GMD_ID_DISPLAY _MMIO(0x510a0)
2915#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
2916#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
2917#define GMD_ID_STEP REG_GENMASK(5, 0)
2918
2919/*GEN11 chicken */
2920#define _PIPEA_CHICKEN 0x70038
2921#define _PIPEB_CHICKEN 0x71038
2922#define _PIPEC_CHICKEN 0x72038
2923#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
2924 _PIPEB_CHICKEN)
2925#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
2926#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
2927#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
2928#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
2929#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
2930
2931/* PCH */
2932
2933#define PCH_DISPLAY_BASE 0xc0000u
2934
2935/* south display engine interrupt: IBX */
2936#define SDE_AUDIO_POWER_D (1 << 27)
2937#define SDE_AUDIO_POWER_C (1 << 26)
2938#define SDE_AUDIO_POWER_B (1 << 25)
2939#define SDE_AUDIO_POWER_SHIFT (25)
2940#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2941#define SDE_GMBUS (1 << 24)
2942#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2943#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2944#define SDE_AUDIO_HDCP_MASK (3 << 22)
2945#define SDE_AUDIO_TRANSB (1 << 21)
2946#define SDE_AUDIO_TRANSA (1 << 20)
2947#define SDE_AUDIO_TRANS_MASK (3 << 20)
2948#define SDE_POISON (1 << 19)
2949/* 18 reserved */
2950#define SDE_FDI_RXB (1 << 17)
2951#define SDE_FDI_RXA (1 << 16)
2952#define SDE_FDI_MASK (3 << 16)
2953#define SDE_AUXD (1 << 15)
2954#define SDE_AUXC (1 << 14)
2955#define SDE_AUXB (1 << 13)
2956#define SDE_AUX_MASK (7 << 13)
2957/* 12 reserved */
2958#define SDE_CRT_HOTPLUG (1 << 11)
2959#define SDE_PORTD_HOTPLUG (1 << 10)
2960#define SDE_PORTC_HOTPLUG (1 << 9)
2961#define SDE_PORTB_HOTPLUG (1 << 8)
2962#define SDE_SDVOB_HOTPLUG (1 << 6)
2963#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
2964 SDE_SDVOB_HOTPLUG | \
2965 SDE_PORTB_HOTPLUG | \
2966 SDE_PORTC_HOTPLUG | \
2967 SDE_PORTD_HOTPLUG)
2968#define SDE_TRANSB_CRC_DONE (1 << 5)
2969#define SDE_TRANSB_CRC_ERR (1 << 4)
2970#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2971#define SDE_TRANSA_CRC_DONE (1 << 2)
2972#define SDE_TRANSA_CRC_ERR (1 << 1)
2973#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2974#define SDE_TRANS_MASK (0x3f)
2975
2976/* south display engine interrupt: CPT - CNP */
2977#define SDE_AUDIO_POWER_D_CPT (1 << 31)
2978#define SDE_AUDIO_POWER_C_CPT (1 << 30)
2979#define SDE_AUDIO_POWER_B_CPT (1 << 29)
2980#define SDE_AUDIO_POWER_SHIFT_CPT 29
2981#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
2982#define SDE_AUXD_CPT (1 << 27)
2983#define SDE_AUXC_CPT (1 << 26)
2984#define SDE_AUXB_CPT (1 << 25)
2985#define SDE_AUX_MASK_CPT (7 << 25)
2986#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
2987#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
2988#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2989#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2990#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2991#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2992#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
2993#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2994 SDE_SDVOB_HOTPLUG_CPT | \
2995 SDE_PORTD_HOTPLUG_CPT | \
2996 SDE_PORTC_HOTPLUG_CPT | \
2997 SDE_PORTB_HOTPLUG_CPT)
2998#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
2999 SDE_PORTD_HOTPLUG_CPT | \
3000 SDE_PORTC_HOTPLUG_CPT | \
3001 SDE_PORTB_HOTPLUG_CPT | \
3002 SDE_PORTA_HOTPLUG_SPT)
3003#define SDE_GMBUS_CPT (1 << 17)
3004#define SDE_ERROR_CPT (1 << 16)
3005#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3006#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3007#define SDE_FDI_RXC_CPT (1 << 8)
3008#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3009#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3010#define SDE_FDI_RXB_CPT (1 << 4)
3011#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3012#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3013#define SDE_FDI_RXA_CPT (1 << 0)
3014#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3015 SDE_AUDIO_CP_REQ_B_CPT | \
3016 SDE_AUDIO_CP_REQ_A_CPT)
3017#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3018 SDE_AUDIO_CP_CHG_B_CPT | \
3019 SDE_AUDIO_CP_CHG_A_CPT)
3020#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3021 SDE_FDI_RXB_CPT | \
3022 SDE_FDI_RXA_CPT)
3023
3024/* south display engine interrupt: ICP/TGP/MTP */
3025#define SDE_PICAINTERRUPT REG_BIT(31)
3026#define SDE_GMBUS_ICP (1 << 23)
3027#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
3028#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
3029#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
3030#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
3031 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
3032 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
3033 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
3034#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
3035 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
3036 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
3037 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
3038 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
3039 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
3040
3041#define SDEISR _MMIO(0xc4000)
3042#define SDEIMR _MMIO(0xc4004)
3043#define SDEIIR _MMIO(0xc4008)
3044#define SDEIER _MMIO(0xc400c)
3045
3046#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
3047 SDEIER, \
3048 SDEIIR)
3049
3050#define SERR_INT _MMIO(0xc4040)
3051#define SERR_INT_POISON (1 << 31)
3052#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
3053
3054/* digital port hotplug */
3055#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
3056#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
3057#define BXT_DDIA_HPD_INVERT (1 << 27)
3058#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
3059#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
3060#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
3061#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
3062#define PORTD_HOTPLUG_ENABLE (1 << 20)
3063#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
3064#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
3065#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
3066#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
3067#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
3068#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
3069#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
3070#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3071#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
3072#define PORTC_HOTPLUG_ENABLE (1 << 12)
3073#define BXT_DDIC_HPD_INVERT (1 << 11)
3074#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
3075#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
3076#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
3077#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
3078#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
3079#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
3080#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
3081#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3082#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
3083#define PORTB_HOTPLUG_ENABLE (1 << 4)
3084#define BXT_DDIB_HPD_INVERT (1 << 3)
3085#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
3086#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
3087#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
3088#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
3089#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
3090#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
3091#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
3092#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3093#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
3094#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
3095 BXT_DDIB_HPD_INVERT | \
3096 BXT_DDIC_HPD_INVERT)
3097
3098#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
3099#define PORTE_HOTPLUG_ENABLE (1 << 4)
3100#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
3101#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
3102#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
3103#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
3104
3105/* This register is a reuse of PCH_PORT_HOTPLUG register. The
3106 * functionality covered in PCH_PORT_HOTPLUG is split into
3107 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
3108 */
3109
3110#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
3111#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
3112#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
3113#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3114#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
3115#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
3116#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
3117#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3118
3119#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
3120#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
3121#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
3122#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
3123
3124#define SHPD_FILTER_CNT _MMIO(0xc4038)
3125#define SHPD_FILTER_CNT_500_ADJ 0x001D9
3126#define SHPD_FILTER_CNT_250 0x000F8
3127
3128#define _PCH_DPLL_A 0xc6014
3129#define _PCH_DPLL_B 0xc6018
3130#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3131
3132#define _PCH_FPA0 0xc6040
3133#define _PCH_FPB0 0xc6048
3134#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
3135#define FP_CB_TUNE (0x3 << 22)
3136
3137#define _PCH_FPA1 0xc6044
3138#define _PCH_FPB1 0xc604c
3139#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
3140
3141#define PCH_DPLL_TEST _MMIO(0xc606c)
3142
3143#define PCH_DREF_CONTROL _MMIO(0xC6200)
3144#define DREF_CONTROL_MASK 0x7fc3
3145#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
3146#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
3147#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
3148#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
3149#define DREF_SSC_SOURCE_DISABLE (0 << 11)
3150#define DREF_SSC_SOURCE_ENABLE (2 << 11)
3151#define DREF_SSC_SOURCE_MASK (3 << 11)
3152#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
3153#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
3154#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
3155#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
3156#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
3157#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
3158#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
3159#define DREF_SSC4_DOWNSPREAD (0 << 6)
3160#define DREF_SSC4_CENTERSPREAD (1 << 6)
3161#define DREF_SSC1_DISABLE (0 << 1)
3162#define DREF_SSC1_ENABLE (1 << 1)
3163#define DREF_SSC4_DISABLE (0)
3164#define DREF_SSC4_ENABLE (1)
3165
3166#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
3167#define FDL_TP1_TIMER_SHIFT 12
3168#define FDL_TP1_TIMER_MASK (3 << 12)
3169#define FDL_TP2_TIMER_SHIFT 10
3170#define FDL_TP2_TIMER_MASK (3 << 10)
3171#define RAWCLK_FREQ_MASK 0x3ff
3172#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
3173#define CNP_RAWCLK_DIV(div) ((div) << 16)
3174#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
3175#define CNP_RAWCLK_DEN(den) ((den) << 26)
3176#define ICP_RAWCLK_NUM(num) ((num) << 11)
3177
3178#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
3179
3180#define PCH_SSC4_PARMS _MMIO(0xc6210)
3181#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
3182
3183#define PCH_DPLL_SEL _MMIO(0xc7000)
3184#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
3185#define TRANS_DPLLA_SEL(pipe) 0
3186#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
3187
3188/* transcoder */
3189
3190#define _PCH_TRANS_HTOTAL_A 0xe0000
3191#define _PCH_TRANS_HTOTAL_B 0xe1000
3192#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
3193#define TRANS_HTOTAL_SHIFT 16
3194#define TRANS_HACTIVE_SHIFT 0
3195
3196#define _PCH_TRANS_HBLANK_A 0xe0004
3197#define _PCH_TRANS_HBLANK_B 0xe1004
3198#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
3199#define TRANS_HBLANK_END_SHIFT 16
3200#define TRANS_HBLANK_START_SHIFT 0
3201
3202#define _PCH_TRANS_HSYNC_A 0xe0008
3203#define _PCH_TRANS_HSYNC_B 0xe1008
3204#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
3205#define TRANS_HSYNC_END_SHIFT 16
3206#define TRANS_HSYNC_START_SHIFT 0
3207
3208#define _PCH_TRANS_VTOTAL_A 0xe000c
3209#define _PCH_TRANS_VTOTAL_B 0xe100c
3210#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
3211#define TRANS_VTOTAL_SHIFT 16
3212#define TRANS_VACTIVE_SHIFT 0
3213
3214#define _PCH_TRANS_VBLANK_A 0xe0010
3215#define _PCH_TRANS_VBLANK_B 0xe1010
3216#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
3217#define TRANS_VBLANK_END_SHIFT 16
3218#define TRANS_VBLANK_START_SHIFT 0
3219
3220#define _PCH_TRANS_VSYNC_A 0xe0014
3221#define _PCH_TRANS_VSYNC_B 0xe1014
3222#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
3223#define TRANS_VSYNC_END_SHIFT 16
3224#define TRANS_VSYNC_START_SHIFT 0
3225
3226#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
3227#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
3228#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
3229
3230#define _PCH_TRANSA_DATA_M1 0xe0030
3231#define _PCH_TRANSB_DATA_M1 0xe1030
3232#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
3233
3234#define _PCH_TRANSA_DATA_N1 0xe0034
3235#define _PCH_TRANSB_DATA_N1 0xe1034
3236#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
3237
3238#define _PCH_TRANSA_DATA_M2 0xe0038
3239#define _PCH_TRANSB_DATA_M2 0xe1038
3240#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
3241
3242#define _PCH_TRANSA_DATA_N2 0xe003c
3243#define _PCH_TRANSB_DATA_N2 0xe103c
3244#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
3245
3246#define _PCH_TRANSA_LINK_M1 0xe0040
3247#define _PCH_TRANSB_LINK_M1 0xe1040
3248#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
3249
3250#define _PCH_TRANSA_LINK_N1 0xe0044
3251#define _PCH_TRANSB_LINK_N1 0xe1044
3252#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
3253
3254#define _PCH_TRANSA_LINK_M2 0xe0048
3255#define _PCH_TRANSB_LINK_M2 0xe1048
3256#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
3257
3258#define _PCH_TRANSA_LINK_N2 0xe004c
3259#define _PCH_TRANSB_LINK_N2 0xe104c
3260#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
3261
3262/* Per-transcoder DIP controls (PCH) */
3263#define _VIDEO_DIP_CTL_A 0xe0200
3264#define _VIDEO_DIP_CTL_B 0xe1200
3265#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3266
3267#define _VIDEO_DIP_DATA_A 0xe0208
3268#define _VIDEO_DIP_DATA_B 0xe1208
3269#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3270
3271#define _VIDEO_DIP_GCP_A 0xe0210
3272#define _VIDEO_DIP_GCP_B 0xe1210
3273#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3274#define GCP_COLOR_INDICATION (1 << 2)
3275#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
3276#define GCP_AV_MUTE (1 << 0)
3277
3278/* Per-transcoder DIP controls (VLV) */
3279#define _VLV_VIDEO_DIP_CTL_A 0x60200
3280#define _VLV_VIDEO_DIP_CTL_B 0x61170
3281#define _CHV_VIDEO_DIP_CTL_C 0x611f0
3282#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3283 _VLV_VIDEO_DIP_CTL_A, \
3284 _VLV_VIDEO_DIP_CTL_B, \
3285 _CHV_VIDEO_DIP_CTL_C)
3286
3287#define _VLV_VIDEO_DIP_DATA_A 0x60208
3288#define _VLV_VIDEO_DIP_DATA_B 0x61174
3289#define _CHV_VIDEO_DIP_DATA_C 0x611f4
3290#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3291 _VLV_VIDEO_DIP_DATA_A, \
3292 _VLV_VIDEO_DIP_DATA_B, \
3293 _CHV_VIDEO_DIP_DATA_C)
3294
3295#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3296#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3297#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
3298#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3299 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
3300 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
3301 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
3302
3303/* Haswell DIP controls */
3304#define _HSW_VIDEO_DIP_CTL_A 0x60200
3305#define _HSW_VIDEO_DIP_CTL_B 0x61200
3306#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
3307
3308#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3309#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3310#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
3311
3312#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
3313#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
3314#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
3315
3316#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3317#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3318#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
3319
3320#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3321#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3322#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
3323
3324#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3325#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3326#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
3327
3328/*ADLP and later: */
3329#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
3330#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
3331#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\
3332 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
3333
3334#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
3335#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
3336#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
3337
3338#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3339#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3340#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
3341#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
3342#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3343#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3344#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3345#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3346#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3347#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3348
3349#define _HSW_VIDEO_DIP_GCP_A 0x60210
3350#define _HSW_VIDEO_DIP_GCP_B 0x61210
3351#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
3352
3353/* Icelake PPS_DATA and _ECC DIP Registers.
3354 * These are available for transcoders B,C and eDP.
3355 * Adding the _A so as to reuse the _MMIO_TRANS2
3356 * definition, with which it offsets to the right location.
3357 */
3358
3359#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
3360#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
3361#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
3362
3363#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
3364#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
3365#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
3366
3367#define _HSW_STEREO_3D_CTL_A 0x70020
3368#define _HSW_STEREO_3D_CTL_B 0x71020
3369#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
3370#define S3D_ENABLE (1 << 31)
3371
3372#define _PCH_TRANSACONF 0xf0008
3373#define _PCH_TRANSBCONF 0xf1008
3374#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
3375#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
3376#define TRANS_ENABLE REG_BIT(31)
3377#define TRANS_STATE_ENABLE REG_BIT(30)
3378#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
3379#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3380#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
3381#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
3382#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
3383#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
3384#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
3385#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
3386#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
3387#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
3388#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
3389
3390#define _TRANSA_CHICKEN1 0xf0060
3391#define _TRANSB_CHICKEN1 0xf1060
3392#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3393#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
3394#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
3395
3396#define _TRANSA_CHICKEN2 0xf0064
3397#define _TRANSB_CHICKEN2 0xf1064
3398#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3399#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
3400#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
3401#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
3402#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3403#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
3404#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
3405
3406#define SOUTH_CHICKEN1 _MMIO(0xc2000)
3407#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3408#define FDIA_PHASE_SYNC_SHIFT_EN 18
3409#define INVERT_DDIE_HPD REG_BIT(28)
3410#define INVERT_DDID_HPD_MTP REG_BIT(27)
3411#define INVERT_TC4_HPD REG_BIT(26)
3412#define INVERT_TC3_HPD REG_BIT(25)
3413#define INVERT_TC2_HPD REG_BIT(24)
3414#define INVERT_TC1_HPD REG_BIT(23)
3415#define INVERT_DDID_HPD (1 << 18)
3416#define INVERT_DDIC_HPD (1 << 17)
3417#define INVERT_DDIB_HPD (1 << 16)
3418#define INVERT_DDIA_HPD (1 << 15)
3419#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3420#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3421#define FDI_BC_BIFURCATION_SELECT (1 << 12)
3422#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
3423#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
3424#define SBCLK_RUN_REFCLK_DIS (1 << 7)
3425#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
3426#define SPT_PWM_GRANULARITY (1 << 0)
3427#define SOUTH_CHICKEN2 _MMIO(0xc2004)
3428#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
3429#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
3430#define LPT_PWM_GRANULARITY (1 << 5)
3431#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
3432
3433#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
3434#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
3435#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
3436#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
3437#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
3438#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
3439#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
3440#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
3441
3442#define PCH_DP_B _MMIO(0xe4100)
3443#define PCH_DP_C _MMIO(0xe4200)
3444#define PCH_DP_D _MMIO(0xe4300)
3445
3446/* CPT */
3447#define _TRANS_DP_CTL_A 0xe0300
3448#define _TRANS_DP_CTL_B 0xe1300
3449#define _TRANS_DP_CTL_C 0xe2300
3450#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
3451#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
3452#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
3453#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
3454#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
3455#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
3456#define TRANS_DP_ENH_FRAMING REG_BIT(18)
3457#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
3458#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
3459#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
3460#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
3461#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
3462#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
3463#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
3464
3465#define _TRANS_DP2_CTL_A 0x600a0
3466#define _TRANS_DP2_CTL_B 0x610a0
3467#define _TRANS_DP2_CTL_C 0x620a0
3468#define _TRANS_DP2_CTL_D 0x630a0
3469#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
3470#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
3471#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
3472#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
3473
3474#define _TRANS_DP2_VFREQHIGH_A 0x600a4
3475#define _TRANS_DP2_VFREQHIGH_B 0x610a4
3476#define _TRANS_DP2_VFREQHIGH_C 0x620a4
3477#define _TRANS_DP2_VFREQHIGH_D 0x630a4
3478#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
3479#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
3480#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
3481
3482#define _TRANS_DP2_VFREQLOW_A 0x600a8
3483#define _TRANS_DP2_VFREQLOW_B 0x610a8
3484#define _TRANS_DP2_VFREQLOW_C 0x620a8
3485#define _TRANS_DP2_VFREQLOW_D 0x630a8
3486#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
3487
3488/* SNB eDP training params */
3489/* SNB A-stepping */
3490#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
3491#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
3492#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
3493#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
3494/* SNB B-stepping */
3495#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
3496#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
3497#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
3498#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
3499#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
3500#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
3501
3502/* IVB */
3503#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
3504#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
3505#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
3506#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
3507#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
3508#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
3509#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
3510
3511/* legacy values */
3512#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
3513#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
3514#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
3515#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
3516#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
3517
3518#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
3519
3520#define VLV_PMWGICZ _MMIO(0x1300a4)
3521
3522#define HSW_EDRAM_CAP _MMIO(0x120010)
3523#define EDRAM_ENABLED 0x1
3524#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
3525#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
3526#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
3527
3528#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
3529#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
3530#define PIXEL_OVERLAP_CNT_SHIFT 30
3531
3532#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
3533#define GEN6_PCODE_READY (1 << 31)
3534#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
3535#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
3536#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
3537#define GEN6_PCODE_ERROR_MASK 0xFF
3538#define GEN6_PCODE_SUCCESS 0x0
3539#define GEN6_PCODE_ILLEGAL_CMD 0x1
3540#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
3541#define GEN6_PCODE_TIMEOUT 0x3
3542#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
3543#define GEN7_PCODE_TIMEOUT 0x2
3544#define GEN7_PCODE_ILLEGAL_DATA 0x3
3545#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
3546#define GEN11_PCODE_LOCKED 0x6
3547#define GEN11_PCODE_REJECTED 0x11
3548#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
3549#define GEN6_PCODE_WRITE_RC6VIDS 0x4
3550#define GEN6_PCODE_READ_RC6VIDS 0x5
3551#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
3552#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
3553#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
3554#define GEN9_PCODE_READ_MEM_LATENCY 0x6
3555#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
3556#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
3557#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
3558#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
3559#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
3560#define SKL_PCODE_CDCLK_CONTROL 0x7
3561#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
3562#define SKL_CDCLK_READY_FOR_CHANGE 0x1
3563#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3564#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3565#define GEN6_READ_OC_PARAMS 0xc
3566#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
3567#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
3568#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
3569#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
3570#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
3571#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
3572#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
3573#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
3574#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
3575#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
3576#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
3577#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
3578#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
3579#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
3580#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
3581 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
3582 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
3583 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
3584#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
3585#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
3586#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
3587#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
3588#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
3589#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
3590#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
3591#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
3592#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
3593#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
3594#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
3595#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
3596#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
3597#define GEN6_PCODE_READ_D_COMP 0x10
3598#define GEN6_PCODE_WRITE_D_COMP 0x11
3599#define ICL_PCODE_EXIT_TCCOLD 0x12
3600#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
3601#define DISPLAY_IPS_CONTROL 0x19
3602#define TGL_PCODE_TCCOLD 0x26
3603#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
3604#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
3605#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
3606 /* See also IPS_CTL */
3607#define IPS_PCODE_CONTROL (1 << 30)
3608#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
3609#define GEN9_PCODE_SAGV_CONTROL 0x21
3610#define GEN9_SAGV_DISABLE 0x0
3611#define GEN9_SAGV_IS_DISABLED 0x1
3612#define GEN9_SAGV_ENABLE 0x3
3613#define DG1_PCODE_STATUS 0x7E
3614#define DG1_UNCORE_GET_INIT_STATUS 0x0
3615#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
3616#define PCODE_POWER_SETUP 0x7C
3617#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
3618#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
3619#define POWER_SETUP_I1_WATTS REG_BIT(31)
3620#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
3621#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3622#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
3623#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
3624/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
3625#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
3626#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
3627/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
3628/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
3629#define PCODE_MBOX_DOMAIN_NONE 0x0
3630#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
3631#define GEN6_PCODE_DATA _MMIO(0x138128)
3632#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3633#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
3634#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
3635
3636#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
3637#define STOLEN_ACCESS_ALLOWED 0x1
3638
3639/* IVYBRIDGE DPF */
3640#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3641#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
3642#define GEN7_PARITY_ERROR_VALID (1 << 13)
3643#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
3644#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
3645#define GEN7_PARITY_ERROR_ROW(reg) \
3646 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
3647#define GEN7_PARITY_ERROR_BANK(reg) \
3648 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
3649#define GEN7_PARITY_ERROR_SUBBANK(reg) \
3650 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
3651#define GEN7_L3CDERRST1_ENABLE (1 << 7)
3652
3653/* These are the 4 32-bit write offset registers for each stream
3654 * output buffer. It determines the offset from the
3655 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
3656 */
3657#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
3658
3659/*
3660 * HSW - ICL power wells
3661 *
3662 * Platforms have up to 3 power well control register sets, each set
3663 * controlling up to 16 power wells via a request/status HW flag tuple:
3664 * - main (HSW_PWR_WELL_CTL[1-4])
3665 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
3666 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
3667 * Each control register set consists of up to 4 registers used by different
3668 * sources that can request a power well to be enabled:
3669 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
3670 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
3671 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
3672 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
3673 */
3674#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
3675#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
3676#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
3677#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
3678#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
3679#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
3680
3681/* HSW/BDW power well */
3682#define HSW_PW_CTL_IDX_GLOBAL 15
3683
3684/* SKL/BXT/GLK power wells */
3685#define SKL_PW_CTL_IDX_PW_2 15
3686#define SKL_PW_CTL_IDX_PW_1 14
3687#define GLK_PW_CTL_IDX_AUX_C 10
3688#define GLK_PW_CTL_IDX_AUX_B 9
3689#define GLK_PW_CTL_IDX_AUX_A 8
3690#define SKL_PW_CTL_IDX_DDI_D 4
3691#define SKL_PW_CTL_IDX_DDI_C 3
3692#define SKL_PW_CTL_IDX_DDI_B 2
3693#define SKL_PW_CTL_IDX_DDI_A_E 1
3694#define GLK_PW_CTL_IDX_DDI_A 1
3695#define SKL_PW_CTL_IDX_MISC_IO 0
3696
3697/* ICL/TGL - power wells */
3698#define TGL_PW_CTL_IDX_PW_5 4
3699#define ICL_PW_CTL_IDX_PW_4 3
3700#define ICL_PW_CTL_IDX_PW_3 2
3701#define ICL_PW_CTL_IDX_PW_2 1
3702#define ICL_PW_CTL_IDX_PW_1 0
3703
3704/* XE_LPD - power wells */
3705#define XELPD_PW_CTL_IDX_PW_D 8
3706#define XELPD_PW_CTL_IDX_PW_C 7
3707#define XELPD_PW_CTL_IDX_PW_B 6
3708#define XELPD_PW_CTL_IDX_PW_A 5
3709
3710#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
3711#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
3712#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
3713#define TGL_PW_CTL_IDX_AUX_TBT6 14
3714#define TGL_PW_CTL_IDX_AUX_TBT5 13
3715#define TGL_PW_CTL_IDX_AUX_TBT4 12
3716#define ICL_PW_CTL_IDX_AUX_TBT4 11
3717#define TGL_PW_CTL_IDX_AUX_TBT3 11
3718#define ICL_PW_CTL_IDX_AUX_TBT3 10
3719#define TGL_PW_CTL_IDX_AUX_TBT2 10
3720#define ICL_PW_CTL_IDX_AUX_TBT2 9
3721#define TGL_PW_CTL_IDX_AUX_TBT1 9
3722#define ICL_PW_CTL_IDX_AUX_TBT1 8
3723#define TGL_PW_CTL_IDX_AUX_TC6 8
3724#define XELPD_PW_CTL_IDX_AUX_E 8
3725#define TGL_PW_CTL_IDX_AUX_TC5 7
3726#define XELPD_PW_CTL_IDX_AUX_D 7
3727#define TGL_PW_CTL_IDX_AUX_TC4 6
3728#define ICL_PW_CTL_IDX_AUX_F 5
3729#define TGL_PW_CTL_IDX_AUX_TC3 5
3730#define ICL_PW_CTL_IDX_AUX_E 4
3731#define TGL_PW_CTL_IDX_AUX_TC2 4
3732#define ICL_PW_CTL_IDX_AUX_D 3
3733#define TGL_PW_CTL_IDX_AUX_TC1 3
3734#define ICL_PW_CTL_IDX_AUX_C 2
3735#define ICL_PW_CTL_IDX_AUX_B 1
3736#define ICL_PW_CTL_IDX_AUX_A 0
3737
3738#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
3739#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
3740#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
3741#define XELPD_PW_CTL_IDX_DDI_E 8
3742#define TGL_PW_CTL_IDX_DDI_TC6 8
3743#define XELPD_PW_CTL_IDX_DDI_D 7
3744#define TGL_PW_CTL_IDX_DDI_TC5 7
3745#define TGL_PW_CTL_IDX_DDI_TC4 6
3746#define ICL_PW_CTL_IDX_DDI_F 5
3747#define TGL_PW_CTL_IDX_DDI_TC3 5
3748#define ICL_PW_CTL_IDX_DDI_E 4
3749#define TGL_PW_CTL_IDX_DDI_TC2 4
3750#define ICL_PW_CTL_IDX_DDI_D 3
3751#define TGL_PW_CTL_IDX_DDI_TC1 3
3752#define ICL_PW_CTL_IDX_DDI_C 2
3753#define ICL_PW_CTL_IDX_DDI_B 1
3754#define ICL_PW_CTL_IDX_DDI_A 0
3755
3756/* HSW - power well misc debug registers */
3757#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
3758#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
3759#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
3760#define HSW_PWR_WELL_FORCE_ON (1 << 19)
3761#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
3762
3763/* SKL Fuse Status */
3764enum skl_power_gate {
3765 SKL_PG0,
3766 SKL_PG1,
3767 SKL_PG2,
3768 ICL_PG3,
3769 ICL_PG4,
3770};
3771
3772#define SKL_FUSE_STATUS _MMIO(0x42000)
3773#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
3774/*
3775 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
3776 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
3777 */
3778#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
3779 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
3780/*
3781 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
3782 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
3783 */
3784#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
3785 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
3786#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
3787
3788/* Per-pipe DDI Function Control */
3789#define _TRANS_DDI_FUNC_CTL_A 0x60400
3790#define _TRANS_DDI_FUNC_CTL_B 0x61400
3791#define _TRANS_DDI_FUNC_CTL_C 0x62400
3792#define _TRANS_DDI_FUNC_CTL_D 0x63400
3793#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
3794#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
3795#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
3796#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
3797
3798#define TRANS_DDI_FUNC_ENABLE (1 << 31)
3799/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3800#define TRANS_DDI_PORT_SHIFT 28
3801#define TGL_TRANS_DDI_PORT_SHIFT 27
3802#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
3803#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
3804#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
3805#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
3806#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
3807#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
3808#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
3809#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
3810#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
3811#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
3812#define TRANS_DDI_BPC_MASK (7 << 20)
3813#define TRANS_DDI_BPC_8 (0 << 20)
3814#define TRANS_DDI_BPC_10 (1 << 20)
3815#define TRANS_DDI_BPC_6 (2 << 20)
3816#define TRANS_DDI_BPC_12 (3 << 20)
3817#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
3818#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
3819#define TRANS_DDI_PVSYNC (1 << 17)
3820#define TRANS_DDI_PHSYNC (1 << 16)
3821#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
3822#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
3823#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
3824#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
3825#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
3826#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
3827#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
3828#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
3829#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
3830#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
3831 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
3832#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
3833#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
3834#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
3835#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
3836#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
3837#define TRANS_DDI_BFI_ENABLE (1 << 4)
3838#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
3839#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
3840#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
3841#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
3842#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
3843 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
3844 | TRANS_DDI_HDMI_SCRAMBLING)
3845
3846#define _TRANS_DDI_FUNC_CTL2_A 0x60404
3847#define _TRANS_DDI_FUNC_CTL2_B 0x61404
3848#define _TRANS_DDI_FUNC_CTL2_C 0x62404
3849#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
3850#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
3851#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
3852#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
3853#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
3854#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
3855#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
3856
3857#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
3858#define DISABLE_DPT_CLK_GATING REG_BIT(1)
3859
3860/* DisplayPort Transport Control */
3861#define _DP_TP_CTL_A 0x64040
3862#define _DP_TP_CTL_B 0x64140
3863#define _TGL_DP_TP_CTL_A 0x60540
3864#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
3865#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
3866#define DP_TP_CTL_ENABLE (1 << 31)
3867#define DP_TP_CTL_FEC_ENABLE (1 << 30)
3868#define DP_TP_CTL_MODE_SST (0 << 27)
3869#define DP_TP_CTL_MODE_MST (1 << 27)
3870#define DP_TP_CTL_FORCE_ACT (1 << 25)
3871#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
3872#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
3873#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19)
3874#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19)
3875#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
3876#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
3877#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
3878#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
3879#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
3880#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
3881#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
3882#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
3883#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
3884#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
3885
3886/* DisplayPort Transport Status */
3887#define _DP_TP_STATUS_A 0x64044
3888#define _DP_TP_STATUS_B 0x64144
3889#define _TGL_DP_TP_STATUS_A 0x60544
3890#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
3891#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
3892#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
3893#define DP_TP_STATUS_IDLE_DONE (1 << 25)
3894#define DP_TP_STATUS_ACT_SENT (1 << 24)
3895#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
3896#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
3897#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
3898#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
3899#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
3900
3901/* DDI Buffer Control */
3902#define _DDI_BUF_CTL_A 0x64000
3903#define _DDI_BUF_CTL_B 0x64100
3904/* Known as DDI_CTL_DE in MTL+ */
3905#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
3906#define DDI_BUF_CTL_ENABLE (1 << 31)
3907#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
3908#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
3909#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
3910#define DDI_BUF_EMP_MASK (0xf << 24)
3911#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
3912#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
3913#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
3914#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
3915#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
3916#define DDI_BUF_PORT_REVERSAL (1 << 16)
3917#define DDI_BUF_IS_IDLE (1 << 7)
3918#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
3919#define DDI_A_4_LANES (1 << 4)
3920#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1)
3921#define DDI_PORT_WIDTH_MASK (7 << 1)
3922#define DDI_PORT_WIDTH_SHIFT 1
3923#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
3924
3925/* DDI Buffer Translations */
3926#define _DDI_BUF_TRANS_A 0x64E00
3927#define _DDI_BUF_TRANS_B 0x64E60
3928#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
3929#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
3930#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
3931
3932/* DDI DP Compliance Control */
3933#define _DDI_DP_COMP_CTL_A 0x605F0
3934#define _DDI_DP_COMP_CTL_B 0x615F0
3935#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
3936#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
3937#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
3938#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
3939#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
3940#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
3941#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
3942#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
3943#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
3944
3945/* DDI DP Compliance Pattern */
3946#define _DDI_DP_COMP_PAT_A 0x605F4
3947#define _DDI_DP_COMP_PAT_B 0x615F4
3948#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
3949
3950/* Sideband Interface (SBI) is programmed indirectly, via
3951 * SBI_ADDR, which contains the register offset; and SBI_DATA,
3952 * which contains the payload */
3953#define SBI_ADDR _MMIO(0xC6000)
3954#define SBI_DATA _MMIO(0xC6004)
3955#define SBI_CTL_STAT _MMIO(0xC6008)
3956#define SBI_CTL_DEST_ICLK (0x0 << 16)
3957#define SBI_CTL_DEST_MPHY (0x1 << 16)
3958#define SBI_CTL_OP_IORD (0x2 << 8)
3959#define SBI_CTL_OP_IOWR (0x3 << 8)
3960#define SBI_CTL_OP_CRRD (0x6 << 8)
3961#define SBI_CTL_OP_CRWR (0x7 << 8)
3962#define SBI_RESPONSE_FAIL (0x1 << 1)
3963#define SBI_RESPONSE_SUCCESS (0x0 << 1)
3964#define SBI_BUSY (0x1 << 0)
3965#define SBI_READY (0x0 << 0)
3966
3967/* SBI offsets */
3968#define SBI_SSCDIVINTPHASE 0x0200
3969#define SBI_SSCDIVINTPHASE6 0x0600
3970#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
3971#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
3972#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
3973#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
3974#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
3975#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
3976#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
3977#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
3978#define SBI_SSCDITHPHASE 0x0204
3979#define SBI_SSCCTL 0x020c
3980#define SBI_SSCCTL6 0x060C
3981#define SBI_SSCCTL_PATHALT (1 << 3)
3982#define SBI_SSCCTL_DISABLE (1 << 0)
3983#define SBI_SSCAUXDIV6 0x0610
3984#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
3985#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
3986#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
3987#define SBI_DBUFF0 0x2a00
3988#define SBI_GEN0 0x1f00
3989#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
3990
3991/* LPT PIXCLK_GATE */
3992#define PIXCLK_GATE _MMIO(0xC6020)
3993#define PIXCLK_GATE_UNGATE (1 << 0)
3994#define PIXCLK_GATE_GATE (0 << 0)
3995
3996/* SPLL */
3997#define SPLL_CTL _MMIO(0x46020)
3998#define SPLL_PLL_ENABLE (1 << 31)
3999#define SPLL_REF_BCLK (0 << 28)
4000#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4001#define SPLL_REF_NON_SSC_HSW (2 << 28)
4002#define SPLL_REF_PCH_SSC_BDW (2 << 28)
4003#define SPLL_REF_LCPLL (3 << 28)
4004#define SPLL_REF_MASK (3 << 28)
4005#define SPLL_FREQ_810MHz (0 << 26)
4006#define SPLL_FREQ_1350MHz (1 << 26)
4007#define SPLL_FREQ_2700MHz (2 << 26)
4008#define SPLL_FREQ_MASK (3 << 26)
4009
4010/* WRPLL */
4011#define _WRPLL_CTL1 0x46040
4012#define _WRPLL_CTL2 0x46060
4013#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
4014#define WRPLL_PLL_ENABLE (1 << 31)
4015#define WRPLL_REF_BCLK (0 << 28)
4016#define WRPLL_REF_PCH_SSC (1 << 28)
4017#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4018#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
4019#define WRPLL_REF_LCPLL (3 << 28)
4020#define WRPLL_REF_MASK (3 << 28)
4021/* WRPLL divider programming */
4022#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
4023#define WRPLL_DIVIDER_REF_MASK (0xff)
4024#define WRPLL_DIVIDER_POST(x) ((x) << 8)
4025#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
4026#define WRPLL_DIVIDER_POST_SHIFT 8
4027#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
4028#define WRPLL_DIVIDER_FB_SHIFT 16
4029#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
4030
4031/* Port clock selection */
4032#define _PORT_CLK_SEL_A 0x46100
4033#define _PORT_CLK_SEL_B 0x46104
4034#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
4035#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
4036#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
4037#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
4038#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
4039#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
4040#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
4041#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
4042#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
4043#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
4044
4045/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
4046#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
4047#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
4048#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
4049#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
4050#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
4051#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
4052#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
4053#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
4054
4055/* Transcoder clock selection */
4056#define _TRANS_CLK_SEL_A 0x46140
4057#define _TRANS_CLK_SEL_B 0x46144
4058#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
4059/* For each transcoder, we need to select the corresponding port clock */
4060#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
4061#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
4062#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
4063#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
4064
4065
4066#define CDCLK_FREQ _MMIO(0x46200)
4067
4068#define _TRANSA_MSA_MISC 0x60410
4069#define _TRANSB_MSA_MISC 0x61410
4070#define _TRANSC_MSA_MISC 0x62410
4071#define _TRANS_EDP_MSA_MISC 0x6f410
4072#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
4073/* See DP_MSA_MISC_* for the bit definitions */
4074
4075#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
4076#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
4077#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
4078#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
4079#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
4080#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
4081#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
4082
4083/* LCPLL Control */
4084#define LCPLL_CTL _MMIO(0x130040)
4085#define LCPLL_PLL_DISABLE (1 << 31)
4086#define LCPLL_PLL_LOCK (1 << 30)
4087#define LCPLL_REF_NON_SSC (0 << 28)
4088#define LCPLL_REF_BCLK (2 << 28)
4089#define LCPLL_REF_PCH_SSC (3 << 28)
4090#define LCPLL_REF_MASK (3 << 28)
4091#define LCPLL_CLK_FREQ_MASK (3 << 26)
4092#define LCPLL_CLK_FREQ_450 (0 << 26)
4093#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
4094#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
4095#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
4096#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
4097#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
4098#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
4099#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
4100#define LCPLL_CD_SOURCE_FCLK (1 << 21)
4101#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
4102
4103/*
4104 * SKL Clocks
4105 */
4106
4107/* CDCLK_CTL */
4108#define CDCLK_CTL _MMIO(0x46000)
4109#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
4110#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
4111#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
4112#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
4113#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
4114#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
4115#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
4116#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
4117#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
4118#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
4119#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
4120#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
4121#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
4122#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
4123#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
4124#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
4125#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
4126#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
4127#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
4128#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
4129#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
4130#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
4131
4132/* CDCLK_SQUASH_CTL */
4133#define CDCLK_SQUASH_CTL _MMIO(0x46008)
4134#define CDCLK_SQUASH_ENABLE REG_BIT(31)
4135#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
4136#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
4137#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
4138#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
4139
4140/* LCPLL_CTL */
4141#define LCPLL1_CTL _MMIO(0x46010)
4142#define LCPLL2_CTL _MMIO(0x46014)
4143#define LCPLL_PLL_ENABLE (1 << 31)
4144
4145/* DPLL control1 */
4146#define DPLL_CTRL1 _MMIO(0x6C058)
4147#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
4148#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
4149#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
4150#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
4151#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
4152#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
4153#define DPLL_CTRL1_LINK_RATE_2700 0
4154#define DPLL_CTRL1_LINK_RATE_1350 1
4155#define DPLL_CTRL1_LINK_RATE_810 2
4156#define DPLL_CTRL1_LINK_RATE_1620 3
4157#define DPLL_CTRL1_LINK_RATE_1080 4
4158#define DPLL_CTRL1_LINK_RATE_2160 5
4159
4160/* DPLL control2 */
4161#define DPLL_CTRL2 _MMIO(0x6C05C)
4162#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
4163#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
4164#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
4165#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
4166#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
4167
4168/* DPLL Status */
4169#define DPLL_STATUS _MMIO(0x6C060)
4170#define DPLL_LOCK(id) (1 << ((id) * 8))
4171
4172/* DPLL cfg */
4173#define _DPLL1_CFGCR1 0x6C040
4174#define _DPLL2_CFGCR1 0x6C048
4175#define _DPLL3_CFGCR1 0x6C050
4176#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
4177#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
4178#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
4179#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
4180#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
4181
4182#define _DPLL1_CFGCR2 0x6C044
4183#define _DPLL2_CFGCR2 0x6C04C
4184#define _DPLL3_CFGCR2 0x6C054
4185#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
4186#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
4187#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
4188#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
4189#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
4190#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
4191#define DPLL_CFGCR2_KDIV_5 (0 << 5)
4192#define DPLL_CFGCR2_KDIV_2 (1 << 5)
4193#define DPLL_CFGCR2_KDIV_3 (2 << 5)
4194#define DPLL_CFGCR2_KDIV_1 (3 << 5)
4195#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
4196#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
4197#define DPLL_CFGCR2_PDIV_1 (0 << 2)
4198#define DPLL_CFGCR2_PDIV_2 (1 << 2)
4199#define DPLL_CFGCR2_PDIV_3 (2 << 2)
4200#define DPLL_CFGCR2_PDIV_7 (4 << 2)
4201#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
4202#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
4203
4204/* ICL Clocks */
4205#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
4206#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
4207#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
4208#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
4209 (tc_port) + 12 : \
4210 (tc_port) - TC_PORT_4 + 21))
4211#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
4212#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4213#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4214#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
4215#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
4216 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4217#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
4218 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4219
4220/*
4221 * DG1 Clocks
4222 * First registers controls the first A and B, while the second register
4223 * controls the phy C and D. The bits on these registers are the
4224 * same, but refer to different phys
4225 */
4226#define _DG1_DPCLKA_CFGCR0 0x164280
4227#define _DG1_DPCLKA1_CFGCR0 0x16C280
4228#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
4229#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
4230#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
4231 _DG1_DPCLKA_CFGCR0, \
4232 _DG1_DPCLKA1_CFGCR0)
4233#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
4234#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
4235#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4236#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4237
4238/* ADLS Clocks */
4239#define _ADLS_DPCLKA_CFGCR0 0x164280
4240#define _ADLS_DPCLKA_CFGCR1 0x1642BC
4241#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
4242 _ADLS_DPCLKA_CFGCR0, \
4243 _ADLS_DPCLKA_CFGCR1)
4244#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
4245/* ADLS DPCLKA_CFGCR0 DDI mask */
4246#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
4247#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
4248#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
4249/* ADLS DPCLKA_CFGCR1 DDI mask */
4250#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
4251#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
4252#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
4253 ADLS_DPCLKA_DDIA_SEL_MASK, \
4254 ADLS_DPCLKA_DDIB_SEL_MASK, \
4255 ADLS_DPCLKA_DDII_SEL_MASK, \
4256 ADLS_DPCLKA_DDIJ_SEL_MASK, \
4257 ADLS_DPCLKA_DDIK_SEL_MASK)
4258
4259/* ICL PLL */
4260#define _DPLL0_ENABLE 0x46010
4261#define _DPLL1_ENABLE 0x46014
4262#define _ADLS_DPLL2_ENABLE 0x46018
4263#define _ADLS_DPLL3_ENABLE 0x46030
4264#define PLL_ENABLE REG_BIT(31)
4265#define PLL_LOCK REG_BIT(30)
4266#define PLL_POWER_ENABLE REG_BIT(27)
4267#define PLL_POWER_STATE REG_BIT(26)
4268#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4269 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4270 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
4271
4272#define _DG2_PLL3_ENABLE 0x4601C
4273
4274#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4275 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4276 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
4277
4278#define TBT_PLL_ENABLE _MMIO(0x46020)
4279
4280#define _MG_PLL1_ENABLE 0x46030
4281#define _MG_PLL2_ENABLE 0x46034
4282#define _MG_PLL3_ENABLE 0x46038
4283#define _MG_PLL4_ENABLE 0x4603C
4284/* Bits are the same as _DPLL0_ENABLE */
4285#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
4286 _MG_PLL2_ENABLE)
4287
4288/* DG1 PLL */
4289#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4290 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4291 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
4292
4293/* ADL-P Type C PLL */
4294#define PORTTC1_PLL_ENABLE 0x46038
4295#define PORTTC2_PLL_ENABLE 0x46040
4296#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
4297 PORTTC1_PLL_ENABLE, \
4298 PORTTC2_PLL_ENABLE)
4299
4300#define _ICL_DPLL0_CFGCR0 0x164000
4301#define _ICL_DPLL1_CFGCR0 0x164080
4302#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
4303 _ICL_DPLL1_CFGCR0)
4304#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
4305#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
4306#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
4307#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
4308#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
4309#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
4310#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
4311#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
4312#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
4313#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
4314#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
4315#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
4316#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
4317#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
4318#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
4319#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
4320
4321#define _ICL_DPLL0_CFGCR1 0x164004
4322#define _ICL_DPLL1_CFGCR1 0x164084
4323#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
4324 _ICL_DPLL1_CFGCR1)
4325#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
4326#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
4327#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
4328#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
4329#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
4330#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
4331#define DPLL_CFGCR1_KDIV_SHIFT (6)
4332#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
4333#define DPLL_CFGCR1_KDIV_1 (1 << 6)
4334#define DPLL_CFGCR1_KDIV_2 (2 << 6)
4335#define DPLL_CFGCR1_KDIV_3 (4 << 6)
4336#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
4337#define DPLL_CFGCR1_PDIV_SHIFT (2)
4338#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
4339#define DPLL_CFGCR1_PDIV_2 (1 << 2)
4340#define DPLL_CFGCR1_PDIV_3 (2 << 2)
4341#define DPLL_CFGCR1_PDIV_5 (4 << 2)
4342#define DPLL_CFGCR1_PDIV_7 (8 << 2)
4343#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
4344#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
4345#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
4346
4347#define _TGL_DPLL0_CFGCR0 0x164284
4348#define _TGL_DPLL1_CFGCR0 0x16428C
4349#define _TGL_TBTPLL_CFGCR0 0x16429C
4350#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4351 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4352 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
4353#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
4354 _TGL_DPLL1_CFGCR0)
4355
4356#define _TGL_DPLL0_DIV0 0x164B00
4357#define _TGL_DPLL1_DIV0 0x164C00
4358#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
4359#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
4360#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
4361
4362#define _TGL_DPLL0_CFGCR1 0x164288
4363#define _TGL_DPLL1_CFGCR1 0x164290
4364#define _TGL_TBTPLL_CFGCR1 0x1642A0
4365#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4366 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4367 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
4368#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
4369 _TGL_DPLL1_CFGCR1)
4370
4371#define _DG1_DPLL2_CFGCR0 0x16C284
4372#define _DG1_DPLL3_CFGCR0 0x16C28C
4373#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4374 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4375 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
4376
4377#define _DG1_DPLL2_CFGCR1 0x16C288
4378#define _DG1_DPLL3_CFGCR1 0x16C290
4379#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4380 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4381 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
4382
4383/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
4384#define _ADLS_DPLL4_CFGCR0 0x164294
4385#define _ADLS_DPLL3_CFGCR0 0x1642C0
4386#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4387 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4388 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
4389
4390#define _ADLS_DPLL4_CFGCR1 0x164298
4391#define _ADLS_DPLL3_CFGCR1 0x1642C4
4392#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4393 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4394 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
4395
4396/* BXT display engine PLL */
4397#define BXT_DE_PLL_CTL _MMIO(0x6d000)
4398#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
4399#define BXT_DE_PLL_RATIO_MASK 0xff
4400
4401#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
4402#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
4403#define BXT_DE_PLL_LOCK (1 << 30)
4404#define BXT_DE_PLL_FREQ_REQ (1 << 23)
4405#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
4406#define ICL_CDCLK_PLL_RATIO(x) (x)
4407#define ICL_CDCLK_PLL_RATIO_MASK 0xff
4408
4409/* GEN9 DC */
4410#define DC_STATE_EN _MMIO(0x45504)
4411#define DC_STATE_DISABLE 0
4412#define DC_STATE_EN_DC3CO REG_BIT(30)
4413#define DC_STATE_DC3CO_STATUS REG_BIT(29)
4414#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
4415#define HOLD_PHY_PG1_LATCH REG_BIT(20)
4416#define DC_STATE_EN_UPTO_DC5 (1 << 0)
4417#define DC_STATE_EN_DC9 (1 << 3)
4418#define DC_STATE_EN_UPTO_DC6 (2 << 0)
4419#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
4420
4421#define DC_STATE_DEBUG _MMIO(0x45520)
4422#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
4423#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
4424
4425#define D_COMP_BDW _MMIO(0x138144)
4426
4427/* Pipe WM_LINETIME - watermark line time */
4428#define _WM_LINETIME_A 0x45270
4429#define _WM_LINETIME_B 0x45274
4430#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
4431#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
4432#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
4433#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
4434#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
4435
4436/* SFUSE_STRAP */
4437#define SFUSE_STRAP _MMIO(0xc2014)
4438#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
4439#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
4440#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
4441#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
4442#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
4443#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
4444#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
4445#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
4446
4447#define WM_MISC _MMIO(0x45260)
4448#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
4449
4450#define WM_DBG _MMIO(0x45280)
4451#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
4452#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
4453#define WM_DBG_DISALLOW_SPRITE (1 << 2)
4454
4455/* Gen4+ Timestamp and Pipe Frame time stamp registers */
4456#define GEN4_TIMESTAMP _MMIO(0x2358)
4457#define ILK_TIMESTAMP_HI _MMIO(0x70070)
4458#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
4459
4460#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
4461#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
4462#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
4463#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
4464#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
4465
4466/* g4x+, except vlv/chv! */
4467#define _PIPE_FRMTMSTMP_A 0x70048
4468#define _PIPE_FRMTMSTMP_B 0x71048
4469#define PIPE_FRMTMSTMP(pipe) \
4470 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
4471
4472/* g4x+, except vlv/chv! */
4473#define _PIPE_FLIPTMSTMP_A 0x7004C
4474#define _PIPE_FLIPTMSTMP_B 0x7104C
4475#define PIPE_FLIPTMSTMP(pipe) \
4476 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
4477
4478/* tgl+ */
4479#define _PIPE_FLIPDONETMSTMP_A 0x70054
4480#define _PIPE_FLIPDONETMSTMP_B 0x71054
4481#define PIPE_FLIPDONETIMSTMP(pipe) \
4482 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
4483
4484#define _VLV_PIPE_MSA_MISC_A 0x70048
4485#define VLV_PIPE_MSA_MISC(pipe) \
4486 _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A)
4487#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
4488#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
4489
4490#define GGC _MMIO(0x108040)
4491#define GMS_MASK REG_GENMASK(15, 8)
4492#define GGMS_MASK REG_GENMASK(7, 6)
4493
4494#define GEN6_GSMBASE _MMIO(0x108100)
4495#define GEN6_DSMBASE _MMIO(0x1080C0)
4496#define GEN6_BDSM_MASK REG_GENMASK64(31, 20)
4497#define GEN11_BDSM_MASK REG_GENMASK64(63, 20)
4498
4499#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
4500#define SGSI_SIDECLK_DIS REG_BIT(17)
4501#define SGGI_DIS REG_BIT(15)
4502#define SGR_DIS REG_BIT(13)
4503
4504#define _ICL_PHY_MISC_A 0x64C00
4505#define _ICL_PHY_MISC_B 0x64C04
4506#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
4507#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
4508#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
4509 ICL_PHY_MISC(port))
4510#define ICL_PHY_MISC_MUX_DDID (1 << 28)
4511#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
4512#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
4513
4514#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
4515#define MODULAR_FIA_MASK (1 << 4)
4516#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
4517#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
4518#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
4519#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
4520#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
4521
4522#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
4523#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
4524
4525#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
4526#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
4527
4528#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
4529#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
4530#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
4531#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
4532
4533#define _TCSS_DDI_STATUS_1 0x161500
4534#define _TCSS_DDI_STATUS_2 0x161504
4535#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
4536 _TCSS_DDI_STATUS_1, \
4537 _TCSS_DDI_STATUS_2))
4538#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
4539#define TCSS_DDI_STATUS_READY REG_BIT(2)
4540#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
4541#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
4542
4543#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
4544#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
4545#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
4546#define SPI_STATIC_REGIONS _MMIO(0x102090)
4547#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
4548#define OROM_OFFSET _MMIO(0x1020c0)
4549#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
4550
4551#define CLKREQ_POLICY _MMIO(0x101038)
4552#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
4553
4554#define CLKGATE_DIS_MISC _MMIO(0x46534)
4555#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
4556
4557#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
4558#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
4559#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
4560#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
4561
4562#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
4563#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
4564#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
4565#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
4566
4567#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
4568#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
4569#define MTL_TRCD_MASK REG_GENMASK(31, 24)
4570#define MTL_TRP_MASK REG_GENMASK(23, 16)
4571#define MTL_DCLK_MASK REG_GENMASK(15, 0)
4572
4573#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
4574#define MTL_TRAS_MASK REG_GENMASK(16, 8)
4575#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
4576
4577#define MTL_MEDIA_GSI_BASE 0x380000
4578
4579#endif /* _I915_REG_H_ */