1/*
   2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 *
  23 * Authors:
  24 *    Ke Yu
  25 *    Kevin Tian <kevin.tian@intel.com>
  26 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27 *
  28 * Contributors:
  29 *    Min He <min.he@intel.com>
  30 *    Ping Gao <ping.a.gao@intel.com>
  31 *    Tina Zhang <tina.zhang@intel.com>
  32 *    Yulei Zhang <yulei.zhang@intel.com>
  33 *    Zhi Wang <zhi.a.wang@intel.com>
  34 *
  35 */
  36
  37#include <linux/slab.h>
  38
  39#include "i915_drv.h"
  40#include "i915_reg.h"
  41#include "gt/intel_engine_regs.h"
  42#include "gt/intel_gpu_commands.h"
  43#include "gt/intel_gt_regs.h"
  44#include "gt/intel_lrc.h"
  45#include "gt/intel_ring.h"
  46#include "gt/intel_gt_requests.h"
  47#include "gt/shmem_utils.h"
  48#include "gvt.h"
  49#include "i915_pvinfo.h"
  50#include "trace.h"
  51
  52#include "display/i9xx_plane_regs.h"
  53#include "display/intel_sprite_regs.h"
  54#include "gem/i915_gem_context.h"
  55#include "gem/i915_gem_pm.h"
  56#include "gt/intel_context.h"
  57
  58#define INVALID_OP    (~0U)
  59
  60#define OP_LEN_MI           9
  61#define OP_LEN_2D           10
  62#define OP_LEN_3D_MEDIA     16
  63#define OP_LEN_MFX_VC       16
  64#define OP_LEN_VEBOX	    16
  65
  66#define CMD_TYPE(cmd)	(((cmd) >> 29) & 7)
  67
  68struct sub_op_bits {
  69	int hi;
  70	int low;
  71};
  72struct decode_info {
  73	const char *name;
  74	int op_len;
  75	int nr_sub_op;
  76	const struct sub_op_bits *sub_op;
  77};
  78
  79#define   MAX_CMD_BUDGET			0x7fffffff
  80#define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  81#define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  82#define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  83
  84#define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  85#define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  86#define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  87
  88/* Render Command Map */
  89
  90/* MI_* command Opcode (28:23) */
  91#define OP_MI_NOOP                          0x0
  92#define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  93#define OP_MI_USER_INTERRUPT                0x2
  94#define OP_MI_WAIT_FOR_EVENT                0x3
  95#define OP_MI_FLUSH                         0x4
  96#define OP_MI_ARB_CHECK                     0x5
  97#define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  98#define OP_MI_REPORT_HEAD                   0x7
  99#define OP_MI_ARB_ON_OFF                    0x8
 100#define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
 101#define OP_MI_BATCH_BUFFER_END              0xA
 102#define OP_MI_SUSPEND_FLUSH                 0xB
 103#define OP_MI_PREDICATE                     0xC  /* IVB+ */
 104#define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
 105#define OP_MI_SET_APPID                     0xE  /* IVB+ */
 106#define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
 107#define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
 108#define OP_MI_DISPLAY_FLIP                  0x14
 109#define OP_MI_SEMAPHORE_MBOX                0x16
 110#define OP_MI_SET_CONTEXT                   0x18
 111#define OP_MI_MATH                          0x1A
 112#define OP_MI_URB_CLEAR                     0x19
 113#define OP_MI_SEMAPHORE_SIGNAL		    0x1B  /* BDW+ */
 114#define OP_MI_SEMAPHORE_WAIT		    0x1C  /* BDW+ */
 115
 116#define OP_MI_STORE_DATA_IMM                0x20
 117#define OP_MI_STORE_DATA_INDEX              0x21
 118#define OP_MI_LOAD_REGISTER_IMM             0x22
 119#define OP_MI_UPDATE_GTT                    0x23
 120#define OP_MI_STORE_REGISTER_MEM            0x24
 121#define OP_MI_FLUSH_DW                      0x26
 122#define OP_MI_CLFLUSH                       0x27
 123#define OP_MI_REPORT_PERF_COUNT             0x28
 124#define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 125#define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 126#define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 127#define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 128#define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 129#define OP_MI_2E			    0x2E  /* BDW+ */
 130#define OP_MI_2F			    0x2F  /* BDW+ */
 131#define OP_MI_BATCH_BUFFER_START            0x31
 132
 133/* Bit definition for dword 0 */
 134#define _CMDBIT_BB_START_IN_PPGTT	(1UL << 8)
 135
 136#define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 137
 138#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 139#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 140#define BATCH_BUFFER_ADR_SPACE_BIT(x)	(((x) >> 8) & 1U)
 141#define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 142
 143/* 2D command: Opcode (28:22) */
 144#define OP_2D(x)    ((2<<7) | x)
 145
 146#define OP_XY_SETUP_BLT                             OP_2D(0x1)
 147#define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 148#define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 149#define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 150#define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 151#define OP_XY_TEXT_BLT                              OP_2D(0x26)
 152#define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 153#define OP_XY_COLOR_BLT                             OP_2D(0x50)
 154#define OP_XY_PAT_BLT                               OP_2D(0x51)
 155#define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 156#define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 157#define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 158#define OP_XY_FULL_BLT                              OP_2D(0x55)
 159#define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 160#define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 161#define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 162#define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 163#define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 164#define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 165#define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 166#define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 167#define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 168#define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 169#define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 170
 171/* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 172#define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 173	((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 174
 175#define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 176
 177#define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 178#define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 179#define OP_3D_MEDIA_0_1_4			OP_3D_MEDIA(0x0, 0x1, 0x04)
 180#define OP_SWTESS_BASE_ADDRESS			OP_3D_MEDIA(0x0, 0x1, 0x03)
 181
 182#define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 183
 184#define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 185
 186#define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 187#define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 188#define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 189#define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 190#define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 191#define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 192
 193#define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 194#define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 195#define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 196#define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 197
 198#define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 199#define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 200#define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 201#define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 202#define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 203#define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 204#define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 205#define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 206#define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 207#define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 208#define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 209#define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 210#define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 211#define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 212#define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 213#define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 214#define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 215#define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 216#define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 217#define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 218#define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 219#define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 220#define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 221#define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 222#define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 223#define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 224#define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 225#define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 226#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 227#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 228#define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 229#define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 230#define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 231#define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 232#define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 233#define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 234#define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 235#define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 236#define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 237#define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 238#define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 239#define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 240#define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 241#define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 242#define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 243#define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 244#define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 245#define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 246#define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 247#define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 248#define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 249#define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 250#define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 251#define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 252#define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 253#define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 254#define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 255#define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 256#define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 257#define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 258#define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 259#define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 260#define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 261#define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 262#define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 263#define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 264
 265#define OP_3DSTATE_VF_INSTANCING 		OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 266#define OP_3DSTATE_VF_SGVS  			OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 267#define OP_3DSTATE_VF_TOPOLOGY   		OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 268#define OP_3DSTATE_WM_CHROMAKEY   		OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 269#define OP_3DSTATE_PS_BLEND   			OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 270#define OP_3DSTATE_WM_DEPTH_STENCIL   		OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 271#define OP_3DSTATE_PS_EXTRA   			OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 272#define OP_3DSTATE_RASTER   			OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 273#define OP_3DSTATE_SBE_SWIZ   			OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 274#define OP_3DSTATE_WM_HZ_OP   			OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 275#define OP_3DSTATE_COMPONENT_PACKING		OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 276
 277#define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 278#define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 279#define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 280#define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 281#define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 282#define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 283#define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 284#define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 285#define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 286#define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 287#define OP_3DSTATE_MULTISAMPLE_BDW		OP_3D_MEDIA(0x3, 0x0, 0x0D)
 288#define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 289#define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 290#define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 291#define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 292#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 293#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 294#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 295#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 296#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 297#define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 298#define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 299#define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 300#define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 301#define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 302#define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 303#define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 304#define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 305
 306/* VCCP Command Parser */
 307
 308/*
 309 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 310 * git://anongit.freedesktop.org/vaapi/intel-driver
 311 * src/i965_defines.h
 312 *
 313 */
 314
 315#define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 316	(3 << 13 | \
 317	 (pipeline) << 11 | \
 318	 (op) << 8 | \
 319	 (sub_opa) << 5 | \
 320	 (sub_opb))
 321
 322#define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 323#define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 324#define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 325#define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 326#define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 327#define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 328#define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 329#define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 330#define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 331#define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 332#define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 333
 334#define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 335
 336#define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 337#define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 338#define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 339#define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 340#define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 341#define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 342#define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 343#define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 344#define OP_MFD_AVC_DPB_STATE			   OP_MFX(2, 1, 1, 6) /* IVB+ */
 345#define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 346#define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 347#define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 348
 349#define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 350#define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 351#define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 352#define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 353#define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 354
 355#define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 356#define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 357#define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 358#define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 359#define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 360
 361#define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 362#define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 363#define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 364
 365#define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 366#define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 367#define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 368
 369#define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 370	(3 << 13 | \
 371	 (pipeline) << 11 | \
 372	 (op) << 8 | \
 373	 (sub_opa) << 5 | \
 374	 (sub_opb))
 375
 376#define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 377#define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 378#define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 379
 380struct parser_exec_state;
 381
 382typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 383
 384#define GVT_CMD_HASH_BITS   7
 385
 386/* which DWords need address fix */
 387#define ADDR_FIX_1(x1)			(1 << (x1))
 388#define ADDR_FIX_2(x1, x2)		(ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 389#define ADDR_FIX_3(x1, x2, x3)		(ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 390#define ADDR_FIX_4(x1, x2, x3, x4)	(ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 391#define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 392
 393#define DWORD_FIELD(dword, end, start) \
 394	FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 395
 396#define OP_LENGTH_BIAS 2
 397#define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 398
 399static int gvt_check_valid_cmd_length(int len, int valid_len)
 400{
 401	if (valid_len != len) {
 402		gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 403			len, valid_len);
 404		return -EFAULT;
 405	}
 406	return 0;
 407}
 408
 409struct cmd_info {
 410	const char *name;
 411	u32 opcode;
 412
 413#define F_LEN_MASK	3U
 414#define F_LEN_CONST  1U
 415#define F_LEN_VAR    0U
 416/* value is const although LEN maybe variable */
 417#define F_LEN_VAR_FIXED    (1<<1)
 418
 419/*
 420 * command has its own ip advance logic
 421 * e.g. MI_BATCH_START, MI_BATCH_END
 422 */
 423#define F_IP_ADVANCE_CUSTOM (1<<2)
 424	u32 flag;
 425
 426#define R_RCS	BIT(RCS0)
 427#define R_VCS1  BIT(VCS0)
 428#define R_VCS2  BIT(VCS1)
 429#define R_VCS	(R_VCS1 | R_VCS2)
 430#define R_BCS	BIT(BCS0)
 431#define R_VECS	BIT(VECS0)
 432#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 433	/* rings that support this cmd: BLT/RCS/VCS/VECS */
 434	intel_engine_mask_t rings;
 435
 436	/* devices that support this cmd: SNB/IVB/HSW/... */
 437	u16 devices;
 438
 439	/* which DWords are address that need fix up.
 440	 * bit 0 means a 32-bit non address operand in command
 441	 * bit 1 means address operand, which could be 32-bit
 442	 * or 64-bit depending on different architectures.(
 443	 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 444	 * No matter the address length, each address only takes
 445	 * one bit in the bitmap.
 446	 */
 447	u16 addr_bitmap;
 448
 449	/* flag == F_LEN_CONST : command length
 450	 * flag == F_LEN_VAR : length bias bits
 451	 * Note: length is in DWord
 452	 */
 453	u32 len;
 454
 455	parser_cmd_handler handler;
 456
 457	/* valid length in DWord */
 458	u32 valid_len;
 459};
 460
 461struct cmd_entry {
 462	struct hlist_node hlist;
 463	const struct cmd_info *info;
 464};
 465
 466enum {
 467	RING_BUFFER_INSTRUCTION,
 468	BATCH_BUFFER_INSTRUCTION,
 469	BATCH_BUFFER_2ND_LEVEL,
 470	RING_BUFFER_CTX,
 471};
 472
 473enum {
 474	GTT_BUFFER,
 475	PPGTT_BUFFER
 476};
 477
 478struct parser_exec_state {
 479	struct intel_vgpu *vgpu;
 480	const struct intel_engine_cs *engine;
 481
 482	int buf_type;
 483
 484	/* batch buffer address type */
 485	int buf_addr_type;
 486
 487	/* graphics memory address of ring buffer start */
 488	unsigned long ring_start;
 489	unsigned long ring_size;
 490	unsigned long ring_head;
 491	unsigned long ring_tail;
 492
 493	/* instruction graphics memory address */
 494	unsigned long ip_gma;
 495
 496	/* mapped va of the instr_gma */
 497	void *ip_va;
 498	void *rb_va;
 499
 500	void *ret_bb_va;
 501	/* next instruction when return from  batch buffer to ring buffer */
 502	unsigned long ret_ip_gma_ring;
 503
 504	/* next instruction when return from 2nd batch buffer to batch buffer */
 505	unsigned long ret_ip_gma_bb;
 506
 507	/* batch buffer address type (GTT or PPGTT)
 508	 * used when ret from 2nd level batch buffer
 509	 */
 510	int saved_buf_addr_type;
 511	bool is_ctx_wa;
 512	bool is_init_ctx;
 513
 514	const struct cmd_info *info;
 515
 516	struct intel_vgpu_workload *workload;
 517};
 518
 519#define gmadr_dw_number(s)	\
 520	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 521
 522static unsigned long bypass_scan_mask = 0;
 523
 524/* ring ALL, type = 0 */
 525static const struct sub_op_bits sub_op_mi[] = {
 526	{31, 29},
 527	{28, 23},
 528};
 529
 530static const struct decode_info decode_info_mi = {
 531	"MI",
 532	OP_LEN_MI,
 533	ARRAY_SIZE(sub_op_mi),
 534	sub_op_mi,
 535};
 536
 537/* ring RCS, command type 2 */
 538static const struct sub_op_bits sub_op_2d[] = {
 539	{31, 29},
 540	{28, 22},
 541};
 542
 543static const struct decode_info decode_info_2d = {
 544	"2D",
 545	OP_LEN_2D,
 546	ARRAY_SIZE(sub_op_2d),
 547	sub_op_2d,
 548};
 549
 550/* ring RCS, command type 3 */
 551static const struct sub_op_bits sub_op_3d_media[] = {
 552	{31, 29},
 553	{28, 27},
 554	{26, 24},
 555	{23, 16},
 556};
 557
 558static const struct decode_info decode_info_3d_media = {
 559	"3D_Media",
 560	OP_LEN_3D_MEDIA,
 561	ARRAY_SIZE(sub_op_3d_media),
 562	sub_op_3d_media,
 563};
 564
 565/* ring VCS, command type 3 */
 566static const struct sub_op_bits sub_op_mfx_vc[] = {
 567	{31, 29},
 568	{28, 27},
 569	{26, 24},
 570	{23, 21},
 571	{20, 16},
 572};
 573
 574static const struct decode_info decode_info_mfx_vc = {
 575	"MFX_VC",
 576	OP_LEN_MFX_VC,
 577	ARRAY_SIZE(sub_op_mfx_vc),
 578	sub_op_mfx_vc,
 579};
 580
 581/* ring VECS, command type 3 */
 582static const struct sub_op_bits sub_op_vebox[] = {
 583	{31, 29},
 584	{28, 27},
 585	{26, 24},
 586	{23, 21},
 587	{20, 16},
 588};
 589
 590static const struct decode_info decode_info_vebox = {
 591	"VEBOX",
 592	OP_LEN_VEBOX,
 593	ARRAY_SIZE(sub_op_vebox),
 594	sub_op_vebox,
 595};
 596
 597static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 598	[RCS0] = {
 599		&decode_info_mi,
 600		NULL,
 601		NULL,
 602		&decode_info_3d_media,
 603		NULL,
 604		NULL,
 605		NULL,
 606		NULL,
 607	},
 608
 609	[VCS0] = {
 610		&decode_info_mi,
 611		NULL,
 612		NULL,
 613		&decode_info_mfx_vc,
 614		NULL,
 615		NULL,
 616		NULL,
 617		NULL,
 618	},
 619
 620	[BCS0] = {
 621		&decode_info_mi,
 622		NULL,
 623		&decode_info_2d,
 624		NULL,
 625		NULL,
 626		NULL,
 627		NULL,
 628		NULL,
 629	},
 630
 631	[VECS0] = {
 632		&decode_info_mi,
 633		NULL,
 634		NULL,
 635		&decode_info_vebox,
 636		NULL,
 637		NULL,
 638		NULL,
 639		NULL,
 640	},
 641
 642	[VCS1] = {
 643		&decode_info_mi,
 644		NULL,
 645		NULL,
 646		&decode_info_mfx_vc,
 647		NULL,
 648		NULL,
 649		NULL,
 650		NULL,
 651	},
 652};
 653
 654static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
 655{
 656	const struct decode_info *d_info;
 657
 658	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 659	if (d_info == NULL)
 660		return INVALID_OP;
 661
 662	return cmd >> (32 - d_info->op_len);
 663}
 664
 665static inline const struct cmd_info *
 666find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
 667	       const struct intel_engine_cs *engine)
 668{
 669	struct cmd_entry *e;
 670
 671	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 672		if (opcode == e->info->opcode &&
 673		    e->info->rings & engine->mask)
 674			return e->info;
 675	}
 676	return NULL;
 677}
 678
 679static inline const struct cmd_info *
 680get_cmd_info(struct intel_gvt *gvt, u32 cmd,
 681	     const struct intel_engine_cs *engine)
 682{
 683	u32 opcode;
 684
 685	opcode = get_opcode(cmd, engine);
 686	if (opcode == INVALID_OP)
 687		return NULL;
 688
 689	return find_cmd_entry(gvt, opcode, engine);
 690}
 691
 692static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 693{
 694	return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 695}
 696
 697static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
 698{
 699	const struct decode_info *d_info;
 700	int i;
 701
 702	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 703	if (d_info == NULL)
 704		return;
 705
 706	gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 707			cmd >> (32 - d_info->op_len), d_info->name);
 708
 709	for (i = 0; i < d_info->nr_sub_op; i++)
 710		pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 711					d_info->sub_op[i].low));
 712
 713	pr_err("\n");
 714}
 715
 716static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 717{
 718	return s->ip_va + (index << 2);
 719}
 720
 721static inline u32 cmd_val(struct parser_exec_state *s, int index)
 722{
 723	return *cmd_ptr(s, index);
 724}
 725
 726static inline bool is_init_ctx(struct parser_exec_state *s)
 727{
 728	return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
 729}
 730
 731static void parser_exec_state_dump(struct parser_exec_state *s)
 732{
 733	int cnt = 0;
 734	int i;
 735
 736	gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
 737		    " ring_head(%08lx) ring_tail(%08lx)\n",
 738		    s->vgpu->id, s->engine->name,
 739		    s->ring_start, s->ring_start + s->ring_size,
 740		    s->ring_head, s->ring_tail);
 741
 742	gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 743			s->buf_type == RING_BUFFER_INSTRUCTION ?
 744			"RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
 745				"CTX_BUFFER" : "BATCH_BUFFER"),
 746			s->buf_addr_type == GTT_BUFFER ?
 747			"GTT" : "PPGTT", s->ip_gma);
 748
 749	if (s->ip_va == NULL) {
 750		gvt_dbg_cmd(" ip_va(NULL)");
 751		return;
 752	}
 753
 754	gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 755			s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 756			cmd_val(s, 2), cmd_val(s, 3));
 757
 758	print_opcode(cmd_val(s, 0), s->engine);
 759
 760	s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 761
 762	while (cnt < 1024) {
 763		gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 764		for (i = 0; i < 8; i++)
 765			gvt_dbg_cmd("%08x ", cmd_val(s, i));
 766		gvt_dbg_cmd("\n");
 767
 768		s->ip_va += 8 * sizeof(u32);
 769		cnt += 8;
 770	}
 771}
 772
 773static inline void update_ip_va(struct parser_exec_state *s)
 774{
 775	unsigned long len = 0;
 776
 777	if (WARN_ON(s->ring_head == s->ring_tail))
 778		return;
 779
 780	if (s->buf_type == RING_BUFFER_INSTRUCTION ||
 781			s->buf_type == RING_BUFFER_CTX) {
 782		unsigned long ring_top = s->ring_start + s->ring_size;
 783
 784		if (s->ring_head > s->ring_tail) {
 785			if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 786				len = (s->ip_gma - s->ring_head);
 787			else if (s->ip_gma >= s->ring_start &&
 788					s->ip_gma <= s->ring_tail)
 789				len = (ring_top - s->ring_head) +
 790					(s->ip_gma - s->ring_start);
 791		} else
 792			len = (s->ip_gma - s->ring_head);
 793
 794		s->ip_va = s->rb_va + len;
 795	} else {/* shadow batch buffer */
 796		s->ip_va = s->ret_bb_va;
 797	}
 798}
 799
 800static inline int ip_gma_set(struct parser_exec_state *s,
 801		unsigned long ip_gma)
 802{
 803	WARN_ON(!IS_ALIGNED(ip_gma, 4));
 804
 805	s->ip_gma = ip_gma;
 806	update_ip_va(s);
 807	return 0;
 808}
 809
 810static inline int ip_gma_advance(struct parser_exec_state *s,
 811		unsigned int dw_len)
 812{
 813	s->ip_gma += (dw_len << 2);
 814
 815	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 816		if (s->ip_gma >= s->ring_start + s->ring_size)
 817			s->ip_gma -= s->ring_size;
 818		update_ip_va(s);
 819	} else {
 820		s->ip_va += (dw_len << 2);
 821	}
 822
 823	return 0;
 824}
 825
 826static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 827{
 828	if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 829		return info->len;
 830	else
 831		return (cmd & ((1U << info->len) - 1)) + 2;
 832	return 0;
 833}
 834
 835static inline int cmd_length(struct parser_exec_state *s)
 836{
 837	return get_cmd_length(s->info, cmd_val(s, 0));
 838}
 839
 840/* do not remove this, some platform may need clflush here */
 841#define patch_value(s, addr, val) do { \
 842	*addr = val; \
 843} while (0)
 844
 845static inline bool is_mocs_mmio(unsigned int offset)
 846{
 847	return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 848		((offset >= 0xb020) && (offset <= 0xb0a0));
 849}
 850
 851static int is_cmd_update_pdps(unsigned int offset,
 852			      struct parser_exec_state *s)
 853{
 854	u32 base = s->workload->engine->mmio_base;
 855	return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
 856}
 857
 858static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
 859				       unsigned int offset, unsigned int index)
 860{
 861	struct intel_vgpu *vgpu = s->vgpu;
 862	struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
 863	struct intel_vgpu_mm *mm;
 864	u64 pdps[GEN8_3LVL_PDPES];
 865
 866	if (shadow_mm->ppgtt_mm.root_entry_type ==
 867	    GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 868		pdps[0] = (u64)cmd_val(s, 2) << 32;
 869		pdps[0] |= cmd_val(s, 4);
 870
 871		mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
 872		if (!mm) {
 873			gvt_vgpu_err("failed to get the 4-level shadow vm\n");
 874			return -EINVAL;
 875		}
 876		intel_vgpu_mm_get(mm);
 877		list_add_tail(&mm->ppgtt_mm.link,
 878			      &s->workload->lri_shadow_mm);
 879		*cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 880		*cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 881	} else {
 882		/* Currently all guests use PML4 table and now can't
 883		 * have a guest with 3-level table but uses LRI for
 884		 * PPGTT update. So this is simply un-testable. */
 885		GEM_BUG_ON(1);
 886		gvt_vgpu_err("invalid shared shadow vm type\n");
 887		return -EINVAL;
 888	}
 889	return 0;
 890}
 891
 892static int cmd_reg_handler(struct parser_exec_state *s,
 893	unsigned int offset, unsigned int index, char *cmd)
 894{
 895	struct intel_vgpu *vgpu = s->vgpu;
 896	struct intel_gvt *gvt = vgpu->gvt;
 897	u32 ctx_sr_ctl;
 898	u32 *vreg, vreg_old;
 899
 900	if (offset + 4 > gvt->device_info.mmio_size) {
 901		gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 902				cmd, offset);
 903		return -EFAULT;
 904	}
 905
 906	if (is_init_ctx(s)) {
 907		struct intel_gvt_mmio_info *mmio_info;
 908
 909		intel_gvt_mmio_set_cmd_accessible(gvt, offset);
 910		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 911		if (mmio_info && mmio_info->write)
 912			intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
 913		return 0;
 914	}
 915
 916	if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
 917		gvt_vgpu_err("%s access to non-render register (%x)\n",
 918				cmd, offset);
 919		return -EBADRQC;
 920	}
 921
 922	if (!strncmp(cmd, "srm", 3) ||
 923			!strncmp(cmd, "lrm", 3)) {
 924		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
 925		    offset == 0x21f0 ||
 926		    (IS_BROADWELL(gvt->gt->i915) &&
 927		     offset == i915_mmio_reg_offset(INSTPM)))
 928			return 0;
 929		else {
 930			gvt_vgpu_err("%s access to register (%x)\n",
 931					cmd, offset);
 932			return -EPERM;
 933		}
 934	}
 935
 936	if (!strncmp(cmd, "lrr-src", 7) ||
 937			!strncmp(cmd, "lrr-dst", 7)) {
 938		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
 939			return 0;
 940		else {
 941			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
 942			return -EPERM;
 943		}
 944	}
 945
 946	if (!strncmp(cmd, "pipe_ctrl", 9)) {
 947		/* TODO: add LRI POST logic here */
 948		return 0;
 949	}
 950
 951	if (strncmp(cmd, "lri", 3))
 952		return -EPERM;
 953
 954	/* below are all lri handlers */
 955	vreg = &vgpu_vreg(s->vgpu, offset);
 956
 957	if (is_cmd_update_pdps(offset, s) &&
 958	    cmd_pdp_mmio_update_handler(s, offset, index))
 959		return -EINVAL;
 960
 961	if (offset == i915_mmio_reg_offset(DERRMR) ||
 962		offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 963		/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 964		patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 965	}
 966
 967	if (is_mocs_mmio(offset))
 968		*vreg = cmd_val(s, index + 1);
 969
 970	vreg_old = *vreg;
 971
 972	if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
 973		u32 cmdval_new, cmdval;
 974		struct intel_gvt_mmio_info *mmio_info;
 975
 976		cmdval = cmd_val(s, index + 1);
 977
 978		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 979		if (!mmio_info) {
 980			cmdval_new = cmdval;
 981		} else {
 982			u64 ro_mask = mmio_info->ro_mask;
 983			int ret;
 984
 985			if (likely(!ro_mask))
 986				ret = mmio_info->write(s->vgpu, offset,
 987						&cmdval, 4);
 988			else {
 989				gvt_vgpu_err("try to write RO reg %x\n",
 990						offset);
 991				ret = -EBADRQC;
 992			}
 993			if (ret)
 994				return ret;
 995			cmdval_new = *vreg;
 996		}
 997		if (cmdval_new != cmdval)
 998			patch_value(s, cmd_ptr(s, index+1), cmdval_new);
 999	}
1000
1001	/* only patch cmd. restore vreg value if changed in mmio write handler*/
1002	*vreg = vreg_old;
1003
1004	/* TODO
1005	 * In order to let workload with inhibit context to generate
1006	 * correct image data into memory, vregs values will be loaded to
1007	 * hw via LRIs in the workload with inhibit context. But as
1008	 * indirect context is loaded prior to LRIs in workload, we don't
1009	 * want reg values specified in indirect context overwritten by
1010	 * LRIs in workloads. So, when scanning an indirect context, we
1011	 * update reg values in it into vregs, so LRIs in workload with
1012	 * inhibit context will restore with correct values
1013	 */
1014	if (GRAPHICS_VER(s->engine->i915) == 9 &&
1015	    intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1016	    !strncmp(cmd, "lri", 3)) {
1017		intel_gvt_read_gpa(s->vgpu,
1018			s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1019		/* check inhibit context */
1020		if (ctx_sr_ctl & 1) {
1021			u32 data = cmd_val(s, index + 1);
1022
1023			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1024				intel_vgpu_mask_mmio_write(vgpu,
1025							offset, &data, 4);
1026			else
1027				vgpu_vreg(vgpu, offset) = data;
1028		}
1029	}
1030
1031	return 0;
1032}
1033
1034#define cmd_reg(s, i) \
1035	(cmd_val(s, i) & GENMASK(22, 2))
1036
1037#define cmd_reg_inhibit(s, i) \
1038	(cmd_val(s, i) & GENMASK(22, 18))
1039
1040#define cmd_gma(s, i) \
1041	(cmd_val(s, i) & GENMASK(31, 2))
1042
1043#define cmd_gma_hi(s, i) \
1044	(cmd_val(s, i) & GENMASK(15, 0))
1045
1046static int cmd_handler_lri(struct parser_exec_state *s)
1047{
1048	int i, ret = 0;
1049	int cmd_len = cmd_length(s);
1050
1051	for (i = 1; i < cmd_len; i += 2) {
1052		if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1053			if (s->engine->id == BCS0 &&
1054			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1055				ret |= 0;
1056			else
1057				ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1058		}
1059		if (ret)
1060			break;
1061		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1062		if (ret)
1063			break;
1064	}
1065	return ret;
1066}
1067
1068static int cmd_handler_lrr(struct parser_exec_state *s)
1069{
1070	int i, ret = 0;
1071	int cmd_len = cmd_length(s);
1072
1073	for (i = 1; i < cmd_len; i += 2) {
1074		if (IS_BROADWELL(s->engine->i915))
1075			ret |= ((cmd_reg_inhibit(s, i) ||
1076				 (cmd_reg_inhibit(s, i + 1)))) ?
1077				-EBADRQC : 0;
1078		if (ret)
1079			break;
1080		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1081		if (ret)
1082			break;
1083		ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1084		if (ret)
1085			break;
1086	}
1087	return ret;
1088}
1089
1090static inline int cmd_address_audit(struct parser_exec_state *s,
1091		unsigned long guest_gma, int op_size, bool index_mode);
1092
1093static int cmd_handler_lrm(struct parser_exec_state *s)
1094{
1095	struct intel_gvt *gvt = s->vgpu->gvt;
1096	int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1097	unsigned long gma;
1098	int i, ret = 0;
1099	int cmd_len = cmd_length(s);
1100
1101	for (i = 1; i < cmd_len;) {
1102		if (IS_BROADWELL(s->engine->i915))
1103			ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1104		if (ret)
1105			break;
1106		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1107		if (ret)
1108			break;
1109		if (cmd_val(s, 0) & (1 << 22)) {
1110			gma = cmd_gma(s, i + 1);
1111			if (gmadr_bytes == 8)
1112				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1113			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1114			if (ret)
1115				break;
1116		}
1117		i += gmadr_dw_number(s) + 1;
1118	}
1119	return ret;
1120}
1121
1122static int cmd_handler_srm(struct parser_exec_state *s)
1123{
1124	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1125	unsigned long gma;
1126	int i, ret = 0;
1127	int cmd_len = cmd_length(s);
1128
1129	for (i = 1; i < cmd_len;) {
1130		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1131		if (ret)
1132			break;
1133		if (cmd_val(s, 0) & (1 << 22)) {
1134			gma = cmd_gma(s, i + 1);
1135			if (gmadr_bytes == 8)
1136				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1137			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1138			if (ret)
1139				break;
1140		}
1141		i += gmadr_dw_number(s) + 1;
1142	}
1143	return ret;
1144}
1145
1146struct cmd_interrupt_event {
1147	int pipe_control_notify;
1148	int mi_flush_dw;
1149	int mi_user_interrupt;
1150};
1151
1152static const struct cmd_interrupt_event cmd_interrupt_events[] = {
1153	[RCS0] = {
1154		.pipe_control_notify = RCS_PIPE_CONTROL,
1155		.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1156		.mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1157	},
1158	[BCS0] = {
1159		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1160		.mi_flush_dw = BCS_MI_FLUSH_DW,
1161		.mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1162	},
1163	[VCS0] = {
1164		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1165		.mi_flush_dw = VCS_MI_FLUSH_DW,
1166		.mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1167	},
1168	[VCS1] = {
1169		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1170		.mi_flush_dw = VCS2_MI_FLUSH_DW,
1171		.mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1172	},
1173	[VECS0] = {
1174		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1175		.mi_flush_dw = VECS_MI_FLUSH_DW,
1176		.mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1177	},
1178};
1179
1180static int cmd_handler_pipe_control(struct parser_exec_state *s)
1181{
1182	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1183	unsigned long gma;
1184	bool index_mode = false;
1185	unsigned int post_sync;
1186	int ret = 0;
1187	u32 hws_pga, val;
1188
1189	post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1190
1191	/* LRI post sync */
1192	if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1193		ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1194	/* post sync */
1195	else if (post_sync) {
1196		if (post_sync == 2)
1197			ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1198		else if (post_sync == 3)
1199			ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1200		else if (post_sync == 1) {
1201			/* check ggtt*/
1202			if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1203				gma = cmd_val(s, 2) & GENMASK(31, 3);
1204				if (gmadr_bytes == 8)
1205					gma |= (cmd_gma_hi(s, 3)) << 32;
1206				/* Store Data Index */
1207				if (cmd_val(s, 1) & (1 << 21))
1208					index_mode = true;
1209				ret |= cmd_address_audit(s, gma, sizeof(u64),
1210						index_mode);
1211				if (ret)
1212					return ret;
1213				if (index_mode) {
1214					hws_pga = s->vgpu->hws_pga[s->engine->id];
1215					gma = hws_pga + gma;
1216					patch_value(s, cmd_ptr(s, 2), gma);
1217					val = cmd_val(s, 1) & (~(1 << 21));
1218					patch_value(s, cmd_ptr(s, 1), val);
1219				}
1220			}
1221		}
1222	}
1223
1224	if (ret)
1225		return ret;
1226
1227	if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1228		set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1229			s->workload->pending_events);
1230	return 0;
1231}
1232
1233static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1234{
1235	set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1236		s->workload->pending_events);
1237	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1238	return 0;
1239}
1240
1241static int cmd_advance_default(struct parser_exec_state *s)
1242{
1243	return ip_gma_advance(s, cmd_length(s));
1244}
1245
1246static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1247{
1248	int ret;
1249
1250	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1251		s->buf_type = BATCH_BUFFER_INSTRUCTION;
1252		ret = ip_gma_set(s, s->ret_ip_gma_bb);
1253		s->buf_addr_type = s->saved_buf_addr_type;
1254	} else if (s->buf_type == RING_BUFFER_CTX) {
1255		ret = ip_gma_set(s, s->ring_tail);
1256	} else {
1257		s->buf_type = RING_BUFFER_INSTRUCTION;
1258		s->buf_addr_type = GTT_BUFFER;
1259		if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1260			s->ret_ip_gma_ring -= s->ring_size;
1261		ret = ip_gma_set(s, s->ret_ip_gma_ring);
1262	}
1263	return ret;
1264}
1265
1266struct mi_display_flip_command_info {
1267	int pipe;
1268	int plane;
1269	int event;
1270	i915_reg_t stride_reg;
1271	i915_reg_t ctrl_reg;
1272	i915_reg_t surf_reg;
1273	u64 stride_val;
1274	u64 tile_val;
1275	u64 surf_val;
1276	bool async_flip;
1277};
1278
1279struct plane_code_mapping {
1280	int pipe;
1281	int plane;
1282	int event;
1283};
1284
1285static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1286		struct mi_display_flip_command_info *info)
1287{
1288	struct drm_i915_private *dev_priv = s->engine->i915;
1289	struct plane_code_mapping gen8_plane_code[] = {
1290		[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1291		[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1292		[2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1293		[3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1294		[4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1295		[5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1296	};
1297	u32 dword0, dword1, dword2;
1298	u32 v;
1299
1300	dword0 = cmd_val(s, 0);
1301	dword1 = cmd_val(s, 1);
1302	dword2 = cmd_val(s, 2);
1303
1304	v = (dword0 & GENMASK(21, 19)) >> 19;
1305	if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1306		return -EBADRQC;
1307
1308	info->pipe = gen8_plane_code[v].pipe;
1309	info->plane = gen8_plane_code[v].plane;
1310	info->event = gen8_plane_code[v].event;
1311	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1312	info->tile_val = (dword1 & 0x1);
1313	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1314	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1315
1316	if (info->plane == PLANE_A) {
1317		info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1318		info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1319		info->surf_reg = DSPSURF(dev_priv, info->pipe);
1320	} else if (info->plane == PLANE_B) {
1321		info->ctrl_reg = SPRCTL(info->pipe);
1322		info->stride_reg = SPRSTRIDE(info->pipe);
1323		info->surf_reg = SPRSURF(info->pipe);
1324	} else {
1325		drm_WARN_ON(&dev_priv->drm, 1);
1326		return -EBADRQC;
1327	}
1328	return 0;
1329}
1330
1331static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1332		struct mi_display_flip_command_info *info)
1333{
1334	struct drm_i915_private *dev_priv = s->engine->i915;
1335	struct intel_vgpu *vgpu = s->vgpu;
1336	u32 dword0 = cmd_val(s, 0);
1337	u32 dword1 = cmd_val(s, 1);
1338	u32 dword2 = cmd_val(s, 2);
1339	u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1340
1341	info->plane = PRIMARY_PLANE;
1342
1343	switch (plane) {
1344	case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1345		info->pipe = PIPE_A;
1346		info->event = PRIMARY_A_FLIP_DONE;
1347		break;
1348	case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1349		info->pipe = PIPE_B;
1350		info->event = PRIMARY_B_FLIP_DONE;
1351		break;
1352	case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1353		info->pipe = PIPE_C;
1354		info->event = PRIMARY_C_FLIP_DONE;
1355		break;
1356
1357	case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1358		info->pipe = PIPE_A;
1359		info->event = SPRITE_A_FLIP_DONE;
1360		info->plane = SPRITE_PLANE;
1361		break;
1362	case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1363		info->pipe = PIPE_B;
1364		info->event = SPRITE_B_FLIP_DONE;
1365		info->plane = SPRITE_PLANE;
1366		break;
1367	case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1368		info->pipe = PIPE_C;
1369		info->event = SPRITE_C_FLIP_DONE;
1370		info->plane = SPRITE_PLANE;
1371		break;
1372
1373	default:
1374		gvt_vgpu_err("unknown plane code %d\n", plane);
1375		return -EBADRQC;
1376	}
1377
1378	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1379	info->tile_val = (dword1 & GENMASK(2, 0));
1380	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1381	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1382
1383	info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1384	info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1385	info->surf_reg = DSPSURF(dev_priv, info->pipe);
1386
1387	return 0;
1388}
1389
1390static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1391		struct mi_display_flip_command_info *info)
1392{
1393	u32 stride, tile;
1394
1395	if (!info->async_flip)
1396		return 0;
1397
1398	if (GRAPHICS_VER(s->engine->i915) >= 9) {
1399		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1400		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1401				GENMASK(12, 10)) >> 10;
1402	} else {
1403		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1404				GENMASK(15, 6)) >> 6;
1405		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1406	}
1407
1408	if (stride != info->stride_val)
1409		gvt_dbg_cmd("cannot change stride during async flip\n");
1410
1411	if (tile != info->tile_val)
1412		gvt_dbg_cmd("cannot change tile during async flip\n");
1413
1414	return 0;
1415}
1416
1417static int gen8_update_plane_mmio_from_mi_display_flip(
1418		struct parser_exec_state *s,
1419		struct mi_display_flip_command_info *info)
1420{
1421	struct drm_i915_private *dev_priv = s->engine->i915;
1422	struct intel_vgpu *vgpu = s->vgpu;
1423
1424	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1425		      info->surf_val << 12);
1426	if (GRAPHICS_VER(dev_priv) >= 9) {
1427		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1428			      info->stride_val);
1429		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1430			      info->tile_val << 10);
1431	} else {
1432		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1433			      info->stride_val << 6);
1434		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1435			      info->tile_val << 10);
1436	}
1437
1438	if (info->plane == PLANE_PRIMARY)
1439		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
1440
1441	if (info->async_flip)
1442		intel_vgpu_trigger_virtual_event(vgpu, info->event);
1443	else
1444		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1445
1446	return 0;
1447}
1448
1449static int decode_mi_display_flip(struct parser_exec_state *s,
1450		struct mi_display_flip_command_info *info)
1451{
1452	if (IS_BROADWELL(s->engine->i915))
1453		return gen8_decode_mi_display_flip(s, info);
1454	if (GRAPHICS_VER(s->engine->i915) >= 9)
1455		return skl_decode_mi_display_flip(s, info);
1456
1457	return -ENODEV;
1458}
1459
1460static int check_mi_display_flip(struct parser_exec_state *s,
1461		struct mi_display_flip_command_info *info)
1462{
1463	return gen8_check_mi_display_flip(s, info);
1464}
1465
1466static int update_plane_mmio_from_mi_display_flip(
1467		struct parser_exec_state *s,
1468		struct mi_display_flip_command_info *info)
1469{
1470	return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1471}
1472
1473static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1474{
1475	struct mi_display_flip_command_info info;
1476	struct intel_vgpu *vgpu = s->vgpu;
1477	int ret;
1478	int i;
1479	int len = cmd_length(s);
1480	u32 valid_len = CMD_LEN(1);
1481
1482	/* Flip Type == Stereo 3D Flip */
1483	if (DWORD_FIELD(2, 1, 0) == 2)
1484		valid_len++;
1485	ret = gvt_check_valid_cmd_length(cmd_length(s),
1486			valid_len);
1487	if (ret)
1488		return ret;
1489
1490	ret = decode_mi_display_flip(s, &info);
1491	if (ret) {
1492		gvt_vgpu_err("fail to decode MI display flip command\n");
1493		return ret;
1494	}
1495
1496	ret = check_mi_display_flip(s, &info);
1497	if (ret) {
1498		gvt_vgpu_err("invalid MI display flip command\n");
1499		return ret;
1500	}
1501
1502	ret = update_plane_mmio_from_mi_display_flip(s, &info);
1503	if (ret) {
1504		gvt_vgpu_err("fail to update plane mmio\n");
1505		return ret;
1506	}
1507
1508	for (i = 0; i < len; i++)
1509		patch_value(s, cmd_ptr(s, i), MI_NOOP);
1510	return 0;
1511}
1512
1513static bool is_wait_for_flip_pending(u32 cmd)
1514{
1515	return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1516			MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1517			MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1518			MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1519			MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1520			MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1521}
1522
1523static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1524{
1525	u32 cmd = cmd_val(s, 0);
1526
1527	if (!is_wait_for_flip_pending(cmd))
1528		return 0;
1529
1530	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1531	return 0;
1532}
1533
1534static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1535{
1536	unsigned long addr;
1537	unsigned long gma_high, gma_low;
1538	struct intel_vgpu *vgpu = s->vgpu;
1539	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1540
1541	if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1542		gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1543		return INTEL_GVT_INVALID_ADDR;
1544	}
1545
1546	gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1547	if (gmadr_bytes == 4) {
1548		addr = gma_low;
1549	} else {
1550		gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1551		addr = (((unsigned long)gma_high) << 32) | gma_low;
1552	}
1553	return addr;
1554}
1555
1556static inline int cmd_address_audit(struct parser_exec_state *s,
1557		unsigned long guest_gma, int op_size, bool index_mode)
1558{
1559	struct intel_vgpu *vgpu = s->vgpu;
1560	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1561	int i;
1562	int ret;
1563
1564	if (op_size > max_surface_size) {
1565		gvt_vgpu_err("command address audit fail name %s\n",
1566			s->info->name);
1567		return -EFAULT;
1568	}
1569
1570	if (index_mode)	{
1571		if (guest_gma >= I915_GTT_PAGE_SIZE) {
1572			ret = -EFAULT;
1573			goto err;
1574		}
1575	} else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1576		ret = -EFAULT;
1577		goto err;
1578	}
1579
1580	return 0;
1581
1582err:
1583	gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1584			s->info->name, guest_gma, op_size);
1585
1586	pr_err("cmd dump: ");
1587	for (i = 0; i < cmd_length(s); i++) {
1588		if (!(i % 4))
1589			pr_err("\n%08x ", cmd_val(s, i));
1590		else
1591			pr_err("%08x ", cmd_val(s, i));
1592	}
1593	pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1594			vgpu->id,
1595			vgpu_aperture_gmadr_base(vgpu),
1596			vgpu_aperture_gmadr_end(vgpu),
1597			vgpu_hidden_gmadr_base(vgpu),
1598			vgpu_hidden_gmadr_end(vgpu));
1599	return ret;
1600}
1601
1602static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1603{
1604	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1605	int op_size = (cmd_length(s) - 3) * sizeof(u32);
1606	int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1607	unsigned long gma, gma_low, gma_high;
1608	u32 valid_len = CMD_LEN(2);
1609	int ret = 0;
1610
1611	/* check ppggt */
1612	if (!(cmd_val(s, 0) & (1 << 22)))
1613		return 0;
1614
1615	/* check if QWORD */
1616	if (DWORD_FIELD(0, 21, 21))
1617		valid_len++;
1618	ret = gvt_check_valid_cmd_length(cmd_length(s),
1619			valid_len);
1620	if (ret)
1621		return ret;
1622
1623	gma = cmd_val(s, 2) & GENMASK(31, 2);
1624
1625	if (gmadr_bytes == 8) {
1626		gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1627		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1628		gma = (gma_high << 32) | gma_low;
1629		core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1630	}
1631	ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1632	return ret;
1633}
1634
1635static inline int unexpected_cmd(struct parser_exec_state *s)
1636{
1637	struct intel_vgpu *vgpu = s->vgpu;
1638
1639	gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1640
1641	return -EBADRQC;
1642}
1643
1644static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1645{
1646	return unexpected_cmd(s);
1647}
1648
1649static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1650{
1651	return unexpected_cmd(s);
1652}
1653
1654static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1655{
1656	return unexpected_cmd(s);
1657}
1658
1659static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1660{
1661	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1662	int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1663			sizeof(u32);
1664	unsigned long gma, gma_high;
1665	u32 valid_len = CMD_LEN(1);
1666	int ret = 0;
1667
1668	if (!(cmd_val(s, 0) & (1 << 22)))
1669		return ret;
1670
1671	/* check inline data */
1672	if (cmd_val(s, 0) & BIT(18))
1673		valid_len = CMD_LEN(9);
1674	ret = gvt_check_valid_cmd_length(cmd_length(s),
1675			valid_len);
1676	if (ret)
1677		return ret;
1678
1679	gma = cmd_val(s, 1) & GENMASK(31, 2);
1680	if (gmadr_bytes == 8) {
1681		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1682		gma = (gma_high << 32) | gma;
1683	}
1684	ret = cmd_address_audit(s, gma, op_size, false);
1685	return ret;
1686}
1687
1688static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1689{
1690	return unexpected_cmd(s);
1691}
1692
1693static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1694{
1695	return unexpected_cmd(s);
1696}
1697
1698static int cmd_handler_mi_conditional_batch_buffer_end(
1699		struct parser_exec_state *s)
1700{
1701	return unexpected_cmd(s);
1702}
1703
1704static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1705{
1706	return unexpected_cmd(s);
1707}
1708
1709static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1710{
1711	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1712	unsigned long gma;
1713	bool index_mode = false;
1714	int ret = 0;
1715	u32 hws_pga, val;
1716	u32 valid_len = CMD_LEN(2);
1717
1718	ret = gvt_check_valid_cmd_length(cmd_length(s),
1719			valid_len);
1720	if (ret) {
1721		/* Check again for Qword */
1722		ret = gvt_check_valid_cmd_length(cmd_length(s),
1723			++valid_len);
1724		return ret;
1725	}
1726
1727	/* Check post-sync and ppgtt bit */
1728	if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1729		gma = cmd_val(s, 1) & GENMASK(31, 3);
1730		if (gmadr_bytes == 8)
1731			gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1732		/* Store Data Index */
1733		if (cmd_val(s, 0) & (1 << 21))
1734			index_mode = true;
1735		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1736		if (ret)
1737			return ret;
1738		if (index_mode) {
1739			hws_pga = s->vgpu->hws_pga[s->engine->id];
1740			gma = hws_pga + gma;
1741			patch_value(s, cmd_ptr(s, 1), gma);
1742			val = cmd_val(s, 0) & (~(1 << 21));
1743			patch_value(s, cmd_ptr(s, 0), val);
1744		}
1745	}
1746	/* Check notify bit */
1747	if ((cmd_val(s, 0) & (1 << 8)))
1748		set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1749			s->workload->pending_events);
1750	return ret;
1751}
1752
1753static void addr_type_update_snb(struct parser_exec_state *s)
1754{
1755	if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1756			(BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1757		s->buf_addr_type = PPGTT_BUFFER;
1758	}
1759}
1760
1761
1762static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1763		unsigned long gma, unsigned long end_gma, void *va)
1764{
1765	unsigned long copy_len, offset;
1766	unsigned long len = 0;
1767	unsigned long gpa;
1768
1769	while (gma != end_gma) {
1770		gpa = intel_vgpu_gma_to_gpa(mm, gma);
1771		if (gpa == INTEL_GVT_INVALID_ADDR) {
1772			gvt_vgpu_err("invalid gma address: %lx\n", gma);
1773			return -EFAULT;
1774		}
1775
1776		offset = gma & (I915_GTT_PAGE_SIZE - 1);
1777
1778		copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1779			I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1780
1781		intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1782
1783		len += copy_len;
1784		gma += copy_len;
1785	}
1786	return len;
1787}
1788
1789
1790/*
1791 * Check whether a batch buffer needs to be scanned. Currently
1792 * the only criteria is based on privilege.
1793 */
1794static int batch_buffer_needs_scan(struct parser_exec_state *s)
1795{
1796	/* Decide privilege based on address space */
1797	if (cmd_val(s, 0) & BIT(8) &&
1798	    !(s->vgpu->scan_nonprivbb & s->engine->mask))
1799		return 0;
1800
1801	return 1;
1802}
1803
1804static const char *repr_addr_type(unsigned int type)
1805{
1806	return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1807}
1808
1809static int find_bb_size(struct parser_exec_state *s,
1810			unsigned long *bb_size,
1811			unsigned long *bb_end_cmd_offset)
1812{
1813	unsigned long gma = 0;
1814	const struct cmd_info *info;
1815	u32 cmd_len = 0;
1816	bool bb_end = false;
1817	struct intel_vgpu *vgpu = s->vgpu;
1818	u32 cmd;
1819	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1820		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1821
1822	*bb_size = 0;
1823	*bb_end_cmd_offset = 0;
1824
1825	/* get the start gm address of the batch buffer */
1826	gma = get_gma_bb_from_cmd(s, 1);
1827	if (gma == INTEL_GVT_INVALID_ADDR)
1828		return -EFAULT;
1829
1830	cmd = cmd_val(s, 0);
1831	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1832	if (info == NULL) {
1833		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1834			     cmd, get_opcode(cmd, s->engine),
1835			     repr_addr_type(s->buf_addr_type),
1836			     s->engine->name, s->workload);
1837		return -EBADRQC;
1838	}
1839	do {
1840		if (copy_gma_to_hva(s->vgpu, mm,
1841				    gma, gma + 4, &cmd) < 0)
1842			return -EFAULT;
1843		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1844		if (info == NULL) {
1845			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1846				     cmd, get_opcode(cmd, s->engine),
1847				     repr_addr_type(s->buf_addr_type),
1848				     s->engine->name, s->workload);
1849			return -EBADRQC;
1850		}
1851
1852		if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1853			bb_end = true;
1854		} else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1855			if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1856				/* chained batch buffer */
1857				bb_end = true;
1858		}
1859
1860		if (bb_end)
1861			*bb_end_cmd_offset = *bb_size;
1862
1863		cmd_len = get_cmd_length(info, cmd) << 2;
1864		*bb_size += cmd_len;
1865		gma += cmd_len;
1866	} while (!bb_end);
1867
1868	return 0;
1869}
1870
1871static int audit_bb_end(struct parser_exec_state *s, void *va)
1872{
1873	struct intel_vgpu *vgpu = s->vgpu;
1874	u32 cmd = *(u32 *)va;
1875	const struct cmd_info *info;
1876
1877	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1878	if (info == NULL) {
1879		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1880			     cmd, get_opcode(cmd, s->engine),
1881			     repr_addr_type(s->buf_addr_type),
1882			     s->engine->name, s->workload);
1883		return -EBADRQC;
1884	}
1885
1886	if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1887	    ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1888	     (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1889		return 0;
1890
1891	return -EBADRQC;
1892}
1893
1894static int perform_bb_shadow(struct parser_exec_state *s)
1895{
1896	struct intel_vgpu *vgpu = s->vgpu;
1897	struct intel_vgpu_shadow_bb *bb;
1898	unsigned long gma = 0;
1899	unsigned long bb_size;
1900	unsigned long bb_end_cmd_offset;
1901	int ret = 0;
1902	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1903		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1904	unsigned long start_offset = 0;
1905
1906	/* get the start gm address of the batch buffer */
1907	gma = get_gma_bb_from_cmd(s, 1);
1908	if (gma == INTEL_GVT_INVALID_ADDR)
1909		return -EFAULT;
1910
1911	ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1912	if (ret)
1913		return ret;
1914
1915	bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1916	if (!bb)
1917		return -ENOMEM;
1918
1919	bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1920
1921	/* the start_offset stores the batch buffer's start gma's
1922	 * offset relative to page boundary. so for non-privileged batch
1923	 * buffer, the shadowed gem object holds exactly the same page
1924	 * layout as original gem object. This is for the convience of
1925	 * replacing the whole non-privilged batch buffer page to this
1926	 * shadowed one in PPGTT at the same gma address. (this replacing
1927	 * action is not implemented yet now, but may be necessary in
1928	 * future).
1929	 * for prileged batch buffer, we just change start gma address to
1930	 * that of shadowed page.
1931	 */
1932	if (bb->ppgtt)
1933		start_offset = gma & ~I915_GTT_PAGE_MASK;
1934
1935	bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1936					       round_up(bb_size + start_offset,
1937							PAGE_SIZE));
1938	if (IS_ERR(bb->obj)) {
1939		ret = PTR_ERR(bb->obj);
1940		goto err_free_bb;
1941	}
1942
1943	bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1944	if (IS_ERR(bb->va)) {
1945		ret = PTR_ERR(bb->va);
1946		goto err_free_obj;
1947	}
1948
1949	ret = copy_gma_to_hva(s->vgpu, mm,
1950			      gma, gma + bb_size,
1951			      bb->va + start_offset);
1952	if (ret < 0) {
1953		gvt_vgpu_err("fail to copy guest ring buffer\n");
1954		ret = -EFAULT;
1955		goto err_unmap;
1956	}
1957
1958	ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1959	if (ret)
1960		goto err_unmap;
1961
1962	i915_gem_object_unlock(bb->obj);
1963	INIT_LIST_HEAD(&bb->list);
1964	list_add(&bb->list, &s->workload->shadow_bb);
1965
1966	bb->bb_start_cmd_va = s->ip_va;
1967
1968	if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1969		bb->bb_offset = s->ip_va - s->rb_va;
1970	else
1971		bb->bb_offset = 0;
1972
1973	/*
1974	 * ip_va saves the virtual address of the shadow batch buffer, while
1975	 * ip_gma saves the graphics address of the original batch buffer.
1976	 * As the shadow batch buffer is just a copy from the originial one,
1977	 * it should be right to use shadow batch buffer'va and original batch
1978	 * buffer's gma in pair. After all, we don't want to pin the shadow
1979	 * buffer here (too early).
1980	 */
1981	s->ip_va = bb->va + start_offset;
1982	s->ip_gma = gma;
1983	return 0;
1984err_unmap:
1985	i915_gem_object_unpin_map(bb->obj);
1986err_free_obj:
1987	i915_gem_object_put(bb->obj);
1988err_free_bb:
1989	kfree(bb);
1990	return ret;
1991}
1992
1993static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1994{
1995	bool second_level;
1996	int ret = 0;
1997	struct intel_vgpu *vgpu = s->vgpu;
1998
1999	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
2000		gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
2001		return -EFAULT;
2002	}
2003
2004	second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2005	if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2006		gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
2007		return -EFAULT;
2008	}
2009
2010	s->saved_buf_addr_type = s->buf_addr_type;
2011	addr_type_update_snb(s);
2012	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2013		s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2014		s->buf_type = BATCH_BUFFER_INSTRUCTION;
2015	} else if (second_level) {
2016		s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2017		s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2018		s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2019	}
2020
2021	if (batch_buffer_needs_scan(s)) {
2022		ret = perform_bb_shadow(s);
2023		if (ret < 0)
2024			gvt_vgpu_err("invalid shadow batch buffer\n");
2025	} else {
2026		/* emulate a batch buffer end to do return right */
2027		ret = cmd_handler_mi_batch_buffer_end(s);
2028		if (ret < 0)
2029			return ret;
2030	}
2031	return ret;
2032}
2033
2034static int mi_noop_index;
2035
2036static const struct cmd_info cmd_info[] = {
2037	{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2038
2039	{"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2040		0, 1, NULL},
2041
2042	{"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2043		0, 1, cmd_handler_mi_user_interrupt},
2044
2045	{"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2046		D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2047
2048	{"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2049
2050	{"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2051		NULL},
2052
2053	{"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2054		NULL},
2055
2056	{"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2057		NULL},
2058
2059	{"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2060		NULL},
2061
2062	{"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2063		D_ALL, 0, 1, NULL},
2064
2065	{"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2066		F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2067		cmd_handler_mi_batch_buffer_end},
2068
2069	{"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2070		0, 1, NULL},
2071
2072	{"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2073		NULL},
2074
2075	{"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2076		D_ALL, 0, 1, NULL},
2077
2078	{"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2079		NULL},
2080
2081	{"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2082		NULL},
2083
2084	{"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2085		R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2086
2087	{"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2088		R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2089
2090	{"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2091
2092	{"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2093		D_ALL, 0, 8, NULL, CMD_LEN(0)},
2094
2095	{"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2096		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2097		NULL, CMD_LEN(0)},
2098
2099	{"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2100		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2101		8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2102
2103	{"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2104		ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2105
2106	{"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2107		0, 8, cmd_handler_mi_store_data_index},
2108
2109	{"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2110		D_ALL, 0, 8, cmd_handler_lri},
2111
2112	{"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2113		cmd_handler_mi_update_gtt},
2114
2115	{"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2116		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2117		cmd_handler_srm, CMD_LEN(2)},
2118
2119	{"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2120		cmd_handler_mi_flush_dw},
2121
2122	{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2123		10, cmd_handler_mi_clflush},
2124
2125	{"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2126		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2127		cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2128
2129	{"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2130		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2131		cmd_handler_lrm, CMD_LEN(2)},
2132
2133	{"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2134		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2135		cmd_handler_lrr, CMD_LEN(1)},
2136
2137	{"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2138		F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2139		8, NULL, CMD_LEN(2)},
2140
2141	{"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2142		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2143
2144	{"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2145		ADDR_FIX_1(2), 8, NULL},
2146
2147	{"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2148		ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2149
2150	{"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2151		8, cmd_handler_mi_op_2f},
2152
2153	{"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2154		F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2155		cmd_handler_mi_batch_buffer_start},
2156
2157	{"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2158		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2159		cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2160
2161	{"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2162		R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2163
2164	{"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2165		ADDR_FIX_2(4, 7), 8, NULL},
2166
2167	{"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2168		0, 8, NULL},
2169
2170	{"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2171		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2172
2173	{"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2174
2175	{"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2176		0, 8, NULL},
2177
2178	{"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2179		ADDR_FIX_1(3), 8, NULL},
2180
2181	{"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2182		D_ALL, 0, 8, NULL},
2183
2184	{"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2185		ADDR_FIX_1(4), 8, NULL},
2186
2187	{"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2188		ADDR_FIX_2(4, 5), 8, NULL},
2189
2190	{"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2191		ADDR_FIX_1(4), 8, NULL},
2192
2193	{"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2194		ADDR_FIX_2(4, 7), 8, NULL},
2195
2196	{"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2197		D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2198
2199	{"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2200
2201	{"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2202		D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2203
2204	{"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2205		R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2206
2207	{"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2208		OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2209		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2210
2211	{"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2212		D_ALL, ADDR_FIX_1(4), 8, NULL},
2213
2214	{"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2215		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2216
2217	{"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2218		D_ALL, ADDR_FIX_1(4), 8, NULL},
2219
2220	{"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2221		D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2222
2223	{"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2224		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2225
2226	{"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2227		OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2228		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2229
2230	{"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2231		ADDR_FIX_2(4, 5), 8, NULL},
2232
2233	{"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2234		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2235
2236	{"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2237		OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2238		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240	{"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2241		OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2242		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2243
2244	{"3DSTATE_BLEND_STATE_POINTERS",
2245		OP_3DSTATE_BLEND_STATE_POINTERS,
2246		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248	{"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2249		OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2250		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2251
2252	{"3DSTATE_BINDING_TABLE_POINTERS_VS",
2253		OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2254		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2255
2256	{"3DSTATE_BINDING_TABLE_POINTERS_HS",
2257		OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2258		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2259
2260	{"3DSTATE_BINDING_TABLE_POINTERS_DS",
2261		OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2262		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263
2264	{"3DSTATE_BINDING_TABLE_POINTERS_GS",
2265		OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2266		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2267
2268	{"3DSTATE_BINDING_TABLE_POINTERS_PS",
2269		OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2270		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272	{"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2273		OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2274		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276	{"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2277		OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2278		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2279
2280	{"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2281		OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2282		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2283
2284	{"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2285		OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2286		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2287
2288	{"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2289		OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2290		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2291
2292	{"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2293		0, 8, NULL},
2294
2295	{"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2296		0, 8, NULL},
2297
2298	{"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2299		0, 8, NULL},
2300
2301	{"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2302		0, 8, NULL},
2303
2304	{"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2305		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2306
2307	{"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2308		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2309
2310	{"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2311		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2312
2313	{"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2314		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2315
2316	{"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2317		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2318
2319	{"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2320		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2321
2322	{"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2323		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2324
2325	{"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2326		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2327
2328	{"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2329		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2330
2331	{"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2332		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2333
2334	{"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2335		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2336
2337	{"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2338		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2339
2340	{"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2341		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2342
2343	{"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2344		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2345
2346	{"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2347		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2348
2349	{"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2350		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2351
2352	{"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2353		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2354
2355	{"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2356		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2357
2358	{"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2359		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2360
2361	{"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2362		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2363
2364	{"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2365		D_BDW_PLUS, 0, 8, NULL},
2366
2367	{"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2368		NULL},
2369
2370	{"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2371		D_BDW_PLUS, 0, 8, NULL},
2372
2373	{"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2374		D_BDW_PLUS, 0, 8, NULL},
2375
2376	{"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2377		8, NULL},
2378
2379	{"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2380		R_RCS, D_BDW_PLUS, 0, 8, NULL},
2381
2382	{"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2383		8, NULL},
2384
2385	{"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2386		NULL},
2387
2388	{"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2389		NULL},
2390
2391	{"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2392		NULL},
2393
2394	{"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2395		D_BDW_PLUS, 0, 8, NULL},
2396
2397	{"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2398		R_RCS, D_ALL, 0, 8, NULL},
2399
2400	{"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2401		D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2402
2403	{"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2404		R_RCS, D_ALL, 0, 1, NULL},
2405
2406	{"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2407
2408	{"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2409		R_RCS, D_ALL, 0, 8, NULL},
2410
2411	{"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2412		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2413
2414	{"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2415
2416	{"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2417
2418	{"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2419
2420	{"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2421		D_BDW_PLUS, 0, 8, NULL},
2422
2423	{"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2424		D_BDW_PLUS, 0, 8, NULL},
2425
2426	{"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2427		D_ALL, 0, 8, NULL},
2428
2429	{"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2430		D_BDW_PLUS, 0, 8, NULL},
2431
2432	{"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2433		D_BDW_PLUS, 0, 8, NULL},
2434
2435	{"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2436
2437	{"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2438
2439	{"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2440
2441	{"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2442		D_ALL, 0, 8, NULL},
2443
2444	{"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2445
2446	{"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2447
2448	{"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2449		R_RCS, D_ALL, 0, 8, NULL},
2450
2451	{"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2452		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2453
2454	{"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2455		0, 8, NULL},
2456
2457	{"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2458		D_ALL, ADDR_FIX_1(2), 8, NULL},
2459
2460	{"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2461		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2462
2463	{"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2464		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2465
2466	{"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2467		D_ALL, 0, 8, NULL},
2468
2469	{"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2470		D_ALL, 0, 8, NULL},
2471
2472	{"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2473		D_ALL, 0, 8, NULL},
2474
2475	{"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2476		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2477
2478	{"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2479		D_BDW_PLUS, 0, 8, NULL},
2480
2481	{"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2482		D_ALL, ADDR_FIX_1(2), 8, NULL},
2483
2484	{"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2485		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2486
2487	{"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2488		R_RCS, D_ALL, 0, 8, NULL},
2489
2490	{"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2491		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2492
2493	{"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2494		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2495
2496	{"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2497		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2498
2499	{"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2500		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2501
2502	{"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2503		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2504
2505	{"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2506		R_RCS, D_ALL, 0, 8, NULL},
2507
2508	{"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2509		D_ALL, 0, 9, NULL},
2510
2511	{"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2512		ADDR_FIX_2(2, 4), 8, NULL},
2513
2514	{"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2515		OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2516		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2517
2518	{"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2519		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2520
2521	{"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2522		OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2523		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2524
2525	{"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2526		D_BDW_PLUS, 0, 8, NULL},
2527
2528	{"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2529		ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2530
2531	{"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2532
2533	{"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2534		1, NULL},
2535
2536	{"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2537		ADDR_FIX_1(1), 8, NULL},
2538
2539	{"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2540
2541	{"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2542		ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2543
2544	{"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2545		ADDR_FIX_1(1), 8, NULL},
2546
2547	{"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2548		F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2549
2550	{"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2551
2552	{"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2553
2554	{"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2555		0, 8, NULL},
2556
2557	{"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2558		D_SKL_PLUS, 0, 8, NULL},
2559
2560	{"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2561		F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2562
2563	{"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2564		0, 16, NULL},
2565
2566	{"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2567		0, 16, NULL},
2568
2569	{"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2570		0, 16, NULL},
2571
2572	{"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2573
2574	{"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2575		0, 16, NULL},
2576
2577	{"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2578		0, 16, NULL},
2579
2580	{"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2581		0, 16, NULL},
2582
2583	{"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2584		0, 8, NULL},
2585
2586	{"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2587		NULL},
2588
2589	{"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2590		F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2591
2592	{"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2593		R_VCS, D_ALL, 0, 12, NULL},
2594
2595	{"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2596		R_VCS, D_ALL, 0, 12, NULL},
2597
2598	{"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2599		R_VCS, D_BDW_PLUS, 0, 12, NULL},
2600
2601	{"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2602		F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2603
2604	{"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2605		F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2606
2607	{"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2608
2609	{"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2610		R_VCS, D_ALL, 0, 12, NULL},
2611
2612	{"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2613		R_VCS, D_ALL, 0, 12, NULL},
2614
2615	{"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2616		R_VCS, D_ALL, 0, 12, NULL},
2617
2618	{"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2619		R_VCS, D_ALL, 0, 12, NULL},
2620
2621	{"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2622		R_VCS, D_ALL, 0, 12, NULL},
2623
2624	{"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2625		R_VCS, D_ALL, 0, 12, NULL},
2626
2627	{"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2628		R_VCS, D_ALL, 0, 6, NULL},
2629
2630	{"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2631		R_VCS, D_ALL, 0, 12, NULL},
2632
2633	{"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2634		R_VCS, D_ALL, 0, 12, NULL},
2635
2636	{"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2637		R_VCS, D_ALL, 0, 12, NULL},
2638
2639	{"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2640		R_VCS, D_ALL, 0, 12, NULL},
2641
2642	{"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2643		R_VCS, D_ALL, 0, 12, NULL},
2644
2645	{"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2646		R_VCS, D_ALL, 0, 12, NULL},
2647
2648	{"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2649		R_VCS, D_ALL, 0, 12, NULL},
2650	{"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2651		R_VCS, D_ALL, 0, 12, NULL},
2652
2653	{"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2654		R_VCS, D_ALL, 0, 12, NULL},
2655
2656	{"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2657		R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2658
2659	{"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2660		R_VCS, D_ALL, 0, 12, NULL},
2661
2662	{"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2663		R_VCS, D_ALL, 0, 12, NULL},
2664
2665	{"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2666		R_VCS, D_ALL, 0, 12, NULL},
2667
2668	{"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2669		R_VCS, D_ALL, 0, 12, NULL},
2670
2671	{"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2672		R_VCS, D_ALL, 0, 12, NULL},
2673
2674	{"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2675		R_VCS, D_ALL, 0, 12, NULL},
2676
2677	{"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2678		R_VCS, D_ALL, 0, 12, NULL},
2679
2680	{"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2681		R_VCS, D_ALL, 0, 12, NULL},
2682
2683	{"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2684		R_VCS, D_ALL, 0, 12, NULL},
2685
2686	{"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2687		R_VCS, D_ALL, 0, 12, NULL},
2688
2689	{"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2690		R_VCS, D_ALL, 0, 12, NULL},
2691
2692	{"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2693		0, 16, NULL},
2694
2695	{"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2696
2697	{"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2698
2699	{"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2700		R_VCS, D_ALL, 0, 12, NULL},
2701
2702	{"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2703		R_VCS, D_ALL, 0, 12, NULL},
2704
2705	{"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2706		R_VCS, D_ALL, 0, 12, NULL},
2707
2708	{"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2709
2710	{"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2711		0, 12, NULL},
2712
2713	{"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2714		0, 12, NULL},
2715};
2716
2717static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2718{
2719	hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2720}
2721
2722/* call the cmd handler, and advance ip */
2723static int cmd_parser_exec(struct parser_exec_state *s)
2724{
2725	struct intel_vgpu *vgpu = s->vgpu;
2726	const struct cmd_info *info;
2727	u32 cmd;
2728	int ret = 0;
2729
2730	cmd = cmd_val(s, 0);
2731
2732	/* fastpath for MI_NOOP */
2733	if (cmd == MI_NOOP)
2734		info = &cmd_info[mi_noop_index];
2735	else
2736		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2737
2738	if (info == NULL) {
2739		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2740			     cmd, get_opcode(cmd, s->engine),
2741			     repr_addr_type(s->buf_addr_type),
2742			     s->engine->name, s->workload);
2743		return -EBADRQC;
2744	}
2745
2746	s->info = info;
2747
2748	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2749			  cmd_length(s), s->buf_type, s->buf_addr_type,
2750			  s->workload, info->name);
2751
2752	if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2753		ret = gvt_check_valid_cmd_length(cmd_length(s),
2754						 info->valid_len);
2755		if (ret)
2756			return ret;
2757	}
2758
2759	if (info->handler) {
2760		ret = info->handler(s);
2761		if (ret < 0) {
2762			gvt_vgpu_err("%s handler error\n", info->name);
2763			return ret;
2764		}
2765	}
2766
2767	if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2768		ret = cmd_advance_default(s);
2769		if (ret) {
2770			gvt_vgpu_err("%s IP advance error\n", info->name);
2771			return ret;
2772		}
2773	}
2774	return 0;
2775}
2776
2777static inline bool gma_out_of_range(unsigned long gma,
2778		unsigned long gma_head, unsigned int gma_tail)
2779{
2780	if (gma_tail >= gma_head)
2781		return (gma < gma_head) || (gma > gma_tail);
2782	else
2783		return (gma > gma_tail) && (gma < gma_head);
2784}
2785
2786/* Keep the consistent return type, e.g EBADRQC for unknown
2787 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2788 * works as the input of VM healthy status.
2789 */
2790static int command_scan(struct parser_exec_state *s,
2791		unsigned long rb_head, unsigned long rb_tail,
2792		unsigned long rb_start, unsigned long rb_len)
2793{
2794
2795	unsigned long gma_head, gma_tail, gma_bottom;
2796	int ret = 0;
2797	struct intel_vgpu *vgpu = s->vgpu;
2798
2799	gma_head = rb_start + rb_head;
2800	gma_tail = rb_start + rb_tail;
2801	gma_bottom = rb_start +  rb_len;
2802
2803	while (s->ip_gma != gma_tail) {
2804		if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2805				s->buf_type == RING_BUFFER_CTX) {
2806			if (!(s->ip_gma >= rb_start) ||
2807				!(s->ip_gma < gma_bottom)) {
2808				gvt_vgpu_err("ip_gma %lx out of ring scope."
2809					"(base:0x%lx, bottom: 0x%lx)\n",
2810					s->ip_gma, rb_start,
2811					gma_bottom);
2812				parser_exec_state_dump(s);
2813				return -EFAULT;
2814			}
2815			if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2816				gvt_vgpu_err("ip_gma %lx out of range."
2817					"base 0x%lx head 0x%lx tail 0x%lx\n",
2818					s->ip_gma, rb_start,
2819					rb_head, rb_tail);
2820				parser_exec_state_dump(s);
2821				break;
2822			}
2823		}
2824		ret = cmd_parser_exec(s);
2825		if (ret) {
2826			gvt_vgpu_err("cmd parser error\n");
2827			parser_exec_state_dump(s);
2828			break;
2829		}
2830	}
2831
2832	return ret;
2833}
2834
2835static int scan_workload(struct intel_vgpu_workload *workload)
2836{
2837	unsigned long gma_head, gma_tail;
2838	struct parser_exec_state s;
2839	int ret = 0;
2840
2841	/* ring base is page aligned */
2842	if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2843		return -EINVAL;
2844
2845	gma_head = workload->rb_start + workload->rb_head;
2846	gma_tail = workload->rb_start + workload->rb_tail;
2847
2848	s.buf_type = RING_BUFFER_INSTRUCTION;
2849	s.buf_addr_type = GTT_BUFFER;
2850	s.vgpu = workload->vgpu;
2851	s.engine = workload->engine;
2852	s.ring_start = workload->rb_start;
2853	s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2854	s.ring_head = gma_head;
2855	s.ring_tail = gma_tail;
2856	s.rb_va = workload->shadow_ring_buffer_va;
2857	s.workload = workload;
2858	s.is_ctx_wa = false;
2859
2860	if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2861		return 0;
2862
2863	ret = ip_gma_set(&s, gma_head);
2864	if (ret)
2865		goto out;
2866
2867	ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2868		workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2869
2870out:
2871	return ret;
2872}
2873
2874static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2875{
2876
2877	unsigned long gma_head, gma_tail, ring_size, ring_tail;
2878	struct parser_exec_state s;
2879	int ret = 0;
2880	struct intel_vgpu_workload *workload = container_of(wa_ctx,
2881				struct intel_vgpu_workload,
2882				wa_ctx);
2883
2884	/* ring base is page aligned */
2885	if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2886					I915_GTT_PAGE_SIZE)))
2887		return -EINVAL;
2888
2889	ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2890	ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2891			PAGE_SIZE);
2892	gma_head = wa_ctx->indirect_ctx.guest_gma;
2893	gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2894
2895	s.buf_type = RING_BUFFER_INSTRUCTION;
2896	s.buf_addr_type = GTT_BUFFER;
2897	s.vgpu = workload->vgpu;
2898	s.engine = workload->engine;
2899	s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2900	s.ring_size = ring_size;
2901	s.ring_head = gma_head;
2902	s.ring_tail = gma_tail;
2903	s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2904	s.workload = workload;
2905	s.is_ctx_wa = true;
2906
2907	ret = ip_gma_set(&s, gma_head);
2908	if (ret)
2909		goto out;
2910
2911	ret = command_scan(&s, 0, ring_tail,
2912		wa_ctx->indirect_ctx.guest_gma, ring_size);
2913out:
2914	return ret;
2915}
2916
2917static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2918{
2919	struct intel_vgpu *vgpu = workload->vgpu;
2920	struct intel_vgpu_submission *s = &vgpu->submission;
2921	unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2922	void *shadow_ring_buffer_va;
2923	int ret;
2924
2925	guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2926
2927	/* calculate workload ring buffer size */
2928	workload->rb_len = (workload->rb_tail + guest_rb_size -
2929			workload->rb_head) % guest_rb_size;
2930
2931	gma_head = workload->rb_start + workload->rb_head;
2932	gma_tail = workload->rb_start + workload->rb_tail;
2933	gma_top = workload->rb_start + guest_rb_size;
2934
2935	if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2936		void *p;
2937
2938		/* realloc the new ring buffer if needed */
2939		p = krealloc(s->ring_scan_buffer[workload->engine->id],
2940			     workload->rb_len, GFP_KERNEL);
2941		if (!p) {
2942			gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2943			return -ENOMEM;
2944		}
2945		s->ring_scan_buffer[workload->engine->id] = p;
2946		s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2947	}
2948
2949	shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2950
2951	/* get shadow ring buffer va */
2952	workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2953
2954	/* head > tail --> copy head <-> top */
2955	if (gma_head > gma_tail) {
2956		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2957				      gma_head, gma_top, shadow_ring_buffer_va);
2958		if (ret < 0) {
2959			gvt_vgpu_err("fail to copy guest ring buffer\n");
2960			return ret;
2961		}
2962		shadow_ring_buffer_va += ret;
2963		gma_head = workload->rb_start;
2964	}
2965
2966	/* copy head or start <-> tail */
2967	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2968				shadow_ring_buffer_va);
2969	if (ret < 0) {
2970		gvt_vgpu_err("fail to copy guest ring buffer\n");
2971		return ret;
2972	}
2973	return 0;
2974}
2975
2976int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2977{
2978	int ret;
2979	struct intel_vgpu *vgpu = workload->vgpu;
2980
2981	ret = shadow_workload_ring_buffer(workload);
2982	if (ret) {
2983		gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2984		return ret;
2985	}
2986
2987	ret = scan_workload(workload);
2988	if (ret) {
2989		gvt_vgpu_err("scan workload error\n");
2990		return ret;
2991	}
2992	return 0;
2993}
2994
2995static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2996{
2997	int ctx_size = wa_ctx->indirect_ctx.size;
2998	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2999	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3000					struct intel_vgpu_workload,
3001					wa_ctx);
3002	struct intel_vgpu *vgpu = workload->vgpu;
3003	struct drm_i915_gem_object *obj;
3004	int ret = 0;
3005	void *map;
3006
3007	obj = i915_gem_object_create_shmem(workload->engine->i915,
3008					   roundup(ctx_size + CACHELINE_BYTES,
3009						   PAGE_SIZE));
3010	if (IS_ERR(obj))
3011		return PTR_ERR(obj);
3012
3013	/* get the va of the shadow batch buffer */
3014	map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3015	if (IS_ERR(map)) {
3016		gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3017		ret = PTR_ERR(map);
3018		goto put_obj;
3019	}
3020
3021	i915_gem_object_lock(obj, NULL);
3022	ret = i915_gem_object_set_to_cpu_domain(obj, false);
3023	i915_gem_object_unlock(obj);
3024	if (ret) {
3025		gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3026		goto unmap_src;
3027	}
3028
3029	ret = copy_gma_to_hva(workload->vgpu,
3030				workload->vgpu->gtt.ggtt_mm,
3031				guest_gma, guest_gma + ctx_size,
3032				map);
3033	if (ret < 0) {
3034		gvt_vgpu_err("fail to copy guest indirect ctx\n");
3035		goto unmap_src;
3036	}
3037
3038	wa_ctx->indirect_ctx.obj = obj;
3039	wa_ctx->indirect_ctx.shadow_va = map;
3040	return 0;
3041
3042unmap_src:
3043	i915_gem_object_unpin_map(obj);
3044put_obj:
3045	i915_gem_object_put(obj);
3046	return ret;
3047}
3048
3049static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3050{
3051	u32 per_ctx_start[CACHELINE_DWORDS] = {};
3052	unsigned char *bb_start_sva;
3053
3054	if (!wa_ctx->per_ctx.valid)
3055		return 0;
3056
3057	per_ctx_start[0] = 0x18800001;
3058	per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3059
3060	bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3061				wa_ctx->indirect_ctx.size;
3062
3063	memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3064
3065	return 0;
3066}
3067
3068int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3069{
3070	int ret;
3071	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3072					struct intel_vgpu_workload,
3073					wa_ctx);
3074	struct intel_vgpu *vgpu = workload->vgpu;
3075
3076	if (wa_ctx->indirect_ctx.size == 0)
3077		return 0;
3078
3079	ret = shadow_indirect_ctx(wa_ctx);
3080	if (ret) {
3081		gvt_vgpu_err("fail to shadow indirect ctx\n");
3082		return ret;
3083	}
3084
3085	combine_wa_ctx(wa_ctx);
3086
3087	ret = scan_wa_ctx(wa_ctx);
3088	if (ret) {
3089		gvt_vgpu_err("scan wa ctx error\n");
3090		return ret;
3091	}
3092
3093	return 0;
3094}
3095
3096/* generate dummy contexts by sending empty requests to HW, and let
3097 * the HW to fill Engine Contexts. This dummy contexts are used for
3098 * initialization purpose (update reg whitelist), so referred to as
3099 * init context here
3100 */
3101void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3102{
3103	const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3104	struct intel_gvt *gvt = vgpu->gvt;
3105	struct intel_engine_cs *engine;
3106	enum intel_engine_id id;
3107
3108	if (gvt->is_reg_whitelist_updated)
3109		return;
3110
3111	/* scan init ctx to update cmd accessible list */
3112	for_each_engine(engine, gvt->gt, id) {
3113		struct parser_exec_state s;
3114		void *vaddr;
3115		int ret;
3116
3117		if (!engine->default_state)
3118			continue;
3119
3120		vaddr = shmem_pin_map(engine->default_state);
3121		if (!vaddr) {
3122			gvt_err("failed to map %s->default state\n",
3123				engine->name);
3124			return;
3125		}
3126
3127		s.buf_type = RING_BUFFER_CTX;
3128		s.buf_addr_type = GTT_BUFFER;
3129		s.vgpu = vgpu;
3130		s.engine = engine;
3131		s.ring_start = 0;
3132		s.ring_size = engine->context_size - start;
3133		s.ring_head = 0;
3134		s.ring_tail = s.ring_size;
3135		s.rb_va = vaddr + start;
3136		s.workload = NULL;
3137		s.is_ctx_wa = false;
3138		s.is_init_ctx = true;
3139
3140		/* skipping the first RING_CTX_SIZE(0x50) dwords */
3141		ret = ip_gma_set(&s, RING_CTX_SIZE);
3142		if (ret == 0) {
3143			ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3144			if (ret)
3145				gvt_err("Scan init ctx error\n");
3146		}
3147
3148		shmem_unpin_map(engine->default_state, vaddr);
3149		if (ret)
3150			return;
3151	}
3152
3153	gvt->is_reg_whitelist_updated = true;
3154}
3155
3156int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3157{
3158	struct intel_vgpu *vgpu = workload->vgpu;
3159	unsigned long gma_head, gma_tail, gma_start, ctx_size;
3160	struct parser_exec_state s;
3161	int ring_id = workload->engine->id;
3162	struct intel_context *ce = vgpu->submission.shadow[ring_id];
3163	int ret;
3164
3165	GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3166
3167	ctx_size = workload->engine->context_size - PAGE_SIZE;
3168
3169	/* Only ring contxt is loaded to HW for inhibit context, no need to
3170	 * scan engine context
3171	 */
3172	if (is_inhibit_context(ce))
3173		return 0;
3174
3175	gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3176	gma_head = 0;
3177	gma_tail = ctx_size;
3178
3179	s.buf_type = RING_BUFFER_CTX;
3180	s.buf_addr_type = GTT_BUFFER;
3181	s.vgpu = workload->vgpu;
3182	s.engine = workload->engine;
3183	s.ring_start = gma_start;
3184	s.ring_size = ctx_size;
3185	s.ring_head = gma_start + gma_head;
3186	s.ring_tail = gma_start + gma_tail;
3187	s.rb_va = ce->lrc_reg_state;
3188	s.workload = workload;
3189	s.is_ctx_wa = false;
3190	s.is_init_ctx = false;
3191
3192	/* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3193	 * context
3194	 */
3195	ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3196	if (ret)
3197		goto out;
3198
3199	ret = command_scan(&s, gma_head, gma_tail,
3200		gma_start, ctx_size);
3201out:
3202	if (ret)
3203		gvt_vgpu_err("scan shadow ctx error\n");
3204
3205	return ret;
3206}
3207
3208static int init_cmd_table(struct intel_gvt *gvt)
3209{
3210	unsigned int gen_type = intel_gvt_get_device_type(gvt);
3211	int i;
3212
3213	for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3214		struct cmd_entry *e;
3215
3216		if (!(cmd_info[i].devices & gen_type))
3217			continue;
3218
3219		e = kzalloc(sizeof(*e), GFP_KERNEL);
3220		if (!e)
3221			return -ENOMEM;
3222
3223		e->info = &cmd_info[i];
3224		if (cmd_info[i].opcode == OP_MI_NOOP)
3225			mi_noop_index = i;
3226
3227		INIT_HLIST_NODE(&e->hlist);
3228		add_cmd_entry(gvt, e);
3229		gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3230			    e->info->name, e->info->opcode, e->info->flag,
3231			    e->info->devices, e->info->rings);
3232	}
3233
3234	return 0;
3235}
3236
3237static void clean_cmd_table(struct intel_gvt *gvt)
3238{
3239	struct hlist_node *tmp;
3240	struct cmd_entry *e;
3241	int i;
3242
3243	hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3244		kfree(e);
3245
3246	hash_init(gvt->cmd_table);
3247}
3248
3249void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3250{
3251	clean_cmd_table(gvt);
3252}
3253
3254int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3255{
3256	int ret;
3257
3258	ret = init_cmd_table(gvt);
3259	if (ret) {
3260		intel_gvt_clean_cmd_parser(gvt);
3261		return ret;
3262	}
3263	return 0;
3264}