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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2008-2021 Intel Corporation
4 */
5
6#include <drm/drm_cache.h>
7
8#include "gem/i915_gem_internal.h"
9
10#include "gen2_engine_cs.h"
11#include "gen6_engine_cs.h"
12#include "gen6_ppgtt.h"
13#include "gen7_renderclear.h"
14#include "i915_drv.h"
15#include "i915_irq.h"
16#include "i915_mitigations.h"
17#include "i915_reg.h"
18#include "intel_breadcrumbs.h"
19#include "intel_context.h"
20#include "intel_engine_regs.h"
21#include "intel_gt.h"
22#include "intel_gt_irq.h"
23#include "intel_gt_regs.h"
24#include "intel_reset.h"
25#include "intel_ring.h"
26#include "shmem_utils.h"
27#include "intel_engine_heartbeat.h"
28#include "intel_engine_pm.h"
29
30/* Rough estimate of the typical request size, performing a flush,
31 * set-context and then emitting the batch.
32 */
33#define LEGACY_REQUEST_SIZE 200
34
35static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
36{
37 /*
38 * Keep the render interrupt unmasked as this papers over
39 * lost interrupts following a reset.
40 */
41 if (engine->class == RENDER_CLASS) {
42 if (GRAPHICS_VER(engine->i915) >= 6)
43 mask &= ~BIT(0);
44 else
45 mask &= ~I915_USER_INTERRUPT;
46 }
47
48 intel_engine_set_hwsp_writemask(engine, mask);
49}
50
51static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
52{
53 u32 addr;
54
55 addr = lower_32_bits(phys);
56 if (GRAPHICS_VER(engine->i915) >= 4)
57 addr |= (phys >> 28) & 0xf0;
58
59 intel_uncore_write(engine->uncore, HWS_PGA, addr);
60}
61
62static struct page *status_page(struct intel_engine_cs *engine)
63{
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
65
66 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
67 return sg_page(obj->mm.pages->sgl);
68}
69
70static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
71{
72 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
73 set_hwstam(engine, ~0u);
74}
75
76static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
77{
78 i915_reg_t hwsp;
79
80 /*
81 * The ring status page addresses are no longer next to the rest of
82 * the ring registers as of gen7.
83 */
84 if (GRAPHICS_VER(engine->i915) == 7) {
85 switch (engine->id) {
86 /*
87 * No more rings exist on Gen7. Default case is only to shut up
88 * gcc switch check warning.
89 */
90 default:
91 GEM_BUG_ON(engine->id);
92 fallthrough;
93 case RCS0:
94 hwsp = RENDER_HWS_PGA_GEN7;
95 break;
96 case BCS0:
97 hwsp = BLT_HWS_PGA_GEN7;
98 break;
99 case VCS0:
100 hwsp = BSD_HWS_PGA_GEN7;
101 break;
102 case VECS0:
103 hwsp = VEBOX_HWS_PGA_GEN7;
104 break;
105 }
106 } else if (GRAPHICS_VER(engine->i915) == 6) {
107 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
108 } else {
109 hwsp = RING_HWS_PGA(engine->mmio_base);
110 }
111
112 intel_uncore_write_fw(engine->uncore, hwsp, offset);
113 intel_uncore_posting_read_fw(engine->uncore, hwsp);
114}
115
116static void flush_cs_tlb(struct intel_engine_cs *engine)
117{
118 if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
119 return;
120
121 /* ring should be idle before issuing a sync flush*/
122 if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
123 drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
124 engine->name);
125
126 ENGINE_WRITE_FW(engine, RING_INSTPM,
127 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
128 INSTPM_SYNC_FLUSH));
129 if (__intel_wait_for_register_fw(engine->uncore,
130 RING_INSTPM(engine->mmio_base),
131 INSTPM_SYNC_FLUSH, 0,
132 2000, 0, NULL))
133 ENGINE_TRACE(engine,
134 "wait for SyncFlush to complete for TLB invalidation timed out\n");
135}
136
137static void ring_setup_status_page(struct intel_engine_cs *engine)
138{
139 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
140 set_hwstam(engine, ~0u);
141
142 flush_cs_tlb(engine);
143}
144
145static struct i915_address_space *vm_alias(struct i915_address_space *vm)
146{
147 if (i915_is_ggtt(vm))
148 vm = &i915_vm_to_ggtt(vm)->alias->vm;
149
150 return vm;
151}
152
153static u32 pp_dir(struct i915_address_space *vm)
154{
155 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir;
156}
157
158static void set_pp_dir(struct intel_engine_cs *engine)
159{
160 struct i915_address_space *vm = vm_alias(engine->gt->vm);
161
162 if (!vm)
163 return;
164
165 ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
166 ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
167
168 if (GRAPHICS_VER(engine->i915) >= 7) {
169 ENGINE_WRITE_FW(engine,
170 RING_MODE_GEN7,
171 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
172 }
173}
174
175static bool stop_ring(struct intel_engine_cs *engine)
176{
177 /* Empty the ring by skipping to the end */
178 ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
179 ENGINE_POSTING_READ(engine, RING_HEAD);
180
181 /* The ring must be empty before it is disabled */
182 ENGINE_WRITE_FW(engine, RING_CTL, 0);
183 ENGINE_POSTING_READ(engine, RING_CTL);
184
185 /* Then reset the disabled ring */
186 ENGINE_WRITE_FW(engine, RING_HEAD, 0);
187 ENGINE_WRITE_FW(engine, RING_TAIL, 0);
188
189 return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
190}
191
192static int xcs_resume(struct intel_engine_cs *engine)
193{
194 struct intel_ring *ring = engine->legacy.ring;
195 ktime_t kt;
196
197 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
198 ring->head, ring->tail);
199
200 /*
201 * Double check the ring is empty & disabled before we resume. Called
202 * from atomic context during PCI probe, so _hardirq().
203 */
204 intel_synchronize_hardirq(engine->i915);
205 if (!stop_ring(engine))
206 goto err;
207
208 if (HWS_NEEDS_PHYSICAL(engine->i915))
209 ring_setup_phys_status_page(engine);
210 else
211 ring_setup_status_page(engine);
212
213 intel_breadcrumbs_reset(engine->breadcrumbs);
214
215 /* Enforce ordering by reading HEAD register back */
216 ENGINE_POSTING_READ(engine, RING_HEAD);
217
218 /*
219 * Initialize the ring. This must happen _after_ we've cleared the ring
220 * registers with the above sequence (the readback of the HEAD registers
221 * also enforces ordering), otherwise the hw might lose the new ring
222 * register values.
223 */
224 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));
225
226 /* Check that the ring offsets point within the ring! */
227 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
228 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
229 intel_ring_update_space(ring);
230
231 set_pp_dir(engine);
232
233 /* First wake the ring up to an empty/idle ring */
234 for ((kt) = ktime_get() + (2 * NSEC_PER_MSEC);
235 ktime_before(ktime_get(), (kt)); cpu_relax()) {
236 /*
237 * In case of resets fails because engine resumes from
238 * incorrect RING_HEAD and then GPU may be then fed
239 * to invalid instrcutions, which may lead to unrecoverable
240 * hang. So at first write doesn't succeed then try again.
241 */
242 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);
243 if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head)
244 break;
245 }
246
247 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);
248 if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) {
249 ENGINE_TRACE(engine, "failed to reset empty ring: [%x, %x]: %x\n",
250 ENGINE_READ_FW(engine, RING_HEAD),
251 ENGINE_READ_FW(engine, RING_TAIL),
252 ring->head);
253 goto err;
254 }
255
256 ENGINE_WRITE_FW(engine, RING_CTL,
257 RING_CTL_SIZE(ring->size) | RING_VALID);
258
259 /* If the head is still not zero, the ring is dead */
260 if (__intel_wait_for_register_fw(engine->uncore,
261 RING_CTL(engine->mmio_base),
262 RING_VALID, RING_VALID,
263 5000, 0, NULL)) {
264 ENGINE_TRACE(engine, "failed to restart\n");
265 goto err;
266 }
267
268 if (GRAPHICS_VER(engine->i915) > 2) {
269 ENGINE_WRITE_FW(engine,
270 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
271 ENGINE_POSTING_READ(engine, RING_MI_MODE);
272 }
273
274 /* Now awake, let it get started */
275 if (ring->tail != ring->head) {
276 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);
277 ENGINE_POSTING_READ(engine, RING_TAIL);
278 }
279
280 /* Papering over lost _interrupts_ immediately following the restart */
281 intel_engine_signal_breadcrumbs(engine);
282 return 0;
283
284err:
285 drm_err(&engine->i915->drm,
286 "%s initialization failed; "
287 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
288 engine->name,
289 ENGINE_READ(engine, RING_CTL),
290 ENGINE_READ(engine, RING_CTL) & RING_VALID,
291 ENGINE_READ(engine, RING_HEAD), ring->head,
292 ENGINE_READ(engine, RING_TAIL), ring->tail,
293 ENGINE_READ(engine, RING_START),
294 i915_ggtt_offset(ring->vma));
295 return -EIO;
296}
297
298static void sanitize_hwsp(struct intel_engine_cs *engine)
299{
300 struct intel_timeline *tl;
301
302 list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
303 intel_timeline_reset_seqno(tl);
304}
305
306static void xcs_sanitize(struct intel_engine_cs *engine)
307{
308 /*
309 * Poison residual state on resume, in case the suspend didn't!
310 *
311 * We have to assume that across suspend/resume (or other loss
312 * of control) that the contents of our pinned buffers has been
313 * lost, replaced by garbage. Since this doesn't always happen,
314 * let's poison such state so that we more quickly spot when
315 * we falsely assume it has been preserved.
316 */
317 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
318 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
319
320 /*
321 * The kernel_context HWSP is stored in the status_page. As above,
322 * that may be lost on resume/initialisation, and so we need to
323 * reset the value in the HWSP.
324 */
325 sanitize_hwsp(engine);
326
327 /* And scrub the dirty cachelines for the HWSP */
328 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
329
330 intel_engine_reset_pinned_contexts(engine);
331}
332
333static void reset_prepare(struct intel_engine_cs *engine)
334{
335 /*
336 * We stop engines, otherwise we might get failed reset and a
337 * dead gpu (on elk). Also as modern gpu as kbl can suffer
338 * from system hang if batchbuffer is progressing when
339 * the reset is issued, regardless of READY_TO_RESET ack.
340 * Thus assume it is best to stop engines on all gens
341 * where we have a gpu reset.
342 *
343 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
344 *
345 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
346 * WaClearRingBufHeadRegAtInit:ctg,elk
347 *
348 * FIXME: Wa for more modern gens needs to be validated
349 */
350 ENGINE_TRACE(engine, "\n");
351 intel_engine_stop_cs(engine);
352
353 if (!stop_ring(engine)) {
354 /* G45 ring initialization often fails to reset head to zero */
355 ENGINE_TRACE(engine,
356 "HEAD not reset to zero, "
357 "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n",
358 ENGINE_READ_FW(engine, RING_CTL),
359 ENGINE_READ_FW(engine, RING_HEAD),
360 ENGINE_READ_FW(engine, RING_TAIL),
361 ENGINE_READ_FW(engine, RING_START));
362 if (!stop_ring(engine)) {
363 drm_err(&engine->i915->drm,
364 "failed to set %s head to zero "
365 "ctl %08x head %08x tail %08x start %08x\n",
366 engine->name,
367 ENGINE_READ_FW(engine, RING_CTL),
368 ENGINE_READ_FW(engine, RING_HEAD),
369 ENGINE_READ_FW(engine, RING_TAIL),
370 ENGINE_READ_FW(engine, RING_START));
371 }
372 }
373}
374
375static void reset_rewind(struct intel_engine_cs *engine, bool stalled)
376{
377 struct i915_request *pos, *rq;
378 unsigned long flags;
379 u32 head;
380
381 rq = NULL;
382 spin_lock_irqsave(&engine->sched_engine->lock, flags);
383 rcu_read_lock();
384 list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) {
385 if (!__i915_request_is_complete(pos)) {
386 rq = pos;
387 break;
388 }
389 }
390 rcu_read_unlock();
391
392 /*
393 * The guilty request will get skipped on a hung engine.
394 *
395 * Users of client default contexts do not rely on logical
396 * state preserved between batches so it is safe to execute
397 * queued requests following the hang. Non default contexts
398 * rely on preserved state, so skipping a batch loses the
399 * evolution of the state and it needs to be considered corrupted.
400 * Executing more queued batches on top of corrupted state is
401 * risky. But we take the risk by trying to advance through
402 * the queued requests in order to make the client behaviour
403 * more predictable around resets, by not throwing away random
404 * amount of batches it has prepared for execution. Sophisticated
405 * clients can use gem_reset_stats_ioctl and dma fence status
406 * (exported via sync_file info ioctl on explicit fences) to observe
407 * when it loses the context state and should rebuild accordingly.
408 *
409 * The context ban, and ultimately the client ban, mechanism are safety
410 * valves if client submission ends up resulting in nothing more than
411 * subsequent hangs.
412 */
413
414 if (rq) {
415 /*
416 * Try to restore the logical GPU state to match the
417 * continuation of the request queue. If we skip the
418 * context/PD restore, then the next request may try to execute
419 * assuming that its context is valid and loaded on the GPU and
420 * so may try to access invalid memory, prompting repeated GPU
421 * hangs.
422 *
423 * If the request was guilty, we still restore the logical
424 * state in case the next request requires it (e.g. the
425 * aliasing ppgtt), but skip over the hung batch.
426 *
427 * If the request was innocent, we try to replay the request
428 * with the restored context.
429 */
430 __i915_request_reset(rq, stalled);
431
432 GEM_BUG_ON(rq->ring != engine->legacy.ring);
433 head = rq->head;
434 } else {
435 head = engine->legacy.ring->tail;
436 }
437 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);
438
439 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
440}
441
442static void reset_finish(struct intel_engine_cs *engine)
443{
444}
445
446static void reset_cancel(struct intel_engine_cs *engine)
447{
448 struct i915_request *request;
449 unsigned long flags;
450
451 spin_lock_irqsave(&engine->sched_engine->lock, flags);
452
453 /* Mark all submitted requests as skipped. */
454 list_for_each_entry(request, &engine->sched_engine->requests, sched.link)
455 i915_request_put(i915_request_mark_eio(request));
456 intel_engine_signal_breadcrumbs(engine);
457
458 /* Remaining _unready_ requests will be nop'ed when submitted */
459
460 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
461}
462
463static void i9xx_submit_request(struct i915_request *request)
464{
465 i915_request_submit(request);
466 wmb(); /* paranoid flush writes out of the WCB before mmio */
467
468 ENGINE_WRITE(request->engine, RING_TAIL,
469 intel_ring_set_tail(request->ring, request->tail));
470}
471
472static void __ring_context_fini(struct intel_context *ce)
473{
474 i915_vma_put(ce->state);
475}
476
477static void ring_context_destroy(struct kref *ref)
478{
479 struct intel_context *ce = container_of(ref, typeof(*ce), ref);
480
481 GEM_BUG_ON(intel_context_is_pinned(ce));
482
483 if (ce->state)
484 __ring_context_fini(ce);
485
486 intel_context_fini(ce);
487 intel_context_free(ce);
488}
489
490static int ring_context_init_default_state(struct intel_context *ce,
491 struct i915_gem_ww_ctx *ww)
492{
493 struct drm_i915_gem_object *obj = ce->state->obj;
494 void *vaddr;
495
496 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
497 if (IS_ERR(vaddr))
498 return PTR_ERR(vaddr);
499
500 shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size);
501
502 i915_gem_object_flush_map(obj);
503 __i915_gem_object_release_map(obj);
504
505 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
506 return 0;
507}
508
509static int ring_context_pre_pin(struct intel_context *ce,
510 struct i915_gem_ww_ctx *ww,
511 void **unused)
512{
513 struct i915_address_space *vm;
514 int err = 0;
515
516 if (ce->default_state &&
517 !test_bit(CONTEXT_VALID_BIT, &ce->flags)) {
518 err = ring_context_init_default_state(ce, ww);
519 if (err)
520 return err;
521 }
522
523 vm = vm_alias(ce->vm);
524 if (vm)
525 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww);
526
527 return err;
528}
529
530static void __context_unpin_ppgtt(struct intel_context *ce)
531{
532 struct i915_address_space *vm;
533
534 vm = vm_alias(ce->vm);
535 if (vm)
536 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
537}
538
539static void ring_context_unpin(struct intel_context *ce)
540{
541}
542
543static void ring_context_post_unpin(struct intel_context *ce)
544{
545 __context_unpin_ppgtt(ce);
546}
547
548static struct i915_vma *
549alloc_context_vma(struct intel_engine_cs *engine)
550{
551 struct drm_i915_private *i915 = engine->i915;
552 struct drm_i915_gem_object *obj;
553 struct i915_vma *vma;
554 int err;
555
556 obj = i915_gem_object_create_shmem(i915, engine->context_size);
557 if (IS_ERR(obj))
558 return ERR_CAST(obj);
559
560 /*
561 * Try to make the context utilize L3 as well as LLC.
562 *
563 * On VLV we don't have L3 controls in the PTEs so we
564 * shouldn't touch the cache level, especially as that
565 * would make the object snooped which might have a
566 * negative performance impact.
567 *
568 * Snooping is required on non-llc platforms in execlist
569 * mode, but since all GGTT accesses use PAT entry 0 we
570 * get snooping anyway regardless of cache_level.
571 *
572 * This is only applicable for Ivy Bridge devices since
573 * later platforms don't have L3 control bits in the PTE.
574 */
575 if (IS_IVYBRIDGE(i915))
576 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
577
578 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
579 if (IS_ERR(vma)) {
580 err = PTR_ERR(vma);
581 goto err_obj;
582 }
583
584 return vma;
585
586err_obj:
587 i915_gem_object_put(obj);
588 return ERR_PTR(err);
589}
590
591static int ring_context_alloc(struct intel_context *ce)
592{
593 struct intel_engine_cs *engine = ce->engine;
594
595 if (!intel_context_has_own_state(ce))
596 ce->default_state = engine->default_state;
597
598 /* One ringbuffer to rule them all */
599 GEM_BUG_ON(!engine->legacy.ring);
600 ce->ring = engine->legacy.ring;
601 ce->timeline = intel_timeline_get(engine->legacy.timeline);
602
603 GEM_BUG_ON(ce->state);
604 if (engine->context_size) {
605 struct i915_vma *vma;
606
607 vma = alloc_context_vma(engine);
608 if (IS_ERR(vma))
609 return PTR_ERR(vma);
610
611 ce->state = vma;
612 }
613
614 return 0;
615}
616
617static int ring_context_pin(struct intel_context *ce, void *unused)
618{
619 return 0;
620}
621
622static void ring_context_reset(struct intel_context *ce)
623{
624 intel_ring_reset(ce->ring, ce->ring->emit);
625 clear_bit(CONTEXT_VALID_BIT, &ce->flags);
626}
627
628static void ring_context_revoke(struct intel_context *ce,
629 struct i915_request *rq,
630 unsigned int preempt_timeout_ms)
631{
632 struct intel_engine_cs *engine;
633
634 if (!rq || !i915_request_is_active(rq))
635 return;
636
637 engine = rq->engine;
638 lockdep_assert_held(&engine->sched_engine->lock);
639 list_for_each_entry_continue(rq, &engine->sched_engine->requests,
640 sched.link)
641 if (rq->context == ce) {
642 i915_request_set_error_once(rq, -EIO);
643 __i915_request_skip(rq);
644 }
645}
646
647static void ring_context_cancel_request(struct intel_context *ce,
648 struct i915_request *rq)
649{
650 struct intel_engine_cs *engine = NULL;
651
652 i915_request_active_engine(rq, &engine);
653
654 if (engine && intel_engine_pulse(engine))
655 intel_gt_handle_error(engine->gt, engine->mask, 0,
656 "request cancellation by %s",
657 current->comm);
658}
659
660static const struct intel_context_ops ring_context_ops = {
661 .alloc = ring_context_alloc,
662
663 .cancel_request = ring_context_cancel_request,
664
665 .revoke = ring_context_revoke,
666
667 .pre_pin = ring_context_pre_pin,
668 .pin = ring_context_pin,
669 .unpin = ring_context_unpin,
670 .post_unpin = ring_context_post_unpin,
671
672 .enter = intel_context_enter_engine,
673 .exit = intel_context_exit_engine,
674
675 .reset = ring_context_reset,
676 .destroy = ring_context_destroy,
677};
678
679static int load_pd_dir(struct i915_request *rq,
680 struct i915_address_space *vm,
681 u32 valid)
682{
683 const struct intel_engine_cs * const engine = rq->engine;
684 u32 *cs;
685
686 cs = intel_ring_begin(rq, 12);
687 if (IS_ERR(cs))
688 return PTR_ERR(cs);
689
690 *cs++ = MI_LOAD_REGISTER_IMM(1);
691 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
692 *cs++ = valid;
693
694 *cs++ = MI_LOAD_REGISTER_IMM(1);
695 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
696 *cs++ = pp_dir(vm);
697
698 /* Stall until the page table load is complete? */
699 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
700 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
701 *cs++ = intel_gt_scratch_offset(engine->gt,
702 INTEL_GT_SCRATCH_FIELD_DEFAULT);
703
704 *cs++ = MI_LOAD_REGISTER_IMM(1);
705 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
706 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
707
708 intel_ring_advance(rq, cs);
709
710 return rq->engine->emit_flush(rq, EMIT_FLUSH);
711}
712
713static int mi_set_context(struct i915_request *rq,
714 struct intel_context *ce,
715 u32 flags)
716{
717 struct intel_engine_cs *engine = rq->engine;
718 struct drm_i915_private *i915 = engine->i915;
719 enum intel_engine_id id;
720 const int num_engines =
721 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
722 bool force_restore = false;
723 int len;
724 u32 *cs;
725
726 len = 4;
727 if (GRAPHICS_VER(i915) == 7)
728 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
729 else if (GRAPHICS_VER(i915) == 5)
730 len += 2;
731 if (flags & MI_FORCE_RESTORE) {
732 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
733 flags &= ~MI_FORCE_RESTORE;
734 force_restore = true;
735 len += 2;
736 }
737
738 cs = intel_ring_begin(rq, len);
739 if (IS_ERR(cs))
740 return PTR_ERR(cs);
741
742 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
743 if (GRAPHICS_VER(i915) == 7) {
744 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
745 if (num_engines) {
746 struct intel_engine_cs *signaller;
747
748 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
749 for_each_engine(signaller, engine->gt, id) {
750 if (signaller == engine)
751 continue;
752
753 *cs++ = i915_mmio_reg_offset(
754 RING_PSMI_CTL(signaller->mmio_base));
755 *cs++ = _MASKED_BIT_ENABLE(
756 GEN6_PSMI_SLEEP_MSG_DISABLE);
757 }
758 }
759 } else if (GRAPHICS_VER(i915) == 5) {
760 /*
761 * This w/a is only listed for pre-production ilk a/b steppings,
762 * but is also mentioned for programming the powerctx. To be
763 * safe, just apply the workaround; we do not use SyncFlush so
764 * this should never take effect and so be a no-op!
765 */
766 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
767 }
768
769 if (force_restore) {
770 /*
771 * The HW doesn't handle being told to restore the current
772 * context very well. Quite often it likes goes to go off and
773 * sulk, especially when it is meant to be reloading PP_DIR.
774 * A very simple fix to force the reload is to simply switch
775 * away from the current context and back again.
776 *
777 * Note that the kernel_context will contain random state
778 * following the INHIBIT_RESTORE. We accept this since we
779 * never use the kernel_context state; it is merely a
780 * placeholder we use to flush other contexts.
781 */
782 *cs++ = MI_SET_CONTEXT;
783 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
784 MI_MM_SPACE_GTT |
785 MI_RESTORE_INHIBIT;
786 }
787
788 *cs++ = MI_NOOP;
789 *cs++ = MI_SET_CONTEXT;
790 *cs++ = i915_ggtt_offset(ce->state) | flags;
791 /*
792 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
793 * WaMiSetContext_Hang:snb,ivb,vlv
794 */
795 *cs++ = MI_NOOP;
796
797 if (GRAPHICS_VER(i915) == 7) {
798 if (num_engines) {
799 struct intel_engine_cs *signaller;
800 i915_reg_t last_reg = INVALID_MMIO_REG; /* keep gcc quiet */
801
802 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
803 for_each_engine(signaller, engine->gt, id) {
804 if (signaller == engine)
805 continue;
806
807 last_reg = RING_PSMI_CTL(signaller->mmio_base);
808 *cs++ = i915_mmio_reg_offset(last_reg);
809 *cs++ = _MASKED_BIT_DISABLE(
810 GEN6_PSMI_SLEEP_MSG_DISABLE);
811 }
812
813 /* Insert a delay before the next switch! */
814 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
815 *cs++ = i915_mmio_reg_offset(last_reg);
816 *cs++ = intel_gt_scratch_offset(engine->gt,
817 INTEL_GT_SCRATCH_FIELD_DEFAULT);
818 *cs++ = MI_NOOP;
819 }
820 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
821 } else if (GRAPHICS_VER(i915) == 5) {
822 *cs++ = MI_SUSPEND_FLUSH;
823 }
824
825 intel_ring_advance(rq, cs);
826
827 return 0;
828}
829
830static int remap_l3_slice(struct i915_request *rq, int slice)
831{
832#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
833 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
834 int i;
835
836 if (!remap_info)
837 return 0;
838
839 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2);
840 if (IS_ERR(cs))
841 return PTR_ERR(cs);
842
843 /*
844 * Note: We do not worry about the concurrent register cacheline hang
845 * here because no other code should access these registers other than
846 * at initialization time.
847 */
848 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);
849 for (i = 0; i < L3LOG_DW; i++) {
850 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
851 *cs++ = remap_info[i];
852 }
853 *cs++ = MI_NOOP;
854 intel_ring_advance(rq, cs);
855
856 return 0;
857#undef L3LOG_DW
858}
859
860static int remap_l3(struct i915_request *rq)
861{
862 struct i915_gem_context *ctx = i915_request_gem_context(rq);
863 int i, err;
864
865 if (!ctx || !ctx->remap_slice)
866 return 0;
867
868 for (i = 0; i < MAX_L3_SLICES; i++) {
869 if (!(ctx->remap_slice & BIT(i)))
870 continue;
871
872 err = remap_l3_slice(rq, i);
873 if (err)
874 return err;
875 }
876
877 ctx->remap_slice = 0;
878 return 0;
879}
880
881static int switch_mm(struct i915_request *rq, struct i915_address_space *vm)
882{
883 int ret;
884
885 if (!vm)
886 return 0;
887
888 ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
889 if (ret)
890 return ret;
891
892 /*
893 * Not only do we need a full barrier (post-sync write) after
894 * invalidating the TLBs, but we need to wait a little bit
895 * longer. Whether this is merely delaying us, or the
896 * subsequent flush is a key part of serialising with the
897 * post-sync op, this extra pass appears vital before a
898 * mm switch!
899 */
900 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G);
901 if (ret)
902 return ret;
903
904 return rq->engine->emit_flush(rq, EMIT_INVALIDATE);
905}
906
907static int clear_residuals(struct i915_request *rq)
908{
909 struct intel_engine_cs *engine = rq->engine;
910 int ret;
911
912 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));
913 if (ret)
914 return ret;
915
916 if (engine->kernel_context->state) {
917 ret = mi_set_context(rq,
918 engine->kernel_context,
919 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT);
920 if (ret)
921 return ret;
922 }
923
924 ret = engine->emit_bb_start(rq,
925 i915_vma_offset(engine->wa_ctx.vma), 0,
926 0);
927 if (ret)
928 return ret;
929
930 ret = engine->emit_flush(rq, EMIT_FLUSH);
931 if (ret)
932 return ret;
933
934 /* Always invalidate before the next switch_mm() */
935 return engine->emit_flush(rq, EMIT_INVALIDATE);
936}
937
938static int switch_context(struct i915_request *rq)
939{
940 struct intel_engine_cs *engine = rq->engine;
941 struct intel_context *ce = rq->context;
942 void **residuals = NULL;
943 int ret;
944
945 GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
946
947 if (engine->wa_ctx.vma && ce != engine->kernel_context) {
948 if (engine->wa_ctx.vma->private != ce &&
949 i915_mitigate_clear_residuals()) {
950 ret = clear_residuals(rq);
951 if (ret)
952 return ret;
953
954 residuals = &engine->wa_ctx.vma->private;
955 }
956 }
957
958 ret = switch_mm(rq, vm_alias(ce->vm));
959 if (ret)
960 return ret;
961
962 if (ce->state) {
963 u32 flags;
964
965 GEM_BUG_ON(engine->id != RCS0);
966
967 /* For resource streamer on HSW+ and power context elsewhere */
968 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);
969 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);
970
971 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;
972 if (test_bit(CONTEXT_VALID_BIT, &ce->flags))
973 flags |= MI_RESTORE_EXT_STATE_EN;
974 else
975 flags |= MI_RESTORE_INHIBIT;
976
977 ret = mi_set_context(rq, ce, flags);
978 if (ret)
979 return ret;
980 }
981
982 ret = remap_l3(rq);
983 if (ret)
984 return ret;
985
986 /*
987 * Now past the point of no return, this request _will_ be emitted.
988 *
989 * Or at least this preamble will be emitted, the request may be
990 * interrupted prior to submitting the user payload. If so, we
991 * still submit the "empty" request in order to preserve global
992 * state tracking such as this, our tracking of the current
993 * dirty context.
994 */
995 if (residuals) {
996 intel_context_put(*residuals);
997 *residuals = intel_context_get(ce);
998 }
999
1000 return 0;
1001}
1002
1003static int ring_request_alloc(struct i915_request *request)
1004{
1005 int ret;
1006
1007 GEM_BUG_ON(!intel_context_is_pinned(request->context));
1008 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);
1009
1010 /*
1011 * Flush enough space to reduce the likelihood of waiting after
1012 * we start building the request - in which case we will just
1013 * have to repeat work.
1014 */
1015 request->reserved_space += LEGACY_REQUEST_SIZE;
1016
1017 /* Unconditionally invalidate GPU caches and TLBs. */
1018 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1019 if (ret)
1020 return ret;
1021
1022 ret = switch_context(request);
1023 if (ret)
1024 return ret;
1025
1026 request->reserved_space -= LEGACY_REQUEST_SIZE;
1027 return 0;
1028}
1029
1030static void gen6_bsd_submit_request(struct i915_request *request)
1031{
1032 struct intel_uncore *uncore = request->engine->uncore;
1033
1034 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1035
1036 /* Every tail move must follow the sequence below */
1037
1038 /* Disable notification that the ring is IDLE. The GT
1039 * will then assume that it is busy and bring it out of rc6.
1040 */
1041 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1042 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1043
1044 /* Clear the context id. Here be magic! */
1045 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
1046
1047 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1048 if (__intel_wait_for_register_fw(uncore,
1049 RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1050 GEN6_BSD_SLEEP_INDICATOR,
1051 0,
1052 1000, 0, NULL))
1053 drm_err(&uncore->i915->drm,
1054 "timed out waiting for the BSD ring to wake up\n");
1055
1056 /* Now that the ring is fully powered up, update the tail */
1057 i9xx_submit_request(request);
1058
1059 /* Let the ring send IDLE messages to the GT again,
1060 * and so let it sleep to conserve power when idle.
1061 */
1062 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1063 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1064
1065 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1066}
1067
1068static void i9xx_set_default_submission(struct intel_engine_cs *engine)
1069{
1070 engine->submit_request = i9xx_submit_request;
1071}
1072
1073static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
1074{
1075 engine->submit_request = gen6_bsd_submit_request;
1076}
1077
1078static void ring_release(struct intel_engine_cs *engine)
1079{
1080 struct drm_i915_private *i915 = engine->i915;
1081
1082 drm_WARN_ON(&i915->drm, GRAPHICS_VER(i915) > 2 &&
1083 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
1084
1085 intel_engine_cleanup_common(engine);
1086
1087 if (engine->wa_ctx.vma) {
1088 intel_context_put(engine->wa_ctx.vma->private);
1089 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1090 }
1091
1092 intel_ring_unpin(engine->legacy.ring);
1093 intel_ring_put(engine->legacy.ring);
1094
1095 intel_timeline_unpin(engine->legacy.timeline);
1096 intel_timeline_put(engine->legacy.timeline);
1097}
1098
1099static void irq_handler(struct intel_engine_cs *engine, u16 iir)
1100{
1101 intel_engine_signal_breadcrumbs(engine);
1102}
1103
1104static void setup_irq(struct intel_engine_cs *engine)
1105{
1106 struct drm_i915_private *i915 = engine->i915;
1107
1108 intel_engine_set_irq_handler(engine, irq_handler);
1109
1110 if (GRAPHICS_VER(i915) >= 6) {
1111 engine->irq_enable = gen6_irq_enable;
1112 engine->irq_disable = gen6_irq_disable;
1113 } else if (GRAPHICS_VER(i915) >= 5) {
1114 engine->irq_enable = gen5_irq_enable;
1115 engine->irq_disable = gen5_irq_disable;
1116 } else {
1117 engine->irq_enable = gen2_irq_enable;
1118 engine->irq_disable = gen2_irq_disable;
1119 }
1120}
1121
1122static void add_to_engine(struct i915_request *rq)
1123{
1124 lockdep_assert_held(&rq->engine->sched_engine->lock);
1125 list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
1126}
1127
1128static void remove_from_engine(struct i915_request *rq)
1129{
1130 spin_lock_irq(&rq->engine->sched_engine->lock);
1131 list_del_init(&rq->sched.link);
1132
1133 /* Prevent further __await_execution() registering a cb, then flush */
1134 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
1135
1136 spin_unlock_irq(&rq->engine->sched_engine->lock);
1137
1138 i915_request_notify_execute_cb_imm(rq);
1139}
1140
1141static void setup_common(struct intel_engine_cs *engine)
1142{
1143 struct drm_i915_private *i915 = engine->i915;
1144
1145 /* gen8+ are only supported with execlists */
1146 GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
1147
1148 setup_irq(engine);
1149
1150 engine->resume = xcs_resume;
1151 engine->sanitize = xcs_sanitize;
1152
1153 engine->reset.prepare = reset_prepare;
1154 engine->reset.rewind = reset_rewind;
1155 engine->reset.cancel = reset_cancel;
1156 engine->reset.finish = reset_finish;
1157
1158 engine->add_active_request = add_to_engine;
1159 engine->remove_active_request = remove_from_engine;
1160
1161 engine->cops = &ring_context_ops;
1162 engine->request_alloc = ring_request_alloc;
1163
1164 /*
1165 * Using a global execution timeline; the previous final breadcrumb is
1166 * equivalent to our next initial bread so we can elide
1167 * engine->emit_init_breadcrumb().
1168 */
1169 engine->emit_fini_breadcrumb = gen2_emit_breadcrumb;
1170 if (GRAPHICS_VER(i915) == 5)
1171 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
1172
1173 engine->set_default_submission = i9xx_set_default_submission;
1174
1175 if (GRAPHICS_VER(i915) >= 6)
1176 engine->emit_bb_start = gen6_emit_bb_start;
1177 else if (GRAPHICS_VER(i915) >= 4)
1178 engine->emit_bb_start = gen4_emit_bb_start;
1179 else if (IS_I830(i915) || IS_I845G(i915))
1180 engine->emit_bb_start = i830_emit_bb_start;
1181 else
1182 engine->emit_bb_start = gen2_emit_bb_start;
1183}
1184
1185static void setup_rcs(struct intel_engine_cs *engine)
1186{
1187 struct drm_i915_private *i915 = engine->i915;
1188
1189 if (HAS_L3_DPF(i915))
1190 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1191
1192 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1193
1194 if (GRAPHICS_VER(i915) >= 7) {
1195 engine->emit_flush = gen7_emit_flush_rcs;
1196 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
1197 } else if (GRAPHICS_VER(i915) == 6) {
1198 engine->emit_flush = gen6_emit_flush_rcs;
1199 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
1200 } else if (GRAPHICS_VER(i915) == 5) {
1201 engine->emit_flush = gen4_emit_flush_rcs;
1202 } else {
1203 if (GRAPHICS_VER(i915) < 4)
1204 engine->emit_flush = gen2_emit_flush;
1205 else
1206 engine->emit_flush = gen4_emit_flush_rcs;
1207 engine->irq_enable_mask = I915_USER_INTERRUPT;
1208 }
1209
1210 if (IS_HASWELL(i915))
1211 engine->emit_bb_start = hsw_emit_bb_start;
1212}
1213
1214static void setup_vcs(struct intel_engine_cs *engine)
1215{
1216 struct drm_i915_private *i915 = engine->i915;
1217
1218 if (GRAPHICS_VER(i915) >= 6) {
1219 /* gen6 bsd needs a special wa for tail updates */
1220 if (GRAPHICS_VER(i915) == 6)
1221 engine->set_default_submission = gen6_bsd_set_default_submission;
1222 engine->emit_flush = gen6_emit_flush_vcs;
1223 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1224
1225 if (GRAPHICS_VER(i915) == 6)
1226 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1227 else
1228 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1229 } else {
1230 engine->emit_flush = gen4_emit_flush_vcs;
1231 if (GRAPHICS_VER(i915) == 5)
1232 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1233 else
1234 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1235 }
1236}
1237
1238static void setup_bcs(struct intel_engine_cs *engine)
1239{
1240 struct drm_i915_private *i915 = engine->i915;
1241
1242 engine->emit_flush = gen6_emit_flush_xcs;
1243 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1244
1245 if (GRAPHICS_VER(i915) == 6)
1246 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1247 else
1248 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1249}
1250
1251static void setup_vecs(struct intel_engine_cs *engine)
1252{
1253 struct drm_i915_private *i915 = engine->i915;
1254
1255 GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
1256
1257 engine->emit_flush = gen6_emit_flush_xcs;
1258 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
1259 engine->irq_enable = hsw_irq_enable_vecs;
1260 engine->irq_disable = hsw_irq_disable_vecs;
1261
1262 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1263}
1264
1265static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,
1266 struct i915_vma * const vma)
1267{
1268 return gen7_setup_clear_gpr_bb(engine, vma);
1269}
1270
1271static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,
1272 struct i915_gem_ww_ctx *ww,
1273 struct i915_vma *vma)
1274{
1275 int err;
1276
1277 err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH);
1278 if (err)
1279 return err;
1280
1281 err = i915_vma_sync(vma);
1282 if (err)
1283 goto err_unpin;
1284
1285 err = gen7_ctx_switch_bb_setup(engine, vma);
1286 if (err)
1287 goto err_unpin;
1288
1289 engine->wa_ctx.vma = vma;
1290 return 0;
1291
1292err_unpin:
1293 i915_vma_unpin(vma);
1294 return err;
1295}
1296
1297static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
1298{
1299 struct drm_i915_gem_object *obj;
1300 struct i915_vma *vma;
1301 int size, err;
1302
1303 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
1304 return NULL;
1305
1306 err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
1307 if (err < 0)
1308 return ERR_PTR(err);
1309 if (!err)
1310 return NULL;
1311
1312 size = ALIGN(err, PAGE_SIZE);
1313
1314 obj = i915_gem_object_create_internal(engine->i915, size);
1315 if (IS_ERR(obj))
1316 return ERR_CAST(obj);
1317
1318 vma = i915_vma_instance(obj, engine->gt->vm, NULL);
1319 if (IS_ERR(vma)) {
1320 i915_gem_object_put(obj);
1321 return ERR_CAST(vma);
1322 }
1323
1324 vma->private = intel_context_create(engine); /* dummy residuals */
1325 if (IS_ERR(vma->private)) {
1326 err = PTR_ERR(vma->private);
1327 vma->private = NULL;
1328 i915_gem_object_put(obj);
1329 return ERR_PTR(err);
1330 }
1331
1332 return vma;
1333}
1334
1335int intel_ring_submission_setup(struct intel_engine_cs *engine)
1336{
1337 struct i915_gem_ww_ctx ww;
1338 struct intel_timeline *timeline;
1339 struct intel_ring *ring;
1340 struct i915_vma *gen7_wa_vma;
1341 int err;
1342
1343 setup_common(engine);
1344
1345 switch (engine->class) {
1346 case RENDER_CLASS:
1347 setup_rcs(engine);
1348 break;
1349 case VIDEO_DECODE_CLASS:
1350 setup_vcs(engine);
1351 break;
1352 case COPY_ENGINE_CLASS:
1353 setup_bcs(engine);
1354 break;
1355 case VIDEO_ENHANCEMENT_CLASS:
1356 setup_vecs(engine);
1357 break;
1358 default:
1359 MISSING_CASE(engine->class);
1360 return -ENODEV;
1361 }
1362
1363 timeline = intel_timeline_create_from_engine(engine,
1364 I915_GEM_HWS_SEQNO_ADDR);
1365 if (IS_ERR(timeline)) {
1366 err = PTR_ERR(timeline);
1367 goto err;
1368 }
1369 GEM_BUG_ON(timeline->has_initial_breadcrumb);
1370
1371 ring = intel_engine_create_ring(engine, SZ_16K);
1372 if (IS_ERR(ring)) {
1373 err = PTR_ERR(ring);
1374 goto err_timeline;
1375 }
1376
1377 GEM_BUG_ON(engine->legacy.ring);
1378 engine->legacy.ring = ring;
1379 engine->legacy.timeline = timeline;
1380
1381 gen7_wa_vma = gen7_ctx_vma(engine);
1382 if (IS_ERR(gen7_wa_vma)) {
1383 err = PTR_ERR(gen7_wa_vma);
1384 goto err_ring;
1385 }
1386
1387 i915_gem_ww_ctx_init(&ww, false);
1388
1389retry:
1390 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww);
1391 if (!err && gen7_wa_vma)
1392 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww);
1393 if (!err)
1394 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);
1395 if (!err)
1396 err = intel_timeline_pin(timeline, &ww);
1397 if (!err) {
1398 err = intel_ring_pin(ring, &ww);
1399 if (err)
1400 intel_timeline_unpin(timeline);
1401 }
1402 if (err)
1403 goto out;
1404
1405 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
1406
1407 if (gen7_wa_vma) {
1408 err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma);
1409 if (err) {
1410 intel_ring_unpin(ring);
1411 intel_timeline_unpin(timeline);
1412 }
1413 }
1414
1415out:
1416 if (err == -EDEADLK) {
1417 err = i915_gem_ww_ctx_backoff(&ww);
1418 if (!err)
1419 goto retry;
1420 }
1421 i915_gem_ww_ctx_fini(&ww);
1422 if (err)
1423 goto err_gen7_put;
1424
1425 /* Finally, take ownership and responsibility for cleanup! */
1426 engine->release = ring_release;
1427
1428 return 0;
1429
1430err_gen7_put:
1431 if (gen7_wa_vma) {
1432 intel_context_put(gen7_wa_vma->private);
1433 i915_gem_object_put(gen7_wa_vma->obj);
1434 }
1435err_ring:
1436 intel_ring_put(ring);
1437err_timeline:
1438 intel_timeline_put(timeline);
1439err:
1440 intel_engine_cleanup_common(engine);
1441 return err;
1442}
1443
1444#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1445#include "selftest_ring_submission.c"
1446#endif