1// SPDX-License-Identifier: MIT
 2/*
 3 * Copyright © 2024 Intel Corporation
 4 */
 5
 6#include "i915_drv.h"
 7#include "intel_gt.h"
 8#include "intel_gt_ccs_mode.h"
 9#include "intel_gt_regs.h"
10
11unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
12{
13	int cslice;
14	u32 mode = 0;
15	int first_ccs = __ffs(CCS_MASK(gt));
16
17	if (!IS_DG2(gt->i915))
18		return 0;
19
20	/* Build the value for the fixed CCS load balancing */
21	for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
22		if (gt->ccs.cslices & BIT(cslice))
23			/*
24			 * If available, assign the cslice
25			 * to the first available engine...
26			 */
27			mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
28
29		else
30			/*
31			 * ... otherwise, mark the cslice as
32			 * unavailable if no CCS dispatches here
33			 */
34			mode |= XEHP_CCS_MODE_CSLICE(cslice,
35						     XEHP_CCS_MODE_CSLICE_MASK);
36	}
37
38	return mode;
39}