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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8#include <linux/limits.h>
9
10#include <drm/display/drm_dsc_helper.h>
11#include <drm/drm_fixed.h>
12
13#include "i915_drv.h"
14#include "intel_crtc.h"
15#include "intel_de.h"
16#include "intel_display_types.h"
17#include "intel_dsi.h"
18#include "intel_qp_tables.h"
19#include "intel_vdsc.h"
20#include "intel_vdsc_regs.h"
21
22bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
23{
24 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
25 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
27
28 if (!HAS_DSC(i915))
29 return false;
30
31 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
32 return false;
33
34 return true;
35}
36
37static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
38{
39 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
40
41 if (DISPLAY_VER(i915) >= 12)
42 return true;
43
44 if (cpu_transcoder == TRANSCODER_EDP ||
45 cpu_transcoder == TRANSCODER_DSI_0 ||
46 cpu_transcoder == TRANSCODER_DSI_1)
47 return false;
48
49 /* There's no pipe A DSC engine on ICL */
50 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
51
52 return true;
53}
54
55static void
56intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
57 int bpp)
58{
59 int bpc = vdsc_cfg->bits_per_component;
60
61 /* Read range_minqp and range_max_qp from qp tables */
62 vdsc_cfg->rc_range_params[buf].range_min_qp =
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
64 vdsc_cfg->rc_range_params[buf].range_max_qp =
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
66}
67
68/*
69 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
70 * Above method use a common formula to derive values for any combination of DSC
71 * variables. The formula approach may yield slight differences in the derived PPS
72 * parameters from the original parameter sets. These differences are not consequential
73 * to the coding performance because all parameter sets have been shown to produce
74 * visually lossless quality (provides the same PPS values as
75 * DSCParameterValuesVESA V1-2 spreadsheet).
76 */
77static void
78calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
79{
80 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
81 int bpc = vdsc_cfg->bits_per_component;
82 int qp_bpc_modifier = (bpc - 8) * 2;
83 int uncompressed_bpg_rate;
84 int first_line_bpg_offset;
85 u32 res, buf_i, bpp_i;
86
87 if (vdsc_cfg->slice_height >= 8)
88 first_line_bpg_offset =
89 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100;
90 else
91 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
92
93 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3;
94 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0,
95 uncompressed_bpg_rate - 3 * bpp);
96
97 /*
98 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
99 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
100 * height < 8.
101 * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma
102 * preservation in second line.
103 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
104 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
105 * fractional bits.
106 */
107 if (vdsc_cfg->native_420) {
108 if (vdsc_cfg->slice_height >= 8)
109 vdsc_cfg->second_line_bpg_offset = 12;
110 else
111 vdsc_cfg->second_line_bpg_offset =
112 2 * (vdsc_cfg->slice_height - 1);
113
114 vdsc_cfg->second_line_offset_adj = 512;
115 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
116 vdsc_cfg->slice_height - 1);
117 }
118
119 /* Our hw supports only 444 modes as of today */
120 if (bpp >= 12)
121 vdsc_cfg->initial_offset = 2048;
122 else if (bpp >= 10)
123 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
124 else if (bpp >= 8)
125 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
126 else
127 vdsc_cfg->initial_offset = 6144;
128
129 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
130 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
131
132 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
133 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
134
135 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
136 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
137
138 if (vdsc_cfg->native_420) {
139 static const s8 ofs_und4[] = {
140 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
141 };
142 static const s8 ofs_und5[] = {
143 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
144 };
145 static const s8 ofs_und6[] = {
146 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
147 };
148 static const s8 ofs_und8[] = {
149 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
150 };
151 /*
152 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
153 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
154 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
155 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
156 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
157 */
158 bpp_i = bpp - 8;
159 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
160 u8 range_bpg_offset;
161
162 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
163
164 /* Calculate range_bpg_offset */
165 if (bpp <= 8) {
166 range_bpg_offset = ofs_und4[buf_i];
167 } else if (bpp <= 10) {
168 res = DIV_ROUND_UP(((bpp - 8) *
169 (ofs_und5[buf_i] - ofs_und4[buf_i])), 2);
170 range_bpg_offset = ofs_und4[buf_i] + res;
171 } else if (bpp <= 12) {
172 res = DIV_ROUND_UP(((bpp - 10) *
173 (ofs_und6[buf_i] - ofs_und5[buf_i])), 2);
174 range_bpg_offset = ofs_und5[buf_i] + res;
175 } else if (bpp <= 16) {
176 res = DIV_ROUND_UP(((bpp - 12) *
177 (ofs_und8[buf_i] - ofs_und6[buf_i])), 4);
178 range_bpg_offset = ofs_und6[buf_i] + res;
179 } else {
180 range_bpg_offset = ofs_und8[buf_i];
181 }
182
183 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
184 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
185 }
186 } else {
187 /* fractional bpp part * 10000 (for precision up to 4 decimal places) */
188 int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel);
189
190 static const s8 ofs_und6[] = {
191 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
192 };
193 static const s8 ofs_und8[] = {
194 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
195 };
196 static const s8 ofs_und12[] = {
197 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
198 };
199 static const s8 ofs_und15[] = {
200 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
201 };
202
203 /*
204 * QP table rows have values in increment of 0.5.
205 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
206 * and so on.
207 * 0.5 fractional part with 4 decimal precision becomes 5000
208 */
209 bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
210
211 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
212 u8 range_bpg_offset;
213
214 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
215
216 /* Calculate range_bpg_offset */
217 if (bpp <= 6) {
218 range_bpg_offset = ofs_und6[buf_i];
219 } else if (bpp <= 8) {
220 res = DIV_ROUND_UP(((bpp - 6) *
221 (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
222 range_bpg_offset = ofs_und6[buf_i] + res;
223 } else if (bpp <= 12) {
224 range_bpg_offset = ofs_und8[buf_i];
225 } else if (bpp <= 15) {
226 res = DIV_ROUND_UP(((bpp - 12) *
227 (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
228 range_bpg_offset = ofs_und12[buf_i] + res;
229 } else {
230 range_bpg_offset = ofs_und15[buf_i];
231 }
232
233 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
234 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
235 }
236 }
237}
238
239static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
240 struct drm_dsc_config *vdsc_cfg)
241{
242 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
243 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
244 if (vdsc_cfg->slice_height > 4095)
245 return -EINVAL;
246 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
247 return -EINVAL;
248 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
249 if (vdsc_cfg->slice_width % 2)
250 return -EINVAL;
251 if (vdsc_cfg->slice_height % 2)
252 return -EINVAL;
253 if (vdsc_cfg->slice_height > 4094)
254 return -EINVAL;
255 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
256 return -EINVAL;
257 }
258
259 return 0;
260}
261
262int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
263{
264 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
266 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
267 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
268 int err;
269 int ret;
270
271 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
272 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
273 pipe_config->dsc.slice_count);
274
275 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
276
277 if (err) {
278 drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
279 return err;
280 }
281
282 /*
283 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
284 * else 1
285 */
286 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
287 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
288
289 if (DISPLAY_VER(dev_priv) >= 14 &&
290 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
291 vdsc_cfg->native_420 = true;
292 /* We do not support YcBCr422 as of now */
293 vdsc_cfg->native_422 = false;
294 vdsc_cfg->simple_422 = false;
295 /* Gen 11 does not support VBR */
296 vdsc_cfg->vbr_enable = false;
297
298 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
299
300 /*
301 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
302 * we need to double the current bpp.
303 */
304 if (vdsc_cfg->native_420)
305 vdsc_cfg->bits_per_pixel <<= 1;
306
307 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
308
309 if (vdsc_cfg->bits_per_component < 8) {
310 drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met bpc: %d\n",
311 vdsc_cfg->bits_per_component);
312 return -EINVAL;
313 }
314
315 drm_dsc_set_rc_buf_thresh(vdsc_cfg);
316
317 /*
318 * From XE_LPD onwards we supports compression bpps in steps of 1
319 * upto uncompressed bpp-1, hence add calculations for all the rc
320 * parameters
321 */
322 if (DISPLAY_VER(dev_priv) >= 13) {
323 calculate_rc_params(vdsc_cfg);
324 } else {
325 if ((compressed_bpp == 8 ||
326 compressed_bpp == 12) &&
327 (vdsc_cfg->bits_per_component == 8 ||
328 vdsc_cfg->bits_per_component == 10 ||
329 vdsc_cfg->bits_per_component == 12))
330 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
331 else
332 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
333
334 if (ret)
335 return ret;
336 }
337
338 /*
339 * BitsPerComponent value determines mux_word_size:
340 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
341 * 48 bits otherwise 64
342 */
343 if (vdsc_cfg->bits_per_component <= 10)
344 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
345 else
346 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
347
348 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
349 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
350 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
351
352 return 0;
353}
354
355enum intel_display_power_domain
356intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
357{
358 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
359 enum pipe pipe = crtc->pipe;
360
361 /*
362 * VDSC/joining uses a separate power well, PW2, and requires
363 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
364 *
365 * - ICL eDP/DSI transcoder
366 * - Display version 12 (except RKL) pipe A
367 *
368 * For any other pipe, VDSC/joining uses the power well associated with
369 * the pipe in use. Hence another reference on the pipe power domain
370 * will suffice. (Except no VDSC/joining on ICL pipe A.)
371 */
372 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
373 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
374 else if (is_pipe_dsc(crtc, cpu_transcoder))
375 return POWER_DOMAIN_PIPE(pipe);
376 else
377 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
378}
379
380static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
381{
382 return crtc_state->dsc.dsc_split ? 2 : 1;
383}
384
385int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
386{
387 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
388 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
389
390 num_vdsc_instances *= num_joined_pipes;
391
392 return num_vdsc_instances;
393}
394
395static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
396 i915_reg_t *dsc_reg, int dsc_reg_num)
397{
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
400 enum pipe pipe = crtc->pipe;
401 bool pipe_dsc;
402
403 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
404
405 if (dsc_reg_num >= 3)
406 MISSING_CASE(dsc_reg_num);
407 if (dsc_reg_num >= 2)
408 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
409 if (dsc_reg_num >= 1)
410 dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
411}
412
413static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
414 int pps, u32 pps_val)
415{
416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
417 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
418 i915_reg_t dsc_reg[2];
419 int i, vdsc_per_pipe, dsc_reg_num;
420
421 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
422 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
423
424 drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
425
426 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
427
428 for (i = 0; i < dsc_reg_num; i++)
429 intel_de_write(i915, dsc_reg[i], pps_val);
430}
431
432static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
433{
434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
436 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
437 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
438 enum pipe pipe = crtc->pipe;
439 u32 pps_val;
440 u32 rc_buf_thresh_dword[4];
441 u32 rc_range_params_dword[8];
442 int i = 0;
443 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
444 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
445
446 /* PPS 0 */
447 pps_val = DSC_PPS0_VER_MAJOR(1) |
448 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
449 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
450 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
451 if (vdsc_cfg->dsc_version_minor == 2) {
452 pps_val |= DSC_PPS0_ALT_ICH_SEL;
453 if (vdsc_cfg->native_420)
454 pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
455 if (vdsc_cfg->native_422)
456 pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
457 }
458 if (vdsc_cfg->block_pred_enable)
459 pps_val |= DSC_PPS0_BLOCK_PREDICTION;
460 if (vdsc_cfg->convert_rgb)
461 pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
462 if (vdsc_cfg->simple_422)
463 pps_val |= DSC_PPS0_422_ENABLE;
464 if (vdsc_cfg->vbr_enable)
465 pps_val |= DSC_PPS0_VBR_ENABLE;
466 intel_dsc_pps_write(crtc_state, 0, pps_val);
467
468 /* PPS 1 */
469 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
470 intel_dsc_pps_write(crtc_state, 1, pps_val);
471
472 /* PPS 2 */
473 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
474 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
475 intel_dsc_pps_write(crtc_state, 2, pps_val);
476
477 /* PPS 3 */
478 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
479 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
480 intel_dsc_pps_write(crtc_state, 3, pps_val);
481
482 /* PPS 4 */
483 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
484 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
485 intel_dsc_pps_write(crtc_state, 4, pps_val);
486
487 /* PPS 5 */
488 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
489 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
490 intel_dsc_pps_write(crtc_state, 5, pps_val);
491
492 /* PPS 6 */
493 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
494 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
495 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
496 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
497 intel_dsc_pps_write(crtc_state, 6, pps_val);
498
499 /* PPS 7 */
500 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
501 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
502 intel_dsc_pps_write(crtc_state, 7, pps_val);
503
504 /* PPS 8 */
505 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
506 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
507 intel_dsc_pps_write(crtc_state, 8, pps_val);
508
509 /* PPS 9 */
510 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
511 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
512 intel_dsc_pps_write(crtc_state, 9, pps_val);
513
514 /* PPS 10 */
515 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
516 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
517 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
518 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
519 intel_dsc_pps_write(crtc_state, 10, pps_val);
520
521 /* PPS 16 */
522 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
523 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
524 vdsc_cfg->slice_width) |
525 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
526 vdsc_cfg->slice_height);
527 intel_dsc_pps_write(crtc_state, 16, pps_val);
528
529 if (DISPLAY_VER(dev_priv) >= 14) {
530 /* PPS 17 */
531 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
532 intel_dsc_pps_write(crtc_state, 17, pps_val);
533
534 /* PPS 18 */
535 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
536 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
537 intel_dsc_pps_write(crtc_state, 18, pps_val);
538 }
539
540 /* Populate the RC_BUF_THRESH registers */
541 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
542 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
543 rc_buf_thresh_dword[i / 4] |=
544 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
545 BITS_PER_BYTE * (i % 4));
546 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
547 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
548 rc_buf_thresh_dword[0]);
549 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
550 rc_buf_thresh_dword[1]);
551 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
552 rc_buf_thresh_dword[2]);
553 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
554 rc_buf_thresh_dword[3]);
555 if (vdsc_instances_per_pipe > 1) {
556 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
557 rc_buf_thresh_dword[0]);
558 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
559 rc_buf_thresh_dword[1]);
560 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
561 rc_buf_thresh_dword[2]);
562 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
563 rc_buf_thresh_dword[3]);
564 }
565 } else {
566 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
567 rc_buf_thresh_dword[0]);
568 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
569 rc_buf_thresh_dword[1]);
570 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
571 rc_buf_thresh_dword[2]);
572 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
573 rc_buf_thresh_dword[3]);
574 if (vdsc_instances_per_pipe > 1) {
575 intel_de_write(dev_priv,
576 ICL_DSC1_RC_BUF_THRESH_0(pipe),
577 rc_buf_thresh_dword[0]);
578 intel_de_write(dev_priv,
579 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
580 rc_buf_thresh_dword[1]);
581 intel_de_write(dev_priv,
582 ICL_DSC1_RC_BUF_THRESH_1(pipe),
583 rc_buf_thresh_dword[2]);
584 intel_de_write(dev_priv,
585 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
586 rc_buf_thresh_dword[3]);
587 }
588 }
589
590 /* Populate the RC_RANGE_PARAMETERS registers */
591 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
592 for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
593 rc_range_params_dword[i / 2] |=
594 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
595 RC_BPG_OFFSET_SHIFT) |
596 (vdsc_cfg->rc_range_params[i].range_max_qp <<
597 RC_MAX_QP_SHIFT) |
598 (vdsc_cfg->rc_range_params[i].range_min_qp <<
599 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
600 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
601 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
602 rc_range_params_dword[0]);
603 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
604 rc_range_params_dword[1]);
605 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
606 rc_range_params_dword[2]);
607 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
608 rc_range_params_dword[3]);
609 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
610 rc_range_params_dword[4]);
611 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
612 rc_range_params_dword[5]);
613 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
614 rc_range_params_dword[6]);
615 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
616 rc_range_params_dword[7]);
617 if (vdsc_instances_per_pipe > 1) {
618 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
619 rc_range_params_dword[0]);
620 intel_de_write(dev_priv,
621 DSCC_RC_RANGE_PARAMETERS_0_UDW,
622 rc_range_params_dword[1]);
623 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
624 rc_range_params_dword[2]);
625 intel_de_write(dev_priv,
626 DSCC_RC_RANGE_PARAMETERS_1_UDW,
627 rc_range_params_dword[3]);
628 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
629 rc_range_params_dword[4]);
630 intel_de_write(dev_priv,
631 DSCC_RC_RANGE_PARAMETERS_2_UDW,
632 rc_range_params_dword[5]);
633 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
634 rc_range_params_dword[6]);
635 intel_de_write(dev_priv,
636 DSCC_RC_RANGE_PARAMETERS_3_UDW,
637 rc_range_params_dword[7]);
638 }
639 } else {
640 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
641 rc_range_params_dword[0]);
642 intel_de_write(dev_priv,
643 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
644 rc_range_params_dword[1]);
645 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
646 rc_range_params_dword[2]);
647 intel_de_write(dev_priv,
648 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
649 rc_range_params_dword[3]);
650 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
651 rc_range_params_dword[4]);
652 intel_de_write(dev_priv,
653 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
654 rc_range_params_dword[5]);
655 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
656 rc_range_params_dword[6]);
657 intel_de_write(dev_priv,
658 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
659 rc_range_params_dword[7]);
660 if (vdsc_instances_per_pipe > 1) {
661 intel_de_write(dev_priv,
662 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
663 rc_range_params_dword[0]);
664 intel_de_write(dev_priv,
665 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
666 rc_range_params_dword[1]);
667 intel_de_write(dev_priv,
668 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
669 rc_range_params_dword[2]);
670 intel_de_write(dev_priv,
671 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
672 rc_range_params_dword[3]);
673 intel_de_write(dev_priv,
674 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
675 rc_range_params_dword[4]);
676 intel_de_write(dev_priv,
677 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
678 rc_range_params_dword[5]);
679 intel_de_write(dev_priv,
680 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
681 rc_range_params_dword[6]);
682 intel_de_write(dev_priv,
683 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
684 rc_range_params_dword[7]);
685 }
686 }
687}
688
689void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
690 const struct intel_crtc_state *crtc_state)
691{
692 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
693 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
694 struct mipi_dsi_device *dsi;
695 struct drm_dsc_picture_parameter_set pps;
696 enum port port;
697
698 if (!crtc_state->dsc.compression_enable)
699 return;
700
701 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
702
703 for_each_dsi_port(port, intel_dsi->ports) {
704 dsi = intel_dsi->dsi_hosts[port]->device;
705
706 mipi_dsi_picture_parameter_set(dsi, &pps);
707 mipi_dsi_compression_mode(dsi, true);
708 }
709}
710
711void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
712 const struct intel_crtc_state *crtc_state)
713{
714 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
715 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
716 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
717
718 if (!crtc_state->dsc.compression_enable)
719 return;
720
721 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
722 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
723
724 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
725 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
726
727 dig_port->write_infoframe(encoder, crtc_state,
728 DP_SDP_PPS, &dp_dsc_pps_sdp,
729 sizeof(dp_dsc_pps_sdp));
730}
731
732static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
733{
734 return is_pipe_dsc(crtc, cpu_transcoder) ?
735 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
736}
737
738static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
739{
740 return is_pipe_dsc(crtc, cpu_transcoder) ?
741 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
742}
743
744void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
745{
746 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
747 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
748 u32 dss_ctl1_val = 0;
749
750 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
751 if (intel_crtc_is_bigjoiner_secondary(crtc_state))
752 dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
753 else
754 dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
755
756 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
757 }
758}
759
760void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
761{
762 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
763 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
764 u32 dss_ctl1_val = 0;
765 u32 dss_ctl2_val = 0;
766 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
767
768 if (!crtc_state->dsc.compression_enable)
769 return;
770
771 intel_dsc_pps_configure(crtc_state);
772
773 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
774 if (vdsc_instances_per_pipe > 1) {
775 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
776 dss_ctl1_val |= JOINER_ENABLE;
777 }
778 if (crtc_state->joiner_pipes) {
779 if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
780 dss_ctl1_val |= ULTRA_JOINER_ENABLE;
781
782 if (intel_crtc_is_ultrajoiner_primary(crtc_state))
783 dss_ctl1_val |= PRIMARY_ULTRA_JOINER_ENABLE;
784
785 dss_ctl1_val |= BIG_JOINER_ENABLE;
786
787 if (intel_crtc_is_bigjoiner_primary(crtc_state))
788 dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
789 }
790 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
791 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
792}
793
794void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
795{
796 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
797 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
798
799 /* Disable only if either of them is enabled */
800 if (old_crtc_state->dsc.compression_enable ||
801 old_crtc_state->joiner_pipes) {
802 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
803 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
804 }
805}
806
807static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
808 bool *all_equal)
809{
810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
811 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
812 i915_reg_t dsc_reg[2];
813 int i, vdsc_per_pipe, dsc_reg_num;
814 u32 val;
815
816 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
817 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
818
819 drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
820
821 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
822
823 *all_equal = true;
824
825 val = intel_de_read(i915, dsc_reg[0]);
826
827 for (i = 1; i < dsc_reg_num; i++) {
828 if (intel_de_read(i915, dsc_reg[i]) != val) {
829 *all_equal = false;
830 break;
831 }
832 }
833
834 return val;
835}
836
837static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
838{
839 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
840 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
841 u32 val;
842 bool all_equal;
843
844 val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
845 drm_WARN_ON(&i915->drm, !all_equal);
846
847 return val;
848}
849
850static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
851{
852 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
854 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
855 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
856 u32 pps_temp;
857
858 /* PPS 0 */
859 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
860
861 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
862 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
863 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
864 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
865 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
866 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
867 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
868 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
869
870 /* PPS 1 */
871 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
872
873 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
874
875 if (vdsc_cfg->native_420)
876 vdsc_cfg->bits_per_pixel >>= 1;
877
878 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
879
880 /* PPS 2 */
881 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
882
883 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;
884 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);
885
886 /* PPS 3 */
887 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
888
889 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
890 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);
891
892 /* PPS 4 */
893 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
894
895 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
896 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
897
898 /* PPS 5 */
899 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
900
901 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
902 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
903
904 /* PPS 6 */
905 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
906
907 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
908 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
909 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
910 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
911
912 /* PPS 7 */
913 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
914
915 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
916 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
917
918 /* PPS 8 */
919 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
920
921 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
922 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);
923
924 /* PPS 9 */
925 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
926
927 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);
928
929 /* PPS 10 */
930 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
931
932 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
933 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
934
935 /* PPS 16 */
936 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
937
938 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
939
940 if (DISPLAY_VER(i915) >= 14) {
941 /* PPS 17 */
942 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
943
944 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
945
946 /* PPS 18 */
947 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
948
949 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
950 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
951 }
952}
953
954void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
955{
956 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
958 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
959 enum intel_display_power_domain power_domain;
960 intel_wakeref_t wakeref;
961 u32 dss_ctl1, dss_ctl2;
962
963 if (!intel_dsc_source_support(crtc_state))
964 return;
965
966 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
967
968 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
969 if (!wakeref)
970 return;
971
972 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
973 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
974
975 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
976 if (!crtc_state->dsc.compression_enable)
977 goto out;
978
979 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
980 (dss_ctl1 & JOINER_ENABLE);
981
982 intel_dsc_get_pps_config(crtc_state);
983out:
984 intel_display_power_put(dev_priv, power_domain, wakeref);
985}
986
987static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
988 const struct intel_crtc_state *crtc_state)
989{
990 drm_printf_indent(p, indent,
991 "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
992 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
993 crtc_state->dsc.slice_count,
994 str_yes_no(crtc_state->dsc.dsc_split));
995}
996
997void intel_vdsc_state_dump(struct drm_printer *p, int indent,
998 const struct intel_crtc_state *crtc_state)
999{
1000 if (!crtc_state->dsc.compression_enable)
1001 return;
1002
1003 intel_vdsc_dump_state(p, indent, crtc_state);
1004 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
1005}