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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022-2023 Intel Corporation
4 */
5
6#include <drm/drm_vblank.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "intel_color.h"
11#include "intel_crtc.h"
12#include "intel_de.h"
13#include "intel_display_types.h"
14#include "intel_vblank.h"
15#include "intel_vrr.h"
16
17/*
18 * This timing diagram depicts the video signal in and
19 * around the vertical blanking period.
20 *
21 * Assumptions about the fictitious mode used in this example:
22 * vblank_start >= 3
23 * vsync_start = vblank_start + 1
24 * vsync_end = vblank_start + 2
25 * vtotal = vblank_start + 3
26 *
27 * start of vblank:
28 * latch double buffered registers
29 * increment frame counter (ctg+)
30 * generate start of vblank interrupt (gen4+)
31 * |
32 * | frame start:
33 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
34 * | may be shifted forward 1-3 extra lines via TRANSCONF
35 * | |
36 * | | start of vsync:
37 * | | generate vsync interrupt
38 * | | |
39 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
40 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
41 * ----va---> <-----------------vb--------------------> <--------va-------------
42 * | | <----vs-----> |
43 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
44 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
45 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
46 * | | |
47 * last visible pixel first visible pixel
48 * | increment frame counter (gen3/4)
49 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
50 *
51 * x = horizontal active
52 * _ = horizontal blanking
53 * hs = horizontal sync
54 * va = vertical active
55 * vb = vertical blanking
56 * vs = vertical sync
57 * vbs = vblank_start (number)
58 *
59 * Summary:
60 * - most events happen at the start of horizontal sync
61 * - frame start happens at the start of horizontal blank, 1-4 lines
62 * (depending on TRANSCONF settings) after the start of vblank
63 * - gen3/4 pixel and frame counter are synchronized with the start
64 * of horizontal active on the first line of vertical active
65 */
66
67/*
68 * Called from drm generic code, passed a 'crtc', which we use as a pipe index.
69 */
70u32 i915_get_vblank_counter(struct drm_crtc *crtc)
71{
72 struct intel_display *display = to_intel_display(crtc->dev);
73 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
74 const struct drm_display_mode *mode = &vblank->hwmode;
75 enum pipe pipe = to_intel_crtc(crtc)->pipe;
76 u32 pixel, vbl_start, hsync_start, htotal;
77 u64 frame;
78
79 /*
80 * On i965gm TV output the frame counter only works up to
81 * the point when we enable the TV encoder. After that the
82 * frame counter ceases to work and reads zero. We need a
83 * vblank wait before enabling the TV encoder and so we
84 * have to enable vblank interrupts while the frame counter
85 * is still in a working state. However the core vblank code
86 * does not like us returning non-zero frame counter values
87 * when we've told it that we don't have a working frame
88 * counter. Thus we must stop non-zero values leaking out.
89 */
90 if (!vblank->max_vblank_count)
91 return 0;
92
93 htotal = mode->crtc_htotal;
94 hsync_start = mode->crtc_hsync_start;
95 vbl_start = intel_mode_vblank_start(mode);
96
97 /* Convert to pixel count */
98 vbl_start *= htotal;
99
100 /* Start of vblank event occurs at start of hsync */
101 vbl_start -= htotal - hsync_start;
102
103 /*
104 * High & low register fields aren't synchronized, so make sure
105 * we get a low value that's stable across two reads of the high
106 * register.
107 */
108 frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
109 PIPEFRAME(display, pipe));
110
111 pixel = frame & PIPE_PIXEL_MASK;
112 frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
113
114 /*
115 * The frame counter increments at beginning of active.
116 * Cook up a vblank counter by also checking the pixel
117 * counter against vblank start.
118 */
119 return (frame + (pixel >= vbl_start)) & 0xffffff;
120}
121
122u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
123{
124 struct intel_display *display = to_intel_display(crtc->dev);
125 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
126 enum pipe pipe = to_intel_crtc(crtc)->pipe;
127
128 if (!vblank->max_vblank_count)
129 return 0;
130
131 return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
132}
133
134static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
135{
136 struct intel_display *display = to_intel_display(crtc);
137 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
138 const struct drm_display_mode *mode = &vblank->hwmode;
139 u32 htotal = mode->crtc_htotal;
140 u32 clock = mode->crtc_clock;
141 u32 scan_prev_time, scan_curr_time, scan_post_time;
142
143 /*
144 * To avoid the race condition where we might cross into the
145 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
146 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
147 * during the same frame.
148 */
149 do {
150 /*
151 * This field provides read back of the display
152 * pipe frame time stamp. The time stamp value
153 * is sampled at every start of vertical blank.
154 */
155 scan_prev_time = intel_de_read_fw(display,
156 PIPE_FRMTMSTMP(crtc->pipe));
157
158 /*
159 * The TIMESTAMP_CTR register has the current
160 * time stamp value.
161 */
162 scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
163
164 scan_post_time = intel_de_read_fw(display,
165 PIPE_FRMTMSTMP(crtc->pipe));
166 } while (scan_post_time != scan_prev_time);
167
168 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
169 clock), 1000 * htotal);
170}
171
172/*
173 * On certain encoders on certain platforms, pipe
174 * scanline register will not work to get the scanline,
175 * since the timings are driven from the PORT or issues
176 * with scanline register updates.
177 * This function will use Framestamp and current
178 * timestamp registers to calculate the scanline.
179 */
180static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
181{
182 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
183 const struct drm_display_mode *mode = &vblank->hwmode;
184 u32 vblank_start = mode->crtc_vblank_start;
185 u32 vtotal = mode->crtc_vtotal;
186 u32 scanline;
187
188 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
189 scanline = min(scanline, vtotal - 1);
190 scanline = (scanline + vblank_start) % vtotal;
191
192 return scanline;
193}
194
195int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
196{
197 struct intel_display *display = to_intel_display(crtc_state);
198
199 /*
200 * The scanline counter increments at the leading edge of hsync.
201 *
202 * On most platforms it starts counting from vtotal-1 on the
203 * first active line. That means the scanline counter value is
204 * always one less than what we would expect. Ie. just after
205 * start of vblank, which also occurs at start of hsync (on the
206 * last active line), the scanline counter will read vblank_start-1.
207 *
208 * On gen2 the scanline counter starts counting from 1 instead
209 * of vtotal-1, so we have to subtract one.
210 *
211 * On HSW+ the behaviour of the scanline counter depends on the output
212 * type. For DP ports it behaves like most other platforms, but on HDMI
213 * there's an extra 1 line difference. So we need to add two instead of
214 * one to the value.
215 *
216 * On VLV/CHV DSI the scanline counter would appear to increment
217 * approx. 1/3 of a scanline before start of vblank. Unfortunately
218 * that means we can't tell whether we're in vblank or not while
219 * we're on that particular line. We must still set scanline_offset
220 * to 1 so that the vblank timestamps come out correct when we query
221 * the scanline counter from within the vblank interrupt handler.
222 * However if queried just before the start of vblank we'll get an
223 * answer that's slightly in the future.
224 */
225 if (DISPLAY_VER(display) == 2)
226 return -1;
227 else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
228 return 2;
229 else
230 return 1;
231}
232
233/*
234 * intel_de_read_fw(), only for fast reads of display block, no need for
235 * forcewake etc.
236 */
237static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
238{
239 struct intel_display *display = to_intel_display(crtc);
240 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
241 const struct drm_display_mode *mode = &vblank->hwmode;
242 enum pipe pipe = crtc->pipe;
243 int position, vtotal;
244
245 if (!crtc->active)
246 return 0;
247
248 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
249 return __intel_get_crtc_scanline_from_timestamp(crtc);
250
251 vtotal = intel_mode_vtotal(mode);
252
253 position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
254
255 /*
256 * On HSW, the DSL reg (0x70000) appears to return 0 if we
257 * read it just before the start of vblank. So try it again
258 * so we don't accidentally end up spanning a vblank frame
259 * increment, causing the pipe_update_end() code to squak at us.
260 *
261 * The nature of this problem means we can't simply check the ISR
262 * bit and return the vblank start value; nor can we use the scanline
263 * debug register in the transcoder as it appears to have the same
264 * problem. We may need to extend this to include other platforms,
265 * but so far testing only shows the problem on HSW.
266 */
267 if (HAS_DDI(display) && !position) {
268 int i, temp;
269
270 for (i = 0; i < 100; i++) {
271 udelay(1);
272 temp = intel_de_read_fw(display,
273 PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
274 if (temp != position) {
275 position = temp;
276 break;
277 }
278 }
279 }
280
281 /*
282 * See update_scanline_offset() for the details on the
283 * scanline_offset adjustment.
284 */
285 return (position + vtotal + crtc->scanline_offset) % vtotal;
286}
287
288/*
289 * The uncore version of the spin lock functions is used to decide
290 * whether we need to lock the uncore lock or not. This is only
291 * needed in i915, not in Xe.
292 *
293 * This lock in i915 is needed because some old platforms (at least
294 * IVB and possibly HSW as well), which are not supported in Xe, need
295 * all register accesses to the same cacheline to be serialized,
296 * otherwise they may hang.
297 */
298#ifdef I915
299static void intel_vblank_section_enter(struct intel_display *display)
300 __acquires(i915->uncore.lock)
301{
302 struct drm_i915_private *i915 = to_i915(display->drm);
303 spin_lock(&i915->uncore.lock);
304}
305
306static void intel_vblank_section_exit(struct intel_display *display)
307 __releases(i915->uncore.lock)
308{
309 struct drm_i915_private *i915 = to_i915(display->drm);
310 spin_unlock(&i915->uncore.lock);
311}
312#else
313static void intel_vblank_section_enter(struct intel_display *display)
314{
315}
316
317static void intel_vblank_section_exit(struct intel_display *display)
318{
319}
320#endif
321
322static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
323 bool in_vblank_irq,
324 int *vpos, int *hpos,
325 ktime_t *stime, ktime_t *etime,
326 const struct drm_display_mode *mode)
327{
328 struct intel_display *display = to_intel_display(_crtc->dev);
329 struct intel_crtc *crtc = to_intel_crtc(_crtc);
330 enum pipe pipe = crtc->pipe;
331 int position;
332 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
333 unsigned long irqflags;
334 bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
335 display->platform.g4x || DISPLAY_VER(display) == 2 ||
336 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
337
338 if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
339 drm_dbg(display->drm,
340 "trying to get scanoutpos for disabled pipe %c\n",
341 pipe_name(pipe));
342 return false;
343 }
344
345 htotal = mode->crtc_htotal;
346 hsync_start = mode->crtc_hsync_start;
347 vtotal = intel_mode_vtotal(mode);
348 vbl_start = intel_mode_vblank_start(mode);
349 vbl_end = intel_mode_vblank_end(mode);
350
351 /*
352 * Enter vblank critical section, as we will do multiple
353 * timing critical raw register reads, potentially with
354 * preemption disabled, so the following code must not block.
355 */
356 local_irq_save(irqflags);
357 intel_vblank_section_enter(display);
358
359 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
360
361 /* Get optional system timestamp before query. */
362 if (stime)
363 *stime = ktime_get();
364
365 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
366 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
367
368 position = __intel_get_crtc_scanline(crtc);
369
370 /*
371 * Already exiting vblank? If so, shift our position
372 * so it looks like we're already apporaching the full
373 * vblank end. This should make the generated timestamp
374 * more or less match when the active portion will start.
375 */
376 if (position >= vbl_start && scanlines < position)
377 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
378 } else if (use_scanline_counter) {
379 /* No obvious pixelcount register. Only query vertical
380 * scanout position from Display scan line register.
381 */
382 position = __intel_get_crtc_scanline(crtc);
383 } else {
384 /*
385 * Have access to pixelcount since start of frame.
386 * We can split this into vertical and horizontal
387 * scanout position.
388 */
389 position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
390
391 /* convert to pixel counts */
392 vbl_start *= htotal;
393 vbl_end *= htotal;
394 vtotal *= htotal;
395
396 /*
397 * In interlaced modes, the pixel counter counts all pixels,
398 * so one field will have htotal more pixels. In order to avoid
399 * the reported position from jumping backwards when the pixel
400 * counter is beyond the length of the shorter field, just
401 * clamp the position the length of the shorter field. This
402 * matches how the scanline counter based position works since
403 * the scanline counter doesn't count the two half lines.
404 */
405 position = min(position, vtotal - 1);
406
407 /*
408 * Start of vblank interrupt is triggered at start of hsync,
409 * just prior to the first active line of vblank. However we
410 * consider lines to start at the leading edge of horizontal
411 * active. So, should we get here before we've crossed into
412 * the horizontal active of the first line in vblank, we would
413 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
414 * always add htotal-hsync_start to the current pixel position.
415 */
416 position = (position + htotal - hsync_start) % vtotal;
417 }
418
419 /* Get optional system timestamp after query. */
420 if (etime)
421 *etime = ktime_get();
422
423 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
424
425 intel_vblank_section_exit(display);
426 local_irq_restore(irqflags);
427
428 /*
429 * While in vblank, position will be negative
430 * counting up towards 0 at vbl_end. And outside
431 * vblank, position will be positive counting
432 * up since vbl_end.
433 */
434 if (position >= vbl_start)
435 position -= vbl_end;
436 else
437 position += vtotal - vbl_end;
438
439 if (use_scanline_counter) {
440 *vpos = position;
441 *hpos = 0;
442 } else {
443 *vpos = position / htotal;
444 *hpos = position - (*vpos * htotal);
445 }
446
447 return true;
448}
449
450bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
451 ktime_t *vblank_time, bool in_vblank_irq)
452{
453 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
454 crtc, max_error, vblank_time, in_vblank_irq,
455 i915_get_crtc_scanoutpos);
456}
457
458int intel_get_crtc_scanline(struct intel_crtc *crtc)
459{
460 struct intel_display *display = to_intel_display(crtc);
461 unsigned long irqflags;
462 int position;
463
464 local_irq_save(irqflags);
465 intel_vblank_section_enter(display);
466
467 position = __intel_get_crtc_scanline(crtc);
468
469 intel_vblank_section_exit(display);
470 local_irq_restore(irqflags);
471
472 return position;
473}
474
475static bool pipe_scanline_is_moving(struct intel_display *display,
476 enum pipe pipe)
477{
478 i915_reg_t reg = PIPEDSL(display, pipe);
479 u32 line1, line2;
480
481 line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
482 msleep(5);
483 line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
484
485 return line1 != line2;
486}
487
488static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
489{
490 struct intel_display *display = to_intel_display(crtc);
491 enum pipe pipe = crtc->pipe;
492
493 /* Wait for the display line to settle/start moving */
494 if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
495 drm_err(display->drm,
496 "pipe %c scanline %s wait timed out\n",
497 pipe_name(pipe), str_on_off(state));
498}
499
500void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
501{
502 wait_for_pipe_scanline_moving(crtc, false);
503}
504
505void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
506{
507 wait_for_pipe_scanline_moving(crtc, true);
508}
509
510void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
511 bool vrr_enable)
512{
513 struct intel_display *display = to_intel_display(crtc_state);
514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
515 u8 mode_flags = crtc_state->mode_flags;
516 struct drm_display_mode adjusted_mode;
517 int vmax_vblank_start = 0;
518 unsigned long irqflags;
519
520 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
521
522 if (vrr_enable) {
523 drm_WARN_ON(display->drm,
524 (mode_flags & I915_MODE_FLAG_VRR) == 0);
525
526 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
527 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
528 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
529 vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
530 } else {
531 mode_flags &= ~I915_MODE_FLAG_VRR;
532 }
533
534 /*
535 * Belts and suspenders locking to guarantee everyone sees 100%
536 * consistent state during fastset seamless refresh rate changes.
537 *
538 * vblank_time_lock takes care of all drm_vblank.c stuff, and
539 * uncore.lock takes care of __intel_get_crtc_scanline() which
540 * may get called elsewhere as well.
541 *
542 * TODO maybe just protect everything (including
543 * __intel_get_crtc_scanline()) with vblank_time_lock?
544 * Need to audit everything to make sure it's safe.
545 */
546 spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
547 intel_vblank_section_enter(display);
548
549 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
550
551 crtc->vmax_vblank_start = vmax_vblank_start;
552
553 crtc->mode_flags = mode_flags;
554
555 crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
556 intel_vblank_section_exit(display);
557 spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
558}
559
560int intel_mode_vdisplay(const struct drm_display_mode *mode)
561{
562 int vdisplay = mode->crtc_vdisplay;
563
564 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
565 vdisplay = DIV_ROUND_UP(vdisplay, 2);
566
567 return vdisplay;
568}
569
570int intel_mode_vblank_start(const struct drm_display_mode *mode)
571{
572 int vblank_start = mode->crtc_vblank_start;
573
574 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
575 vblank_start = DIV_ROUND_UP(vblank_start, 2);
576
577 return vblank_start;
578}
579
580int intel_mode_vblank_end(const struct drm_display_mode *mode)
581{
582 int vblank_end = mode->crtc_vblank_end;
583
584 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
585 vblank_end /= 2;
586
587 return vblank_end;
588}
589
590int intel_mode_vtotal(const struct drm_display_mode *mode)
591{
592 int vtotal = mode->crtc_vtotal;
593
594 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
595 vtotal /= 2;
596
597 return vtotal;
598}
599
600void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
601 const struct intel_crtc_state *new_crtc_state,
602 struct intel_vblank_evade_ctx *evade)
603{
604 struct intel_display *display = to_intel_display(new_crtc_state);
605 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
606 const struct intel_crtc_state *crtc_state;
607 const struct drm_display_mode *adjusted_mode;
608
609 evade->crtc = crtc;
610
611 evade->need_vlv_dsi_wa = (display->platform.valleyview ||
612 display->platform.cherryview) &&
613 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
614
615 /*
616 * During fastsets/etc. the transcoder is still
617 * running with the old timings at this point.
618 *
619 * TODO: maybe just use the active timings here?
620 */
621 if (intel_crtc_needs_modeset(new_crtc_state))
622 crtc_state = new_crtc_state;
623 else
624 crtc_state = old_crtc_state;
625
626 adjusted_mode = &crtc_state->hw.adjusted_mode;
627
628 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
629 /* timing changes should happen with VRR disabled */
630 drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
631 new_crtc_state->update_m_n || new_crtc_state->update_lrr);
632
633 if (intel_vrr_is_push_sent(crtc_state))
634 evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
635 else
636 evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
637 } else {
638 evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
639 }
640
641 /* FIXME needs to be calibrated sensibly */
642 evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
643 VBLANK_EVASION_TIME_US);
644 evade->max = evade->vblank_start - 1;
645
646 /*
647 * M/N and TRANS_VTOTAL are double buffered on the transcoder's
648 * undelayed vblank, so with seamless M/N and LRR we must evade
649 * both vblanks.
650 *
651 * DSB execution waits for the transcoder's undelayed vblank,
652 * hence we must kick off the commit before that.
653 */
654 if (intel_color_uses_dsb(new_crtc_state) ||
655 new_crtc_state->update_m_n || new_crtc_state->update_lrr)
656 evade->min -= intel_mode_vblank_start(adjusted_mode) -
657 intel_mode_vdisplay(adjusted_mode);
658}
659
660/* must be called with vblank interrupt already enabled! */
661int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
662{
663 struct intel_crtc *crtc = evade->crtc;
664 struct intel_display *display = to_intel_display(crtc);
665 long timeout = msecs_to_jiffies_timeout(1);
666 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
667 DEFINE_WAIT(wait);
668 int scanline;
669
670 if (evade->min <= 0 || evade->max <= 0)
671 return 0;
672
673 for (;;) {
674 /*
675 * prepare_to_wait() has a memory barrier, which guarantees
676 * other CPUs can see the task state update by the time we
677 * read the scanline.
678 */
679 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
680
681 scanline = intel_get_crtc_scanline(crtc);
682 if (scanline < evade->min || scanline > evade->max)
683 break;
684
685 if (!timeout) {
686 drm_err(display->drm,
687 "Potential atomic update failure on pipe %c\n",
688 pipe_name(crtc->pipe));
689 break;
690 }
691
692 local_irq_enable();
693
694 timeout = schedule_timeout(timeout);
695
696 local_irq_disable();
697 }
698
699 finish_wait(wq, &wait);
700
701 /*
702 * On VLV/CHV DSI the scanline counter would appear to
703 * increment approx. 1/3 of a scanline before start of vblank.
704 * The registers still get latched at start of vblank however.
705 * This means we must not write any registers on the first
706 * line of vblank (since not the whole line is actually in
707 * vblank). And unfortunately we can't use the interrupt to
708 * wait here since it will fire too soon. We could use the
709 * frame start interrupt instead since it will fire after the
710 * critical scanline, but that would require more changes
711 * in the interrupt code. So for now we'll just do the nasty
712 * thing and poll for the bad scanline to pass us by.
713 *
714 * FIXME figure out if BXT+ DSI suffers from this as well
715 */
716 while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
717 scanline = intel_get_crtc_scanline(crtc);
718
719 return scanline;
720}