1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2024 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_TDF_H__
 7#define __INTEL_TDF_H__
 8
 9/*
10 * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can
11 * be enabled through various PAT index modes. Idea is to use this caching mode
12 * when for example rendering onto the display surface, with the promise that
13 * KMD will ensure transient cache entries are always flushed by the time we do
14 * the display flip, since display engine is never coherent with CPU/GPU caches.
15 */
16
17struct drm_i915_private;
18
19#ifdef I915
20static inline void intel_td_flush(struct drm_i915_private *i915) {}
21#else
22void intel_td_flush(struct drm_i915_private *i915);
23#endif
24
25#endif