Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28
29#include <drm/drm_fourcc.h>
30
31#include "gem/i915_gem_internal.h"
32#include "gem/i915_gem_object_frontbuffer.h"
33#include "gem/i915_gem_pm.h"
34#include "gt/intel_gpu_commands.h"
35#include "gt/intel_ring.h"
36
37#include "i915_drv.h"
38#include "i915_reg.h"
39#include "intel_color_regs.h"
40#include "intel_de.h"
41#include "intel_display_types.h"
42#include "intel_frontbuffer.h"
43#include "intel_overlay.h"
44#include "intel_pci_config.h"
45
46/* Limits for overlay size. According to intel doc, the real limits are:
47 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
48 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
49 * the mininum of both. */
50#define IMAGE_MAX_WIDTH 2048
51#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
52/* on 830 and 845 these large limits result in the card hanging */
53#define IMAGE_MAX_WIDTH_LEGACY 1024
54#define IMAGE_MAX_HEIGHT_LEGACY 1088
55
56/* overlay register definitions */
57/* OCMD register */
58#define OCMD_TILED_SURFACE (0x1<<19)
59#define OCMD_MIRROR_MASK (0x3<<17)
60#define OCMD_MIRROR_MODE (0x3<<17)
61#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
62#define OCMD_MIRROR_VERTICAL (0x2<<17)
63#define OCMD_MIRROR_BOTH (0x3<<17)
64#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
65#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
66#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
67#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
68#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
69#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
70#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
71#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
72#define OCMD_YUV_422_PACKED (0x8<<10)
73#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
74#define OCMD_YUV_420_PLANAR (0xc<<10)
75#define OCMD_YUV_422_PLANAR (0xd<<10)
76#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
77#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
78#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
79#define OCMD_BUF_TYPE_MASK (0x1<<5)
80#define OCMD_BUF_TYPE_FRAME (0x0<<5)
81#define OCMD_BUF_TYPE_FIELD (0x1<<5)
82#define OCMD_TEST_MODE (0x1<<4)
83#define OCMD_BUFFER_SELECT (0x3<<2)
84#define OCMD_BUFFER0 (0x0<<2)
85#define OCMD_BUFFER1 (0x1<<2)
86#define OCMD_FIELD_SELECT (0x1<<2)
87#define OCMD_FIELD0 (0x0<<1)
88#define OCMD_FIELD1 (0x1<<1)
89#define OCMD_ENABLE (0x1<<0)
90
91/* OCONFIG register */
92#define OCONF_PIPE_MASK (0x1<<18)
93#define OCONF_PIPE_A (0x0<<18)
94#define OCONF_PIPE_B (0x1<<18)
95#define OCONF_GAMMA2_ENABLE (0x1<<16)
96#define OCONF_CSC_MODE_BT601 (0x0<<5)
97#define OCONF_CSC_MODE_BT709 (0x1<<5)
98#define OCONF_CSC_BYPASS (0x1<<4)
99#define OCONF_CC_OUT_8BIT (0x1<<3)
100#define OCONF_TEST_MODE (0x1<<2)
101#define OCONF_THREE_LINE_BUFFER (0x1<<0)
102#define OCONF_TWO_LINE_BUFFER (0x0<<0)
103
104/* DCLRKM (dst-key) register */
105#define DST_KEY_ENABLE (0x1<<31)
106#define CLK_RGB24_MASK 0x0
107#define CLK_RGB16_MASK 0x070307
108#define CLK_RGB15_MASK 0x070707
109
110#define RGB30_TO_COLORKEY(c) \
111 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
112#define RGB16_TO_COLORKEY(c) \
113 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
114#define RGB15_TO_COLORKEY(c) \
115 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
116#define RGB8I_TO_COLORKEY(c) \
117 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
118
119/* overlay flip addr flag */
120#define OFC_UPDATE 0x1
121
122/* polyphase filter coefficients */
123#define N_HORIZ_Y_TAPS 5
124#define N_VERT_Y_TAPS 3
125#define N_HORIZ_UV_TAPS 3
126#define N_VERT_UV_TAPS 3
127#define N_PHASES 17
128#define MAX_TAPS 5
129
130/* memory bufferd overlay registers */
131struct overlay_registers {
132 u32 OBUF_0Y;
133 u32 OBUF_1Y;
134 u32 OBUF_0U;
135 u32 OBUF_0V;
136 u32 OBUF_1U;
137 u32 OBUF_1V;
138 u32 OSTRIDE;
139 u32 YRGB_VPH;
140 u32 UV_VPH;
141 u32 HORZ_PH;
142 u32 INIT_PHS;
143 u32 DWINPOS;
144 u32 DWINSZ;
145 u32 SWIDTH;
146 u32 SWIDTHSW;
147 u32 SHEIGHT;
148 u32 YRGBSCALE;
149 u32 UVSCALE;
150 u32 OCLRC0;
151 u32 OCLRC1;
152 u32 DCLRKV;
153 u32 DCLRKM;
154 u32 SCLRKVH;
155 u32 SCLRKVL;
156 u32 SCLRKEN;
157 u32 OCONFIG;
158 u32 OCMD;
159 u32 RESERVED1; /* 0x6C */
160 u32 OSTART_0Y;
161 u32 OSTART_1Y;
162 u32 OSTART_0U;
163 u32 OSTART_0V;
164 u32 OSTART_1U;
165 u32 OSTART_1V;
166 u32 OTILEOFF_0Y;
167 u32 OTILEOFF_1Y;
168 u32 OTILEOFF_0U;
169 u32 OTILEOFF_0V;
170 u32 OTILEOFF_1U;
171 u32 OTILEOFF_1V;
172 u32 FASTHSCALE; /* 0xA0 */
173 u32 UVSCALEV; /* 0xA4 */
174 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
175 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
176 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
177 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
178 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
179 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
180 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
181 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
182 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
183};
184
185struct intel_overlay {
186 struct drm_i915_private *i915;
187 struct intel_context *context;
188 struct intel_crtc *crtc;
189 struct i915_vma *vma;
190 struct i915_vma *old_vma;
191 struct intel_frontbuffer *frontbuffer;
192 bool active;
193 bool pfit_active;
194 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
195 u32 color_key:24;
196 u32 color_key_enabled:1;
197 u32 brightness, contrast, saturation;
198 u32 old_xscale, old_yscale;
199 /* register access */
200 struct drm_i915_gem_object *reg_bo;
201 struct overlay_registers __iomem *regs;
202 u32 flip_addr;
203 /* flip handling */
204 struct i915_active last_flip;
205 void (*flip_complete)(struct intel_overlay *ovl);
206};
207
208static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
209 bool enable)
210{
211 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
212 u8 val;
213
214 /* WA_OVERLAY_CLKGATE:alm */
215 if (enable)
216 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);
217 else
218 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),
219 OVRUNIT_CLOCK_GATE_DISABLE);
220
221 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
222 pci_bus_read_config_byte(pdev->bus,
223 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
224 if (enable)
225 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
226 else
227 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
228 pci_bus_write_config_byte(pdev->bus,
229 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
230}
231
232static struct i915_request *
233alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
234{
235 struct i915_request *rq;
236 int err;
237
238 overlay->flip_complete = fn;
239
240 rq = i915_request_create(overlay->context);
241 if (IS_ERR(rq))
242 return rq;
243
244 err = i915_active_add_request(&overlay->last_flip, rq);
245 if (err) {
246 i915_request_add(rq);
247 return ERR_PTR(err);
248 }
249
250 return rq;
251}
252
253/* overlay needs to be disable in OCMD reg */
254static int intel_overlay_on(struct intel_overlay *overlay)
255{
256 struct drm_i915_private *dev_priv = overlay->i915;
257 struct i915_request *rq;
258 u32 *cs;
259
260 drm_WARN_ON(&dev_priv->drm, overlay->active);
261
262 rq = alloc_request(overlay, NULL);
263 if (IS_ERR(rq))
264 return PTR_ERR(rq);
265
266 cs = intel_ring_begin(rq, 4);
267 if (IS_ERR(cs)) {
268 i915_request_add(rq);
269 return PTR_ERR(cs);
270 }
271
272 overlay->active = true;
273
274 if (IS_I830(dev_priv))
275 i830_overlay_clock_gating(dev_priv, false);
276
277 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
278 *cs++ = overlay->flip_addr | OFC_UPDATE;
279 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
280 *cs++ = MI_NOOP;
281 intel_ring_advance(rq, cs);
282
283 i915_request_add(rq);
284
285 return i915_active_wait(&overlay->last_flip);
286}
287
288static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
289 struct i915_vma *vma)
290{
291 enum pipe pipe = overlay->crtc->pipe;
292 struct intel_frontbuffer *frontbuffer = NULL;
293
294 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
295
296 if (vma)
297 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj));
298
299 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
300 INTEL_FRONTBUFFER_OVERLAY(pipe));
301
302 if (overlay->frontbuffer)
303 intel_frontbuffer_put(overlay->frontbuffer);
304 overlay->frontbuffer = frontbuffer;
305
306 intel_frontbuffer_flip_prepare(overlay->i915,
307 INTEL_FRONTBUFFER_OVERLAY(pipe));
308
309 overlay->old_vma = overlay->vma;
310 if (vma)
311 overlay->vma = i915_vma_get(vma);
312 else
313 overlay->vma = NULL;
314}
315
316/* overlay needs to be enabled in OCMD reg */
317static int intel_overlay_continue(struct intel_overlay *overlay,
318 struct i915_vma *vma,
319 bool load_polyphase_filter)
320{
321 struct drm_i915_private *dev_priv = overlay->i915;
322 struct i915_request *rq;
323 u32 flip_addr = overlay->flip_addr;
324 u32 tmp, *cs;
325
326 drm_WARN_ON(&dev_priv->drm, !overlay->active);
327
328 if (load_polyphase_filter)
329 flip_addr |= OFC_UPDATE;
330
331 /* check for underruns */
332 tmp = intel_de_read(dev_priv, DOVSTA);
333 if (tmp & (1 << 17))
334 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
335
336 rq = alloc_request(overlay, NULL);
337 if (IS_ERR(rq))
338 return PTR_ERR(rq);
339
340 cs = intel_ring_begin(rq, 2);
341 if (IS_ERR(cs)) {
342 i915_request_add(rq);
343 return PTR_ERR(cs);
344 }
345
346 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
347 *cs++ = flip_addr;
348 intel_ring_advance(rq, cs);
349
350 intel_overlay_flip_prepare(overlay, vma);
351 i915_request_add(rq);
352
353 return 0;
354}
355
356static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
357{
358 struct i915_vma *vma;
359
360 vma = fetch_and_zero(&overlay->old_vma);
361 if (drm_WARN_ON(&overlay->i915->drm, !vma))
362 return;
363
364 intel_frontbuffer_flip_complete(overlay->i915,
365 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
366
367 i915_vma_unpin(vma);
368 i915_vma_put(vma);
369}
370
371static void
372intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
373{
374 intel_overlay_release_old_vma(overlay);
375}
376
377static void intel_overlay_off_tail(struct intel_overlay *overlay)
378{
379 struct drm_i915_private *dev_priv = overlay->i915;
380
381 intel_overlay_release_old_vma(overlay);
382
383 overlay->crtc->overlay = NULL;
384 overlay->crtc = NULL;
385 overlay->active = false;
386
387 if (IS_I830(dev_priv))
388 i830_overlay_clock_gating(dev_priv, true);
389}
390
391static void intel_overlay_last_flip_retire(struct i915_active *active)
392{
393 struct intel_overlay *overlay =
394 container_of(active, typeof(*overlay), last_flip);
395
396 if (overlay->flip_complete)
397 overlay->flip_complete(overlay);
398}
399
400/* overlay needs to be disabled in OCMD reg */
401static int intel_overlay_off(struct intel_overlay *overlay)
402{
403 struct i915_request *rq;
404 u32 *cs, flip_addr = overlay->flip_addr;
405
406 drm_WARN_ON(&overlay->i915->drm, !overlay->active);
407
408 /* According to intel docs the overlay hw may hang (when switching
409 * off) without loading the filter coeffs. It is however unclear whether
410 * this applies to the disabling of the overlay or to the switching off
411 * of the hw. Do it in both cases */
412 flip_addr |= OFC_UPDATE;
413
414 rq = alloc_request(overlay, intel_overlay_off_tail);
415 if (IS_ERR(rq))
416 return PTR_ERR(rq);
417
418 cs = intel_ring_begin(rq, 6);
419 if (IS_ERR(cs)) {
420 i915_request_add(rq);
421 return PTR_ERR(cs);
422 }
423
424 /* wait for overlay to go idle */
425 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
426 *cs++ = flip_addr;
427 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
428
429 /* turn overlay off */
430 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
431 *cs++ = flip_addr;
432 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
433
434 intel_ring_advance(rq, cs);
435
436 intel_overlay_flip_prepare(overlay, NULL);
437 i915_request_add(rq);
438
439 return i915_active_wait(&overlay->last_flip);
440}
441
442/* recover from an interruption due to a signal
443 * We have to be careful not to repeat work forever an make forward progess. */
444static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
445{
446 return i915_active_wait(&overlay->last_flip);
447}
448
449/* Wait for pending overlay flip and release old frame.
450 * Needs to be called before the overlay register are changed
451 * via intel_overlay_(un)map_regs
452 */
453static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
454{
455 struct drm_i915_private *dev_priv = overlay->i915;
456 struct i915_request *rq;
457 u32 *cs;
458
459 /*
460 * Only wait if there is actually an old frame to release to
461 * guarantee forward progress.
462 */
463 if (!overlay->old_vma)
464 return 0;
465
466 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
467 intel_overlay_release_old_vid_tail(overlay);
468 return 0;
469 }
470
471 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
472 if (IS_ERR(rq))
473 return PTR_ERR(rq);
474
475 cs = intel_ring_begin(rq, 2);
476 if (IS_ERR(cs)) {
477 i915_request_add(rq);
478 return PTR_ERR(cs);
479 }
480
481 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
482 *cs++ = MI_NOOP;
483 intel_ring_advance(rq, cs);
484
485 i915_request_add(rq);
486
487 return i915_active_wait(&overlay->last_flip);
488}
489
490void intel_overlay_reset(struct drm_i915_private *dev_priv)
491{
492 struct intel_overlay *overlay = dev_priv->display.overlay;
493
494 if (!overlay)
495 return;
496
497 overlay->old_xscale = 0;
498 overlay->old_yscale = 0;
499 overlay->crtc = NULL;
500 overlay->active = false;
501}
502
503static int packed_depth_bytes(u32 format)
504{
505 switch (format & I915_OVERLAY_DEPTH_MASK) {
506 case I915_OVERLAY_YUV422:
507 return 4;
508 case I915_OVERLAY_YUV411:
509 /* return 6; not implemented */
510 default:
511 return -EINVAL;
512 }
513}
514
515static int packed_width_bytes(u32 format, short width)
516{
517 switch (format & I915_OVERLAY_DEPTH_MASK) {
518 case I915_OVERLAY_YUV422:
519 return width << 1;
520 default:
521 return -EINVAL;
522 }
523}
524
525static int uv_hsubsampling(u32 format)
526{
527 switch (format & I915_OVERLAY_DEPTH_MASK) {
528 case I915_OVERLAY_YUV422:
529 case I915_OVERLAY_YUV420:
530 return 2;
531 case I915_OVERLAY_YUV411:
532 case I915_OVERLAY_YUV410:
533 return 4;
534 default:
535 return -EINVAL;
536 }
537}
538
539static int uv_vsubsampling(u32 format)
540{
541 switch (format & I915_OVERLAY_DEPTH_MASK) {
542 case I915_OVERLAY_YUV420:
543 case I915_OVERLAY_YUV410:
544 return 2;
545 case I915_OVERLAY_YUV422:
546 case I915_OVERLAY_YUV411:
547 return 1;
548 default:
549 return -EINVAL;
550 }
551}
552
553static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
554{
555 u32 sw;
556
557 if (DISPLAY_VER(dev_priv) == 2)
558 sw = ALIGN((offset & 31) + width, 32);
559 else
560 sw = ALIGN((offset & 63) + width, 64);
561
562 if (sw == 0)
563 return 0;
564
565 return (sw - 32) >> 3;
566}
567
568static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
569 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
570 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
571 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
572 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
573 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
574 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
575 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
576 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
577 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
578 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
579 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
580 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
581 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
582 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
583 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
584 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
585 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
586};
587
588static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
589 [ 0] = { 0x3000, 0x1800, 0x1800, },
590 [ 1] = { 0xb000, 0x18d0, 0x2e60, },
591 [ 2] = { 0xb000, 0x1990, 0x2ce0, },
592 [ 3] = { 0xb020, 0x1a68, 0x2b40, },
593 [ 4] = { 0xb040, 0x1b20, 0x29e0, },
594 [ 5] = { 0xb060, 0x1bd8, 0x2880, },
595 [ 6] = { 0xb080, 0x1c88, 0x3e60, },
596 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
597 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
598 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
599 [10] = { 0xb100, 0x1eb8, 0x3620, },
600 [11] = { 0xb100, 0x1f18, 0x34a0, },
601 [12] = { 0xb100, 0x1f68, 0x3360, },
602 [13] = { 0xb0e0, 0x1fa8, 0x3240, },
603 [14] = { 0xb0c0, 0x1fe0, 0x3140, },
604 [15] = { 0xb060, 0x1ff0, 0x30a0, },
605 [16] = { 0x3000, 0x0800, 0x3000, },
606};
607
608static void update_polyphase_filter(struct overlay_registers __iomem *regs)
609{
610 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
611 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
612 sizeof(uv_static_hcoeffs));
613}
614
615static bool update_scaling_factors(struct intel_overlay *overlay,
616 struct overlay_registers __iomem *regs,
617 struct drm_intel_overlay_put_image *params)
618{
619 /* fixed point with a 12 bit shift */
620 u32 xscale, yscale, xscale_UV, yscale_UV;
621#define FP_SHIFT 12
622#define FRACT_MASK 0xfff
623 bool scale_changed = false;
624 int uv_hscale = uv_hsubsampling(params->flags);
625 int uv_vscale = uv_vsubsampling(params->flags);
626
627 if (params->dst_width > 1)
628 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
629 params->dst_width;
630 else
631 xscale = 1 << FP_SHIFT;
632
633 if (params->dst_height > 1)
634 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
635 params->dst_height;
636 else
637 yscale = 1 << FP_SHIFT;
638
639 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
640 xscale_UV = xscale/uv_hscale;
641 yscale_UV = yscale/uv_vscale;
642 /* make the Y scale to UV scale ratio an exact multiply */
643 xscale = xscale_UV * uv_hscale;
644 yscale = yscale_UV * uv_vscale;
645 /*} else {
646 xscale_UV = 0;
647 yscale_UV = 0;
648 }*/
649
650 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
651 scale_changed = true;
652 overlay->old_xscale = xscale;
653 overlay->old_yscale = yscale;
654
655 iowrite32(((yscale & FRACT_MASK) << 20) |
656 ((xscale >> FP_SHIFT) << 16) |
657 ((xscale & FRACT_MASK) << 3),
658 ®s->YRGBSCALE);
659
660 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
661 ((xscale_UV >> FP_SHIFT) << 16) |
662 ((xscale_UV & FRACT_MASK) << 3),
663 ®s->UVSCALE);
664
665 iowrite32((((yscale >> FP_SHIFT) << 16) |
666 ((yscale_UV >> FP_SHIFT) << 0)),
667 ®s->UVSCALEV);
668
669 if (scale_changed)
670 update_polyphase_filter(regs);
671
672 return scale_changed;
673}
674
675static void update_colorkey(struct intel_overlay *overlay,
676 struct overlay_registers __iomem *regs)
677{
678 const struct intel_plane_state *state =
679 to_intel_plane_state(overlay->crtc->base.primary->state);
680 u32 key = overlay->color_key;
681 u32 format = 0;
682 u32 flags = 0;
683
684 if (overlay->color_key_enabled)
685 flags |= DST_KEY_ENABLE;
686
687 if (state->uapi.visible)
688 format = state->hw.fb->format->format;
689
690 switch (format) {
691 case DRM_FORMAT_C8:
692 key = RGB8I_TO_COLORKEY(key);
693 flags |= CLK_RGB24_MASK;
694 break;
695 case DRM_FORMAT_XRGB1555:
696 key = RGB15_TO_COLORKEY(key);
697 flags |= CLK_RGB15_MASK;
698 break;
699 case DRM_FORMAT_RGB565:
700 key = RGB16_TO_COLORKEY(key);
701 flags |= CLK_RGB16_MASK;
702 break;
703 case DRM_FORMAT_XRGB2101010:
704 case DRM_FORMAT_XBGR2101010:
705 key = RGB30_TO_COLORKEY(key);
706 flags |= CLK_RGB24_MASK;
707 break;
708 default:
709 flags |= CLK_RGB24_MASK;
710 break;
711 }
712
713 iowrite32(key, ®s->DCLRKV);
714 iowrite32(flags, ®s->DCLRKM);
715}
716
717static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
718{
719 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
720
721 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
722 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
723 case I915_OVERLAY_YUV422:
724 cmd |= OCMD_YUV_422_PLANAR;
725 break;
726 case I915_OVERLAY_YUV420:
727 cmd |= OCMD_YUV_420_PLANAR;
728 break;
729 case I915_OVERLAY_YUV411:
730 case I915_OVERLAY_YUV410:
731 cmd |= OCMD_YUV_410_PLANAR;
732 break;
733 }
734 } else { /* YUV packed */
735 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
736 case I915_OVERLAY_YUV422:
737 cmd |= OCMD_YUV_422_PACKED;
738 break;
739 case I915_OVERLAY_YUV411:
740 cmd |= OCMD_YUV_411_PACKED;
741 break;
742 }
743
744 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
745 case I915_OVERLAY_NO_SWAP:
746 break;
747 case I915_OVERLAY_UV_SWAP:
748 cmd |= OCMD_UV_SWAP;
749 break;
750 case I915_OVERLAY_Y_SWAP:
751 cmd |= OCMD_Y_SWAP;
752 break;
753 case I915_OVERLAY_Y_AND_UV_SWAP:
754 cmd |= OCMD_Y_AND_UV_SWAP;
755 break;
756 }
757 }
758
759 return cmd;
760}
761
762static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
763{
764 struct i915_gem_ww_ctx ww;
765 struct i915_vma *vma;
766 int ret;
767
768 i915_gem_ww_ctx_init(&ww, true);
769retry:
770 ret = i915_gem_object_lock(new_bo, &ww);
771 if (!ret) {
772 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0,
773 NULL, PIN_MAPPABLE);
774 ret = PTR_ERR_OR_ZERO(vma);
775 }
776 if (ret == -EDEADLK) {
777 ret = i915_gem_ww_ctx_backoff(&ww);
778 if (!ret)
779 goto retry;
780 }
781 i915_gem_ww_ctx_fini(&ww);
782 if (ret)
783 return ERR_PTR(ret);
784
785 return vma;
786}
787
788static int intel_overlay_do_put_image(struct intel_overlay *overlay,
789 struct drm_i915_gem_object *new_bo,
790 struct drm_intel_overlay_put_image *params)
791{
792 struct overlay_registers __iomem *regs = overlay->regs;
793 struct drm_i915_private *dev_priv = overlay->i915;
794 u32 swidth, swidthsw, sheight, ostride;
795 enum pipe pipe = overlay->crtc->pipe;
796 bool scale_changed = false;
797 struct i915_vma *vma;
798 int ret, tmp_width;
799
800 drm_WARN_ON(&dev_priv->drm,
801 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
802
803 ret = intel_overlay_release_old_vid(overlay);
804 if (ret != 0)
805 return ret;
806
807 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
808
809 vma = intel_overlay_pin_fb(new_bo);
810 if (IS_ERR(vma)) {
811 ret = PTR_ERR(vma);
812 goto out_pin_section;
813 }
814
815 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
816
817 if (!overlay->active) {
818 const struct intel_crtc_state *crtc_state =
819 overlay->crtc->config;
820 u32 oconfig = 0;
821
822 if (crtc_state->gamma_enable &&
823 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
824 oconfig |= OCONF_CC_OUT_8BIT;
825 if (crtc_state->gamma_enable)
826 oconfig |= OCONF_GAMMA2_ENABLE;
827 if (DISPLAY_VER(dev_priv) == 4)
828 oconfig |= OCONF_CSC_MODE_BT709;
829 oconfig |= pipe == 0 ?
830 OCONF_PIPE_A : OCONF_PIPE_B;
831 iowrite32(oconfig, ®s->OCONFIG);
832
833 ret = intel_overlay_on(overlay);
834 if (ret != 0)
835 goto out_unpin;
836 }
837
838 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS);
839 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ);
840
841 if (params->flags & I915_OVERLAY_YUV_PACKED)
842 tmp_width = packed_width_bytes(params->flags,
843 params->src_width);
844 else
845 tmp_width = params->src_width;
846
847 swidth = params->src_width;
848 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
849 sheight = params->src_height;
850 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y);
851 ostride = params->stride_Y;
852
853 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
854 int uv_hscale = uv_hsubsampling(params->flags);
855 int uv_vscale = uv_vsubsampling(params->flags);
856 u32 tmp_U, tmp_V;
857
858 swidth |= (params->src_width / uv_hscale) << 16;
859 sheight |= (params->src_height / uv_vscale) << 16;
860
861 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
862 params->src_width / uv_hscale);
863 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
864 params->src_width / uv_hscale);
865 swidthsw |= max(tmp_U, tmp_V) << 16;
866
867 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
868 ®s->OBUF_0U);
869 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
870 ®s->OBUF_0V);
871
872 ostride |= params->stride_UV << 16;
873 }
874
875 iowrite32(swidth, ®s->SWIDTH);
876 iowrite32(swidthsw, ®s->SWIDTHSW);
877 iowrite32(sheight, ®s->SHEIGHT);
878 iowrite32(ostride, ®s->OSTRIDE);
879
880 scale_changed = update_scaling_factors(overlay, regs, params);
881
882 update_colorkey(overlay, regs);
883
884 iowrite32(overlay_cmd_reg(params), ®s->OCMD);
885
886 ret = intel_overlay_continue(overlay, vma, scale_changed);
887 if (ret)
888 goto out_unpin;
889
890 return 0;
891
892out_unpin:
893 i915_vma_unpin(vma);
894out_pin_section:
895 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
896
897 return ret;
898}
899
900int intel_overlay_switch_off(struct intel_overlay *overlay)
901{
902 struct drm_i915_private *dev_priv = overlay->i915;
903 int ret;
904
905 drm_WARN_ON(&dev_priv->drm,
906 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
907
908 ret = intel_overlay_recover_from_interrupt(overlay);
909 if (ret != 0)
910 return ret;
911
912 if (!overlay->active)
913 return 0;
914
915 ret = intel_overlay_release_old_vid(overlay);
916 if (ret != 0)
917 return ret;
918
919 iowrite32(0, &overlay->regs->OCMD);
920
921 return intel_overlay_off(overlay);
922}
923
924static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
925 struct intel_crtc *crtc)
926{
927 if (!crtc->active)
928 return -EINVAL;
929
930 /* can't use the overlay with double wide pipe */
931 if (crtc->config->double_wide)
932 return -EINVAL;
933
934 return 0;
935}
936
937static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
938{
939 struct drm_i915_private *dev_priv = overlay->i915;
940 u32 ratio;
941
942 /* XXX: This is not the same logic as in the xorg driver, but more in
943 * line with the intel documentation for the i965
944 */
945 if (DISPLAY_VER(dev_priv) >= 4) {
946 u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
947
948 /* on i965 use the PGM reg to read out the autoscaler values */
949 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
950 } else {
951 u32 tmp;
952
953 if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
954 tmp = intel_de_read(dev_priv,
955 PFIT_AUTO_RATIOS(dev_priv));
956 else
957 tmp = intel_de_read(dev_priv,
958 PFIT_PGM_RATIOS(dev_priv));
959
960 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
961 }
962
963 overlay->pfit_vscale_ratio = ratio;
964}
965
966static int check_overlay_dst(struct intel_overlay *overlay,
967 struct drm_intel_overlay_put_image *rec)
968{
969 const struct intel_crtc_state *crtc_state =
970 overlay->crtc->config;
971 struct drm_rect req, clipped;
972
973 drm_rect_init(&req, rec->dst_x, rec->dst_y,
974 rec->dst_width, rec->dst_height);
975
976 clipped = req;
977
978 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src))
979 return -EINVAL;
980
981 if (!drm_rect_equals(&clipped, &req))
982 return -EINVAL;
983
984 return 0;
985}
986
987static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
988{
989 u32 tmp;
990
991 /* downscaling limit is 8.0 */
992 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
993 if (tmp > 7)
994 return -EINVAL;
995
996 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
997 if (tmp > 7)
998 return -EINVAL;
999
1000 return 0;
1001}
1002
1003static int check_overlay_src(struct drm_i915_private *dev_priv,
1004 struct drm_intel_overlay_put_image *rec,
1005 struct drm_i915_gem_object *new_bo)
1006{
1007 int uv_hscale = uv_hsubsampling(rec->flags);
1008 int uv_vscale = uv_vsubsampling(rec->flags);
1009 u32 stride_mask;
1010 int depth;
1011 u32 tmp;
1012
1013 /* check src dimensions */
1014 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
1015 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1016 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
1017 return -EINVAL;
1018 } else {
1019 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1020 rec->src_width > IMAGE_MAX_WIDTH)
1021 return -EINVAL;
1022 }
1023
1024 /* better safe than sorry, use 4 as the maximal subsampling ratio */
1025 if (rec->src_height < N_VERT_Y_TAPS*4 ||
1026 rec->src_width < N_HORIZ_Y_TAPS*4)
1027 return -EINVAL;
1028
1029 /* check alignment constraints */
1030 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1031 case I915_OVERLAY_RGB:
1032 /* not implemented */
1033 return -EINVAL;
1034
1035 case I915_OVERLAY_YUV_PACKED:
1036 if (uv_vscale != 1)
1037 return -EINVAL;
1038
1039 depth = packed_depth_bytes(rec->flags);
1040 if (depth < 0)
1041 return depth;
1042
1043 /* ignore UV planes */
1044 rec->stride_UV = 0;
1045 rec->offset_U = 0;
1046 rec->offset_V = 0;
1047 /* check pixel alignment */
1048 if (rec->offset_Y % depth)
1049 return -EINVAL;
1050 break;
1051
1052 case I915_OVERLAY_YUV_PLANAR:
1053 if (uv_vscale < 0 || uv_hscale < 0)
1054 return -EINVAL;
1055 /* no offset restrictions for planar formats */
1056 break;
1057
1058 default:
1059 return -EINVAL;
1060 }
1061
1062 if (rec->src_width % uv_hscale)
1063 return -EINVAL;
1064
1065 /* stride checking */
1066 if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1067 stride_mask = 255;
1068 else
1069 stride_mask = 63;
1070
1071 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1072 return -EINVAL;
1073 if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
1074 return -EINVAL;
1075
1076 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1077 4096 : 8192;
1078 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1079 return -EINVAL;
1080
1081 /* check buffer dimensions */
1082 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1083 case I915_OVERLAY_RGB:
1084 case I915_OVERLAY_YUV_PACKED:
1085 /* always 4 Y values per depth pixels */
1086 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1087 return -EINVAL;
1088
1089 tmp = rec->stride_Y*rec->src_height;
1090 if (rec->offset_Y + tmp > new_bo->base.size)
1091 return -EINVAL;
1092 break;
1093
1094 case I915_OVERLAY_YUV_PLANAR:
1095 if (rec->src_width > rec->stride_Y)
1096 return -EINVAL;
1097 if (rec->src_width/uv_hscale > rec->stride_UV)
1098 return -EINVAL;
1099
1100 tmp = rec->stride_Y * rec->src_height;
1101 if (rec->offset_Y + tmp > new_bo->base.size)
1102 return -EINVAL;
1103
1104 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1105 if (rec->offset_U + tmp > new_bo->base.size ||
1106 rec->offset_V + tmp > new_bo->base.size)
1107 return -EINVAL;
1108 break;
1109 }
1110
1111 return 0;
1112}
1113
1114int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv)
1116{
1117 struct drm_intel_overlay_put_image *params = data;
1118 struct drm_i915_private *dev_priv = to_i915(dev);
1119 struct intel_overlay *overlay;
1120 struct drm_crtc *drmmode_crtc;
1121 struct intel_crtc *crtc;
1122 struct drm_i915_gem_object *new_bo;
1123 int ret;
1124
1125 overlay = dev_priv->display.overlay;
1126 if (!overlay) {
1127 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1128 return -ENODEV;
1129 }
1130
1131 if (!(params->flags & I915_OVERLAY_ENABLE)) {
1132 drm_modeset_lock_all(dev);
1133 ret = intel_overlay_switch_off(overlay);
1134 drm_modeset_unlock_all(dev);
1135
1136 return ret;
1137 }
1138
1139 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1140 if (!drmmode_crtc)
1141 return -ENOENT;
1142 crtc = to_intel_crtc(drmmode_crtc);
1143
1144 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1145 if (!new_bo)
1146 return -ENOENT;
1147
1148 drm_modeset_lock_all(dev);
1149
1150 if (i915_gem_object_is_tiled(new_bo)) {
1151 drm_dbg_kms(&dev_priv->drm,
1152 "buffer used for overlay image can not be tiled\n");
1153 ret = -EINVAL;
1154 goto out_unlock;
1155 }
1156
1157 ret = intel_overlay_recover_from_interrupt(overlay);
1158 if (ret != 0)
1159 goto out_unlock;
1160
1161 if (overlay->crtc != crtc) {
1162 ret = intel_overlay_switch_off(overlay);
1163 if (ret != 0)
1164 goto out_unlock;
1165
1166 ret = check_overlay_possible_on_crtc(overlay, crtc);
1167 if (ret != 0)
1168 goto out_unlock;
1169
1170 overlay->crtc = crtc;
1171 crtc->overlay = overlay;
1172
1173 /* line too wide, i.e. one-line-mode */
1174 if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&
1175 crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1176 overlay->pfit_active = true;
1177 update_pfit_vscale_ratio(overlay);
1178 } else
1179 overlay->pfit_active = false;
1180 }
1181
1182 ret = check_overlay_dst(overlay, params);
1183 if (ret != 0)
1184 goto out_unlock;
1185
1186 if (overlay->pfit_active) {
1187 params->dst_y = (((u32)params->dst_y << 12) /
1188 overlay->pfit_vscale_ratio);
1189 /* shifting right rounds downwards, so add 1 */
1190 params->dst_height = (((u32)params->dst_height << 12) /
1191 overlay->pfit_vscale_ratio) + 1;
1192 }
1193
1194 if (params->src_scan_height > params->src_height ||
1195 params->src_scan_width > params->src_width) {
1196 ret = -EINVAL;
1197 goto out_unlock;
1198 }
1199
1200 ret = check_overlay_src(dev_priv, params, new_bo);
1201 if (ret != 0)
1202 goto out_unlock;
1203
1204 /* Check scaling after src size to prevent a divide-by-zero. */
1205 ret = check_overlay_scaling(params);
1206 if (ret != 0)
1207 goto out_unlock;
1208
1209 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1210 if (ret != 0)
1211 goto out_unlock;
1212
1213 drm_modeset_unlock_all(dev);
1214 i915_gem_object_put(new_bo);
1215
1216 return 0;
1217
1218out_unlock:
1219 drm_modeset_unlock_all(dev);
1220 i915_gem_object_put(new_bo);
1221
1222 return ret;
1223}
1224
1225static void update_reg_attrs(struct intel_overlay *overlay,
1226 struct overlay_registers __iomem *regs)
1227{
1228 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1229 ®s->OCLRC0);
1230 iowrite32(overlay->saturation, ®s->OCLRC1);
1231}
1232
1233static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1234{
1235 int i;
1236
1237 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1238 return false;
1239
1240 for (i = 0; i < 3; i++) {
1241 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1242 return false;
1243 }
1244
1245 return true;
1246}
1247
1248static bool check_gamma5_errata(u32 gamma5)
1249{
1250 int i;
1251
1252 for (i = 0; i < 3; i++) {
1253 if (((gamma5 >> i*8) & 0xff) == 0x80)
1254 return false;
1255 }
1256
1257 return true;
1258}
1259
1260static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1261{
1262 if (!check_gamma_bounds(0, attrs->gamma0) ||
1263 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1264 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1265 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1266 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1267 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1268 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1269 return -EINVAL;
1270
1271 if (!check_gamma5_errata(attrs->gamma5))
1272 return -EINVAL;
1273
1274 return 0;
1275}
1276
1277int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file_priv)
1279{
1280 struct drm_intel_overlay_attrs *attrs = data;
1281 struct drm_i915_private *dev_priv = to_i915(dev);
1282 struct intel_overlay *overlay;
1283 int ret;
1284
1285 overlay = dev_priv->display.overlay;
1286 if (!overlay) {
1287 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1288 return -ENODEV;
1289 }
1290
1291 drm_modeset_lock_all(dev);
1292
1293 ret = -EINVAL;
1294 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1295 attrs->color_key = overlay->color_key;
1296 attrs->brightness = overlay->brightness;
1297 attrs->contrast = overlay->contrast;
1298 attrs->saturation = overlay->saturation;
1299
1300 if (DISPLAY_VER(dev_priv) != 2) {
1301 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1302 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1303 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1304 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1305 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1306 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1307 }
1308 } else {
1309 if (attrs->brightness < -128 || attrs->brightness > 127)
1310 goto out_unlock;
1311 if (attrs->contrast > 255)
1312 goto out_unlock;
1313 if (attrs->saturation > 1023)
1314 goto out_unlock;
1315
1316 overlay->color_key = attrs->color_key;
1317 overlay->brightness = attrs->brightness;
1318 overlay->contrast = attrs->contrast;
1319 overlay->saturation = attrs->saturation;
1320
1321 update_reg_attrs(overlay, overlay->regs);
1322
1323 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1324 if (DISPLAY_VER(dev_priv) == 2)
1325 goto out_unlock;
1326
1327 if (overlay->active) {
1328 ret = -EBUSY;
1329 goto out_unlock;
1330 }
1331
1332 ret = check_gamma(attrs);
1333 if (ret)
1334 goto out_unlock;
1335
1336 intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1337 intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1338 intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1339 intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1340 intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1341 intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1342 }
1343 }
1344 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1345
1346 ret = 0;
1347out_unlock:
1348 drm_modeset_unlock_all(dev);
1349
1350 return ret;
1351}
1352
1353static int get_registers(struct intel_overlay *overlay, bool use_phys)
1354{
1355 struct drm_i915_private *i915 = overlay->i915;
1356 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV);
1357 struct i915_vma *vma;
1358 int err;
1359
1360 if (!IS_METEORLAKE(i915)) /* Wa_22018444074 */
1361 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1362 if (IS_ERR(obj))
1363 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1364 if (IS_ERR(obj))
1365 return PTR_ERR(obj);
1366
1367 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1368 if (IS_ERR(vma)) {
1369 err = PTR_ERR(vma);
1370 goto err_put_bo;
1371 }
1372
1373 if (use_phys)
1374 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1375 else
1376 overlay->flip_addr = i915_ggtt_offset(vma);
1377 overlay->regs = i915_vma_pin_iomap(vma);
1378 i915_vma_unpin(vma);
1379
1380 if (IS_ERR(overlay->regs)) {
1381 err = PTR_ERR(overlay->regs);
1382 goto err_put_bo;
1383 }
1384
1385 overlay->reg_bo = obj;
1386 return 0;
1387
1388err_put_bo:
1389 i915_gem_object_put(obj);
1390 return err;
1391}
1392
1393void intel_overlay_setup(struct drm_i915_private *dev_priv)
1394{
1395 struct intel_overlay *overlay;
1396 struct intel_engine_cs *engine;
1397 int ret;
1398
1399 if (!HAS_OVERLAY(dev_priv))
1400 return;
1401
1402 engine = to_gt(dev_priv)->engine[RCS0];
1403 if (!engine || !engine->kernel_context)
1404 return;
1405
1406 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1407 if (!overlay)
1408 return;
1409
1410 overlay->i915 = dev_priv;
1411 overlay->context = engine->kernel_context;
1412 overlay->color_key = 0x0101fe;
1413 overlay->color_key_enabled = true;
1414 overlay->brightness = -19;
1415 overlay->contrast = 75;
1416 overlay->saturation = 146;
1417
1418 i915_active_init(&overlay->last_flip,
1419 NULL, intel_overlay_last_flip_retire, 0);
1420
1421 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1422 if (ret)
1423 goto out_free;
1424
1425 memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1426 update_polyphase_filter(overlay->regs);
1427 update_reg_attrs(overlay, overlay->regs);
1428
1429 dev_priv->display.overlay = overlay;
1430 drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1431 return;
1432
1433out_free:
1434 kfree(overlay);
1435}
1436
1437void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1438{
1439 struct intel_overlay *overlay;
1440
1441 overlay = fetch_and_zero(&dev_priv->display.overlay);
1442 if (!overlay)
1443 return;
1444
1445 /*
1446 * The bo's should be free'd by the generic code already.
1447 * Furthermore modesetting teardown happens beforehand so the
1448 * hardware should be off already.
1449 */
1450 drm_WARN_ON(&dev_priv->drm, overlay->active);
1451
1452 i915_gem_object_put(overlay->reg_bo);
1453 i915_active_fini(&overlay->last_flip);
1454
1455 kfree(overlay);
1456}
1457
1458#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1459
1460struct intel_overlay_snapshot {
1461 struct overlay_registers regs;
1462 unsigned long base;
1463 u32 dovsta;
1464 u32 isr;
1465};
1466
1467struct intel_overlay_snapshot *
1468intel_overlay_snapshot_capture(struct intel_display *display)
1469{
1470 struct drm_i915_private *dev_priv = to_i915(display->drm);
1471 struct intel_overlay *overlay = dev_priv->display.overlay;
1472 struct intel_overlay_snapshot *error;
1473
1474 if (!overlay || !overlay->active)
1475 return NULL;
1476
1477 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1478 if (error == NULL)
1479 return NULL;
1480
1481 error->dovsta = intel_de_read(dev_priv, DOVSTA);
1482 error->isr = intel_de_read(dev_priv, GEN2_ISR);
1483 error->base = overlay->flip_addr;
1484
1485 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1486
1487 return error;
1488}
1489
1490void
1491intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error,
1492 struct drm_printer *p)
1493{
1494 if (!error)
1495 return;
1496
1497 drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1498 error->dovsta, error->isr);
1499 drm_printf(p, " Register file at 0x%08lx:\n", error->base);
1500
1501#define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x)
1502 P(OBUF_0Y);
1503 P(OBUF_1Y);
1504 P(OBUF_0U);
1505 P(OBUF_0V);
1506 P(OBUF_1U);
1507 P(OBUF_1V);
1508 P(OSTRIDE);
1509 P(YRGB_VPH);
1510 P(UV_VPH);
1511 P(HORZ_PH);
1512 P(INIT_PHS);
1513 P(DWINPOS);
1514 P(DWINSZ);
1515 P(SWIDTH);
1516 P(SWIDTHSW);
1517 P(SHEIGHT);
1518 P(YRGBSCALE);
1519 P(UVSCALE);
1520 P(OCLRC0);
1521 P(OCLRC1);
1522 P(DCLRKV);
1523 P(DCLRKM);
1524 P(SCLRKVH);
1525 P(SCLRKVL);
1526 P(SCLRKEN);
1527 P(OCONFIG);
1528 P(OCMD);
1529 P(OSTART_0Y);
1530 P(OSTART_1Y);
1531 P(OSTART_0U);
1532 P(OSTART_0V);
1533 P(OSTART_1U);
1534 P(OSTART_1V);
1535 P(OTILEOFF_0Y);
1536 P(OTILEOFF_1Y);
1537 P(OTILEOFF_0U);
1538 P(OTILEOFF_0V);
1539 P(OTILEOFF_1U);
1540 P(OTILEOFF_1V);
1541 P(FASTHSCALE);
1542 P(UVSCALEV);
1543#undef P
1544}
1545
1546#endif