1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Daniel Vetter <daniel.vetter@ffwll.ch>
 25 *
 26 */
 27
 28#include "i915_drv.h"
 29#include "i915_reg.h"
 30#include "intel_de.h"
 31#include "intel_display_irq.h"
 32#include "intel_display_trace.h"
 33#include "intel_display_types.h"
 34#include "intel_fbc.h"
 35#include "intel_fifo_underrun.h"
 36#include "intel_pch_display.h"
 37
 38/**
 39 * DOC: fifo underrun handling
 40 *
 41 * The i915 driver checks for display fifo underruns using the interrupt signals
 42 * provided by the hardware. This is enabled by default and fairly useful to
 43 * debug display issues, especially watermark settings.
 44 *
 45 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
 46 * and occupying the cpu underrun interrupts are disabled after the first
 47 * occurrence until the next modeset on a given pipe.
 48 *
 49 * Note that underrun detection on gmch platforms is a bit more ugly since there
 50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
 51 * interrupt register). Also on some other platforms underrun interrupts are
 52 * shared, which means that if we detect an underrun we need to disable underrun
 53 * reporting on all pipes.
 54 *
 55 * The code also supports underrun detection on the PCH transcoder.
 56 */
 57
 58static bool ivb_can_enable_err_int(struct drm_device *dev)
 59{
 60	struct intel_display *display = to_intel_display(dev);
 61	struct drm_i915_private *dev_priv = to_i915(dev);
 62	struct intel_crtc *crtc;
 63	enum pipe pipe;
 64
 65	lockdep_assert_held(&dev_priv->irq_lock);
 66
 67	for_each_pipe(dev_priv, pipe) {
 68		crtc = intel_crtc_for_pipe(display, pipe);
 69
 70		if (crtc->cpu_fifo_underrun_disabled)
 71			return false;
 72	}
 73
 74	return true;
 75}
 76
 77static bool cpt_can_enable_serr_int(struct drm_device *dev)
 78{
 79	struct intel_display *display = to_intel_display(dev);
 80	struct drm_i915_private *dev_priv = to_i915(dev);
 81	enum pipe pipe;
 82	struct intel_crtc *crtc;
 83
 84	lockdep_assert_held(&dev_priv->irq_lock);
 85
 86	for_each_pipe(dev_priv, pipe) {
 87		crtc = intel_crtc_for_pipe(display, pipe);
 88
 89		if (crtc->pch_fifo_underrun_disabled)
 90			return false;
 91	}
 92
 93	return true;
 94}
 95
 96static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 97{
 98	struct intel_display *display = to_intel_display(crtc);
 99	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
100	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
101	u32 enable_mask;
102
103	lockdep_assert_held(&dev_priv->irq_lock);
104
105	if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
106		return;
107
108	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
109	intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
110	intel_de_posting_read(dev_priv, reg);
111
112	trace_intel_cpu_fifo_underrun(display, crtc->pipe);
113	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
114}
115
116static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
117					     enum pipe pipe,
118					     bool enable, bool old)
119{
120	struct drm_i915_private *dev_priv = to_i915(dev);
121	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
122
123	lockdep_assert_held(&dev_priv->irq_lock);
124
125	if (enable) {
126		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
127
128		intel_de_write(dev_priv, reg,
129			       enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
130		intel_de_posting_read(dev_priv, reg);
131	} else {
132		if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS)
133			drm_err(&dev_priv->drm, "pipe %c underrun\n",
134				pipe_name(pipe));
135	}
136}
137
138static void ilk_set_fifo_underrun_reporting(struct drm_device *dev,
139					    enum pipe pipe, bool enable)
140{
141	struct drm_i915_private *dev_priv = to_i915(dev);
142	u32 bit = (pipe == PIPE_A) ?
143		DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
144
145	if (enable)
146		ilk_enable_display_irq(dev_priv, bit);
147	else
148		ilk_disable_display_irq(dev_priv, bit);
149}
150
151static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
152{
153	struct intel_display *display = to_intel_display(crtc);
154	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
155	enum pipe pipe = crtc->pipe;
156	u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT);
157
158	lockdep_assert_held(&dev_priv->irq_lock);
159
160	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
161		return;
162
163	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
164	intel_de_posting_read(dev_priv, GEN7_ERR_INT);
165
166	trace_intel_cpu_fifo_underrun(display, pipe);
167	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
168}
169
170static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
171					    enum pipe pipe, bool enable,
172					    bool old)
173{
174	struct drm_i915_private *dev_priv = to_i915(dev);
175	if (enable) {
176		intel_de_write(dev_priv, GEN7_ERR_INT,
177			       ERR_INT_FIFO_UNDERRUN(pipe));
178
179		if (!ivb_can_enable_err_int(dev))
180			return;
181
182		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
183	} else {
184		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
185
186		if (old &&
187		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
188			drm_err(&dev_priv->drm,
189				"uncleared fifo underrun on pipe %c\n",
190				pipe_name(pipe));
191		}
192	}
193}
194
195static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
196					    enum pipe pipe, bool enable)
197{
198	struct drm_i915_private *dev_priv = to_i915(dev);
199
200	if (enable)
201		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
202	else
203		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
204}
205
206static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
207					    enum pipe pch_transcoder,
208					    bool enable)
209{
210	struct drm_i915_private *dev_priv = to_i915(dev);
211	u32 bit = (pch_transcoder == PIPE_A) ?
212		SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
213
214	if (enable)
215		ibx_enable_display_interrupt(dev_priv, bit);
216	else
217		ibx_disable_display_interrupt(dev_priv, bit);
218}
219
220static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
221{
222	struct intel_display *display = to_intel_display(crtc);
223	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
224	enum pipe pch_transcoder = crtc->pipe;
225	u32 serr_int = intel_de_read(dev_priv, SERR_INT);
226
227	lockdep_assert_held(&dev_priv->irq_lock);
228
229	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
230		return;
231
232	intel_de_write(dev_priv, SERR_INT,
233		       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
234	intel_de_posting_read(dev_priv, SERR_INT);
235
236	trace_intel_pch_fifo_underrun(display, pch_transcoder);
237	drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n",
238		pipe_name(pch_transcoder));
239}
240
241static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
242					    enum pipe pch_transcoder,
243					    bool enable, bool old)
244{
245	struct drm_i915_private *dev_priv = to_i915(dev);
246
247	if (enable) {
248		intel_de_write(dev_priv, SERR_INT,
249			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
250
251		if (!cpt_can_enable_serr_int(dev))
252			return;
253
254		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
255	} else {
256		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
257
258		if (old && intel_de_read(dev_priv, SERR_INT) &
259		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
260			drm_err(&dev_priv->drm,
261				"uncleared pch fifo underrun on pch transcoder %c\n",
262				pipe_name(pch_transcoder));
263		}
264	}
265}
266
267static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
268						    enum pipe pipe, bool enable)
269{
270	struct intel_display *display = to_intel_display(dev);
271	struct drm_i915_private *dev_priv = to_i915(dev);
272	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
273	bool old;
274
275	lockdep_assert_held(&dev_priv->irq_lock);
276
277	old = !crtc->cpu_fifo_underrun_disabled;
278	crtc->cpu_fifo_underrun_disabled = !enable;
279
280	if (HAS_GMCH(dev_priv))
281		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
282	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
283		ilk_set_fifo_underrun_reporting(dev, pipe, enable);
284	else if (DISPLAY_VER(dev_priv) == 7)
285		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
286	else if (DISPLAY_VER(dev_priv) >= 8)
287		bdw_set_fifo_underrun_reporting(dev, pipe, enable);
288
289	return old;
290}
291
292/**
293 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
294 * @dev_priv: i915 device instance
295 * @pipe: (CPU) pipe to set state for
296 * @enable: whether underruns should be reported or not
297 *
298 * This function sets the fifo underrun state for @pipe. It is used in the
299 * modeset code to avoid false positives since on many platforms underruns are
300 * expected when disabling or enabling the pipe.
301 *
302 * Notice that on some platforms disabling underrun reports for one pipe
303 * disables for all due to shared interrupts. Actual reporting is still per-pipe
304 * though.
305 *
306 * Returns the previous state of underrun reporting.
307 */
308bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
309					   enum pipe pipe, bool enable)
310{
311	unsigned long flags;
312	bool ret;
313
314	spin_lock_irqsave(&dev_priv->irq_lock, flags);
315	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
316						      enable);
317	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318
319	return ret;
320}
321
322/**
323 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
324 * @dev_priv: i915 device instance
325 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
326 * @enable: whether underruns should be reported or not
327 *
328 * This function makes us disable or enable PCH fifo underruns for a specific
329 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
330 * underrun reporting for one transcoder may also disable all the other PCH
331 * error interruts for the other transcoders, due to the fact that there's just
332 * one interrupt mask/enable bit for all the transcoders.
333 *
334 * Returns the previous state of underrun reporting.
335 */
336bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
337					   enum pipe pch_transcoder,
338					   bool enable)
339{
340	struct intel_display *display = &dev_priv->display;
341	struct intel_crtc *crtc =
342		intel_crtc_for_pipe(display, pch_transcoder);
343	unsigned long flags;
344	bool old;
345
346	/*
347	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
348	 * has only one pch transcoder A that all pipes can use. To avoid racy
349	 * pch transcoder -> pipe lookups from interrupt code simply store the
350	 * underrun statistics in crtc A. Since we never expose this anywhere
351	 * nor use it outside of the fifo underrun code here using the "wrong"
352	 * crtc on LPT won't cause issues.
353	 */
354
355	spin_lock_irqsave(&dev_priv->irq_lock, flags);
356
357	old = !crtc->pch_fifo_underrun_disabled;
358	crtc->pch_fifo_underrun_disabled = !enable;
359
360	if (HAS_PCH_IBX(dev_priv))
361		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
362						pch_transcoder,
363						enable);
364	else
365		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
366						pch_transcoder,
367						enable, old);
368
369	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
370	return old;
371}
372
373/**
374 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
375 * @dev_priv: i915 device instance
376 * @pipe: (CPU) pipe to set state for
377 *
378 * This handles a CPU fifo underrun interrupt, generating an underrun warning
379 * into dmesg if underrun reporting is enabled and then disables the underrun
380 * interrupt to avoid an irq storm.
381 */
382void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
383					 enum pipe pipe)
384{
385	struct intel_display *display = &dev_priv->display;
386	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
387
388	/* We may be called too early in init, thanks BIOS! */
389	if (crtc == NULL)
390		return;
391
392	/* GMCH can't disable fifo underruns, filter them. */
393	if (HAS_GMCH(dev_priv) &&
394	    crtc->cpu_fifo_underrun_disabled)
395		return;
396
397	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
398		trace_intel_cpu_fifo_underrun(display, pipe);
399
400		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
401	}
402
403	intel_fbc_handle_fifo_underrun_irq(&dev_priv->display);
404}
405
406/**
407 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
408 * @dev_priv: i915 device instance
409 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
410 *
411 * This handles a PCH fifo underrun interrupt, generating an underrun warning
412 * into dmesg if underrun reporting is enabled and then disables the underrun
413 * interrupt to avoid an irq storm.
414 */
415void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
416					 enum pipe pch_transcoder)
417{
418	struct intel_display *display = &dev_priv->display;
419
420	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
421						  false)) {
422		trace_intel_pch_fifo_underrun(display, pch_transcoder);
423		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",
424			pipe_name(pch_transcoder));
425	}
426}
427
428/**
429 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
430 * @dev_priv: i915 device instance
431 *
432 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
433 * error interrupt may have been disabled, and so CPU fifo underruns won't
434 * necessarily raise an interrupt, and on GMCH platforms where underruns never
435 * raise an interrupt.
436 */
437void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
438{
439	struct intel_crtc *crtc;
440
441	spin_lock_irq(&dev_priv->irq_lock);
442
443	for_each_intel_crtc(&dev_priv->drm, crtc) {
444		if (crtc->cpu_fifo_underrun_disabled)
445			continue;
446
447		if (HAS_GMCH(dev_priv))
448			i9xx_check_fifo_underruns(crtc);
449		else if (DISPLAY_VER(dev_priv) == 7)
450			ivb_check_fifo_underruns(crtc);
451	}
452
453	spin_unlock_irq(&dev_priv->irq_lock);
454}
455
456/**
457 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
458 * @dev_priv: i915 device instance
459 *
460 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
461 * error interrupt may have been disabled, and so PCH fifo underruns won't
462 * necessarily raise an interrupt.
463 */
464void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
465{
466	struct intel_crtc *crtc;
467
468	spin_lock_irq(&dev_priv->irq_lock);
469
470	for_each_intel_crtc(&dev_priv->drm, crtc) {
471		if (crtc->pch_fifo_underrun_disabled)
472			continue;
473
474		if (HAS_PCH_CPT(dev_priv))
475			cpt_check_pch_fifo_underruns(crtc);
476	}
477
478	spin_unlock_irq(&dev_priv->irq_lock);
479}
480
481void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
482					struct intel_crtc *crtc,
483					bool enable)
484{
485	crtc->cpu_fifo_underrun_disabled = !enable;
486
487	/*
488	 * We track the PCH trancoder underrun reporting state
489	 * within the crtc. With crtc for pipe A housing the underrun
490	 * reporting state for PCH transcoder A, crtc for pipe B housing
491	 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
492	 * and marking underrun reporting as disabled for the non-existing
493	 * PCH transcoders B and C would prevent enabling the south
494	 * error interrupt (see cpt_can_enable_serr_int()).
495	 */
496	if (intel_has_pch_trancoder(i915, crtc->pipe))
497		crtc->pch_fifo_underrun_disabled = !enable;
498}