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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27#include <linux/gpio/consumer.h>
28#include <linux/gpio/machine.h>
29#include <linux/mfd/intel_soc_pmic.h>
30#include <linux/pinctrl/consumer.h>
31#include <linux/pinctrl/machine.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <linux/unaligned.h>
36
37#include <drm/drm_crtc.h>
38#include <drm/drm_edid.h>
39
40#include <video/mipi_display.h>
41
42#include "i915_drv.h"
43#include "i915_reg.h"
44#include "intel_de.h"
45#include "intel_display_types.h"
46#include "intel_dsi.h"
47#include "intel_dsi_vbt.h"
48#include "intel_gmbus_regs.h"
49#include "intel_pps_regs.h"
50#include "vlv_dsi.h"
51#include "vlv_dsi_regs.h"
52#include "vlv_sideband.h"
53
54#define MIPI_TRANSFER_MODE_SHIFT 0
55#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
56#define MIPI_PORT_SHIFT 3
57
58struct i2c_adapter_lookup {
59 u16 target_addr;
60 struct intel_dsi *intel_dsi;
61 acpi_handle dev_handle;
62};
63
64#define CHV_GPIO_IDX_START_N 0
65#define CHV_GPIO_IDX_START_E 73
66#define CHV_GPIO_IDX_START_SW 100
67#define CHV_GPIO_IDX_START_SE 198
68
69/* ICL DSI Display GPIO Pins */
70#define ICL_GPIO_DDSP_HPD_A 0
71#define ICL_GPIO_L_VDDEN_1 1
72#define ICL_GPIO_L_BKLTEN_1 2
73#define ICL_GPIO_DDPA_CTRLCLK_1 3
74#define ICL_GPIO_DDPA_CTRLDATA_1 4
75#define ICL_GPIO_DDSP_HPD_B 5
76#define ICL_GPIO_L_VDDEN_2 6
77#define ICL_GPIO_L_BKLTEN_2 7
78#define ICL_GPIO_DDPA_CTRLCLK_2 8
79#define ICL_GPIO_DDPA_CTRLDATA_2 9
80
81static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
82 u8 seq_port)
83{
84 /*
85 * If single link DSI is being used on any port, the VBT sequence block
86 * send packet apparently always has 0 for the port. Just use the port
87 * we have configured, and ignore the sequence block port.
88 */
89 if (hweight8(intel_dsi->ports) == 1)
90 return ffs(intel_dsi->ports) - 1;
91
92 if (seq_port) {
93 if (intel_dsi->ports & BIT(PORT_B))
94 return PORT_B;
95 if (intel_dsi->ports & BIT(PORT_C))
96 return PORT_C;
97 }
98
99 return PORT_A;
100}
101
102static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
103 const u8 *data)
104{
105 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
106 struct mipi_dsi_device *dsi_device;
107 u8 type, flags, seq_port;
108 u16 len;
109 enum port port;
110
111 drm_dbg_kms(&dev_priv->drm, "\n");
112
113 flags = *data++;
114 type = *data++;
115
116 len = *((u16 *) data);
117 data += 2;
118
119 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
120
121 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
122
123 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
124 goto out;
125
126 dsi_device = intel_dsi->dsi_hosts[port]->device;
127 if (!dsi_device) {
128 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
129 port_name(port));
130 goto out;
131 }
132
133 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
134 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
135 else
136 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
137
138 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
139
140 switch (type) {
141 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
142 mipi_dsi_generic_write(dsi_device, NULL, 0);
143 break;
144 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
145 mipi_dsi_generic_write(dsi_device, data, 1);
146 break;
147 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
148 mipi_dsi_generic_write(dsi_device, data, 2);
149 break;
150 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
151 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
152 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
153 drm_dbg(&dev_priv->drm,
154 "Generic Read not yet implemented or used\n");
155 break;
156 case MIPI_DSI_GENERIC_LONG_WRITE:
157 mipi_dsi_generic_write(dsi_device, data, len);
158 break;
159 case MIPI_DSI_DCS_SHORT_WRITE:
160 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
161 break;
162 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
163 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
164 break;
165 case MIPI_DSI_DCS_READ:
166 drm_dbg(&dev_priv->drm,
167 "DCS Read not yet implemented or used\n");
168 break;
169 case MIPI_DSI_DCS_LONG_WRITE:
170 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
171 break;
172 }
173
174 if (DISPLAY_VER(dev_priv) < 11)
175 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
176
177out:
178 data += len;
179
180 return data;
181}
182
183static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
184{
185 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
186 u32 delay = *((const u32 *) data);
187
188 drm_dbg_kms(&i915->drm, "%d usecs\n", delay);
189
190 usleep_range(delay, delay + 10);
191 data += 4;
192
193 return data;
194}
195
196static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index,
197 const char *con_id, u8 idx, bool value)
198{
199 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
200 /* XXX: this table is a quick ugly hack. */
201 static struct gpio_desc *soc_gpio_table[U8_MAX + 1];
202 struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index];
203
204 if (gpio_desc) {
205 gpiod_set_value(gpio_desc, value);
206 } else {
207 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, con_id, idx,
208 value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
209 if (IS_ERR(gpio_desc)) {
210 drm_err(&dev_priv->drm,
211 "GPIO index %u request failed (%pe)\n",
212 gpio_index, gpio_desc);
213 return;
214 }
215
216 soc_gpio_table[gpio_index] = gpio_desc;
217 }
218}
219
220static void soc_opaque_gpio_set_value(struct intel_connector *connector,
221 u8 gpio_index, const char *chip,
222 const char *con_id, u8 idx, bool value)
223{
224 struct gpiod_lookup_table *lookup;
225
226 lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
227 if (!lookup)
228 return;
229
230 lookup->dev_id = "0000:00:02.0";
231 lookup->table[0] =
232 GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH);
233
234 gpiod_add_lookup_table(lookup);
235
236 soc_gpio_set_value(connector, gpio_index, con_id, idx, value);
237
238 gpiod_remove_lookup_table(lookup);
239 kfree(lookup);
240}
241
242static void vlv_gpio_set_value(struct intel_connector *connector,
243 u8 gpio_source, u8 gpio_index, bool value)
244{
245 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
246
247 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
248 if (connector->panel.vbt.dsi.seq_version < 3) {
249 if (gpio_source == 1) {
250 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
251 return;
252 }
253 if (gpio_source > 1) {
254 drm_dbg_kms(&dev_priv->drm,
255 "unknown gpio source %u\n", gpio_source);
256 return;
257 }
258 }
259
260 soc_opaque_gpio_set_value(connector, gpio_index,
261 "INT33FC:01", "Panel N", gpio_index, value);
262}
263
264static void chv_gpio_set_value(struct intel_connector *connector,
265 u8 gpio_source, u8 gpio_index, bool value)
266{
267 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
268
269 if (connector->panel.vbt.dsi.seq_version >= 3) {
270 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
271 /* XXX: it's unclear whether 255->57 is part of SE. */
272 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:03", "Panel SE",
273 gpio_index - CHV_GPIO_IDX_START_SE, value);
274 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
275 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:00", "Panel SW",
276 gpio_index - CHV_GPIO_IDX_START_SW, value);
277 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
278 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:02", "Panel E",
279 gpio_index - CHV_GPIO_IDX_START_E, value);
280 } else {
281 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N",
282 gpio_index - CHV_GPIO_IDX_START_N, value);
283 }
284 } else {
285 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
286 if (gpio_source != 0) {
287 drm_dbg_kms(&dev_priv->drm,
288 "unknown gpio source %u\n", gpio_source);
289 return;
290 }
291
292 if (gpio_index >= CHV_GPIO_IDX_START_E) {
293 drm_dbg_kms(&dev_priv->drm,
294 "invalid gpio index %u for GPIO N\n",
295 gpio_index);
296 return;
297 }
298
299 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N",
300 gpio_index - CHV_GPIO_IDX_START_N, value);
301 }
302}
303
304static void bxt_gpio_set_value(struct intel_connector *connector,
305 u8 gpio_index, bool value)
306{
307 soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value);
308}
309
310enum {
311 MIPI_RESET_1 = 0,
312 MIPI_AVDD_EN_1,
313 MIPI_BKLT_EN_1,
314 MIPI_AVEE_EN_1,
315 MIPI_VIO_EN_1,
316 MIPI_RESET_2,
317 MIPI_AVDD_EN_2,
318 MIPI_BKLT_EN_2,
319 MIPI_AVEE_EN_2,
320 MIPI_VIO_EN_2,
321};
322
323static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
324 int gpio, bool value)
325{
326 struct intel_display *display = &dev_priv->display;
327 int index;
328
329 if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
330 return;
331
332 switch (gpio) {
333 case MIPI_RESET_1:
334 case MIPI_RESET_2:
335 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
336
337 /*
338 * Disable HPD to set the pin to output, and set output
339 * value. The HPD pin should not be enabled for DSI anyway,
340 * assuming the board design and VBT are sane, and the pin isn't
341 * used by a non-DSI encoder.
342 *
343 * The locking protects against concurrent SHOTPLUG_CTL_DDI
344 * modifications in irq setup and handling.
345 */
346 spin_lock_irq(&dev_priv->irq_lock);
347 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
348 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
349 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
350 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0);
351 spin_unlock_irq(&dev_priv->irq_lock);
352 break;
353 case MIPI_AVDD_EN_1:
354 case MIPI_AVDD_EN_2:
355 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
356
357 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), PANEL_POWER_ON,
358 value ? PANEL_POWER_ON : 0);
359 break;
360 case MIPI_BKLT_EN_1:
361 case MIPI_BKLT_EN_2:
362 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
363
364 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), EDP_BLC_ENABLE,
365 value ? EDP_BLC_ENABLE : 0);
366 break;
367 case MIPI_AVEE_EN_1:
368 case MIPI_AVEE_EN_2:
369 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
370
371 intel_de_rmw(display, GPIO(display, index),
372 GPIO_CLOCK_VAL_OUT,
373 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
374 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
375 break;
376 case MIPI_VIO_EN_1:
377 case MIPI_VIO_EN_2:
378 index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
379
380 intel_de_rmw(display, GPIO(display, index),
381 GPIO_DATA_VAL_OUT,
382 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
383 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
384 break;
385 default:
386 MISSING_CASE(gpio);
387 }
388}
389
390static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
391{
392 struct drm_device *dev = intel_dsi->base.base.dev;
393 struct drm_i915_private *i915 = to_i915(dev);
394 struct intel_connector *connector = intel_dsi->attached_connector;
395 u8 gpio_source = 0, gpio_index = 0, gpio_number;
396 bool value;
397 int size;
398 bool native = DISPLAY_VER(i915) >= 11;
399
400 if (connector->panel.vbt.dsi.seq_version >= 3) {
401 size = 3;
402
403 gpio_index = data[0];
404 gpio_number = data[1];
405 value = data[2] & BIT(0);
406
407 if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1))
408 native = false;
409 } else {
410 size = 2;
411
412 gpio_number = data[0];
413 value = data[1] & BIT(0);
414
415 if (connector->panel.vbt.dsi.seq_version == 2)
416 gpio_source = (data[1] >> 1) & 3;
417 }
418
419 drm_dbg_kms(&i915->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
420 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value));
421
422 if (native)
423 icl_native_gpio_set_value(i915, gpio_number, value);
424 else if (DISPLAY_VER(i915) >= 9)
425 bxt_gpio_set_value(connector, gpio_index, value);
426 else if (IS_VALLEYVIEW(i915))
427 vlv_gpio_set_value(connector, gpio_source, gpio_number, value);
428 else if (IS_CHERRYVIEW(i915))
429 chv_gpio_set_value(connector, gpio_source, gpio_number, value);
430
431 return data + size;
432}
433
434#ifdef CONFIG_ACPI
435static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
436{
437 struct i2c_adapter_lookup *lookup = data;
438 struct intel_dsi *intel_dsi = lookup->intel_dsi;
439 struct acpi_resource_i2c_serialbus *sb;
440 struct i2c_adapter *adapter;
441 acpi_handle adapter_handle;
442 acpi_status status;
443
444 if (!i2c_acpi_get_i2c_resource(ares, &sb))
445 return 1;
446
447 if (lookup->target_addr != sb->slave_address)
448 return 1;
449
450 status = acpi_get_handle(lookup->dev_handle,
451 sb->resource_source.string_ptr,
452 &adapter_handle);
453 if (ACPI_FAILURE(status))
454 return 1;
455
456 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
457 if (adapter)
458 intel_dsi->i2c_bus_num = adapter->nr;
459
460 return 1;
461}
462
463static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
464 const u16 target_addr)
465{
466 struct drm_device *drm_dev = intel_dsi->base.base.dev;
467 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
468 struct i2c_adapter_lookup lookup = {
469 .target_addr = target_addr,
470 .intel_dsi = intel_dsi,
471 .dev_handle = acpi_device_handle(adev),
472 };
473 LIST_HEAD(resource_list);
474
475 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
476 acpi_dev_free_resource_list(&resource_list);
477}
478#else
479static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
480 const u16 target_addr)
481{
482}
483#endif
484
485static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
486{
487 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
488 struct i2c_adapter *adapter;
489 struct i2c_msg msg;
490 int ret;
491 u8 vbt_i2c_bus_num = *(data + 2);
492 u16 target_addr = *(u16 *)(data + 3);
493 u8 reg_offset = *(data + 5);
494 u8 payload_size = *(data + 6);
495 u8 *payload_data;
496
497 drm_dbg_kms(&i915->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",
498 vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7);
499
500 if (intel_dsi->i2c_bus_num < 0) {
501 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
502 i2c_acpi_find_adapter(intel_dsi, target_addr);
503 }
504
505 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
506 if (!adapter) {
507 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
508 goto err_bus;
509 }
510
511 payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
512 if (!payload_data)
513 goto err_alloc;
514
515 payload_data[0] = reg_offset;
516 memcpy(&payload_data[1], (data + 7), payload_size);
517
518 msg.addr = target_addr;
519 msg.flags = 0;
520 msg.len = payload_size + 1;
521 msg.buf = payload_data;
522
523 ret = i2c_transfer(adapter, &msg, 1);
524 if (ret < 0)
525 drm_err(&i915->drm,
526 "Failed to xfer payload of size (%u) to reg (%u)\n",
527 payload_size, reg_offset);
528
529 kfree(payload_data);
530err_alloc:
531 i2c_put_adapter(adapter);
532err_bus:
533 return data + payload_size + 7;
534}
535
536static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
537{
538 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
539
540 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
541
542 return data + *(data + 5) + 6;
543}
544
545static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
546{
547 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
548#ifdef CONFIG_PMIC_OPREGION
549 u32 value, mask, reg_address;
550 u16 i2c_address;
551 int ret;
552
553 /* byte 0 aka PMIC Flag is reserved */
554 i2c_address = get_unaligned_le16(data + 1);
555 reg_address = get_unaligned_le32(data + 3);
556 value = get_unaligned_le32(data + 7);
557 mask = get_unaligned_le32(data + 11);
558
559 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
560 reg_address,
561 value, mask);
562 if (ret)
563 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
564#else
565 drm_err(&i915->drm,
566 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
567#endif
568
569 return data + 15;
570}
571
572typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
573 const u8 *data);
574static const fn_mipi_elem_exec exec_elem[] = {
575 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
576 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
577 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
578 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
579 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
580 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
581};
582
583/*
584 * MIPI Sequence from VBT #53 parsing logic
585 * We have already separated each seqence during bios parsing
586 * Following is generic execution function for any sequence
587 */
588
589static const char * const seq_name[] = {
590 [MIPI_SEQ_END] = "MIPI_SEQ_END",
591 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
592 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
593 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
594 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
595 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
596 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
597 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
598 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
599 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
600 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
601 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
602};
603
604static const char *sequence_name(enum mipi_seq seq_id)
605{
606 if (seq_id < ARRAY_SIZE(seq_name))
607 return seq_name[seq_id];
608
609 return "(unknown)";
610}
611
612static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
613 enum mipi_seq seq_id)
614{
615 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
616 struct intel_connector *connector = intel_dsi->attached_connector;
617 const u8 *data;
618 fn_mipi_elem_exec mipi_elem_exec;
619
620 if (drm_WARN_ON(&dev_priv->drm,
621 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
622 return;
623
624 data = connector->panel.vbt.dsi.sequence[seq_id];
625 if (!data)
626 return;
627
628 drm_WARN_ON(&dev_priv->drm, *data != seq_id);
629
630 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
631 seq_id, sequence_name(seq_id));
632
633 /* Skip Sequence Byte. */
634 data++;
635
636 /* Skip Size of Sequence. */
637 if (connector->panel.vbt.dsi.seq_version >= 3)
638 data += 4;
639
640 while (*data != MIPI_SEQ_ELEM_END) {
641 u8 operation_byte = *data++;
642 u8 operation_size = 0;
643
644 if (operation_byte < ARRAY_SIZE(exec_elem))
645 mipi_elem_exec = exec_elem[operation_byte];
646 else
647 mipi_elem_exec = NULL;
648
649 /* Size of Operation. */
650 if (connector->panel.vbt.dsi.seq_version >= 3)
651 operation_size = *data++;
652
653 if (mipi_elem_exec) {
654 const u8 *next = data + operation_size;
655
656 data = mipi_elem_exec(intel_dsi, data);
657
658 /* Consistency check if we have size. */
659 if (operation_size && data != next) {
660 drm_err(&dev_priv->drm,
661 "Inconsistent operation size\n");
662 return;
663 }
664 } else if (operation_size) {
665 /* We have size, skip. */
666 drm_dbg_kms(&dev_priv->drm,
667 "Unsupported MIPI operation byte %u\n",
668 operation_byte);
669 data += operation_size;
670 } else {
671 /* No size, can't skip without parsing. */
672 drm_err(&dev_priv->drm,
673 "Unsupported MIPI operation byte %u\n",
674 operation_byte);
675 return;
676 }
677 }
678}
679
680void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
681 enum mipi_seq seq_id)
682{
683 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
684 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
685 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
686 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
687
688 intel_dsi_vbt_exec(intel_dsi, seq_id);
689
690 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
691 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
692 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
693 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
694}
695
696void intel_dsi_log_params(struct intel_dsi *intel_dsi)
697{
698 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
699
700 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
701 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
702 intel_dsi->pixel_overlap);
703 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
704 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
705 drm_dbg_kms(&i915->drm, "Video mode format %s\n",
706 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
707 "non-burst with sync pulse" :
708 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
709 "non-burst with sync events" :
710 intel_dsi->video_mode == BURST_MODE ?
711 "burst" : "<unknown>");
712 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
713 intel_dsi->burst_mode_ratio);
714 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
715 drm_dbg_kms(&i915->drm, "Eot %s\n",
716 str_enabled_disabled(intel_dsi->eotp_pkt));
717 drm_dbg_kms(&i915->drm, "Clockstop %s\n",
718 str_enabled_disabled(!intel_dsi->clock_stop));
719 drm_dbg_kms(&i915->drm, "Mode %s\n",
720 intel_dsi->operation_mode ? "command" : "video");
721 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
722 drm_dbg_kms(&i915->drm,
723 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
724 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
725 drm_dbg_kms(&i915->drm,
726 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
727 else
728 drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
729 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
730 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
731 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
732 intel_dsi->lp_rx_timeout);
733 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
734 intel_dsi->turn_arnd_val);
735 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
736 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
737 intel_dsi->hs_to_lp_count);
738 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
739 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
740 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
741 intel_dsi->clk_lp_to_hs_count);
742 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
743 intel_dsi->clk_hs_to_lp_count);
744 drm_dbg_kms(&i915->drm, "BTA %s\n",
745 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
746}
747
748bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
749{
750 struct drm_device *dev = intel_dsi->base.base.dev;
751 struct drm_i915_private *dev_priv = to_i915(dev);
752 struct intel_connector *connector = intel_dsi->attached_connector;
753 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
754 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
755 struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode;
756 u16 burst_mode_ratio;
757 enum port port;
758
759 drm_dbg_kms(&dev_priv->drm, "\n");
760
761 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
762 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
763 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
764 intel_dsi->pixel_format =
765 pixel_format_from_register_bits(
766 mipi_config->videomode_color_format << 7);
767
768 intel_dsi->dual_link = mipi_config->dual_link;
769 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
770 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
771 intel_dsi->video_mode = mipi_config->video_transfer_mode;
772 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
773 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
774 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
775 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
776 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
777 intel_dsi->init_count = mipi_config->master_init_timer;
778 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
779 intel_dsi->video_frmt_cfg_bits =
780 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
781 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
782
783 /* Starting point, adjusted depending on dual link and burst mode */
784 intel_dsi->pclk = mode->clock;
785
786 /* In dual link mode each port needs half of pixel clock */
787 if (intel_dsi->dual_link) {
788 intel_dsi->pclk /= 2;
789
790 /* we can enable pixel_overlap if needed by panel. In this
791 * case we need to increase the pixelclock for extra pixels
792 */
793 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
794 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
795 }
796 }
797
798 /* Burst Mode Ratio
799 * Target ddr frequency from VBT / non burst ddr freq
800 * multiply by 100 to preserve remainder
801 */
802 if (intel_dsi->video_mode == BURST_MODE) {
803 u32 bitrate;
804
805 if (mipi_config->target_burst_mode_freq == 0) {
806 drm_err(&dev_priv->drm, "Burst mode target is not set\n");
807 return false;
808 }
809
810 bitrate = intel_dsi_bitrate(intel_dsi);
811
812 /*
813 * Sometimes the VBT contains a slightly lower clock, then
814 * the bitrate we have calculated, in this case just replace it
815 * with the calculated bitrate.
816 */
817 if (mipi_config->target_burst_mode_freq < bitrate &&
818 intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq,
819 bitrate))
820 mipi_config->target_burst_mode_freq = bitrate;
821
822 if (mipi_config->target_burst_mode_freq < bitrate) {
823 drm_err(&dev_priv->drm, "Burst mode freq is less than computed\n");
824 return false;
825 }
826
827 burst_mode_ratio =
828 DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate);
829
830 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
831 } else
832 burst_mode_ratio = 100;
833
834 intel_dsi->burst_mode_ratio = burst_mode_ratio;
835
836 /* delays in VBT are in unit of 100us, so need to convert
837 * here in ms
838 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
839 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
840 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
841 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
842 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
843 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
844
845 intel_dsi->i2c_bus_num = -1;
846
847 /* a regular driver would get the device in probe */
848 for_each_dsi_port(port, intel_dsi->ports) {
849 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
850 }
851
852 return true;
853}
854
855/*
856 * On some BYT/CHT devs some sequences are incomplete and we need to manually
857 * control some GPIOs. We need to add a GPIO lookup table before we get these.
858 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
859 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
860 */
861static struct gpiod_lookup_table pmic_panel_gpio_table = {
862 /* Intel GFX is consumer */
863 .dev_id = "0000:00:02.0",
864 .table = {
865 /* Panel EN/DISABLE */
866 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
867 { }
868 },
869};
870
871static struct gpiod_lookup_table soc_panel_gpio_table = {
872 .dev_id = "0000:00:02.0",
873 .table = {
874 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
875 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
876 { }
877 },
878};
879
880static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
881 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
882 "pwm0_grp", "pwm"),
883};
884
885void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
886{
887 struct drm_device *dev = intel_dsi->base.base.dev;
888 struct drm_i915_private *dev_priv = to_i915(dev);
889 struct intel_connector *connector = intel_dsi->attached_connector;
890 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
891 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
892 struct gpiod_lookup_table *gpiod_lookup_table = NULL;
893 bool want_backlight_gpio = false;
894 bool want_panel_gpio = false;
895 struct pinctrl *pinctrl;
896 int ret;
897
898 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
899 mipi_config->pwm_blc == PPS_BLC_PMIC) {
900 gpiod_lookup_table = &pmic_panel_gpio_table;
901 want_panel_gpio = true;
902 }
903
904 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
905 gpiod_lookup_table = &soc_panel_gpio_table;
906 want_panel_gpio = true;
907 want_backlight_gpio = true;
908
909 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
910 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
911 ARRAY_SIZE(soc_pwm_pinctrl_map));
912 if (ret)
913 drm_err(&dev_priv->drm,
914 "Failed to register pwm0 pinmux mapping\n");
915
916 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
917 if (IS_ERR(pinctrl))
918 drm_err(&dev_priv->drm,
919 "Failed to set pinmux to PWM\n");
920 }
921
922 if (gpiod_lookup_table)
923 gpiod_add_lookup_table(gpiod_lookup_table);
924
925 if (want_panel_gpio) {
926 intel_dsi->gpio_panel = devm_gpiod_get(dev->dev, "panel", flags);
927 if (IS_ERR(intel_dsi->gpio_panel)) {
928 drm_err(&dev_priv->drm,
929 "Failed to own gpio for panel control\n");
930 intel_dsi->gpio_panel = NULL;
931 }
932 }
933
934 if (want_backlight_gpio) {
935 intel_dsi->gpio_backlight =
936 devm_gpiod_get(dev->dev, "backlight", flags);
937 if (IS_ERR(intel_dsi->gpio_backlight)) {
938 drm_err(&dev_priv->drm,
939 "Failed to own gpio for backlight control\n");
940 intel_dsi->gpio_backlight = NULL;
941 }
942 }
943
944 if (gpiod_lookup_table)
945 gpiod_remove_lookup_table(gpiod_lookup_table);
946}