1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_DPIO_PHY_H__
  7#define __INTEL_DPIO_PHY_H__
  8
  9#include <linux/types.h>
 10
 11enum pipe;
 12enum port;
 13struct intel_crtc_state;
 14struct intel_digital_port;
 15struct intel_display;
 16struct intel_encoder;
 17
 18enum dpio_channel {
 19	DPIO_CH0,
 20	DPIO_CH1,
 21};
 22
 23enum dpio_phy {
 24	DPIO_PHY0,
 25	DPIO_PHY1,
 26	DPIO_PHY2,
 27};
 28
 29#ifdef I915
 30void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
 31			     enum dpio_phy *phy, enum dpio_channel *ch);
 32void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
 33				    const struct intel_crtc_state *crtc_state);
 34void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
 35void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
 36bool bxt_dpio_phy_is_enabled(struct intel_display *display,
 37			     enum dpio_phy phy);
 38bool bxt_dpio_phy_verify_state(struct intel_display *display,
 39			       enum dpio_phy phy);
 40u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
 41void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 42				      u8 lane_lat_optim_mask);
 43u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
 44
 45enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
 46enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
 47enum dpio_phy vlv_pipe_to_phy(enum pipe pipe);
 48enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);
 49
 50void chv_set_phy_signal_level(struct intel_encoder *encoder,
 51			      const struct intel_crtc_state *crtc_state,
 52			      u32 deemph_reg_value, u32 margin_reg_value,
 53			      bool uniq_trans_scale);
 54void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 55			      const struct intel_crtc_state *crtc_state,
 56			      bool reset);
 57void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 58			    const struct intel_crtc_state *crtc_state);
 59void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 60				const struct intel_crtc_state *crtc_state);
 61void chv_phy_release_cl2_override(struct intel_encoder *encoder);
 62void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 63			      const struct intel_crtc_state *old_crtc_state);
 64
 65void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 66			      const struct intel_crtc_state *crtc_state,
 67			      u32 demph_reg_value, u32 preemph_reg_value,
 68			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 69void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 70			    const struct intel_crtc_state *crtc_state);
 71void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 72				const struct intel_crtc_state *crtc_state);
 73void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 74			 const struct intel_crtc_state *old_crtc_state);
 75#else
 76static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
 77					   enum dpio_phy *phy, enum dpio_channel *ch)
 78{
 79}
 80static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
 81						  const struct intel_crtc_state *crtc_state)
 82{
 83}
 84static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
 85{
 86}
 87static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
 88{
 89}
 90static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
 91					   enum dpio_phy phy)
 92{
 93	return false;
 94}
 95static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
 96					     enum dpio_phy phy)
 97{
 98	return true;
 99}
100static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
101{
102	return 0;
103}
104static inline void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
105						    u8 lane_lat_optim_mask)
106{
107}
108static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
109{
110	return 0;
111}
112static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
113{
114	return DPIO_CH0;
115}
116static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
117{
118	return DPIO_PHY0;
119}
120static inline enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)
121{
122	return DPIO_PHY0;
123}
124static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
125{
126	return DPIO_CH0;
127}
128static inline void chv_set_phy_signal_level(struct intel_encoder *encoder,
129					    const struct intel_crtc_state *crtc_state,
130					    u32 deemph_reg_value, u32 margin_reg_value,
131					    bool uniq_trans_scale)
132{
133}
134static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder,
135					    const struct intel_crtc_state *crtc_state,
136					    bool reset)
137{
138}
139static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
140					  const struct intel_crtc_state *crtc_state)
141{
142}
143static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
144					      const struct intel_crtc_state *crtc_state)
145{
146}
147static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder)
148{
149}
150static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder,
151					    const struct intel_crtc_state *old_crtc_state)
152{
153}
154
155static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder,
156					    const struct intel_crtc_state *crtc_state,
157					    u32 demph_reg_value, u32 preemph_reg_value,
158					    u32 uniqtranscale_reg_value, u32 tx3_demph)
159{
160}
161static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
162					  const struct intel_crtc_state *crtc_state)
163{
164}
165static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
166					      const struct intel_crtc_state *crtc_state)
167{
168}
169static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
170				       const struct intel_crtc_state *old_crtc_state)
171{
172}
173#endif
174
175#endif /* __INTEL_DPIO_PHY_H__ */