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1/*
2 * Copyright © 2008 Intel Corporation
3 * 2014 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26#include <drm/drm_atomic.h>
27#include <drm/drm_atomic_helper.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_fixed.h>
30#include <drm/drm_probe_helper.h>
31
32#include "i915_drv.h"
33#include "i915_reg.h"
34#include "intel_atomic.h"
35#include "intel_audio.h"
36#include "intel_connector.h"
37#include "intel_crtc.h"
38#include "intel_ddi.h"
39#include "intel_de.h"
40#include "intel_display_driver.h"
41#include "intel_display_types.h"
42#include "intel_dp.h"
43#include "intel_dp_hdcp.h"
44#include "intel_dp_link_training.h"
45#include "intel_dp_mst.h"
46#include "intel_dp_test.h"
47#include "intel_dp_tunnel.h"
48#include "intel_dpio_phy.h"
49#include "intel_hdcp.h"
50#include "intel_hotplug.h"
51#include "intel_link_bw.h"
52#include "intel_psr.h"
53#include "intel_vdsc.h"
54#include "skl_scaler.h"
55
56static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
57 bool dsc)
58{
59 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
60 const struct drm_display_mode *adjusted_mode =
61 &crtc_state->hw.adjusted_mode;
62
63 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc)
64 return INT_MAX;
65
66 /*
67 * DSC->DPT interface width:
68 * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)
69 * LNL+: 144 bits (not a bottleneck in any config)
70 *
71 * Bspec/49259 suggests that the FEC overhead needs to be
72 * applied here, though HW people claim that neither this FEC
73 * or any other overhead is applicable here (that is the actual
74 * available_bw is just symbol_clock * 72). However based on
75 * testing on MTL-P the
76 * - DELL U3224KBA display
77 * - Unigraf UCD-500 CTS test sink
78 * devices the
79 * - 5120x2880/995.59Mhz
80 * - 6016x3384/1357.23Mhz
81 * - 6144x3456/1413.39Mhz
82 * modes (all the ones having a DPT limit on the above devices),
83 * both the channel coding efficiency and an additional 3%
84 * overhead needs to be accounted for.
85 */
86 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
87 drm_dp_bw_channel_coding_efficiency(true)),
88 mul_u32_u32(adjusted_mode->crtc_clock, 1030000));
89}
90
91static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
92 const struct intel_connector *connector,
93 bool ssc, int dsc_slice_count, int bpp_x16)
94{
95 const struct drm_display_mode *adjusted_mode =
96 &crtc_state->hw.adjusted_mode;
97 unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
98 int overhead;
99
100 flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
101 flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
102 flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
103
104 if (dsc_slice_count)
105 flags |= DRM_DP_BW_OVERHEAD_DSC;
106
107 overhead = drm_dp_bw_overhead(crtc_state->lane_count,
108 adjusted_mode->hdisplay,
109 dsc_slice_count,
110 bpp_x16,
111 flags);
112
113 /*
114 * TODO: clarify whether a minimum required by the fixed FEC overhead
115 * in the bspec audio programming sequence is required here.
116 */
117 return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
118}
119
120static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
121 const struct intel_connector *connector,
122 int overhead,
123 int bpp_x16,
124 struct intel_link_m_n *m_n)
125{
126 const struct drm_display_mode *adjusted_mode =
127 &crtc_state->hw.adjusted_mode;
128
129 /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */
130 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
131 adjusted_mode->crtc_clock,
132 crtc_state->port_clock,
133 overhead,
134 m_n);
135
136 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
137}
138
139static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
140{
141 int effective_data_rate =
142 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
143
144 /*
145 * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted
146 * to calculate PBN with the BW overhead passed to it.
147 */
148 return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
149}
150
151static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connector,
152 const struct intel_crtc_state *crtc_state)
153{
154 const struct drm_display_mode *adjusted_mode =
155 &crtc_state->hw.adjusted_mode;
156 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
157
158 return intel_dp_dsc_get_slice_count(connector,
159 adjusted_mode->clock,
160 adjusted_mode->hdisplay,
161 num_joined_pipes);
162}
163
164static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
165 struct intel_crtc_state *crtc_state,
166 int max_bpp,
167 int min_bpp,
168 struct link_config_limits *limits,
169 struct drm_connector_state *conn_state,
170 int step,
171 bool dsc)
172{
173 struct drm_atomic_state *state = crtc_state->uapi.state;
174 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
175 struct intel_dp *intel_dp = &intel_mst->primary->dp;
176 struct drm_dp_mst_topology_state *mst_state;
177 struct intel_connector *connector =
178 to_intel_connector(conn_state->connector);
179 struct drm_i915_private *i915 = to_i915(connector->base.dev);
180 const struct drm_display_mode *adjusted_mode =
181 &crtc_state->hw.adjusted_mode;
182 int bpp, slots = -EINVAL;
183 int dsc_slice_count = 0;
184 int max_dpt_bpp;
185 int ret = 0;
186
187 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
188 if (IS_ERR(mst_state))
189 return PTR_ERR(mst_state);
190
191 crtc_state->lane_count = limits->max_lane_count;
192 crtc_state->port_clock = limits->max_rate;
193
194 if (dsc) {
195 if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
196 return -EINVAL;
197
198 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
199 }
200
201 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
202 crtc_state->port_clock,
203 crtc_state->lane_count);
204
205 max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
206 if (max_bpp > max_dpt_bpp) {
207 drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n",
208 max_bpp, max_dpt_bpp);
209 max_bpp = max_dpt_bpp;
210 }
211
212 drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
213 min_bpp, max_bpp);
214
215 if (dsc) {
216 dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state);
217 if (!dsc_slice_count) {
218 drm_dbg_kms(&i915->drm, "Can't get valid DSC slice count\n");
219
220 return -ENOSPC;
221 }
222 }
223
224 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
225 int local_bw_overhead;
226 int remote_bw_overhead;
227 int link_bpp_x16;
228 int remote_tu;
229 fixed20_12 pbn;
230
231 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
232
233 link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
234 intel_dp_output_bpp(crtc_state->output_format, bpp));
235
236 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
237 false, dsc_slice_count, link_bpp_x16);
238 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
239 true, dsc_slice_count, link_bpp_x16);
240
241 intel_dp_mst_compute_m_n(crtc_state, connector,
242 local_bw_overhead,
243 link_bpp_x16,
244 &crtc_state->dp_m_n);
245
246 /*
247 * The TU size programmed to the HW determines which slots in
248 * an MTP frame are used for this stream, which needs to match
249 * the payload size programmed to the first downstream branch
250 * device's payload table.
251 *
252 * Note that atm the payload's PBN value DRM core sends via
253 * the ALLOCATE_PAYLOAD side-band message matches the payload
254 * size (which it calculates from the PBN value) it programs
255 * to the first branch device's payload table. The allocation
256 * in the payload table could be reduced though (to
257 * crtc_state->dp_m_n.tu), provided that the driver doesn't
258 * enable SSC on the corresponding link.
259 */
260 pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
261 link_bpp_x16,
262 remote_bw_overhead));
263 remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
264
265 /*
266 * Aligning the TUs ensures that symbols consisting of multiple
267 * (4) symbol cycles don't get split between two consecutive
268 * MTPs, as required by Bspec.
269 * TODO: remove the alignment restriction for 128b/132b links
270 * on some platforms, where Bspec allows this.
271 */
272 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
273
274 /*
275 * Also align PBNs accordingly, since MST core will derive its
276 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
277 * The above comment about the difference between the PBN
278 * allocated for the whole path and the TUs allocated for the
279 * first branch device's link also applies here.
280 */
281 pbn.full = remote_tu * mst_state->pbn_div.full;
282 crtc_state->pbn = dfixed_trunc(pbn);
283
284 drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);
285 crtc_state->dp_m_n.tu = remote_tu;
286
287 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
288 connector->port,
289 crtc_state->pbn);
290 if (slots == -EDEADLK)
291 return slots;
292
293 if (slots >= 0) {
294 drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);
295
296 break;
297 }
298 }
299
300 /* We failed to find a proper bpp/timeslots, return error */
301 if (ret)
302 slots = ret;
303
304 if (slots < 0) {
305 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
306 slots);
307 } else {
308 if (!dsc)
309 crtc_state->pipe_bpp = bpp;
310 else
311 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
312 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
313 }
314
315 return slots;
316}
317
318static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
319 struct intel_crtc_state *crtc_state,
320 struct drm_connector_state *conn_state,
321 struct link_config_limits *limits)
322{
323 int slots = -EINVAL;
324
325 /*
326 * FIXME: allocate the BW according to link_bpp, which in the case of
327 * YUV420 is only half of the pipe bpp value.
328 */
329 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
330 fxp_q4_to_int(limits->link.max_bpp_x16),
331 fxp_q4_to_int(limits->link.min_bpp_x16),
332 limits,
333 conn_state, 2 * 3, false);
334
335 if (slots < 0)
336 return slots;
337
338 return 0;
339}
340
341static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
342 struct intel_crtc_state *crtc_state,
343 struct drm_connector_state *conn_state,
344 struct link_config_limits *limits)
345{
346 struct intel_connector *connector =
347 to_intel_connector(conn_state->connector);
348 struct drm_i915_private *i915 = to_i915(connector->base.dev);
349 int slots = -EINVAL;
350 int i, num_bpc;
351 u8 dsc_bpc[3] = {};
352 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
353 u8 dsc_max_bpc;
354 int min_compressed_bpp, max_compressed_bpp;
355
356 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
357 if (DISPLAY_VER(i915) >= 12)
358 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
359 else
360 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
361
362 max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
363 min_bpp = limits->pipe.min_bpp;
364
365 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
366 dsc_bpc);
367
368 drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
369 min_bpp, max_bpp);
370
371 sink_max_bpp = dsc_bpc[0] * 3;
372 sink_min_bpp = sink_max_bpp;
373
374 for (i = 1; i < num_bpc; i++) {
375 if (sink_min_bpp > dsc_bpc[i] * 3)
376 sink_min_bpp = dsc_bpc[i] * 3;
377 if (sink_max_bpp < dsc_bpc[i] * 3)
378 sink_max_bpp = dsc_bpc[i] * 3;
379 }
380
381 drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
382 sink_min_bpp, sink_max_bpp);
383
384 if (min_bpp < sink_min_bpp)
385 min_bpp = sink_min_bpp;
386
387 if (max_bpp > sink_max_bpp)
388 max_bpp = sink_max_bpp;
389
390 crtc_state->pipe_bpp = max_bpp;
391
392 max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
393 crtc_state,
394 max_bpp / 3);
395 max_compressed_bpp = min(max_compressed_bpp,
396 fxp_q4_to_int(limits->link.max_bpp_x16));
397
398 min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
399 min_compressed_bpp = max(min_compressed_bpp,
400 fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
401
402 drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
403 min_compressed_bpp, max_compressed_bpp);
404
405 /* Align compressed bpps according to our own constraints */
406 max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
407 crtc_state->pipe_bpp);
408 min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
409 crtc_state->pipe_bpp);
410
411 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
412 min_compressed_bpp, limits,
413 conn_state, 1, true);
414
415 if (slots < 0)
416 return slots;
417
418 return 0;
419}
420static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
421 struct intel_crtc_state *crtc_state,
422 struct drm_connector_state *conn_state)
423{
424 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
425 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
426 struct intel_dp *intel_dp = &intel_mst->primary->dp;
427 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
428 struct drm_dp_mst_topology_state *topology_state;
429 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
430 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
431
432 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
433 if (IS_ERR(topology_state)) {
434 drm_dbg_kms(&i915->drm, "slot update failed\n");
435 return PTR_ERR(topology_state);
436 }
437
438 drm_dp_mst_update_slots(topology_state, link_coding_cap);
439
440 return 0;
441}
442
443static int mode_hblank_period_ns(const struct drm_display_mode *mode)
444{
445 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
446 NSEC_PER_SEC / 1000),
447 mode->crtc_clock);
448}
449
450static bool
451hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
452 const struct intel_crtc_state *crtc_state,
453 const struct link_config_limits *limits)
454{
455 const struct drm_display_mode *adjusted_mode =
456 &crtc_state->hw.adjusted_mode;
457 bool is_uhbr_sink = connector->mst_port &&
458 drm_dp_128b132b_supported(connector->mst_port->dpcd);
459 int hblank_limit = is_uhbr_sink ? 500 : 300;
460
461 if (!connector->dp.dsc_hblank_expansion_quirk)
462 return false;
463
464 if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
465 return false;
466
467 if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
468 return false;
469
470 if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state))
471 return false;
472
473 return true;
474}
475
476static bool
477adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
478 const struct intel_crtc_state *crtc_state,
479 struct link_config_limits *limits,
480 bool dsc)
481{
482 struct drm_i915_private *i915 = to_i915(connector->base.dev);
483 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
484 int min_bpp_x16 = limits->link.min_bpp_x16;
485
486 if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
487 return true;
488
489 if (!dsc) {
490 if (intel_dp_supports_dsc(connector, crtc_state)) {
491 drm_dbg_kms(&i915->drm,
492 "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
493 crtc->base.base.id, crtc->base.name,
494 connector->base.base.id, connector->base.name);
495 return false;
496 }
497
498 drm_dbg_kms(&i915->drm,
499 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
500 crtc->base.base.id, crtc->base.name,
501 connector->base.base.id, connector->base.name);
502
503 if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))
504 return false;
505
506 limits->link.min_bpp_x16 = fxp_q4_from_int(24);
507
508 return true;
509 }
510
511 drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
512
513 if (limits->max_rate < 540000)
514 min_bpp_x16 = fxp_q4_from_int(13);
515 else if (limits->max_rate < 810000)
516 min_bpp_x16 = fxp_q4_from_int(10);
517
518 if (limits->link.min_bpp_x16 >= min_bpp_x16)
519 return true;
520
521 drm_dbg_kms(&i915->drm,
522 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",
523 crtc->base.base.id, crtc->base.name,
524 connector->base.base.id, connector->base.name,
525 FXP_Q4_ARGS(min_bpp_x16));
526
527 if (limits->link.max_bpp_x16 < min_bpp_x16)
528 return false;
529
530 limits->link.min_bpp_x16 = min_bpp_x16;
531
532 return true;
533}
534
535static bool
536intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
537 const struct intel_connector *connector,
538 struct intel_crtc_state *crtc_state,
539 bool dsc,
540 struct link_config_limits *limits)
541{
542 /*
543 * for MST we always configure max link bw - the spec doesn't
544 * seem to suggest we should do otherwise.
545 */
546 limits->min_rate = limits->max_rate =
547 intel_dp_max_link_rate(intel_dp);
548
549 limits->min_lane_count = limits->max_lane_count =
550 intel_dp_max_lane_count(intel_dp);
551
552 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
553 /*
554 * FIXME: If all the streams can't fit into the link with
555 * their current pipe_bpp we should reduce pipe_bpp across
556 * the board until things start to fit. Until then we
557 * limit to <= 8bpc since that's what was hardcoded for all
558 * MST streams previously. This hack should be removed once
559 * we have the proper retry logic in place.
560 */
561 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
562
563 intel_dp_test_compute_config(intel_dp, crtc_state, limits);
564
565 if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
566 crtc_state,
567 dsc,
568 limits))
569 return false;
570
571 return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
572 crtc_state,
573 limits,
574 dsc);
575}
576
577static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
578 struct intel_crtc_state *pipe_config,
579 struct drm_connector_state *conn_state)
580{
581 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
582 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
583 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
584 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
585 struct intel_dp *intel_dp = &intel_mst->primary->dp;
586 struct intel_connector *connector =
587 to_intel_connector(conn_state->connector);
588 const struct drm_display_mode *adjusted_mode =
589 &pipe_config->hw.adjusted_mode;
590 struct link_config_limits limits;
591 bool dsc_needed, joiner_needs_dsc;
592 int num_joined_pipes;
593 int ret = 0;
594
595 if (pipe_config->fec_enable &&
596 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
597 return -EINVAL;
598
599 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
600 return -EINVAL;
601
602 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
603 adjusted_mode->crtc_hdisplay,
604 adjusted_mode->crtc_clock);
605 if (num_joined_pipes > 1)
606 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
607
608 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
609 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
610 pipe_config->has_pch_encoder = false;
611
612 joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes);
613
614 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
615 !intel_dp_mst_compute_config_limits(intel_dp,
616 connector,
617 pipe_config,
618 false,
619 &limits);
620
621 if (!dsc_needed) {
622 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
623 conn_state, &limits);
624
625 if (ret == -EDEADLK)
626 return ret;
627
628 if (ret)
629 dsc_needed = true;
630 }
631
632 /* enable compression if the mode doesn't fit available BW */
633 if (dsc_needed) {
634 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
635 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
636 str_yes_no(intel_dp->force_dsc_en));
637
638 if (!intel_dp_supports_dsc(connector, pipe_config))
639 return -EINVAL;
640
641 if (!intel_dp_mst_compute_config_limits(intel_dp,
642 connector,
643 pipe_config,
644 true,
645 &limits))
646 return -EINVAL;
647
648 /*
649 * FIXME: As bpc is hardcoded to 8, as mentioned above,
650 * WARN and ignore the debug flag force_dsc_bpc for now.
651 */
652 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
653 /*
654 * Try to get at least some timeslots and then see, if
655 * we can fit there with DSC.
656 */
657 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
658
659 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
660 conn_state, &limits);
661 if (ret < 0)
662 return ret;
663
664 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
665 conn_state, &limits,
666 pipe_config->dp_m_n.tu, false);
667 }
668
669 if (ret)
670 return ret;
671
672 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
673 if (ret)
674 return ret;
675
676 pipe_config->limited_color_range =
677 intel_dp_limited_color_range(pipe_config, conn_state);
678
679 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
680 pipe_config->lane_lat_optim_mask =
681 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
682
683 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
684
685 intel_ddi_compute_min_voltage_level(pipe_config);
686
687 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
688
689 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
690 pipe_config);
691}
692
693/*
694 * Iterate over all connectors and return a mask of
695 * all CPU transcoders streaming over the same DP link.
696 */
697static unsigned int
698intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
699 struct intel_dp *mst_port)
700{
701 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
702 const struct intel_digital_connector_state *conn_state;
703 struct intel_connector *connector;
704 u8 transcoders = 0;
705 int i;
706
707 if (DISPLAY_VER(dev_priv) < 12)
708 return 0;
709
710 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
711 const struct intel_crtc_state *crtc_state;
712 struct intel_crtc *crtc;
713
714 if (connector->mst_port != mst_port || !conn_state->base.crtc)
715 continue;
716
717 crtc = to_intel_crtc(conn_state->base.crtc);
718 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
719
720 if (!crtc_state->hw.active)
721 continue;
722
723 transcoders |= BIT(crtc_state->cpu_transcoder);
724 }
725
726 return transcoders;
727}
728
729static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
730 struct drm_dp_mst_topology_mgr *mst_mgr,
731 struct drm_dp_mst_port *parent_port)
732{
733 const struct intel_digital_connector_state *conn_state;
734 struct intel_connector *connector;
735 u8 mask = 0;
736 int i;
737
738 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
739 if (!conn_state->base.crtc)
740 continue;
741
742 if (&connector->mst_port->mst_mgr != mst_mgr)
743 continue;
744
745 if (connector->port != parent_port &&
746 !drm_dp_mst_port_downstream_of_parent(mst_mgr,
747 connector->port,
748 parent_port))
749 continue;
750
751 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
752 }
753
754 return mask;
755}
756
757static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
758 struct drm_dp_mst_topology_mgr *mst_mgr,
759 struct intel_link_bw_limits *limits)
760{
761 struct drm_i915_private *i915 = to_i915(state->base.dev);
762 struct intel_crtc *crtc;
763 u8 mst_pipe_mask;
764 u8 fec_pipe_mask = 0;
765 int ret;
766
767 mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
768
769 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
770 struct intel_crtc_state *crtc_state =
771 intel_atomic_get_new_crtc_state(state, crtc);
772
773 /* Atomic connector check should've added all the MST CRTCs. */
774 if (drm_WARN_ON(&i915->drm, !crtc_state))
775 return -EINVAL;
776
777 if (crtc_state->fec_enable)
778 fec_pipe_mask |= BIT(crtc->pipe);
779 }
780
781 if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
782 return 0;
783
784 limits->force_fec_pipes |= mst_pipe_mask;
785
786 ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
787 mst_pipe_mask);
788
789 return ret ? : -EAGAIN;
790}
791
792static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
793 struct drm_dp_mst_topology_mgr *mst_mgr,
794 struct drm_dp_mst_topology_state *mst_state,
795 struct intel_link_bw_limits *limits)
796{
797 struct drm_dp_mst_port *mst_port;
798 u8 mst_port_pipes;
799 int ret;
800
801 ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
802 if (ret != -ENOSPC)
803 return ret;
804
805 mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
806
807 ret = intel_link_bw_reduce_bpp(state, limits,
808 mst_port_pipes, "MST link BW");
809
810 return ret ? : -EAGAIN;
811}
812
813/**
814 * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
815 * @state: intel atomic state
816 * @limits: link BW limits
817 *
818 * Check the link configuration for all modeset MST outputs. If the
819 * configuration is invalid @limits will be updated if possible to
820 * reduce the total BW, after which the configuration for all CRTCs in
821 * @state must be recomputed with the updated @limits.
822 *
823 * Returns:
824 * - 0 if the confugration is valid
825 * - %-EAGAIN, if the configuration is invalid and @limits got updated
826 * with fallback values with which the configuration of all CRTCs in
827 * @state must be recomputed
828 * - Other negative error, if the configuration is invalid without a
829 * fallback possibility, or the check failed for another reason
830 */
831int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
832 struct intel_link_bw_limits *limits)
833{
834 struct drm_dp_mst_topology_mgr *mgr;
835 struct drm_dp_mst_topology_state *mst_state;
836 int ret;
837 int i;
838
839 for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
840 ret = intel_dp_mst_check_fec_change(state, mgr, limits);
841 if (ret)
842 return ret;
843
844 ret = intel_dp_mst_check_bw(state, mgr, mst_state,
845 limits);
846 if (ret)
847 return ret;
848 }
849
850 return 0;
851}
852
853static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
854 struct intel_crtc_state *crtc_state,
855 struct drm_connector_state *conn_state)
856{
857 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
858 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
859 struct intel_dp *intel_dp = &intel_mst->primary->dp;
860
861 /* lowest numbered transcoder will be designated master */
862 crtc_state->mst_master_transcoder =
863 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
864
865 return 0;
866}
867
868/*
869 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
870 * that shares the same MST stream as mode changed,
871 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
872 * a fastset when possible.
873 *
874 * On TGL+ this is required since each stream go through a master transcoder,
875 * so if the master transcoder needs modeset, all other streams in the
876 * topology need a modeset. All platforms need to add the atomic state
877 * for all streams in the topology, since a modeset on one may require
878 * changing the MST link BW usage of the others, which in turn needs a
879 * recomputation of the corresponding CRTC states.
880 */
881static int
882intel_dp_mst_atomic_topology_check(struct intel_connector *connector,
883 struct intel_atomic_state *state)
884{
885 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
886 struct drm_connector_list_iter connector_list_iter;
887 struct intel_connector *connector_iter;
888 int ret = 0;
889
890 if (!intel_connector_needs_modeset(state, &connector->base))
891 return 0;
892
893 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
894 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
895 struct intel_digital_connector_state *conn_iter_state;
896 struct intel_crtc_state *crtc_state;
897 struct intel_crtc *crtc;
898
899 if (connector_iter->mst_port != connector->mst_port ||
900 connector_iter == connector)
901 continue;
902
903 conn_iter_state = intel_atomic_get_digital_connector_state(state,
904 connector_iter);
905 if (IS_ERR(conn_iter_state)) {
906 ret = PTR_ERR(conn_iter_state);
907 break;
908 }
909
910 if (!conn_iter_state->base.crtc)
911 continue;
912
913 crtc = to_intel_crtc(conn_iter_state->base.crtc);
914 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
915 if (IS_ERR(crtc_state)) {
916 ret = PTR_ERR(crtc_state);
917 break;
918 }
919
920 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
921 if (ret)
922 break;
923 crtc_state->uapi.mode_changed = true;
924 }
925 drm_connector_list_iter_end(&connector_list_iter);
926
927 return ret;
928}
929
930static int
931intel_dp_mst_atomic_check(struct drm_connector *connector,
932 struct drm_atomic_state *_state)
933{
934 struct intel_atomic_state *state = to_intel_atomic_state(_state);
935 struct intel_connector *intel_connector =
936 to_intel_connector(connector);
937 int ret;
938
939 ret = intel_digital_connector_atomic_check(connector, &state->base);
940 if (ret)
941 return ret;
942
943 ret = intel_dp_mst_atomic_topology_check(intel_connector, state);
944 if (ret)
945 return ret;
946
947 if (intel_connector_needs_modeset(state, connector)) {
948 ret = intel_dp_tunnel_atomic_check_state(state,
949 intel_connector->mst_port,
950 intel_connector);
951 if (ret)
952 return ret;
953 }
954
955 return drm_dp_atomic_release_time_slots(&state->base,
956 &intel_connector->mst_port->mst_mgr,
957 intel_connector->port);
958}
959
960static void clear_act_sent(struct intel_encoder *encoder,
961 const struct intel_crtc_state *crtc_state)
962{
963 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
964
965 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
966 DP_TP_STATUS_ACT_SENT);
967}
968
969static void wait_for_act_sent(struct intel_encoder *encoder,
970 const struct intel_crtc_state *crtc_state)
971{
972 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
973 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
974 struct intel_dp *intel_dp = &intel_mst->primary->dp;
975
976 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
977 DP_TP_STATUS_ACT_SENT, 1))
978 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
979
980 drm_dp_check_act_status(&intel_dp->mst_mgr);
981}
982
983static void intel_mst_disable_dp(struct intel_atomic_state *state,
984 struct intel_encoder *encoder,
985 const struct intel_crtc_state *old_crtc_state,
986 const struct drm_connector_state *old_conn_state)
987{
988 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
989 struct intel_digital_port *dig_port = intel_mst->primary;
990 struct intel_dp *intel_dp = &dig_port->dp;
991 struct intel_connector *connector =
992 to_intel_connector(old_conn_state->connector);
993 struct drm_i915_private *i915 = to_i915(connector->base.dev);
994
995 drm_dbg_kms(&i915->drm, "active links %d\n",
996 intel_dp->active_mst_links);
997
998 if (intel_dp->active_mst_links == 1)
999 intel_dp->link_trained = false;
1000
1001 intel_hdcp_disable(intel_mst->connector);
1002
1003 intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
1004}
1005
1006static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
1007 struct intel_encoder *encoder,
1008 const struct intel_crtc_state *old_crtc_state,
1009 const struct drm_connector_state *old_conn_state)
1010{
1011 struct intel_display *display = to_intel_display(encoder);
1012 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1013 struct intel_digital_port *dig_port = intel_mst->primary;
1014 struct intel_dp *intel_dp = &dig_port->dp;
1015 struct intel_connector *connector =
1016 to_intel_connector(old_conn_state->connector);
1017 struct drm_dp_mst_topology_state *old_mst_state =
1018 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1019 struct drm_dp_mst_topology_state *new_mst_state =
1020 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1021 const struct drm_dp_mst_atomic_payload *old_payload =
1022 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
1023 struct drm_dp_mst_atomic_payload *new_payload =
1024 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
1025 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1026 struct intel_crtc *pipe_crtc;
1027 bool last_mst_stream;
1028 int i;
1029
1030 intel_dp->active_mst_links--;
1031 last_mst_stream = intel_dp->active_mst_links == 0;
1032 drm_WARN_ON(&dev_priv->drm,
1033 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
1034 !intel_dp_mst_is_master_trans(old_crtc_state));
1035
1036 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1037 const struct intel_crtc_state *old_pipe_crtc_state =
1038 intel_atomic_get_old_crtc_state(state, pipe_crtc);
1039
1040 intel_crtc_vblank_off(old_pipe_crtc_state);
1041 }
1042
1043 intel_disable_transcoder(old_crtc_state);
1044
1045 drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
1046
1047 clear_act_sent(encoder, old_crtc_state);
1048
1049 intel_de_rmw(dev_priv,
1050 TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),
1051 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
1052
1053 wait_for_act_sent(encoder, old_crtc_state);
1054
1055 drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
1056 old_payload, new_payload);
1057
1058 intel_ddi_disable_transcoder_func(old_crtc_state);
1059
1060 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1061 const struct intel_crtc_state *old_pipe_crtc_state =
1062 intel_atomic_get_old_crtc_state(state, pipe_crtc);
1063
1064 intel_dsc_disable(old_pipe_crtc_state);
1065
1066 if (DISPLAY_VER(dev_priv) >= 9)
1067 skl_scaler_disable(old_pipe_crtc_state);
1068 else
1069 ilk_pfit_disable(old_pipe_crtc_state);
1070 }
1071
1072 /*
1073 * Power down mst path before disabling the port, otherwise we end
1074 * up getting interrupts from the sink upon detecting link loss.
1075 */
1076 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
1077 false);
1078
1079 /*
1080 * BSpec 4287: disable DIP after the transcoder is disabled and before
1081 * the transcoder clock select is set to none.
1082 */
1083 intel_dp_set_infoframes(&dig_port->base, false,
1084 old_crtc_state, NULL);
1085 /*
1086 * From TGL spec: "If multi-stream slave transcoder: Configure
1087 * Transcoder Clock Select to direct no clock to the transcoder"
1088 *
1089 * From older GENs spec: "Configure Transcoder Clock Select to direct
1090 * no clock to the transcoder"
1091 */
1092 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
1093 intel_ddi_disable_transcoder_clock(old_crtc_state);
1094
1095
1096 intel_mst->connector = NULL;
1097 if (last_mst_stream)
1098 dig_port->base.post_disable(state, &dig_port->base,
1099 old_crtc_state, NULL);
1100
1101 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1102 intel_dp->active_mst_links);
1103}
1104
1105static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
1106 struct intel_encoder *encoder,
1107 const struct intel_crtc_state *old_crtc_state,
1108 const struct drm_connector_state *old_conn_state)
1109{
1110 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1111 struct intel_digital_port *dig_port = intel_mst->primary;
1112 struct intel_dp *intel_dp = &dig_port->dp;
1113
1114 if (intel_dp->active_mst_links == 0 &&
1115 dig_port->base.post_pll_disable)
1116 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
1117}
1118
1119static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
1120 struct intel_encoder *encoder,
1121 const struct intel_crtc_state *pipe_config,
1122 const struct drm_connector_state *conn_state)
1123{
1124 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1125 struct intel_digital_port *dig_port = intel_mst->primary;
1126 struct intel_dp *intel_dp = &dig_port->dp;
1127
1128 if (intel_dp->active_mst_links == 0)
1129 dig_port->base.pre_pll_enable(state, &dig_port->base,
1130 pipe_config, NULL);
1131 else
1132 /*
1133 * The port PLL state needs to get updated for secondary
1134 * streams as for the primary stream.
1135 */
1136 intel_ddi_update_active_dpll(state, &dig_port->base,
1137 to_intel_crtc(pipe_config->uapi.crtc));
1138}
1139
1140static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,
1141 int link_rate, int lane_count)
1142{
1143 return intel_dp->link.mst_probed_rate == link_rate &&
1144 intel_dp->link.mst_probed_lane_count == lane_count;
1145}
1146
1147static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,
1148 int link_rate, int lane_count)
1149{
1150 intel_dp->link.mst_probed_rate = link_rate;
1151 intel_dp->link.mst_probed_lane_count = lane_count;
1152}
1153
1154static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,
1155 const struct intel_crtc_state *crtc_state)
1156{
1157 if (intel_mst_probed_link_params_valid(intel_dp,
1158 crtc_state->port_clock, crtc_state->lane_count))
1159 return;
1160
1161 drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr);
1162
1163 intel_mst_set_probed_link_params(intel_dp,
1164 crtc_state->port_clock, crtc_state->lane_count);
1165}
1166
1167static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
1168 struct intel_encoder *encoder,
1169 const struct intel_crtc_state *pipe_config,
1170 const struct drm_connector_state *conn_state)
1171{
1172 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1173 struct intel_digital_port *dig_port = intel_mst->primary;
1174 struct intel_dp *intel_dp = &dig_port->dp;
1175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1176 struct intel_connector *connector =
1177 to_intel_connector(conn_state->connector);
1178 struct drm_dp_mst_topology_state *mst_state =
1179 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1180 int ret;
1181 bool first_mst_stream;
1182
1183 /* MST encoders are bound to a crtc, not to a connector,
1184 * force the mapping here for get_hw_state.
1185 */
1186 connector->encoder = encoder;
1187 intel_mst->connector = connector;
1188 first_mst_stream = intel_dp->active_mst_links == 0;
1189 drm_WARN_ON(&dev_priv->drm,
1190 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
1191 !intel_dp_mst_is_master_trans(pipe_config));
1192
1193 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1194 intel_dp->active_mst_links);
1195
1196 if (first_mst_stream)
1197 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
1198
1199 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
1200
1201 intel_dp_sink_enable_decompression(state, connector, pipe_config);
1202
1203 if (first_mst_stream) {
1204 dig_port->base.pre_enable(state, &dig_port->base,
1205 pipe_config, NULL);
1206
1207 intel_mst_reprobe_topology(intel_dp, pipe_config);
1208 }
1209
1210 intel_dp->active_mst_links++;
1211
1212 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
1213 drm_atomic_get_mst_payload_state(mst_state, connector->port));
1214 if (ret < 0)
1215 intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);
1216
1217 /*
1218 * Before Gen 12 this is not done as part of
1219 * dig_port->base.pre_enable() and should be done here. For
1220 * Gen 12+ the step in which this should be done is different for the
1221 * first MST stream, so it's done on the DDI for the first stream and
1222 * here for the following ones.
1223 */
1224 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
1225 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
1226
1227 intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
1228 intel_ddi_set_dp_msa(pipe_config, conn_state);
1229}
1230
1231static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
1232{
1233 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1234 u32 clear = 0;
1235 u32 set = 0;
1236
1237 if (!IS_ALDERLAKE_P(i915))
1238 return;
1239
1240 if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
1241 return;
1242
1243 /* Wa_14013163432:adlp */
1244 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1245 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
1246
1247 /* Wa_14014143976:adlp */
1248 if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
1249 if (intel_dp_is_uhbr(crtc_state))
1250 set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1251 else if (crtc_state->fec_enable)
1252 clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1253
1254 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1255 set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
1256 }
1257
1258 if (!clear && !set)
1259 return;
1260
1261 intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
1262}
1263
1264static void intel_mst_enable_dp(struct intel_atomic_state *state,
1265 struct intel_encoder *encoder,
1266 const struct intel_crtc_state *pipe_config,
1267 const struct drm_connector_state *conn_state)
1268{
1269 struct intel_display *display = to_intel_display(encoder);
1270 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1271 struct intel_digital_port *dig_port = intel_mst->primary;
1272 struct intel_dp *intel_dp = &dig_port->dp;
1273 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1275 struct drm_dp_mst_topology_state *mst_state =
1276 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1277 enum transcoder trans = pipe_config->cpu_transcoder;
1278 bool first_mst_stream = intel_dp->active_mst_links == 1;
1279 struct intel_crtc *pipe_crtc;
1280 int ret, i;
1281
1282 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
1283
1284 if (intel_dp_is_uhbr(pipe_config)) {
1285 const struct drm_display_mode *adjusted_mode =
1286 &pipe_config->hw.adjusted_mode;
1287 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
1288
1289 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
1290 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
1291 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
1292 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
1293 }
1294
1295 enable_bs_jitter_was(pipe_config);
1296
1297 intel_ddi_enable_transcoder_func(encoder, pipe_config);
1298
1299 clear_act_sent(encoder, pipe_config);
1300
1301 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0,
1302 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1303
1304 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1305 intel_dp->active_mst_links);
1306
1307 wait_for_act_sent(encoder, pipe_config);
1308
1309 if (first_mst_stream)
1310 intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
1311
1312 ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr,
1313 drm_atomic_get_mst_payload_state(mst_state,
1314 connector->port));
1315 if (ret < 0)
1316 intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);
1317
1318 if (DISPLAY_VER(dev_priv) >= 12)
1319 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
1320 FECSTALL_DIS_DPTSTREAM_DPTTG,
1321 pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
1322
1323 intel_audio_sdp_split_update(pipe_config);
1324
1325 intel_enable_transcoder(pipe_config);
1326
1327 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config, i) {
1328 const struct intel_crtc_state *pipe_crtc_state =
1329 intel_atomic_get_new_crtc_state(state, pipe_crtc);
1330
1331 intel_crtc_vblank_on(pipe_crtc_state);
1332 }
1333
1334 intel_hdcp_enable(state, encoder, pipe_config, conn_state);
1335}
1336
1337static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
1338 enum pipe *pipe)
1339{
1340 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1341 *pipe = intel_mst->pipe;
1342 if (intel_mst->connector)
1343 return true;
1344 return false;
1345}
1346
1347static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
1348 struct intel_crtc_state *pipe_config)
1349{
1350 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1351 struct intel_digital_port *dig_port = intel_mst->primary;
1352
1353 dig_port->base.get_config(&dig_port->base, pipe_config);
1354}
1355
1356static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
1357 struct intel_crtc_state *crtc_state)
1358{
1359 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1360 struct intel_digital_port *dig_port = intel_mst->primary;
1361
1362 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
1363}
1364
1365static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
1366{
1367 struct intel_connector *intel_connector = to_intel_connector(connector);
1368 struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
1369 struct intel_dp *intel_dp = intel_connector->mst_port;
1370 const struct drm_edid *drm_edid;
1371 int ret;
1372
1373 if (drm_connector_is_unregistered(connector))
1374 return intel_connector_update_modes(connector, NULL);
1375
1376 if (!intel_display_driver_check_access(i915))
1377 return drm_edid_connector_add_modes(connector);
1378
1379 drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
1380
1381 ret = intel_connector_update_modes(connector, drm_edid);
1382
1383 drm_edid_free(drm_edid);
1384
1385 return ret;
1386}
1387
1388static int
1389intel_dp_mst_connector_late_register(struct drm_connector *connector)
1390{
1391 struct intel_connector *intel_connector = to_intel_connector(connector);
1392 int ret;
1393
1394 ret = drm_dp_mst_connector_late_register(connector,
1395 intel_connector->port);
1396 if (ret < 0)
1397 return ret;
1398
1399 ret = intel_connector_register(connector);
1400 if (ret < 0)
1401 drm_dp_mst_connector_early_unregister(connector,
1402 intel_connector->port);
1403
1404 return ret;
1405}
1406
1407static void
1408intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
1409{
1410 struct intel_connector *intel_connector = to_intel_connector(connector);
1411
1412 intel_connector_unregister(connector);
1413 drm_dp_mst_connector_early_unregister(connector,
1414 intel_connector->port);
1415}
1416
1417static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
1418 .fill_modes = drm_helper_probe_single_connector_modes,
1419 .atomic_get_property = intel_digital_connector_atomic_get_property,
1420 .atomic_set_property = intel_digital_connector_atomic_set_property,
1421 .late_register = intel_dp_mst_connector_late_register,
1422 .early_unregister = intel_dp_mst_connector_early_unregister,
1423 .destroy = intel_connector_destroy,
1424 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1425 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1426};
1427
1428static int intel_dp_mst_get_modes(struct drm_connector *connector)
1429{
1430 return intel_dp_mst_get_ddc_modes(connector);
1431}
1432
1433static int
1434intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
1435 struct drm_display_mode *mode,
1436 struct drm_modeset_acquire_ctx *ctx,
1437 enum drm_mode_status *status)
1438{
1439 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1440 struct intel_connector *intel_connector = to_intel_connector(connector);
1441 struct intel_dp *intel_dp = intel_connector->mst_port;
1442 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
1443 struct drm_dp_mst_port *port = intel_connector->port;
1444 const int min_bpp = 18;
1445 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
1446 int max_rate, mode_rate, max_lanes, max_link_clock;
1447 int ret;
1448 bool dsc = false;
1449 u16 dsc_max_compressed_bpp = 0;
1450 u8 dsc_slice_count = 0;
1451 int target_clock = mode->clock;
1452 int num_joined_pipes;
1453
1454 if (drm_connector_is_unregistered(connector)) {
1455 *status = MODE_ERROR;
1456 return 0;
1457 }
1458
1459 *status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1460 if (*status != MODE_OK)
1461 return 0;
1462
1463 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1464 *status = MODE_H_ILLEGAL;
1465 return 0;
1466 }
1467
1468 if (mode->clock < 10000) {
1469 *status = MODE_CLOCK_LOW;
1470 return 0;
1471 }
1472
1473 max_link_clock = intel_dp_max_link_rate(intel_dp);
1474 max_lanes = intel_dp_max_lane_count(intel_dp);
1475
1476 max_rate = intel_dp_max_link_data_rate(intel_dp,
1477 max_link_clock, max_lanes);
1478 mode_rate = intel_dp_link_required(mode->clock, min_bpp);
1479
1480 /*
1481 * TODO:
1482 * - Also check if compression would allow for the mode
1483 * - Calculate the overhead using drm_dp_bw_overhead() /
1484 * drm_dp_bw_channel_coding_efficiency(), similarly to the
1485 * compute config code, as drm_dp_calc_pbn_mode() doesn't
1486 * account with all the overheads.
1487 * - Check here and during compute config the BW reported by
1488 * DFP_Link_Available_Payload_Bandwidth_Number (or the
1489 * corresponding link capabilities of the sink) in case the
1490 * stream is uncompressed for it by the last branch device.
1491 */
1492 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, intel_connector,
1493 mode->hdisplay, target_clock);
1494 max_dotclk *= num_joined_pipes;
1495
1496 ret = drm_modeset_lock(&mgr->base.lock, ctx);
1497 if (ret)
1498 return ret;
1499
1500 if (mode_rate > max_rate || mode->clock > max_dotclk ||
1501 drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
1502 *status = MODE_CLOCK_HIGH;
1503 return 0;
1504 }
1505
1506 if (intel_dp_has_dsc(intel_connector)) {
1507 /*
1508 * TBD pass the connector BPC,
1509 * for now U8_MAX so that max BPC on that platform would be picked
1510 */
1511 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
1512
1513 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1514 dsc_max_compressed_bpp =
1515 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1516 max_link_clock,
1517 max_lanes,
1518 target_clock,
1519 mode->hdisplay,
1520 num_joined_pipes,
1521 INTEL_OUTPUT_FORMAT_RGB,
1522 pipe_bpp, 64);
1523 dsc_slice_count =
1524 intel_dp_dsc_get_slice_count(intel_connector,
1525 target_clock,
1526 mode->hdisplay,
1527 num_joined_pipes);
1528 }
1529
1530 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1531 }
1532
1533 if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc) {
1534 *status = MODE_CLOCK_HIGH;
1535 return 0;
1536 }
1537
1538 if (mode_rate > max_rate && !dsc) {
1539 *status = MODE_CLOCK_HIGH;
1540 return 0;
1541 }
1542
1543 *status = intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1544 return 0;
1545}
1546
1547static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1548 struct drm_atomic_state *state)
1549{
1550 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1551 connector);
1552 struct intel_connector *intel_connector = to_intel_connector(connector);
1553 struct intel_dp *intel_dp = intel_connector->mst_port;
1554 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1555
1556 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1557}
1558
1559static int
1560intel_dp_mst_detect(struct drm_connector *connector,
1561 struct drm_modeset_acquire_ctx *ctx, bool force)
1562{
1563 struct drm_i915_private *i915 = to_i915(connector->dev);
1564 struct intel_connector *intel_connector = to_intel_connector(connector);
1565 struct intel_dp *intel_dp = intel_connector->mst_port;
1566
1567 if (!intel_display_device_enabled(i915))
1568 return connector_status_disconnected;
1569
1570 if (drm_connector_is_unregistered(connector))
1571 return connector_status_disconnected;
1572
1573 if (!intel_display_driver_check_access(i915))
1574 return connector->status;
1575
1576 intel_dp_flush_connector_commits(intel_connector);
1577
1578 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1579 intel_connector->port);
1580}
1581
1582static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1583 .get_modes = intel_dp_mst_get_modes,
1584 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1585 .atomic_best_encoder = intel_mst_atomic_best_encoder,
1586 .atomic_check = intel_dp_mst_atomic_check,
1587 .detect_ctx = intel_dp_mst_detect,
1588};
1589
1590static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1591{
1592 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1593
1594 drm_encoder_cleanup(encoder);
1595 kfree(intel_mst);
1596}
1597
1598static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1599 .destroy = intel_dp_mst_encoder_destroy,
1600};
1601
1602static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1603{
1604 if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1605 enum pipe pipe;
1606 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1607 return false;
1608 return true;
1609 }
1610 return false;
1611}
1612
1613static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1614 struct drm_connector *connector,
1615 const char *pathprop)
1616{
1617 struct drm_i915_private *i915 = to_i915(connector->dev);
1618
1619 drm_object_attach_property(&connector->base,
1620 i915->drm.mode_config.path_property, 0);
1621 drm_object_attach_property(&connector->base,
1622 i915->drm.mode_config.tile_property, 0);
1623
1624 intel_attach_force_audio_property(connector);
1625 intel_attach_broadcast_rgb_property(connector);
1626
1627 /*
1628 * Reuse the prop from the SST connector because we're
1629 * not allowed to create new props after device registration.
1630 */
1631 connector->max_bpc_property =
1632 intel_dp->attached_connector->base.max_bpc_property;
1633 if (connector->max_bpc_property)
1634 drm_connector_attach_max_bpc_property(connector, 6, 12);
1635
1636 return drm_connector_set_path_property(connector, pathprop);
1637}
1638
1639static void
1640intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1641 struct intel_connector *connector)
1642{
1643 u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1644
1645 if (!connector->dp.dsc_decompression_aux)
1646 return;
1647
1648 if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
1649 return;
1650
1651 intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
1652}
1653
1654static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
1655{
1656 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1657 struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;
1658 struct drm_dp_desc desc;
1659 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1660
1661 if (!aux)
1662 return false;
1663
1664 /*
1665 * A logical port's OUI (at least for affected sinks) is all 0, so
1666 * instead of that the parent port's OUI is used for identification.
1667 */
1668 if (drm_dp_mst_port_is_logical(connector->port)) {
1669 aux = drm_dp_mst_aux_for_parent(connector->port);
1670 if (!aux)
1671 aux = &connector->mst_port->aux;
1672 }
1673
1674 if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)
1675 return false;
1676
1677 if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0)
1678 return false;
1679
1680 if (!drm_dp_has_quirk(&desc,
1681 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
1682 return false;
1683
1684 /*
1685 * UHBR (MST sink) devices requiring this quirk don't advertise the
1686 * HBLANK expansion support. Presuming that they perform HBLANK
1687 * expansion internally, or are affected by this issue on modes with a
1688 * short HBLANK for other reasons.
1689 */
1690 if (!drm_dp_128b132b_supported(dpcd) &&
1691 !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
1692 return false;
1693
1694 drm_dbg_kms(&i915->drm,
1695 "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
1696 connector->base.base.id, connector->base.name);
1697
1698 return true;
1699}
1700
1701static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1702 struct drm_dp_mst_port *port,
1703 const char *pathprop)
1704{
1705 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1706 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1707 struct drm_device *dev = dig_port->base.base.dev;
1708 struct drm_i915_private *dev_priv = to_i915(dev);
1709 struct intel_connector *intel_connector;
1710 struct drm_connector *connector;
1711 enum pipe pipe;
1712 int ret;
1713
1714 intel_connector = intel_connector_alloc();
1715 if (!intel_connector)
1716 return NULL;
1717
1718 intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1719 intel_connector->sync_state = intel_dp_connector_sync_state;
1720 intel_connector->mst_port = intel_dp;
1721 intel_connector->port = port;
1722 drm_dp_mst_get_port_malloc(port);
1723
1724 intel_dp_init_modeset_retry_work(intel_connector);
1725
1726 intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
1727 intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
1728 intel_connector->dp.dsc_hblank_expansion_quirk =
1729 detect_dsc_hblank_expansion_quirk(intel_connector);
1730
1731 connector = &intel_connector->base;
1732 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1733 DRM_MODE_CONNECTOR_DisplayPort);
1734 if (ret) {
1735 drm_dp_mst_put_port_malloc(port);
1736 intel_connector_free(intel_connector);
1737 return NULL;
1738 }
1739
1740 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1741
1742 for_each_pipe(dev_priv, pipe) {
1743 struct drm_encoder *enc =
1744 &intel_dp->mst_encoders[pipe]->base.base;
1745
1746 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1747 if (ret)
1748 goto err;
1749 }
1750
1751 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1752 if (ret)
1753 goto err;
1754
1755 ret = intel_dp_hdcp_init(dig_port, intel_connector);
1756 if (ret)
1757 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1758 connector->name, connector->base.id);
1759
1760 return connector;
1761
1762err:
1763 drm_connector_cleanup(connector);
1764 return NULL;
1765}
1766
1767static void
1768intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1769{
1770 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1771
1772 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1773}
1774
1775static const struct drm_dp_mst_topology_cbs mst_cbs = {
1776 .add_connector = intel_dp_add_mst_connector,
1777 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1778};
1779
1780static struct intel_dp_mst_encoder *
1781intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1782{
1783 struct intel_dp_mst_encoder *intel_mst;
1784 struct intel_encoder *intel_encoder;
1785 struct drm_device *dev = dig_port->base.base.dev;
1786
1787 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1788
1789 if (!intel_mst)
1790 return NULL;
1791
1792 intel_mst->pipe = pipe;
1793 intel_encoder = &intel_mst->base;
1794 intel_mst->primary = dig_port;
1795
1796 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1797 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1798
1799 intel_encoder->type = INTEL_OUTPUT_DP_MST;
1800 intel_encoder->power_domain = dig_port->base.power_domain;
1801 intel_encoder->port = dig_port->base.port;
1802 intel_encoder->cloneable = 0;
1803 /*
1804 * This is wrong, but broken userspace uses the intersection
1805 * of possible_crtcs of all the encoders of a given connector
1806 * to figure out which crtcs can drive said connector. What
1807 * should be used instead is the union of possible_crtcs.
1808 * To keep such userspace functioning we must misconfigure
1809 * this to make sure the intersection is not empty :(
1810 */
1811 intel_encoder->pipe_mask = ~0;
1812
1813 intel_encoder->compute_config = intel_dp_mst_compute_config;
1814 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1815 intel_encoder->disable = intel_mst_disable_dp;
1816 intel_encoder->post_disable = intel_mst_post_disable_dp;
1817 intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1818 intel_encoder->update_pipe = intel_ddi_update_pipe;
1819 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1820 intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1821 intel_encoder->enable = intel_mst_enable_dp;
1822 intel_encoder->audio_enable = intel_audio_codec_enable;
1823 intel_encoder->audio_disable = intel_audio_codec_disable;
1824 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1825 intel_encoder->get_config = intel_dp_mst_enc_get_config;
1826 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1827
1828 return intel_mst;
1829
1830}
1831
1832static bool
1833intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1834{
1835 struct intel_dp *intel_dp = &dig_port->dp;
1836 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1837 enum pipe pipe;
1838
1839 for_each_pipe(dev_priv, pipe)
1840 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1841 return true;
1842}
1843
1844int
1845intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1846{
1847 return dig_port->dp.active_mst_links;
1848}
1849
1850int
1851intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1852{
1853 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1854 struct intel_dp *intel_dp = &dig_port->dp;
1855 enum port port = dig_port->base.port;
1856 int ret;
1857
1858 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1859 return 0;
1860
1861 if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1862 return 0;
1863
1864 if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1865 return 0;
1866
1867 intel_dp->mst_mgr.cbs = &mst_cbs;
1868
1869 /* create encoders */
1870 intel_dp_create_fake_mst_encoders(dig_port);
1871 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1872 &intel_dp->aux, 16, 3, conn_base_id);
1873 if (ret) {
1874 intel_dp->mst_mgr.cbs = NULL;
1875 return ret;
1876 }
1877
1878 return 0;
1879}
1880
1881bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1882{
1883 return intel_dp->mst_mgr.cbs;
1884}
1885
1886void
1887intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1888{
1889 struct intel_dp *intel_dp = &dig_port->dp;
1890
1891 if (!intel_dp_mst_source_support(intel_dp))
1892 return;
1893
1894 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1895 /* encoders will get killed by normal cleanup */
1896
1897 intel_dp->mst_mgr.cbs = NULL;
1898}
1899
1900bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1901{
1902 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1903}
1904
1905bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1906{
1907 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1908 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1909}
1910
1911/**
1912 * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1913 * @state: atomic state
1914 * @connector: connector to add the state for
1915 * @crtc: the CRTC @connector is attached to
1916 *
1917 * Add the MST topology state for @connector to @state.
1918 *
1919 * Returns 0 on success, negative error code on failure.
1920 */
1921static int
1922intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1923 struct intel_connector *connector,
1924 struct intel_crtc *crtc)
1925{
1926 struct drm_dp_mst_topology_state *mst_state;
1927
1928 if (!connector->mst_port)
1929 return 0;
1930
1931 mst_state = drm_atomic_get_mst_topology_state(&state->base,
1932 &connector->mst_port->mst_mgr);
1933 if (IS_ERR(mst_state))
1934 return PTR_ERR(mst_state);
1935
1936 mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1937
1938 return 0;
1939}
1940
1941/**
1942 * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1943 * @state: atomic state
1944 * @crtc: CRTC to add the state for
1945 *
1946 * Add the MST topology state for @crtc to @state.
1947 *
1948 * Returns 0 on success, negative error code on failure.
1949 */
1950int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1951 struct intel_crtc *crtc)
1952{
1953 struct drm_connector *_connector;
1954 struct drm_connector_state *conn_state;
1955 int i;
1956
1957 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1958 struct intel_connector *connector = to_intel_connector(_connector);
1959 int ret;
1960
1961 if (conn_state->crtc != &crtc->base)
1962 continue;
1963
1964 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1965 if (ret)
1966 return ret;
1967 }
1968
1969 return 0;
1970}
1971
1972static struct intel_connector *
1973get_connector_in_state_for_crtc(struct intel_atomic_state *state,
1974 const struct intel_crtc *crtc)
1975{
1976 struct drm_connector_state *old_conn_state;
1977 struct drm_connector_state *new_conn_state;
1978 struct drm_connector *_connector;
1979 int i;
1980
1981 for_each_oldnew_connector_in_state(&state->base, _connector,
1982 old_conn_state, new_conn_state, i) {
1983 struct intel_connector *connector =
1984 to_intel_connector(_connector);
1985
1986 if (old_conn_state->crtc == &crtc->base ||
1987 new_conn_state->crtc == &crtc->base)
1988 return connector;
1989 }
1990
1991 return NULL;
1992}
1993
1994/**
1995 * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
1996 * @state: atomic state
1997 * @crtc: CRTC for which to check the modeset requirement
1998 *
1999 * Check if any change in a MST topology requires a forced modeset on @crtc in
2000 * this topology. One such change is enabling/disabling the DSC decompression
2001 * state in the first branch device's UFP DPCD as required by one CRTC, while
2002 * the other @crtc in the same topology is still active, requiring a full modeset
2003 * on @crtc.
2004 */
2005bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
2006 struct intel_crtc *crtc)
2007{
2008 const struct intel_connector *crtc_connector;
2009 const struct drm_connector_state *conn_state;
2010 const struct drm_connector *_connector;
2011 int i;
2012
2013 if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
2014 INTEL_OUTPUT_DP_MST))
2015 return false;
2016
2017 crtc_connector = get_connector_in_state_for_crtc(state, crtc);
2018
2019 if (!crtc_connector)
2020 /* None of the connectors in the topology needs modeset */
2021 return false;
2022
2023 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
2024 const struct intel_connector *connector =
2025 to_intel_connector(_connector);
2026 const struct intel_crtc_state *new_crtc_state;
2027 const struct intel_crtc_state *old_crtc_state;
2028 struct intel_crtc *crtc_iter;
2029
2030 if (connector->mst_port != crtc_connector->mst_port ||
2031 !conn_state->crtc)
2032 continue;
2033
2034 crtc_iter = to_intel_crtc(conn_state->crtc);
2035
2036 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
2037 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
2038
2039 if (!intel_crtc_needs_modeset(new_crtc_state))
2040 continue;
2041
2042 if (old_crtc_state->dsc.compression_enable ==
2043 new_crtc_state->dsc.compression_enable)
2044 continue;
2045 /*
2046 * Toggling the decompression flag because of this stream in
2047 * the first downstream branch device's UFP DPCD may reset the
2048 * whole branch device. To avoid the reset while other streams
2049 * are also active modeset the whole MST topology in this
2050 * case.
2051 */
2052 if (connector->dp.dsc_decompression_aux ==
2053 &connector->mst_port->aux)
2054 return true;
2055 }
2056
2057 return false;
2058}
2059
2060/**
2061 * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing
2062 * @intel_dp: DP port object
2063 *
2064 * Prepare an MST link for topology probing, programming the target
2065 * link parameters to DPCD. This step is a requirement of the enumaration
2066 * of path resources during probing.
2067 */
2068void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
2069{
2070 int link_rate = intel_dp_max_link_rate(intel_dp);
2071 int lane_count = intel_dp_max_lane_count(intel_dp);
2072 u8 rate_select;
2073 u8 link_bw;
2074
2075 if (intel_dp->link_trained)
2076 return;
2077
2078 if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
2079 return;
2080
2081 intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
2082
2083 intel_dp_link_training_set_mode(intel_dp, link_rate, false);
2084 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
2085 drm_dp_enhanced_frame_cap(intel_dp->dpcd));
2086
2087 intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
2088}
2089
2090/*
2091 * intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD
2092 * @intel_dp: DP port object
2093 *
2094 * Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD
2095 * state. A long HPD pulse - not long enough to be detected as a disconnected
2096 * state - could've reset the DPCD state, which requires tearing
2097 * down/recreating the MST topology.
2098 *
2099 * Returns %true if the SW MST enabled and DPCD states match, %false
2100 * otherwise.
2101 */
2102bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)
2103{
2104 struct intel_display *display = to_intel_display(intel_dp);
2105 struct intel_connector *connector = intel_dp->attached_connector;
2106 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2107 struct intel_encoder *encoder = &dig_port->base;
2108 int ret;
2109 u8 val;
2110
2111 if (!intel_dp->is_mst)
2112 return true;
2113
2114 ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val);
2115
2116 /* Adjust the expected register value for SST + SideBand. */
2117 if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {
2118 drm_dbg_kms(display->drm,
2119 "[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n",
2120 connector->base.base.id, connector->base.name,
2121 encoder->base.base.id, encoder->base.name,
2122 ret, val);
2123
2124 return false;
2125 }
2126
2127 return true;
2128}