1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5#ifndef __INTEL_DISPLAY_POWER_WELL_H__
  6#define __INTEL_DISPLAY_POWER_WELL_H__
  7
  8#include <linux/types.h>
  9
 10#include "intel_display_power.h"
 11#include "intel_dpio_phy.h"
 12
 13struct drm_i915_private;
 14struct i915_power_well_ops;
 15struct intel_display;
 16struct intel_encoder;
 17
 18#define for_each_power_well(__dev_priv, __power_well)				\
 19	for ((__power_well) = (__dev_priv)->display.power.domains.power_wells;	\
 20	     (__power_well) - (__dev_priv)->display.power.domains.power_wells <	\
 21		(__dev_priv)->display.power.domains.power_well_count;		\
 22	     (__power_well)++)
 23
 24#define for_each_power_well_reverse(__dev_priv, __power_well)			\
 25	for ((__power_well) = (__dev_priv)->display.power.domains.power_wells +		\
 26			      (__dev_priv)->display.power.domains.power_well_count - 1;	\
 27	     (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0;	\
 28	     (__power_well)--)
 29
 30/*
 31 * i915_power_well_id:
 32 *
 33 * IDs used to look up power wells. Power wells accessed directly bypassing
 34 * the power domains framework must be assigned a unique ID. The rest of power
 35 * wells must be assigned DISP_PW_ID_NONE.
 36 */
 37enum i915_power_well_id {
 38	DISP_PW_ID_NONE = 0,		/* must be kept zero */
 39
 40	VLV_DISP_PW_DISP2D,
 41	BXT_DISP_PW_DPIO_CMN_A,
 42	VLV_DISP_PW_DPIO_CMN_BC,
 43	GLK_DISP_PW_DPIO_CMN_C,
 44	CHV_DISP_PW_DPIO_CMN_D,
 45	HSW_DISP_PW_GLOBAL,
 46	SKL_DISP_PW_MISC_IO,
 47	SKL_DISP_PW_1,
 48	SKL_DISP_PW_2,
 49	ICL_DISP_PW_3,
 50	SKL_DISP_DC_OFF,
 51	TGL_DISP_PW_TC_COLD_OFF,
 52};
 53
 54struct i915_power_well_instance {
 55	const char *name;
 56	const struct i915_power_domain_list {
 57		const enum intel_display_power_domain *list;
 58		u8 count;
 59	} *domain_list;
 60
 61	/* unique identifier for this power well */
 62	enum i915_power_well_id id;
 63	/*
 64	 * Arbitraty data associated with this power well. Platform and power
 65	 * well specific.
 66	 */
 67	union {
 68		struct {
 69			/*
 70			 * request/status flag index in the PUNIT power well
 71			 * control/status registers.
 72			 */
 73			u8 idx;
 74		} vlv;
 75		struct {
 76			enum dpio_phy phy;
 77		} bxt;
 78		struct {
 79			/*
 80			 * request/status flag index in the power well
 81			 * constrol/status registers.
 82			 */
 83			u8 idx;
 84		} hsw;
 85		struct {
 86			u8 aux_ch;
 87		} xelpdp;
 88	};
 89};
 90
 91struct i915_power_well_desc {
 92	const struct i915_power_well_ops *ops;
 93	const struct i915_power_well_instance_list {
 94		const struct i915_power_well_instance *list;
 95		u8 count;
 96	} *instances;
 97
 98	/* Mask of pipes whose IRQ logic is backed by the pw */
 99	u16 irq_pipe_mask:4;
100	u16 always_on:1;
101	/*
102	 * Instead of waiting for the status bit to ack enables,
103	 * just wait a specific amount of time and then consider
104	 * the well enabled.
105	 */
106	u16 fixed_enable_delay:1;
107	/* The pw is backing the VGA functionality */
108	u16 has_vga:1;
109	u16 has_fuses:1;
110	/*
111	 * The pw is for an ICL+ TypeC PHY port in
112	 * Thunderbolt mode.
113	 */
114	u16 is_tc_tbt:1;
115	/* Enable timeout if greater than the default 1ms */
116	u16 enable_timeout;
117};
118
119struct i915_power_well {
120	const struct i915_power_well_desc *desc;
121	struct intel_power_domain_mask domains;
122	/* power well enable/disable usage count */
123	int count;
124	/* cached hw enabled state */
125	bool hw_enabled;
126	/* index into desc->instances->list */
127	u8 instance_idx;
128};
129
130struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
131					  enum i915_power_well_id id);
132
133void intel_power_well_enable(struct drm_i915_private *i915,
134			     struct i915_power_well *power_well);
135void intel_power_well_disable(struct drm_i915_private *i915,
136			      struct i915_power_well *power_well);
137void intel_power_well_sync_hw(struct drm_i915_private *i915,
138			      struct i915_power_well *power_well);
139void intel_power_well_get(struct drm_i915_private *i915,
140			  struct i915_power_well *power_well);
141void intel_power_well_put(struct drm_i915_private *i915,
142			  struct i915_power_well *power_well);
143bool intel_power_well_is_enabled(struct drm_i915_private *i915,
144				 struct i915_power_well *power_well);
145bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
146bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
147					 enum i915_power_well_id power_well_id);
148bool intel_power_well_is_always_on(struct i915_power_well *power_well);
149const char *intel_power_well_name(struct i915_power_well *power_well);
150struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well);
151int intel_power_well_refcount(struct i915_power_well *power_well);
152
153void chv_phy_powergate_lanes(struct intel_encoder *encoder,
154			     bool override, unsigned int mask);
155bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
156			  enum dpio_channel ch, bool override);
157
158void gen9_enable_dc5(struct intel_display *display);
159void skl_enable_dc6(struct intel_display *display);
160void gen9_sanitize_dc_state(struct intel_display *display);
161void gen9_set_dc_state(struct intel_display *display, u32 state);
162void gen9_disable_dc_states(struct intel_display *display);
163void bxt_enable_dc9(struct intel_display *display);
164void bxt_disable_dc9(struct intel_display *display);
165
166extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
167extern const struct i915_power_well_ops chv_pipe_power_well_ops;
168extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
169extern const struct i915_power_well_ops i830_pipes_power_well_ops;
170extern const struct i915_power_well_ops hsw_power_well_ops;
171extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
172extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
173extern const struct i915_power_well_ops vlv_display_power_well_ops;
174extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
175extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
176extern const struct i915_power_well_ops icl_aux_power_well_ops;
177extern const struct i915_power_well_ops icl_ddi_power_well_ops;
178extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
179extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
180extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
181
182#endif