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1/*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30#include "i915_reg_defs.h"
31#include "intel_display_limits.h"
32
33enum drm_scaling_filter;
34struct dpll;
35struct drm_atomic_state;
36struct drm_connector;
37struct drm_device;
38struct drm_display_mode;
39struct drm_encoder;
40struct drm_file;
41struct drm_format_info;
42struct drm_framebuffer;
43struct drm_i915_private;
44struct drm_mode_fb_cmd2;
45struct drm_modeset_acquire_ctx;
46struct drm_plane;
47struct drm_plane_state;
48struct i915_address_space;
49struct i915_gtt_view;
50struct intel_atomic_state;
51struct intel_crtc;
52struct intel_crtc_state;
53struct intel_digital_port;
54struct intel_display;
55struct intel_dp;
56struct intel_encoder;
57struct intel_initial_plane_config;
58struct intel_link_m_n;
59struct intel_plane;
60struct intel_plane_state;
61struct intel_power_domain_mask;
62struct intel_remapped_info;
63struct intel_rotation_info;
64struct pci_dev;
65struct work_struct;
66
67
68#define pipe_name(p) ((p) + 'A')
69
70static inline const char *transcoder_name(enum transcoder transcoder)
71{
72 switch (transcoder) {
73 case TRANSCODER_A:
74 return "A";
75 case TRANSCODER_B:
76 return "B";
77 case TRANSCODER_C:
78 return "C";
79 case TRANSCODER_D:
80 return "D";
81 case TRANSCODER_EDP:
82 return "EDP";
83 case TRANSCODER_DSI_A:
84 return "DSI A";
85 case TRANSCODER_DSI_C:
86 return "DSI C";
87 default:
88 return "<invalid>";
89 }
90}
91
92static inline bool transcoder_is_dsi(enum transcoder transcoder)
93{
94 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
95}
96
97#define plane_name(p) ((p) + 'A')
98
99#define for_each_plane_id_on_crtc(__crtc, __p) \
100 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
101 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
102
103#define for_each_dbuf_slice(__dev_priv, __slice) \
104 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
105 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
106
107#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
108 for_each_dbuf_slice((__dev_priv), (__slice)) \
109 for_each_if((__mask) & BIT(__slice))
110
111#define port_name(p) ((p) + 'A')
112
113/*
114 * Ports identifier referenced from other drivers.
115 * Expected to remain stable over time
116 */
117static inline const char *port_identifier(enum port port)
118{
119 switch (port) {
120 case PORT_A:
121 return "Port A";
122 case PORT_B:
123 return "Port B";
124 case PORT_C:
125 return "Port C";
126 case PORT_D:
127 return "Port D";
128 case PORT_E:
129 return "Port E";
130 case PORT_F:
131 return "Port F";
132 case PORT_G:
133 return "Port G";
134 case PORT_H:
135 return "Port H";
136 case PORT_I:
137 return "Port I";
138 default:
139 return "<invalid>";
140 }
141}
142
143enum tc_port {
144 TC_PORT_NONE = -1,
145
146 TC_PORT_1 = 0,
147 TC_PORT_2,
148 TC_PORT_3,
149 TC_PORT_4,
150 TC_PORT_5,
151 TC_PORT_6,
152
153 I915_MAX_TC_PORTS
154};
155
156enum aux_ch {
157 AUX_CH_NONE = -1,
158
159 AUX_CH_A,
160 AUX_CH_B,
161 AUX_CH_C,
162 AUX_CH_D,
163 AUX_CH_E, /* ICL+ */
164 AUX_CH_F,
165 AUX_CH_G,
166 AUX_CH_H,
167 AUX_CH_I,
168
169 /* tgl+ */
170 AUX_CH_USBC1 = AUX_CH_D,
171 AUX_CH_USBC2,
172 AUX_CH_USBC3,
173 AUX_CH_USBC4,
174 AUX_CH_USBC5,
175 AUX_CH_USBC6,
176
177 /* XE_LPD repositions D/E offsets and bitfields */
178 AUX_CH_D_XELPD = AUX_CH_USBC5,
179 AUX_CH_E_XELPD,
180};
181
182enum phy {
183 PHY_NONE = -1,
184
185 PHY_A = 0,
186 PHY_B,
187 PHY_C,
188 PHY_D,
189 PHY_E,
190 PHY_F,
191 PHY_G,
192 PHY_H,
193 PHY_I,
194
195 I915_MAX_PHYS
196};
197
198#define phy_name(a) ((a) + 'A')
199
200enum phy_fia {
201 FIA1,
202 FIA2,
203 FIA3,
204};
205
206#define for_each_hpd_pin(__pin) \
207 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
208
209#define for_each_pipe(__dev_priv, __p) \
210 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
211 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
212
213#define for_each_pipe_masked(__dev_priv, __p, __mask) \
214 for_each_pipe(__dev_priv, __p) \
215 for_each_if((__mask) & BIT(__p))
216
217#define for_each_cpu_transcoder(__dev_priv, __t) \
218 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
219 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
220
221#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
222 for_each_cpu_transcoder(__dev_priv, __t) \
223 for_each_if ((__mask) & BIT(__t))
224
225#define for_each_sprite(__dev_priv, __p, __s) \
226 for ((__s) = 0; \
227 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
228 (__s)++)
229
230#define for_each_port(__port) \
231 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
232
233#define for_each_port_masked(__port, __ports_mask) \
234 for_each_port(__port) \
235 for_each_if((__ports_mask) & BIT(__port))
236
237#define for_each_phy_masked(__phy, __phys_mask) \
238 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
239 for_each_if((__phys_mask) & BIT(__phy))
240
241#define for_each_crtc(dev, crtc) \
242 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
243
244#define for_each_intel_plane(dev, intel_plane) \
245 list_for_each_entry(intel_plane, \
246 &(dev)->mode_config.plane_list, \
247 base.head)
248
249#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
250 list_for_each_entry(intel_plane, \
251 &(dev)->mode_config.plane_list, \
252 base.head) \
253 for_each_if((plane_mask) & \
254 drm_plane_mask(&intel_plane->base))
255
256#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
257 list_for_each_entry(intel_plane, \
258 &(dev)->mode_config.plane_list, \
259 base.head) \
260 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
261
262#define for_each_intel_crtc(dev, intel_crtc) \
263 list_for_each_entry(intel_crtc, \
264 &(dev)->mode_config.crtc_list, \
265 base.head)
266
267#define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
268 list_for_each_entry(intel_crtc, \
269 &(dev)->mode_config.crtc_list, \
270 base.head) \
271 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
272
273#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \
274 list_for_each_entry_reverse((intel_crtc), \
275 &(dev)->mode_config.crtc_list, \
276 base.head) \
277 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
278
279#define for_each_intel_encoder(dev, intel_encoder) \
280 list_for_each_entry(intel_encoder, \
281 &(dev)->mode_config.encoder_list, \
282 base.head)
283
284#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
285 list_for_each_entry(intel_encoder, \
286 &(dev)->mode_config.encoder_list, \
287 base.head) \
288 for_each_if((encoder_mask) & \
289 drm_encoder_mask(&intel_encoder->base))
290
291#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
292 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
293 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
294 intel_encoder_can_psr(intel_encoder))
295
296#define for_each_intel_dp(dev, intel_encoder) \
297 for_each_intel_encoder(dev, intel_encoder) \
298 for_each_if(intel_encoder_is_dp(intel_encoder))
299
300#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
301 for_each_intel_encoder((dev), (intel_encoder)) \
302 for_each_if(intel_encoder_can_psr(intel_encoder))
303
304#define for_each_intel_connector_iter(intel_connector, iter) \
305 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
306
307#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
308 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
309 for_each_if((intel_encoder)->base.crtc == (__crtc))
310
311#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
312 for ((__i) = 0; \
313 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
314 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
315 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
316 (__i)++) \
317 for_each_if(plane)
318
319#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
320 for ((__i) = 0; \
321 (__i) < (__state)->base.dev->mode_config.num_crtc && \
322 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
323 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
324 (__i)++) \
325 for_each_if(crtc)
326
327#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
328 for ((__i) = 0; \
329 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
330 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
331 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
332 (__i)++) \
333 for_each_if(plane)
334
335#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
336 for ((__i) = 0; \
337 (__i) < (__state)->base.dev->mode_config.num_crtc && \
338 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
339 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
340 (__i)++) \
341 for_each_if(crtc)
342
343#define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
344 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
345 (__i) >= 0 && \
346 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
347 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
348 (__i)--) \
349 for_each_if(crtc)
350
351#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
352 for ((__i) = 0; \
353 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
354 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
355 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
356 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
357 (__i)++) \
358 for_each_if(plane)
359
360#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
361 for ((__i) = 0; \
362 (__i) < (__state)->base.dev->mode_config.num_crtc && \
363 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
364 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
365 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
366 (__i)++) \
367 for_each_if(crtc)
368
369#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
370 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
371 (__i) >= 0 && \
372 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
373 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
374 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
375 (__i)--) \
376 for_each_if(crtc)
377
378#define intel_atomic_crtc_state_for_each_plane_state( \
379 plane, plane_state, \
380 crtc_state) \
381 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
382 ((crtc_state)->uapi.plane_mask)) \
383 for_each_if ((plane_state = \
384 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
385
386#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
387 for ((__i) = 0; \
388 (__i) < (__state)->base.num_connector; \
389 (__i)++) \
390 for_each_if ((__state)->base.connectors[__i].ptr && \
391 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
392 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
393
394#define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
395 for ((i) = 0; \
396 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
397 (i)++) \
398 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
399
400#define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
401 for ((i) = (I915_MAX_PIPES * 2 - 1); \
402 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
403 (i)--) \
404 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
405
406#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \
407 for_each_crtc_in_masks(display, crtc, \
408 _intel_modeset_primary_pipes(crtc_state), \
409 _intel_modeset_secondary_pipes(crtc_state), \
410 i)
411
412#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \
413 for_each_crtc_in_masks_reverse(display, crtc, \
414 _intel_modeset_primary_pipes(crtc_state), \
415 _intel_modeset_secondary_pipes(crtc_state), \
416 i)
417
418int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
419int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
420 struct intel_crtc *crtc);
421u8 intel_calc_active_pipes(struct intel_atomic_state *state,
422 u8 active_pipes);
423void intel_link_compute_m_n(u16 bpp, int nlanes,
424 int pixel_clock, int link_clock,
425 int bw_overhead,
426 struct intel_link_m_n *m_n);
427u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
428 u32 pixel_format, u64 modifier);
429enum drm_mode_status
430intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
431 const struct drm_display_mode *mode,
432 int num_joined_pipes);
433enum drm_mode_status
434intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
435 const struct drm_display_mode *mode);
436enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
437bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
438bool is_trans_port_sync_master(const struct intel_crtc_state *state);
439u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
440bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
441bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
442bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
443bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
444bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
445bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
446bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
447u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
448u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
449u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
450struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
451bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
452bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
453 const struct intel_crtc_state *pipe_config,
454 bool fastset);
455
456void intel_plane_destroy(struct drm_plane *plane);
457void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
458void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
459void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
460void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
461void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
462void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
463int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
464int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
465 const char *name, u32 reg, int ref_freq);
466int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
467 const char *name, u32 reg);
468void intel_init_display_hooks(struct drm_i915_private *dev_priv);
469unsigned int intel_fb_xy_to_linear(int x, int y,
470 const struct intel_plane_state *state,
471 int plane);
472void intel_add_fb_offsets(int *x, int *y,
473 const struct intel_plane_state *state, int plane);
474unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
475unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
476bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
477void intel_encoder_destroy(struct drm_encoder *encoder);
478struct drm_display_mode *
479intel_encoder_current_mode(struct intel_encoder *encoder);
480void intel_encoder_get_config(struct intel_encoder *encoder,
481 struct intel_crtc_state *crtc_state);
482bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
483bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
484bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
485enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
486 enum port port);
487
488enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
489bool intel_encoder_is_combo(struct intel_encoder *encoder);
490bool intel_encoder_is_snps(struct intel_encoder *encoder);
491bool intel_encoder_is_tc(struct intel_encoder *encoder);
492enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
493
494int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
495void vlv_wait_port_ready(struct intel_display *display,
496 struct intel_digital_port *dig_port,
497 unsigned int expected_mask);
498
499bool intel_fuzzy_clock_check(int clock1, int clock2);
500
501void intel_zero_m_n(struct intel_link_m_n *m_n);
502void intel_set_m_n(struct drm_i915_private *i915,
503 const struct intel_link_m_n *m_n,
504 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
505 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
506void intel_get_m_n(struct drm_i915_private *i915,
507 struct intel_link_m_n *m_n,
508 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
509 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
510bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
511 enum transcoder transcoder);
512void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
513 enum transcoder cpu_transcoder,
514 const struct intel_link_m_n *m_n);
515void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
516 enum transcoder cpu_transcoder,
517 const struct intel_link_m_n *m_n);
518void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
519 enum transcoder cpu_transcoder,
520 struct intel_link_m_n *m_n);
521void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
522 enum transcoder cpu_transcoder,
523 struct intel_link_m_n *m_n);
524int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
525int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
526enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
527enum intel_display_power_domain
528intel_aux_power_domain(struct intel_digital_port *dig_port);
529void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
530 struct intel_crtc_state *crtc_state);
531void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
532
533int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
534unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
535
536bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
537
538struct intel_encoder *
539intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
540 const struct intel_crtc_state *crtc_state);
541void intel_plane_disable_noatomic(struct intel_crtc *crtc,
542 struct intel_plane *plane);
543void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
544 struct intel_plane_state *plane_state,
545 bool visible);
546void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
547
548void intel_update_watermarks(struct drm_i915_private *i915);
549
550bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
551 struct intel_crtc *crtc);
552
553/* modesetting */
554int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
555 const char *reason, u8 pipe_mask);
556int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
557 const char *reason);
558int intel_modeset_commit_pipes(struct drm_i915_private *i915,
559 u8 pipe_mask,
560 struct drm_modeset_acquire_ctx *ctx);
561void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
562 struct intel_power_domain_mask *old_domains);
563void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
564 struct intel_power_domain_mask *domains);
565
566/* interface for intel_display_driver.c */
567void intel_setup_outputs(struct drm_i915_private *i915);
568int intel_initial_commit(struct drm_device *dev);
569void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
570void intel_update_czclk(struct drm_i915_private *i915);
571void intel_atomic_helper_free_state_worker(struct work_struct *work);
572enum drm_mode_status intel_mode_valid(struct drm_device *dev,
573 const struct drm_display_mode *mode);
574int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
575 bool nonblock);
576
577void intel_hpd_poll_fini(struct drm_i915_private *i915);
578
579/* modesetting asserts */
580void assert_transcoder(struct drm_i915_private *dev_priv,
581 enum transcoder cpu_transcoder, bool state);
582#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
583#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
584
585bool assert_port_valid(struct drm_i915_private *i915, enum port port);
586
587/*
588 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
589 * state sanity checks to check for unexpected conditions which may not
590 * necessarily be a user visible problem. This will either drm_WARN() or
591 * drm_err() depending on the verbose_state_checks module param, to enable
592 * distros and users to tailor their preferred amount of i915 abrt spam.
593 */
594#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \
595 int __ret_warn_on = !!(condition); \
596 if (unlikely(__ret_warn_on)) \
597 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
598 drm_err((__display)->drm, format); \
599 unlikely(__ret_warn_on); \
600})
601
602bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
603int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
604
605#endif