Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/iopoll.h>
29#include <linux/string_helpers.h>
30
31#include <drm/display/drm_scdc_helper.h>
32#include <drm/drm_privacy_screen_consumer.h>
33
34#include "i915_drv.h"
35#include "i915_reg.h"
36#include "icl_dsi.h"
37#include "intel_audio.h"
38#include "intel_audio_regs.h"
39#include "intel_backlight.h"
40#include "intel_combo_phy.h"
41#include "intel_combo_phy_regs.h"
42#include "intel_connector.h"
43#include "intel_crtc.h"
44#include "intel_cx0_phy.h"
45#include "intel_cx0_phy_regs.h"
46#include "intel_ddi.h"
47#include "intel_ddi_buf_trans.h"
48#include "intel_de.h"
49#include "intel_display_power.h"
50#include "intel_display_types.h"
51#include "intel_dkl_phy.h"
52#include "intel_dkl_phy_regs.h"
53#include "intel_dp.h"
54#include "intel_dp_aux.h"
55#include "intel_dp_link_training.h"
56#include "intel_dp_mst.h"
57#include "intel_dp_test.h"
58#include "intel_dp_tunnel.h"
59#include "intel_dpio_phy.h"
60#include "intel_dsi.h"
61#include "intel_encoder.h"
62#include "intel_fdi.h"
63#include "intel_fifo_underrun.h"
64#include "intel_gmbus.h"
65#include "intel_hdcp.h"
66#include "intel_hdmi.h"
67#include "intel_hotplug.h"
68#include "intel_hti.h"
69#include "intel_lspcon.h"
70#include "intel_mg_phy_regs.h"
71#include "intel_modeset_lock.h"
72#include "intel_pps.h"
73#include "intel_psr.h"
74#include "intel_quirks.h"
75#include "intel_snps_phy.h"
76#include "intel_tc.h"
77#include "intel_vdsc.h"
78#include "intel_vdsc_regs.h"
79#include "skl_scaler.h"
80#include "skl_universal_plane.h"
81
82static const u8 index_to_dp_signal_levels[] = {
83 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
84 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
85 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
86 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
87 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
88 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
89 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
90 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
91 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
92 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
93};
94
95static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
96 const struct intel_ddi_buf_trans *trans)
97{
98 int level;
99
100 level = intel_bios_hdmi_level_shift(encoder->devdata);
101 if (level < 0)
102 level = trans->hdmi_default_entry;
103
104 return level;
105}
106
107static bool has_buf_trans_select(struct drm_i915_private *i915)
108{
109 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
110}
111
112static bool has_iboost(struct drm_i915_private *i915)
113{
114 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
115}
116
117/*
118 * Starting with Haswell, DDI port buffers must be programmed with correct
119 * values in advance. This function programs the correct values for
120 * DP/eDP/FDI use cases.
121 */
122void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
123 const struct intel_crtc_state *crtc_state)
124{
125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
126 u32 iboost_bit = 0;
127 int i, n_entries;
128 enum port port = encoder->port;
129 const struct intel_ddi_buf_trans *trans;
130
131 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
132 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
133 return;
134
135 /* If we're boosting the current, set bit 31 of trans1 */
136 if (has_iboost(dev_priv) &&
137 intel_bios_dp_boost_level(encoder->devdata))
138 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
139
140 for (i = 0; i < n_entries; i++) {
141 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
142 trans->entries[i].hsw.trans1 | iboost_bit);
143 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
144 trans->entries[i].hsw.trans2);
145 }
146}
147
148/*
149 * Starting with Haswell, DDI port buffers must be programmed with correct
150 * values in advance. This function programs the correct values for
151 * HDMI/DVI use cases.
152 */
153static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
154 const struct intel_crtc_state *crtc_state)
155{
156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
157 int level = intel_ddi_level(encoder, crtc_state, 0);
158 u32 iboost_bit = 0;
159 int n_entries;
160 enum port port = encoder->port;
161 const struct intel_ddi_buf_trans *trans;
162
163 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
164 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
165 return;
166
167 /* If we're boosting the current, set bit 31 of trans1 */
168 if (has_iboost(dev_priv) &&
169 intel_bios_hdmi_boost_level(encoder->devdata))
170 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
171
172 /* Entry 9 is for HDMI: */
173 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
174 trans->entries[level].hsw.trans1 | iboost_bit);
175 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
176 trans->entries[level].hsw.trans2);
177}
178
179static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
180{
181 int ret;
182
183 /* FIXME: find out why Bspec's 100us timeout is too short */
184 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) &
185 XELPDP_PORT_BUF_PHY_IDLE), 10000);
186 if (ret)
187 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
188 port_name(port));
189}
190
191void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
192 enum port port)
193{
194 if (IS_BROXTON(dev_priv)) {
195 udelay(16);
196 return;
197 }
198
199 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
200 DDI_BUF_IS_IDLE), 8))
201 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
202 port_name(port));
203}
204
205static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
206{
207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
208 enum port port = encoder->port;
209 int timeout_us;
210 int ret;
211
212 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
213 if (DISPLAY_VER(dev_priv) < 10) {
214 usleep_range(518, 1000);
215 return;
216 }
217
218 if (DISPLAY_VER(dev_priv) >= 14) {
219 timeout_us = 10000;
220 } else if (IS_DG2(dev_priv)) {
221 timeout_us = 1200;
222 } else if (DISPLAY_VER(dev_priv) >= 12) {
223 if (intel_encoder_is_tc(encoder))
224 timeout_us = 3000;
225 else
226 timeout_us = 1000;
227 } else {
228 timeout_us = 500;
229 }
230
231 if (DISPLAY_VER(dev_priv) >= 14)
232 ret = _wait_for(!(intel_de_read(dev_priv,
233 XELPDP_PORT_BUF_CTL1(dev_priv, port)) &
234 XELPDP_PORT_BUF_PHY_IDLE),
235 timeout_us, 10, 10);
236 else
237 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
238 timeout_us, 10, 10);
239
240 if (ret)
241 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
242 port_name(port));
243}
244
245static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
246{
247 switch (pll->info->id) {
248 case DPLL_ID_WRPLL1:
249 return PORT_CLK_SEL_WRPLL1;
250 case DPLL_ID_WRPLL2:
251 return PORT_CLK_SEL_WRPLL2;
252 case DPLL_ID_SPLL:
253 return PORT_CLK_SEL_SPLL;
254 case DPLL_ID_LCPLL_810:
255 return PORT_CLK_SEL_LCPLL_810;
256 case DPLL_ID_LCPLL_1350:
257 return PORT_CLK_SEL_LCPLL_1350;
258 case DPLL_ID_LCPLL_2700:
259 return PORT_CLK_SEL_LCPLL_2700;
260 default:
261 MISSING_CASE(pll->info->id);
262 return PORT_CLK_SEL_NONE;
263 }
264}
265
266static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state)
268{
269 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
270 int clock = crtc_state->port_clock;
271 const enum intel_dpll_id id = pll->info->id;
272
273 switch (id) {
274 default:
275 /*
276 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
277 * here, so do warn if this get passed in
278 */
279 MISSING_CASE(id);
280 return DDI_CLK_SEL_NONE;
281 case DPLL_ID_ICL_TBTPLL:
282 switch (clock) {
283 case 162000:
284 return DDI_CLK_SEL_TBT_162;
285 case 270000:
286 return DDI_CLK_SEL_TBT_270;
287 case 540000:
288 return DDI_CLK_SEL_TBT_540;
289 case 810000:
290 return DDI_CLK_SEL_TBT_810;
291 default:
292 MISSING_CASE(clock);
293 return DDI_CLK_SEL_NONE;
294 }
295 case DPLL_ID_ICL_MGPLL1:
296 case DPLL_ID_ICL_MGPLL2:
297 case DPLL_ID_ICL_MGPLL3:
298 case DPLL_ID_ICL_MGPLL4:
299 case DPLL_ID_TGL_MGPLL5:
300 case DPLL_ID_TGL_MGPLL6:
301 return DDI_CLK_SEL_MG;
302 }
303}
304
305static u32 ddi_buf_phy_link_rate(int port_clock)
306{
307 switch (port_clock) {
308 case 162000:
309 return DDI_BUF_PHY_LINK_RATE(0);
310 case 216000:
311 return DDI_BUF_PHY_LINK_RATE(4);
312 case 243000:
313 return DDI_BUF_PHY_LINK_RATE(5);
314 case 270000:
315 return DDI_BUF_PHY_LINK_RATE(1);
316 case 324000:
317 return DDI_BUF_PHY_LINK_RATE(6);
318 case 432000:
319 return DDI_BUF_PHY_LINK_RATE(7);
320 case 540000:
321 return DDI_BUF_PHY_LINK_RATE(2);
322 case 810000:
323 return DDI_BUF_PHY_LINK_RATE(3);
324 default:
325 MISSING_CASE(port_clock);
326 return DDI_BUF_PHY_LINK_RATE(0);
327 }
328}
329
330static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
331 const struct intel_crtc_state *crtc_state)
332{
333 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
335 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
336
337 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
338 intel_dp->DP = dig_port->saved_port_bits |
339 DDI_PORT_WIDTH(crtc_state->lane_count) |
340 DDI_BUF_TRANS_SELECT(0);
341
342 if (DISPLAY_VER(i915) >= 14) {
343 if (intel_dp_is_uhbr(crtc_state))
344 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
345 else
346 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
347 }
348
349 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) {
350 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
351 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
352 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
353 }
354}
355
356static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
357 enum port port)
358{
359 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
360
361 switch (val) {
362 case DDI_CLK_SEL_NONE:
363 return 0;
364 case DDI_CLK_SEL_TBT_162:
365 return 162000;
366 case DDI_CLK_SEL_TBT_270:
367 return 270000;
368 case DDI_CLK_SEL_TBT_540:
369 return 540000;
370 case DDI_CLK_SEL_TBT_810:
371 return 810000;
372 default:
373 MISSING_CASE(val);
374 return 0;
375 }
376}
377
378static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
379{
380 /* CRT dotclock is determined via other means */
381 if (pipe_config->has_pch_encoder)
382 return;
383
384 pipe_config->hw.adjusted_mode.crtc_clock =
385 intel_crtc_dotclock(pipe_config);
386}
387
388void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
389 const struct drm_connector_state *conn_state)
390{
391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
393 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
394 u32 temp;
395
396 if (!intel_crtc_has_dp_encoder(crtc_state))
397 return;
398
399 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
400
401 temp = DP_MSA_MISC_SYNC_CLOCK;
402
403 switch (crtc_state->pipe_bpp) {
404 case 18:
405 temp |= DP_MSA_MISC_6_BPC;
406 break;
407 case 24:
408 temp |= DP_MSA_MISC_8_BPC;
409 break;
410 case 30:
411 temp |= DP_MSA_MISC_10_BPC;
412 break;
413 case 36:
414 temp |= DP_MSA_MISC_12_BPC;
415 break;
416 default:
417 MISSING_CASE(crtc_state->pipe_bpp);
418 break;
419 }
420
421 /* nonsense combination */
422 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
423 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
424
425 if (crtc_state->limited_color_range)
426 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
427
428 /*
429 * As per DP 1.2 spec section 2.3.4.3 while sending
430 * YCBCR 444 signals we should program MSA MISC1/0 fields with
431 * colorspace information.
432 */
433 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
434 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
435
436 /*
437 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
438 * of Color Encoding Format and Content Color Gamut] while sending
439 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
440 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
441 */
442 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
443 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
444
445 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder),
446 temp);
447}
448
449static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
450{
451 if (master_transcoder == TRANSCODER_EDP)
452 return 0;
453 else
454 return master_transcoder + 1;
455}
456
457static void
458intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
459 const struct intel_crtc_state *crtc_state)
460{
461 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
462 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
463 u32 val = 0;
464
465 if (intel_dp_is_uhbr(crtc_state))
466 val = TRANS_DP2_128B132B_CHANNEL_CODING;
467
468 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
469}
470
471/*
472 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
473 *
474 * Only intended to be used by intel_ddi_enable_transcoder_func() and
475 * intel_ddi_config_transcoder_func().
476 */
477static u32
478intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
479 const struct intel_crtc_state *crtc_state)
480{
481 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
483 enum pipe pipe = crtc->pipe;
484 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
485 enum port port = encoder->port;
486 u32 temp;
487
488 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
489 temp = TRANS_DDI_FUNC_ENABLE;
490 if (DISPLAY_VER(dev_priv) >= 12)
491 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
492 else
493 temp |= TRANS_DDI_SELECT_PORT(port);
494
495 switch (crtc_state->pipe_bpp) {
496 default:
497 MISSING_CASE(crtc_state->pipe_bpp);
498 fallthrough;
499 case 18:
500 temp |= TRANS_DDI_BPC_6;
501 break;
502 case 24:
503 temp |= TRANS_DDI_BPC_8;
504 break;
505 case 30:
506 temp |= TRANS_DDI_BPC_10;
507 break;
508 case 36:
509 temp |= TRANS_DDI_BPC_12;
510 break;
511 }
512
513 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
514 temp |= TRANS_DDI_PVSYNC;
515 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
516 temp |= TRANS_DDI_PHSYNC;
517
518 if (cpu_transcoder == TRANSCODER_EDP) {
519 switch (pipe) {
520 default:
521 MISSING_CASE(pipe);
522 fallthrough;
523 case PIPE_A:
524 /* On Haswell, can only use the always-on power well for
525 * eDP when not using the panel fitter, and when not
526 * using motion blur mitigation (which we don't
527 * support). */
528 if (crtc_state->pch_pfit.force_thru)
529 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
530 else
531 temp |= TRANS_DDI_EDP_INPUT_A_ON;
532 break;
533 case PIPE_B:
534 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
535 break;
536 case PIPE_C:
537 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
538 break;
539 }
540 }
541
542 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
543 if (crtc_state->has_hdmi_sink)
544 temp |= TRANS_DDI_MODE_SELECT_HDMI;
545 else
546 temp |= TRANS_DDI_MODE_SELECT_DVI;
547
548 if (crtc_state->hdmi_scrambling)
549 temp |= TRANS_DDI_HDMI_SCRAMBLING;
550 if (crtc_state->hdmi_high_tmds_clock_ratio)
551 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
552 if (DISPLAY_VER(dev_priv) >= 14)
553 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
555 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
556 temp |= (crtc_state->fdi_lanes - 1) << 1;
557 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
558 if (intel_dp_is_uhbr(crtc_state))
559 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
560 else
561 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
562 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
563
564 if (DISPLAY_VER(dev_priv) >= 12) {
565 enum transcoder master;
566
567 master = crtc_state->mst_master_transcoder;
568 drm_WARN_ON(&dev_priv->drm,
569 master == INVALID_TRANSCODER);
570 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
571 }
572 } else {
573 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
574 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
575 }
576
577 if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
578 crtc_state->master_transcoder != INVALID_TRANSCODER) {
579 u8 master_select =
580 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
581
582 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
583 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
584 }
585
586 return temp;
587}
588
589void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
590 const struct intel_crtc_state *crtc_state)
591{
592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
594 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
595
596 if (DISPLAY_VER(dev_priv) >= 11) {
597 enum transcoder master_transcoder = crtc_state->master_transcoder;
598 u32 ctl2 = 0;
599
600 if (master_transcoder != INVALID_TRANSCODER) {
601 u8 master_select =
602 bdw_trans_port_sync_master_select(master_transcoder);
603
604 ctl2 |= PORT_SYNC_MODE_ENABLE |
605 PORT_SYNC_MODE_MASTER_SELECT(master_select);
606 }
607
608 intel_de_write(dev_priv,
609 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
610 ctl2);
611 }
612
613 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
614 intel_ddi_transcoder_func_reg_val_get(encoder,
615 crtc_state));
616}
617
618/*
619 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
620 * bit.
621 */
622static void
623intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
624 const struct intel_crtc_state *crtc_state)
625{
626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
628 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
629 u32 ctl;
630
631 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
632 ctl &= ~TRANS_DDI_FUNC_ENABLE;
633 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
634 ctl);
635}
636
637void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
638{
639 struct intel_display *display = to_intel_display(crtc_state);
640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
642 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
643 u32 ctl;
644
645 if (DISPLAY_VER(dev_priv) >= 11)
646 intel_de_write(dev_priv,
647 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
648 0);
649
650 ctl = intel_de_read(dev_priv,
651 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
652
653 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
654
655 ctl &= ~TRANS_DDI_FUNC_ENABLE;
656
657 if (IS_DISPLAY_VER(dev_priv, 8, 10))
658 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
659 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
660
661 if (DISPLAY_VER(dev_priv) >= 12) {
662 if (!intel_dp_mst_is_master_trans(crtc_state)) {
663 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
664 TRANS_DDI_MODE_SELECT_MASK);
665 }
666 } else {
667 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
668 }
669
670 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
671 ctl);
672
673 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
674 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
675 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");
676 /* Quirk time at 100ms for reliable operation */
677 msleep(100);
678 }
679}
680
681int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
682 enum transcoder cpu_transcoder,
683 bool enable, u32 hdcp_mask)
684{
685 struct drm_device *dev = intel_encoder->base.dev;
686 struct drm_i915_private *dev_priv = to_i915(dev);
687 intel_wakeref_t wakeref;
688 int ret = 0;
689
690 wakeref = intel_display_power_get_if_enabled(dev_priv,
691 intel_encoder->power_domain);
692 if (drm_WARN_ON(dev, !wakeref))
693 return -ENXIO;
694
695 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
696 hdcp_mask, enable ? hdcp_mask : 0);
697 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
698 return ret;
699}
700
701bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
702{
703 struct drm_device *dev = intel_connector->base.dev;
704 struct drm_i915_private *dev_priv = to_i915(dev);
705 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
706 int type = intel_connector->base.connector_type;
707 enum port port = encoder->port;
708 enum transcoder cpu_transcoder;
709 intel_wakeref_t wakeref;
710 enum pipe pipe = 0;
711 u32 tmp;
712 bool ret;
713
714 wakeref = intel_display_power_get_if_enabled(dev_priv,
715 encoder->power_domain);
716 if (!wakeref)
717 return false;
718
719 if (!encoder->get_hw_state(encoder, &pipe)) {
720 ret = false;
721 goto out;
722 }
723
724 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
725 cpu_transcoder = TRANSCODER_EDP;
726 else
727 cpu_transcoder = (enum transcoder) pipe;
728
729 tmp = intel_de_read(dev_priv,
730 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
731
732 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
733 case TRANS_DDI_MODE_SELECT_HDMI:
734 case TRANS_DDI_MODE_SELECT_DVI:
735 ret = type == DRM_MODE_CONNECTOR_HDMIA;
736 break;
737
738 case TRANS_DDI_MODE_SELECT_DP_SST:
739 ret = type == DRM_MODE_CONNECTOR_eDP ||
740 type == DRM_MODE_CONNECTOR_DisplayPort;
741 break;
742
743 case TRANS_DDI_MODE_SELECT_DP_MST:
744 /* if the transcoder is in MST state then
745 * connector isn't connected */
746 ret = false;
747 break;
748
749 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
750 if (HAS_DP20(dev_priv))
751 /* 128b/132b */
752 ret = false;
753 else
754 /* FDI */
755 ret = type == DRM_MODE_CONNECTOR_VGA;
756 break;
757
758 default:
759 ret = false;
760 break;
761 }
762
763out:
764 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
765
766 return ret;
767}
768
769static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
770 u8 *pipe_mask, bool *is_dp_mst)
771{
772 struct drm_device *dev = encoder->base.dev;
773 struct drm_i915_private *dev_priv = to_i915(dev);
774 enum port port = encoder->port;
775 intel_wakeref_t wakeref;
776 enum pipe p;
777 u32 tmp;
778 u8 mst_pipe_mask;
779
780 *pipe_mask = 0;
781 *is_dp_mst = false;
782
783 wakeref = intel_display_power_get_if_enabled(dev_priv,
784 encoder->power_domain);
785 if (!wakeref)
786 return;
787
788 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
789 if (!(tmp & DDI_BUF_CTL_ENABLE))
790 goto out;
791
792 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
793 tmp = intel_de_read(dev_priv,
794 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP));
795
796 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
797 default:
798 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
799 fallthrough;
800 case TRANS_DDI_EDP_INPUT_A_ON:
801 case TRANS_DDI_EDP_INPUT_A_ONOFF:
802 *pipe_mask = BIT(PIPE_A);
803 break;
804 case TRANS_DDI_EDP_INPUT_B_ONOFF:
805 *pipe_mask = BIT(PIPE_B);
806 break;
807 case TRANS_DDI_EDP_INPUT_C_ONOFF:
808 *pipe_mask = BIT(PIPE_C);
809 break;
810 }
811
812 goto out;
813 }
814
815 mst_pipe_mask = 0;
816 for_each_pipe(dev_priv, p) {
817 enum transcoder cpu_transcoder = (enum transcoder)p;
818 unsigned int port_mask, ddi_select;
819 intel_wakeref_t trans_wakeref;
820
821 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
822 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
823 if (!trans_wakeref)
824 continue;
825
826 if (DISPLAY_VER(dev_priv) >= 12) {
827 port_mask = TGL_TRANS_DDI_PORT_MASK;
828 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
829 } else {
830 port_mask = TRANS_DDI_PORT_MASK;
831 ddi_select = TRANS_DDI_SELECT_PORT(port);
832 }
833
834 tmp = intel_de_read(dev_priv,
835 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
836 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
837 trans_wakeref);
838
839 if ((tmp & port_mask) != ddi_select)
840 continue;
841
842 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
843 (HAS_DP20(dev_priv) &&
844 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
845 mst_pipe_mask |= BIT(p);
846
847 *pipe_mask |= BIT(p);
848 }
849
850 if (!*pipe_mask)
851 drm_dbg_kms(&dev_priv->drm,
852 "No pipe for [ENCODER:%d:%s] found\n",
853 encoder->base.base.id, encoder->base.name);
854
855 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
856 drm_dbg_kms(&dev_priv->drm,
857 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
858 encoder->base.base.id, encoder->base.name,
859 *pipe_mask);
860 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
861 }
862
863 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
864 drm_dbg_kms(&dev_priv->drm,
865 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
866 encoder->base.base.id, encoder->base.name,
867 *pipe_mask, mst_pipe_mask);
868 else
869 *is_dp_mst = mst_pipe_mask;
870
871out:
872 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
873 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
874 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
875 BXT_PHY_LANE_POWERDOWN_ACK |
876 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
877 drm_err(&dev_priv->drm,
878 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
879 encoder->base.base.id, encoder->base.name, tmp);
880 }
881
882 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
883}
884
885bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
886 enum pipe *pipe)
887{
888 u8 pipe_mask;
889 bool is_mst;
890
891 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
892
893 if (is_mst || !pipe_mask)
894 return false;
895
896 *pipe = ffs(pipe_mask) - 1;
897
898 return true;
899}
900
901static enum intel_display_power_domain
902intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
903 const struct intel_crtc_state *crtc_state)
904{
905 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
906
907 /*
908 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
909 * DC states enabled at the same time, while for driver initiated AUX
910 * transfers we need the same AUX IOs to be powered but with DC states
911 * disabled. Accordingly use the AUX_IO_<port> power domain here which
912 * leaves DC states enabled.
913 *
914 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
915 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
916 * well, so we can acquire a wider AUX_<port> power domain reference
917 * instead of a specific AUX_IO_<port> reference without powering up any
918 * extra wells.
919 */
920 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))
921 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
922 else if (DISPLAY_VER(i915) < 14 &&
923 (intel_crtc_has_dp_encoder(crtc_state) ||
924 intel_encoder_is_tc(&dig_port->base)))
925 return intel_aux_power_domain(dig_port);
926 else
927 return POWER_DOMAIN_INVALID;
928}
929
930static void
931main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
932 const struct intel_crtc_state *crtc_state)
933{
934 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
935 enum intel_display_power_domain domain =
936 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
937
938 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
939
940 if (domain == POWER_DOMAIN_INVALID)
941 return;
942
943 dig_port->aux_wakeref = intel_display_power_get(i915, domain);
944}
945
946static void
947main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
948 const struct intel_crtc_state *crtc_state)
949{
950 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
951 enum intel_display_power_domain domain =
952 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
953 intel_wakeref_t wf;
954
955 wf = fetch_and_zero(&dig_port->aux_wakeref);
956 if (!wf)
957 return;
958
959 intel_display_power_put(i915, domain, wf);
960}
961
962static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
963 struct intel_crtc_state *crtc_state)
964{
965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
966 struct intel_digital_port *dig_port;
967
968 /*
969 * TODO: Add support for MST encoders. Atm, the following should never
970 * happen since fake-MST encoders don't set their get_power_domains()
971 * hook.
972 */
973 if (drm_WARN_ON(&dev_priv->drm,
974 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
975 return;
976
977 dig_port = enc_to_dig_port(encoder);
978
979 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
980 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
981 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
982 dig_port->ddi_io_power_domain);
983 }
984
985 main_link_aux_power_domain_get(dig_port, crtc_state);
986}
987
988void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
989 const struct intel_crtc_state *crtc_state)
990{
991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
993 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
994 enum phy phy = intel_encoder_to_phy(encoder);
995 u32 val;
996
997 if (cpu_transcoder == TRANSCODER_EDP)
998 return;
999
1000 if (DISPLAY_VER(dev_priv) >= 13)
1001 val = TGL_TRANS_CLK_SEL_PORT(phy);
1002 else if (DISPLAY_VER(dev_priv) >= 12)
1003 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
1004 else
1005 val = TRANS_CLK_SEL_PORT(encoder->port);
1006
1007 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
1008}
1009
1010void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
1011{
1012 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1013 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1014 u32 val;
1015
1016 if (cpu_transcoder == TRANSCODER_EDP)
1017 return;
1018
1019 if (DISPLAY_VER(dev_priv) >= 12)
1020 val = TGL_TRANS_CLK_SEL_DISABLED;
1021 else
1022 val = TRANS_CLK_SEL_DISABLED;
1023
1024 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
1025}
1026
1027static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1028 enum port port, u8 iboost)
1029{
1030 u32 tmp;
1031
1032 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
1033 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1034 if (iboost)
1035 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1036 else
1037 tmp |= BALANCE_LEG_DISABLE(port);
1038 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
1039}
1040
1041static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1042 const struct intel_crtc_state *crtc_state,
1043 int level)
1044{
1045 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1047 u8 iboost;
1048
1049 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1050 iboost = intel_bios_hdmi_boost_level(encoder->devdata);
1051 else
1052 iboost = intel_bios_dp_boost_level(encoder->devdata);
1053
1054 if (iboost == 0) {
1055 const struct intel_ddi_buf_trans *trans;
1056 int n_entries;
1057
1058 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1059 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1060 return;
1061
1062 iboost = trans->entries[level].hsw.i_boost;
1063 }
1064
1065 /* Make sure that the requested I_boost is valid */
1066 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1067 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
1068 return;
1069 }
1070
1071 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
1072
1073 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1074 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1075}
1076
1077static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1078 const struct intel_crtc_state *crtc_state)
1079{
1080 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1082 int n_entries;
1083
1084 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1085
1086 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1087 n_entries = 1;
1088 if (drm_WARN_ON(&dev_priv->drm,
1089 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1090 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1091
1092 return index_to_dp_signal_levels[n_entries - 1] &
1093 DP_TRAIN_VOLTAGE_SWING_MASK;
1094}
1095
1096/*
1097 * We assume that the full set of pre-emphasis values can be
1098 * used on all DDI platforms. Should that change we need to
1099 * rethink this code.
1100 */
1101static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1102{
1103 return DP_TRAIN_PRE_EMPH_LEVEL_3;
1104}
1105
1106static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1107 int lane)
1108{
1109 if (crtc_state->port_clock > 600000)
1110 return 0;
1111
1112 if (crtc_state->lane_count == 4)
1113 return lane >= 1 ? LOADGEN_SELECT : 0;
1114 else
1115 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1116}
1117
1118static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1119 const struct intel_crtc_state *crtc_state)
1120{
1121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1122 const struct intel_ddi_buf_trans *trans;
1123 enum phy phy = intel_encoder_to_phy(encoder);
1124 int n_entries, ln;
1125 u32 val;
1126
1127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1129 return;
1130
1131 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1132 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1133
1134 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1135 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1136 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1137 intel_dp->hobl_active ? val : 0);
1138 }
1139
1140 /* Set PORT_TX_DW5 */
1141 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1142 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1143 TAP2_DISABLE | TAP3_DISABLE);
1144 val |= SCALING_MODE_SEL(0x2);
1145 val |= RTERM_SELECT(0x6);
1146 val |= TAP3_DISABLE;
1147 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1148
1149 /* Program PORT_TX_DW2 */
1150 for (ln = 0; ln < 4; ln++) {
1151 int level = intel_ddi_level(encoder, crtc_state, ln);
1152
1153 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1154 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1155 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1156 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1157 RCOMP_SCALAR(0x98));
1158 }
1159
1160 /* Program PORT_TX_DW4 */
1161 /* We cannot write to GRP. It would overwrite individual loadgen. */
1162 for (ln = 0; ln < 4; ln++) {
1163 int level = intel_ddi_level(encoder, crtc_state, ln);
1164
1165 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1166 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1167 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1168 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1169 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1170 }
1171
1172 /* Program PORT_TX_DW7 */
1173 for (ln = 0; ln < 4; ln++) {
1174 int level = intel_ddi_level(encoder, crtc_state, ln);
1175
1176 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1177 N_SCALAR_MASK,
1178 N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1179 }
1180}
1181
1182static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1183 const struct intel_crtc_state *crtc_state)
1184{
1185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1186 enum phy phy = intel_encoder_to_phy(encoder);
1187 u32 val;
1188 int ln;
1189
1190 /*
1191 * 1. If port type is eDP or DP,
1192 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1193 * else clear to 0b.
1194 */
1195 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1196 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1197 val &= ~COMMON_KEEPER_EN;
1198 else
1199 val |= COMMON_KEEPER_EN;
1200 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1201
1202 /* 2. Program loadgen select */
1203 /*
1204 * Program PORT_TX_DW4 depending on Bit rate and used lanes
1205 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1206 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1207 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1208 */
1209 for (ln = 0; ln < 4; ln++) {
1210 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1211 LOADGEN_SELECT,
1212 icl_combo_phy_loadgen_select(crtc_state, ln));
1213 }
1214
1215 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1216 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1217 0, SUS_CLOCK_CONFIG);
1218
1219 /* 4. Clear training enable to change swing values */
1220 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1221 val &= ~TX_TRAINING_EN;
1222 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1223
1224 /* 5. Program swing and de-emphasis */
1225 icl_ddi_combo_vswing_program(encoder, crtc_state);
1226
1227 /* 6. Set training enable to trigger update */
1228 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1229 val |= TX_TRAINING_EN;
1230 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1231}
1232
1233static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1234 const struct intel_crtc_state *crtc_state)
1235{
1236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1237 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1238 const struct intel_ddi_buf_trans *trans;
1239 int n_entries, ln;
1240
1241 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1242 return;
1243
1244 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1245 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1246 return;
1247
1248 for (ln = 0; ln < 2; ln++) {
1249 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1250 CRI_USE_FS32, 0);
1251 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1252 CRI_USE_FS32, 0);
1253 }
1254
1255 /* Program MG_TX_SWINGCTRL with values from vswing table */
1256 for (ln = 0; ln < 2; ln++) {
1257 int level;
1258
1259 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1260
1261 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1262 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1263 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1264
1265 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1266
1267 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1268 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1269 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1270 }
1271
1272 /* Program MG_TX_DRVCTRL with values from vswing table */
1273 for (ln = 0; ln < 2; ln++) {
1274 int level;
1275
1276 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1277
1278 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1279 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1280 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1281 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1282 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1283 CRI_TXDEEMPH_OVERRIDE_EN);
1284
1285 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1286
1287 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1288 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1289 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1290 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1291 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1292 CRI_TXDEEMPH_OVERRIDE_EN);
1293
1294 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1295 }
1296
1297 /*
1298 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1299 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1300 * values from table for which TX1 and TX2 enabled.
1301 */
1302 for (ln = 0; ln < 2; ln++) {
1303 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1304 CFG_LOW_RATE_LKREN_EN,
1305 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1306 }
1307
1308 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1309 for (ln = 0; ln < 2; ln++) {
1310 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1311 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1312 CFG_AMI_CK_DIV_OVERRIDE_EN,
1313 crtc_state->port_clock > 500000 ?
1314 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1315 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1316
1317 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1318 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1319 CFG_AMI_CK_DIV_OVERRIDE_EN,
1320 crtc_state->port_clock > 500000 ?
1321 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1322 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1323 }
1324
1325 /* Program MG_TX_PISO_READLOAD with values from vswing table */
1326 for (ln = 0; ln < 2; ln++) {
1327 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1328 0, CRI_CALCINIT);
1329 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1330 0, CRI_CALCINIT);
1331 }
1332}
1333
1334static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1335 const struct intel_crtc_state *crtc_state)
1336{
1337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1338 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1339 const struct intel_ddi_buf_trans *trans;
1340 int n_entries, ln;
1341
1342 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1343 return;
1344
1345 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1346 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1347 return;
1348
1349 for (ln = 0; ln < 2; ln++) {
1350 int level;
1351
1352 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1353
1354 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1355
1356 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1357 DKL_TX_PRESHOOT_COEFF_MASK |
1358 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1359 DKL_TX_VSWING_CONTROL_MASK,
1360 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1361 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1362 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1363
1364 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1365
1366 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1367 DKL_TX_PRESHOOT_COEFF_MASK |
1368 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1369 DKL_TX_VSWING_CONTROL_MASK,
1370 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1371 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1372 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1373
1374 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1375 DKL_TX_DP20BITMODE, 0);
1376
1377 if (IS_ALDERLAKE_P(dev_priv)) {
1378 u32 val;
1379
1380 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1381 if (ln == 0) {
1382 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1383 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1384 } else {
1385 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1386 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1387 }
1388 } else {
1389 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1390 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1391 }
1392
1393 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1394 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1395 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1396 val);
1397 }
1398 }
1399}
1400
1401static int translate_signal_level(struct intel_dp *intel_dp,
1402 u8 signal_levels)
1403{
1404 struct intel_display *display = to_intel_display(intel_dp);
1405 int i;
1406
1407 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1408 if (index_to_dp_signal_levels[i] == signal_levels)
1409 return i;
1410 }
1411
1412 drm_WARN(display->drm, 1,
1413 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1414 signal_levels);
1415
1416 return 0;
1417}
1418
1419static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1420 const struct intel_crtc_state *crtc_state,
1421 int lane)
1422{
1423 u8 train_set = intel_dp->train_set[lane];
1424
1425 if (intel_dp_is_uhbr(crtc_state)) {
1426 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1427 } else {
1428 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1429 DP_TRAIN_PRE_EMPHASIS_MASK);
1430
1431 return translate_signal_level(intel_dp, signal_levels);
1432 }
1433}
1434
1435int intel_ddi_level(struct intel_encoder *encoder,
1436 const struct intel_crtc_state *crtc_state,
1437 int lane)
1438{
1439 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1440 const struct intel_ddi_buf_trans *trans;
1441 int level, n_entries;
1442
1443 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1444 if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1445 return 0;
1446
1447 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1448 level = intel_ddi_hdmi_level(encoder, trans);
1449 else
1450 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1451 lane);
1452
1453 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1454 level = n_entries - 1;
1455
1456 return level;
1457}
1458
1459static void
1460hsw_set_signal_levels(struct intel_encoder *encoder,
1461 const struct intel_crtc_state *crtc_state)
1462{
1463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1464 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1465 int level = intel_ddi_level(encoder, crtc_state, 0);
1466 enum port port = encoder->port;
1467 u32 signal_levels;
1468
1469 if (has_iboost(dev_priv))
1470 skl_ddi_set_iboost(encoder, crtc_state, level);
1471
1472 /* HDMI ignores the rest */
1473 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1474 return;
1475
1476 signal_levels = DDI_BUF_TRANS_SELECT(level);
1477
1478 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1479 signal_levels);
1480
1481 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1482 intel_dp->DP |= signal_levels;
1483
1484 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1485 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1486}
1487
1488static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1489 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1490{
1491 mutex_lock(&i915->display.dpll.lock);
1492
1493 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1494
1495 /*
1496 * "This step and the step before must be
1497 * done with separate register writes."
1498 */
1499 intel_de_rmw(i915, reg, clk_off, 0);
1500
1501 mutex_unlock(&i915->display.dpll.lock);
1502}
1503
1504static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1505 u32 clk_off)
1506{
1507 mutex_lock(&i915->display.dpll.lock);
1508
1509 intel_de_rmw(i915, reg, 0, clk_off);
1510
1511 mutex_unlock(&i915->display.dpll.lock);
1512}
1513
1514static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1515 u32 clk_off)
1516{
1517 return !(intel_de_read(i915, reg) & clk_off);
1518}
1519
1520static struct intel_shared_dpll *
1521_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1522 u32 clk_sel_mask, u32 clk_sel_shift)
1523{
1524 enum intel_dpll_id id;
1525
1526 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1527
1528 return intel_get_shared_dpll_by_id(i915, id);
1529}
1530
1531static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1532 const struct intel_crtc_state *crtc_state)
1533{
1534 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1535 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1536 enum phy phy = intel_encoder_to_phy(encoder);
1537
1538 if (drm_WARN_ON(&i915->drm, !pll))
1539 return;
1540
1541 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1542 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1543 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1544 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1545}
1546
1547static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1548{
1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1550 enum phy phy = intel_encoder_to_phy(encoder);
1551
1552 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1553 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1554}
1555
1556static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1557{
1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1559 enum phy phy = intel_encoder_to_phy(encoder);
1560
1561 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1562 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1563}
1564
1565static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1566{
1567 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1568 enum phy phy = intel_encoder_to_phy(encoder);
1569
1570 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1571 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1572 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1573}
1574
1575static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1576 const struct intel_crtc_state *crtc_state)
1577{
1578 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1579 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1580 enum phy phy = intel_encoder_to_phy(encoder);
1581
1582 if (drm_WARN_ON(&i915->drm, !pll))
1583 return;
1584
1585 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1586 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1587 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1588 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1589}
1590
1591static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1592{
1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1594 enum phy phy = intel_encoder_to_phy(encoder);
1595
1596 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1597 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1598}
1599
1600static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1601{
1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1603 enum phy phy = intel_encoder_to_phy(encoder);
1604
1605 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1606 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1607}
1608
1609static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1610{
1611 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1612 enum phy phy = intel_encoder_to_phy(encoder);
1613
1614 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1615 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1616 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1617}
1618
1619static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1620 const struct intel_crtc_state *crtc_state)
1621{
1622 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1623 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1624 enum phy phy = intel_encoder_to_phy(encoder);
1625
1626 if (drm_WARN_ON(&i915->drm, !pll))
1627 return;
1628
1629 /*
1630 * If we fail this, something went very wrong: first 2 PLLs should be
1631 * used by first 2 phys and last 2 PLLs by last phys
1632 */
1633 if (drm_WARN_ON(&i915->drm,
1634 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1635 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1636 return;
1637
1638 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1640 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1641 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1642}
1643
1644static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1645{
1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1647 enum phy phy = intel_encoder_to_phy(encoder);
1648
1649 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1650 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1651}
1652
1653static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1654{
1655 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1656 enum phy phy = intel_encoder_to_phy(encoder);
1657
1658 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1659 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1660}
1661
1662static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1663{
1664 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1665 enum phy phy = intel_encoder_to_phy(encoder);
1666 enum intel_dpll_id id;
1667 u32 val;
1668
1669 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1670 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1671 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1672 id = val;
1673
1674 /*
1675 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1676 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1677 * bit for phy C and D.
1678 */
1679 if (phy >= PHY_C)
1680 id += DPLL_ID_DG1_DPLL2;
1681
1682 return intel_get_shared_dpll_by_id(i915, id);
1683}
1684
1685static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1686 const struct intel_crtc_state *crtc_state)
1687{
1688 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1689 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1690 enum phy phy = intel_encoder_to_phy(encoder);
1691
1692 if (drm_WARN_ON(&i915->drm, !pll))
1693 return;
1694
1695 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1696 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1697 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1698 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1699}
1700
1701static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1702{
1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1704 enum phy phy = intel_encoder_to_phy(encoder);
1705
1706 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1707 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1708}
1709
1710static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1711{
1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1713 enum phy phy = intel_encoder_to_phy(encoder);
1714
1715 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1716 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1717}
1718
1719struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1720{
1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1722 enum phy phy = intel_encoder_to_phy(encoder);
1723
1724 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1725 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1726 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1727}
1728
1729static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1730 const struct intel_crtc_state *crtc_state)
1731{
1732 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1733 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1734 enum port port = encoder->port;
1735
1736 if (drm_WARN_ON(&i915->drm, !pll))
1737 return;
1738
1739 /*
1740 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1741 * MG does not exist, but the programming is required to ungate DDIC and DDID."
1742 */
1743 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1744
1745 icl_ddi_combo_enable_clock(encoder, crtc_state);
1746}
1747
1748static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1749{
1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1751 enum port port = encoder->port;
1752
1753 icl_ddi_combo_disable_clock(encoder);
1754
1755 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1756}
1757
1758static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1759{
1760 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1761 enum port port = encoder->port;
1762 u32 tmp;
1763
1764 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1765
1766 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1767 return false;
1768
1769 return icl_ddi_combo_is_clock_enabled(encoder);
1770}
1771
1772static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1773 const struct intel_crtc_state *crtc_state)
1774{
1775 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1776 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1777 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1778 enum port port = encoder->port;
1779
1780 if (drm_WARN_ON(&i915->drm, !pll))
1781 return;
1782
1783 intel_de_write(i915, DDI_CLK_SEL(port),
1784 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1785
1786 mutex_lock(&i915->display.dpll.lock);
1787
1788 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1789 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1790
1791 mutex_unlock(&i915->display.dpll.lock);
1792}
1793
1794static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1795{
1796 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1797 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1798 enum port port = encoder->port;
1799
1800 mutex_lock(&i915->display.dpll.lock);
1801
1802 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1803 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1804
1805 mutex_unlock(&i915->display.dpll.lock);
1806
1807 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1808}
1809
1810static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1811{
1812 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1813 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1814 enum port port = encoder->port;
1815 u32 tmp;
1816
1817 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1818
1819 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1820 return false;
1821
1822 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1823
1824 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1825}
1826
1827static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1828{
1829 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1830 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1831 enum port port = encoder->port;
1832 enum intel_dpll_id id;
1833 u32 tmp;
1834
1835 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1836
1837 switch (tmp & DDI_CLK_SEL_MASK) {
1838 case DDI_CLK_SEL_TBT_162:
1839 case DDI_CLK_SEL_TBT_270:
1840 case DDI_CLK_SEL_TBT_540:
1841 case DDI_CLK_SEL_TBT_810:
1842 id = DPLL_ID_ICL_TBTPLL;
1843 break;
1844 case DDI_CLK_SEL_MG:
1845 id = icl_tc_port_to_pll_id(tc_port);
1846 break;
1847 default:
1848 MISSING_CASE(tmp);
1849 fallthrough;
1850 case DDI_CLK_SEL_NONE:
1851 return NULL;
1852 }
1853
1854 return intel_get_shared_dpll_by_id(i915, id);
1855}
1856
1857static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1858{
1859 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1860 enum intel_dpll_id id;
1861
1862 switch (encoder->port) {
1863 case PORT_A:
1864 id = DPLL_ID_SKL_DPLL0;
1865 break;
1866 case PORT_B:
1867 id = DPLL_ID_SKL_DPLL1;
1868 break;
1869 case PORT_C:
1870 id = DPLL_ID_SKL_DPLL2;
1871 break;
1872 default:
1873 MISSING_CASE(encoder->port);
1874 return NULL;
1875 }
1876
1877 return intel_get_shared_dpll_by_id(i915, id);
1878}
1879
1880static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1881 const struct intel_crtc_state *crtc_state)
1882{
1883 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1884 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1885 enum port port = encoder->port;
1886
1887 if (drm_WARN_ON(&i915->drm, !pll))
1888 return;
1889
1890 mutex_lock(&i915->display.dpll.lock);
1891
1892 intel_de_rmw(i915, DPLL_CTRL2,
1893 DPLL_CTRL2_DDI_CLK_OFF(port) |
1894 DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1895 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1896 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1897
1898 mutex_unlock(&i915->display.dpll.lock);
1899}
1900
1901static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1902{
1903 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1904 enum port port = encoder->port;
1905
1906 mutex_lock(&i915->display.dpll.lock);
1907
1908 intel_de_rmw(i915, DPLL_CTRL2,
1909 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1910
1911 mutex_unlock(&i915->display.dpll.lock);
1912}
1913
1914static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1915{
1916 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1917 enum port port = encoder->port;
1918
1919 /*
1920 * FIXME Not sure if the override affects both
1921 * the PLL selection and the CLK_OFF bit.
1922 */
1923 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1924}
1925
1926static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1927{
1928 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1929 enum port port = encoder->port;
1930 enum intel_dpll_id id;
1931 u32 tmp;
1932
1933 tmp = intel_de_read(i915, DPLL_CTRL2);
1934
1935 /*
1936 * FIXME Not sure if the override affects both
1937 * the PLL selection and the CLK_OFF bit.
1938 */
1939 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1940 return NULL;
1941
1942 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1943 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1944
1945 return intel_get_shared_dpll_by_id(i915, id);
1946}
1947
1948void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1949 const struct intel_crtc_state *crtc_state)
1950{
1951 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1952 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1953 enum port port = encoder->port;
1954
1955 if (drm_WARN_ON(&i915->drm, !pll))
1956 return;
1957
1958 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1959}
1960
1961void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1962{
1963 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1964 enum port port = encoder->port;
1965
1966 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1967}
1968
1969bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1970{
1971 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1972 enum port port = encoder->port;
1973
1974 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1975}
1976
1977static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1978{
1979 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1980 enum port port = encoder->port;
1981 enum intel_dpll_id id;
1982 u32 tmp;
1983
1984 tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1985
1986 switch (tmp & PORT_CLK_SEL_MASK) {
1987 case PORT_CLK_SEL_WRPLL1:
1988 id = DPLL_ID_WRPLL1;
1989 break;
1990 case PORT_CLK_SEL_WRPLL2:
1991 id = DPLL_ID_WRPLL2;
1992 break;
1993 case PORT_CLK_SEL_SPLL:
1994 id = DPLL_ID_SPLL;
1995 break;
1996 case PORT_CLK_SEL_LCPLL_810:
1997 id = DPLL_ID_LCPLL_810;
1998 break;
1999 case PORT_CLK_SEL_LCPLL_1350:
2000 id = DPLL_ID_LCPLL_1350;
2001 break;
2002 case PORT_CLK_SEL_LCPLL_2700:
2003 id = DPLL_ID_LCPLL_2700;
2004 break;
2005 default:
2006 MISSING_CASE(tmp);
2007 fallthrough;
2008 case PORT_CLK_SEL_NONE:
2009 return NULL;
2010 }
2011
2012 return intel_get_shared_dpll_by_id(i915, id);
2013}
2014
2015void intel_ddi_enable_clock(struct intel_encoder *encoder,
2016 const struct intel_crtc_state *crtc_state)
2017{
2018 if (encoder->enable_clock)
2019 encoder->enable_clock(encoder, crtc_state);
2020}
2021
2022void intel_ddi_disable_clock(struct intel_encoder *encoder)
2023{
2024 if (encoder->disable_clock)
2025 encoder->disable_clock(encoder);
2026}
2027
2028void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2029{
2030 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2031 u32 port_mask;
2032 bool ddi_clk_needed;
2033
2034 /*
2035 * In case of DP MST, we sanitize the primary encoder only, not the
2036 * virtual ones.
2037 */
2038 if (encoder->type == INTEL_OUTPUT_DP_MST)
2039 return;
2040
2041 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2042 u8 pipe_mask;
2043 bool is_mst;
2044
2045 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2046 /*
2047 * In the unlikely case that BIOS enables DP in MST mode, just
2048 * warn since our MST HW readout is incomplete.
2049 */
2050 if (drm_WARN_ON(&i915->drm, is_mst))
2051 return;
2052 }
2053
2054 port_mask = BIT(encoder->port);
2055 ddi_clk_needed = encoder->base.crtc;
2056
2057 if (encoder->type == INTEL_OUTPUT_DSI) {
2058 struct intel_encoder *other_encoder;
2059
2060 port_mask = intel_dsi_encoder_ports(encoder);
2061 /*
2062 * Sanity check that we haven't incorrectly registered another
2063 * encoder using any of the ports of this DSI encoder.
2064 */
2065 for_each_intel_encoder(&i915->drm, other_encoder) {
2066 if (other_encoder == encoder)
2067 continue;
2068
2069 if (drm_WARN_ON(&i915->drm,
2070 port_mask & BIT(other_encoder->port)))
2071 return;
2072 }
2073 /*
2074 * For DSI we keep the ddi clocks gated
2075 * except during enable/disable sequence.
2076 */
2077 ddi_clk_needed = false;
2078 }
2079
2080 if (ddi_clk_needed || !encoder->is_clock_enabled ||
2081 !encoder->is_clock_enabled(encoder))
2082 return;
2083
2084 drm_dbg_kms(&i915->drm,
2085 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2086 encoder->base.base.id, encoder->base.name);
2087
2088 encoder->disable_clock(encoder);
2089}
2090
2091static void
2092icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2093 const struct intel_crtc_state *crtc_state)
2094{
2095 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2096 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
2097 u32 ln0, ln1, pin_assignment;
2098 u8 width;
2099
2100 if (DISPLAY_VER(dev_priv) >= 14)
2101 return;
2102
2103 if (!intel_encoder_is_tc(&dig_port->base) ||
2104 intel_tc_port_in_tbt_alt_mode(dig_port))
2105 return;
2106
2107 if (DISPLAY_VER(dev_priv) >= 12) {
2108 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
2109 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
2110 } else {
2111 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2112 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2113 }
2114
2115 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2116 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2117
2118 /* DPPATC */
2119 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2120 width = crtc_state->lane_count;
2121
2122 switch (pin_assignment) {
2123 case 0x0:
2124 drm_WARN_ON(&dev_priv->drm,
2125 !intel_tc_port_in_legacy_mode(dig_port));
2126 if (width == 1) {
2127 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2128 } else {
2129 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2130 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2131 }
2132 break;
2133 case 0x1:
2134 if (width == 4) {
2135 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2136 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2137 }
2138 break;
2139 case 0x2:
2140 if (width == 2) {
2141 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2142 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2143 }
2144 break;
2145 case 0x3:
2146 case 0x5:
2147 if (width == 1) {
2148 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2149 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2150 } else {
2151 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2152 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2153 }
2154 break;
2155 case 0x4:
2156 case 0x6:
2157 if (width == 1) {
2158 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2159 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2160 } else {
2161 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2162 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2163 }
2164 break;
2165 default:
2166 MISSING_CASE(pin_assignment);
2167 }
2168
2169 if (DISPLAY_VER(dev_priv) >= 12) {
2170 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
2171 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
2172 } else {
2173 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2174 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2175 }
2176}
2177
2178static enum transcoder
2179tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2180{
2181 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2182 return crtc_state->mst_master_transcoder;
2183 else
2184 return crtc_state->cpu_transcoder;
2185}
2186
2187i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2188 const struct intel_crtc_state *crtc_state)
2189{
2190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2191
2192 if (DISPLAY_VER(dev_priv) >= 12)
2193 return TGL_DP_TP_CTL(dev_priv,
2194 tgl_dp_tp_transcoder(crtc_state));
2195 else
2196 return DP_TP_CTL(encoder->port);
2197}
2198
2199i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2200 const struct intel_crtc_state *crtc_state)
2201{
2202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2203
2204 if (DISPLAY_VER(dev_priv) >= 12)
2205 return TGL_DP_TP_STATUS(dev_priv,
2206 tgl_dp_tp_transcoder(crtc_state));
2207 else
2208 return DP_TP_STATUS(encoder->port);
2209}
2210
2211static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2212 const struct intel_crtc_state *crtc_state,
2213 bool enable)
2214{
2215 struct intel_display *display = to_intel_display(intel_dp);
2216
2217 if (!crtc_state->vrr.enable)
2218 return;
2219
2220 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2221 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2222 drm_dbg_kms(display->drm,
2223 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2224 str_enable_disable(enable));
2225}
2226
2227static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2228 const struct intel_crtc_state *crtc_state,
2229 bool enable)
2230{
2231 struct intel_display *display = to_intel_display(intel_dp);
2232
2233 if (!crtc_state->fec_enable)
2234 return;
2235
2236 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
2237 enable ? DP_FEC_READY : 0) <= 0)
2238 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
2239 str_enabled_disabled(enable));
2240
2241 if (enable &&
2242 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
2243 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
2244 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
2245}
2246
2247static int read_fec_detected_status(struct drm_dp_aux *aux)
2248{
2249 int ret;
2250 u8 status;
2251
2252 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status);
2253 if (ret < 0)
2254 return ret;
2255
2256 return status;
2257}
2258
2259static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2260{
2261 struct intel_display *display = to_intel_display(aux->drm_dev);
2262 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2263 int status;
2264 int err;
2265
2266 err = readx_poll_timeout(read_fec_detected_status, aux, status,
2267 status & mask || status < 0,
2268 10000, 200000);
2269
2270 if (err || status < 0) {
2271 drm_dbg_kms(display->drm,
2272 "Failed waiting for FEC %s to get detected: %d (status %d)\n",
2273 str_enabled_disabled(enabled), err, status);
2274 return err ? err : status;
2275 }
2276
2277 return 0;
2278}
2279
2280int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2281 const struct intel_crtc_state *crtc_state,
2282 bool enabled)
2283{
2284 struct intel_display *display = to_intel_display(encoder);
2285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2286 int ret;
2287
2288 if (!crtc_state->fec_enable)
2289 return 0;
2290
2291 if (enabled)
2292 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
2293 DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2294 else
2295 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state),
2296 DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2297
2298 if (ret) {
2299 drm_err(display->drm,
2300 "Timeout waiting for FEC live state to get %s\n",
2301 str_enabled_disabled(enabled));
2302 return ret;
2303 }
2304 /*
2305 * At least the Synoptics MST hub doesn't set the detected flag for
2306 * FEC decoding disabling so skip waiting for that.
2307 */
2308 if (enabled) {
2309 ret = wait_for_fec_detected(&intel_dp->aux, enabled);
2310 if (ret)
2311 return ret;
2312 }
2313
2314 return 0;
2315}
2316
2317static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2318 const struct intel_crtc_state *crtc_state)
2319{
2320 struct intel_display *display = to_intel_display(encoder);
2321 int i;
2322 int ret;
2323
2324 if (!crtc_state->fec_enable)
2325 return;
2326
2327 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2328 0, DP_TP_CTL_FEC_ENABLE);
2329
2330 if (DISPLAY_VER(display) < 30)
2331 return;
2332
2333 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2334 if (!ret)
2335 return;
2336
2337 for (i = 0; i < 3; i++) {
2338 drm_dbg_kms(display->drm, "Retry FEC enabling\n");
2339
2340 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2341 DP_TP_CTL_FEC_ENABLE, 0);
2342
2343 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
2344 if (ret)
2345 continue;
2346
2347 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2348 0, DP_TP_CTL_FEC_ENABLE);
2349
2350 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2351 if (!ret)
2352 return;
2353 }
2354
2355 drm_err(display->drm, "Failed to enable FEC after retries\n");
2356}
2357
2358static void intel_ddi_disable_fec(struct intel_encoder *encoder,
2359 const struct intel_crtc_state *crtc_state)
2360{
2361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2362
2363 if (!crtc_state->fec_enable)
2364 return;
2365
2366 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2367 DP_TP_CTL_FEC_ENABLE, 0);
2368 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2369}
2370
2371static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2372 const struct intel_crtc_state *crtc_state)
2373{
2374 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2375 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2376
2377 if (intel_encoder_is_combo(encoder)) {
2378 enum phy phy = intel_encoder_to_phy(encoder);
2379 bool lane_reversal =
2380 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2381
2382 intel_combo_phy_power_up_lanes(i915, phy, false,
2383 crtc_state->lane_count,
2384 lane_reversal);
2385 }
2386}
2387
2388/*
2389 * Splitter enable for eDP MSO is limited to certain pipes, on certain
2390 * platforms.
2391 */
2392static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2393{
2394 if (DISPLAY_VER(i915) > 20)
2395 return ~0;
2396 else if (IS_ALDERLAKE_P(i915))
2397 return BIT(PIPE_A) | BIT(PIPE_B);
2398 else
2399 return BIT(PIPE_A);
2400}
2401
2402static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2403 struct intel_crtc_state *pipe_config)
2404{
2405 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2406 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2407 enum pipe pipe = crtc->pipe;
2408 u32 dss1;
2409
2410 if (!HAS_MSO(i915))
2411 return;
2412
2413 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2414
2415 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2416 if (!pipe_config->splitter.enable)
2417 return;
2418
2419 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2420 pipe_config->splitter.enable = false;
2421 return;
2422 }
2423
2424 switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2425 default:
2426 drm_WARN(&i915->drm, true,
2427 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2428 fallthrough;
2429 case SPLITTER_CONFIGURATION_2_SEGMENT:
2430 pipe_config->splitter.link_count = 2;
2431 break;
2432 case SPLITTER_CONFIGURATION_4_SEGMENT:
2433 pipe_config->splitter.link_count = 4;
2434 break;
2435 }
2436
2437 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2438}
2439
2440static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2441{
2442 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2443 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2444 enum pipe pipe = crtc->pipe;
2445 u32 dss1 = 0;
2446
2447 if (!HAS_MSO(i915))
2448 return;
2449
2450 if (crtc_state->splitter.enable) {
2451 dss1 |= SPLITTER_ENABLE;
2452 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2453 if (crtc_state->splitter.link_count == 2)
2454 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2455 else
2456 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2457 }
2458
2459 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2460 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2461 OVERLAP_PIXELS_MASK, dss1);
2462}
2463
2464static u8 mtl_get_port_width(u8 lane_count)
2465{
2466 switch (lane_count) {
2467 case 1:
2468 return 0;
2469 case 2:
2470 return 1;
2471 case 3:
2472 return 4;
2473 case 4:
2474 return 3;
2475 default:
2476 MISSING_CASE(lane_count);
2477 return 4;
2478 }
2479}
2480
2481static void
2482mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2483{
2484 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2485 enum port port = encoder->port;
2486 i915_reg_t reg;
2487 u32 set_bits, wait_bits;
2488
2489 if (DISPLAY_VER(dev_priv) >= 20) {
2490 reg = DDI_BUF_CTL(port);
2491 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
2492 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
2493 } else {
2494 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
2495 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
2496 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
2497 }
2498
2499 intel_de_rmw(dev_priv, reg, 0, set_bits);
2500 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
2501 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
2502 port_name(port));
2503 }
2504}
2505
2506static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2507 const struct intel_crtc_state *crtc_state)
2508{
2509 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2510 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2511 enum port port = encoder->port;
2512 u32 val;
2513
2514 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
2515 val &= ~XELPDP_PORT_WIDTH_MASK;
2516 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
2517
2518 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
2519 if (intel_dp_is_uhbr(crtc_state))
2520 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2521 else
2522 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2523
2524 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
2525 val |= XELPDP_PORT_REVERSAL;
2526
2527 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
2528}
2529
2530static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2531{
2532 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2533 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2534 u32 val;
2535
2536 val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2537 XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2538 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
2539 XELPDP_PORT_BUF_IO_SELECT_TBT, val);
2540}
2541
2542static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2543 struct intel_encoder *encoder,
2544 const struct intel_crtc_state *crtc_state,
2545 const struct drm_connector_state *conn_state)
2546{
2547 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2548 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2549
2550 intel_dp_set_link_params(intel_dp,
2551 crtc_state->port_clock,
2552 crtc_state->lane_count);
2553
2554 /*
2555 * We only configure what the register value will be here. Actual
2556 * enabling happens during link training farther down.
2557 */
2558 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2559
2560 /*
2561 * 1. Enable Power Wells
2562 *
2563 * This was handled at the beginning of intel_atomic_commit_tail(),
2564 * before we called down into this function.
2565 */
2566
2567 /* 2. PMdemand was already set */
2568
2569 /* 3. Select Thunderbolt */
2570 mtl_port_buf_ctl_io_selection(encoder);
2571
2572 /* 4. Enable Panel Power if PPS is required */
2573 intel_pps_on(intel_dp);
2574
2575 /* 5. Enable the port PLL */
2576 intel_ddi_enable_clock(encoder, crtc_state);
2577
2578 /*
2579 * 6.a Configure Transcoder Clock Select to direct the Port clock to the
2580 * Transcoder.
2581 */
2582 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2583
2584 /*
2585 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2586 */
2587 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2588
2589 /*
2590 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2591 * Transport Select
2592 */
2593 intel_ddi_config_transcoder_func(encoder, crtc_state);
2594
2595 /*
2596 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2597 */
2598 intel_ddi_mso_configure(crtc_state);
2599
2600 if (!is_mst)
2601 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2602
2603 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2604 if (!is_mst)
2605 intel_dp_sink_enable_decompression(state,
2606 to_intel_connector(conn_state->connector),
2607 crtc_state);
2608
2609 /*
2610 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2611 * in the FEC_CONFIGURATION register to 1 before initiating link
2612 * training
2613 */
2614 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2615
2616 intel_dp_check_frl_training(intel_dp);
2617 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2618
2619 /*
2620 * 6. The rest of the below are substeps under the bspec's "Enable and
2621 * Train Display Port" step. Note that steps that are specific to
2622 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2623 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2624 * us when active_mst_links==0, so any steps designated for "single
2625 * stream or multi-stream master transcoder" can just be performed
2626 * unconditionally here.
2627 *
2628 * mtl_ddi_prepare_link_retrain() that is called by
2629 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2630 * 6.i and 6.j
2631 *
2632 * 6.k Follow DisplayPort specification training sequence (see notes for
2633 * failure handling)
2634 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2635 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2636 * (timeout after 800 us)
2637 */
2638 intel_dp_start_link_train(state, intel_dp, crtc_state);
2639
2640 /* 6.n Set DP_TP_CTL link training to Normal */
2641 if (!is_trans_port_sync_mode(crtc_state))
2642 intel_dp_stop_link_train(intel_dp, crtc_state);
2643
2644 /* 6.o Configure and enable FEC if needed */
2645 intel_ddi_enable_fec(encoder, crtc_state);
2646
2647 if (!is_mst)
2648 intel_dsc_dp_pps_write(encoder, crtc_state);
2649}
2650
2651static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2652 struct intel_encoder *encoder,
2653 const struct intel_crtc_state *crtc_state,
2654 const struct drm_connector_state *conn_state)
2655{
2656 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2658 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2659 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2660
2661 intel_dp_set_link_params(intel_dp,
2662 crtc_state->port_clock,
2663 crtc_state->lane_count);
2664
2665 /*
2666 * We only configure what the register value will be here. Actual
2667 * enabling happens during link training farther down.
2668 */
2669 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2670
2671 /*
2672 * 1. Enable Power Wells
2673 *
2674 * This was handled at the beginning of intel_atomic_commit_tail(),
2675 * before we called down into this function.
2676 */
2677
2678 /* 2. Enable Panel Power if PPS is required */
2679 intel_pps_on(intel_dp);
2680
2681 /*
2682 * 3. For non-TBT Type-C ports, set FIA lane count
2683 * (DFLEXDPSP.DPX4TXLATC)
2684 *
2685 * This was done before tgl_ddi_pre_enable_dp by
2686 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2687 */
2688
2689 /*
2690 * 4. Enable the port PLL.
2691 *
2692 * The PLL enabling itself was already done before this function by
2693 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
2694 * configure the PLL to port mapping here.
2695 */
2696 intel_ddi_enable_clock(encoder, crtc_state);
2697
2698 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2699 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2700 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2701 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2702 dig_port->ddi_io_power_domain);
2703 }
2704
2705 /* 6. Program DP_MODE */
2706 icl_program_mg_dp_mode(dig_port, crtc_state);
2707
2708 /*
2709 * 7. The rest of the below are substeps under the bspec's "Enable and
2710 * Train Display Port" step. Note that steps that are specific to
2711 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2712 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2713 * us when active_mst_links==0, so any steps designated for "single
2714 * stream or multi-stream master transcoder" can just be performed
2715 * unconditionally here.
2716 */
2717
2718 /*
2719 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2720 * Transcoder.
2721 */
2722 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2723
2724 if (HAS_DP20(dev_priv))
2725 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2726
2727 /*
2728 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2729 * Transport Select
2730 */
2731 intel_ddi_config_transcoder_func(encoder, crtc_state);
2732
2733 /*
2734 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2735 * selected
2736 *
2737 * This will be handled by the intel_dp_start_link_train() farther
2738 * down this function.
2739 */
2740
2741 /* 7.e Configure voltage swing and related IO settings */
2742 encoder->set_signal_levels(encoder, crtc_state);
2743
2744 /*
2745 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2746 * the used lanes of the DDI.
2747 */
2748 intel_ddi_power_up_lanes(encoder, crtc_state);
2749
2750 /*
2751 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2752 */
2753 intel_ddi_mso_configure(crtc_state);
2754
2755 if (!is_mst)
2756 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2757
2758 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2759 if (!is_mst)
2760 intel_dp_sink_enable_decompression(state,
2761 to_intel_connector(conn_state->connector),
2762 crtc_state);
2763 /*
2764 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2765 * in the FEC_CONFIGURATION register to 1 before initiating link
2766 * training
2767 */
2768 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2769
2770 intel_dp_check_frl_training(intel_dp);
2771 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2772
2773 /*
2774 * 7.i Follow DisplayPort specification training sequence (see notes for
2775 * failure handling)
2776 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2777 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2778 * (timeout after 800 us)
2779 */
2780 intel_dp_start_link_train(state, intel_dp, crtc_state);
2781
2782 /* 7.k Set DP_TP_CTL link training to Normal */
2783 if (!is_trans_port_sync_mode(crtc_state))
2784 intel_dp_stop_link_train(intel_dp, crtc_state);
2785
2786 /* 7.l Configure and enable FEC if needed */
2787 intel_ddi_enable_fec(encoder, crtc_state);
2788
2789 if (!is_mst)
2790 intel_dsc_dp_pps_write(encoder, crtc_state);
2791}
2792
2793static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2794 struct intel_encoder *encoder,
2795 const struct intel_crtc_state *crtc_state,
2796 const struct drm_connector_state *conn_state)
2797{
2798 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2799 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2800 enum port port = encoder->port;
2801 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2802 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2803
2804 if (DISPLAY_VER(dev_priv) < 11)
2805 drm_WARN_ON(&dev_priv->drm,
2806 is_mst && (port == PORT_A || port == PORT_E));
2807 else
2808 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2809
2810 intel_dp_set_link_params(intel_dp,
2811 crtc_state->port_clock,
2812 crtc_state->lane_count);
2813
2814 /*
2815 * We only configure what the register value will be here. Actual
2816 * enabling happens during link training farther down.
2817 */
2818 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2819
2820 intel_pps_on(intel_dp);
2821
2822 intel_ddi_enable_clock(encoder, crtc_state);
2823
2824 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2825 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2826 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2827 dig_port->ddi_io_power_domain);
2828 }
2829
2830 icl_program_mg_dp_mode(dig_port, crtc_state);
2831
2832 if (has_buf_trans_select(dev_priv))
2833 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2834
2835 encoder->set_signal_levels(encoder, crtc_state);
2836
2837 intel_ddi_power_up_lanes(encoder, crtc_state);
2838
2839 if (!is_mst)
2840 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2841 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2842 if (!is_mst)
2843 intel_dp_sink_enable_decompression(state,
2844 to_intel_connector(conn_state->connector),
2845 crtc_state);
2846 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2847 intel_dp_start_link_train(state, intel_dp, crtc_state);
2848 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2849 !is_trans_port_sync_mode(crtc_state))
2850 intel_dp_stop_link_train(intel_dp, crtc_state);
2851
2852 intel_ddi_enable_fec(encoder, crtc_state);
2853
2854 if (!is_mst) {
2855 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2856 intel_dsc_dp_pps_write(encoder, crtc_state);
2857 }
2858}
2859
2860static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2861 struct intel_encoder *encoder,
2862 const struct intel_crtc_state *crtc_state,
2863 const struct drm_connector_state *conn_state)
2864{
2865 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2866
2867 if (HAS_DP20(dev_priv))
2868 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
2869 crtc_state);
2870
2871 /* Panel replay has to be enabled in sink dpcd before link training. */
2872 if (crtc_state->has_panel_replay)
2873 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);
2874
2875 if (DISPLAY_VER(dev_priv) >= 14)
2876 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2877 else if (DISPLAY_VER(dev_priv) >= 12)
2878 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2879 else
2880 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2881
2882 /* MST will call a setting of MSA after an allocating of Virtual Channel
2883 * from MST encoder pre_enable callback.
2884 */
2885 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2886 intel_ddi_set_dp_msa(crtc_state, conn_state);
2887}
2888
2889static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2890 struct intel_encoder *encoder,
2891 const struct intel_crtc_state *crtc_state,
2892 const struct drm_connector_state *conn_state)
2893{
2894 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2895 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2896 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2897
2898 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2899 intel_ddi_enable_clock(encoder, crtc_state);
2900
2901 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2902 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2903 dig_port->ddi_io_power_domain);
2904
2905 icl_program_mg_dp_mode(dig_port, crtc_state);
2906
2907 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2908
2909 dig_port->set_infoframes(encoder,
2910 crtc_state->has_infoframe,
2911 crtc_state, conn_state);
2912}
2913
2914static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2915 struct intel_encoder *encoder,
2916 const struct intel_crtc_state *crtc_state,
2917 const struct drm_connector_state *conn_state)
2918{
2919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2921 enum pipe pipe = crtc->pipe;
2922
2923 /*
2924 * When called from DP MST code:
2925 * - conn_state will be NULL
2926 * - encoder will be the main encoder (ie. mst->primary)
2927 * - the main connector associated with this port
2928 * won't be active or linked to a crtc
2929 * - crtc_state will be the state of the first stream to
2930 * be activated on this port, and it may not be the same
2931 * stream that will be deactivated last, but each stream
2932 * should have a state that is identical when it comes to
2933 * the DP link parameteres
2934 */
2935
2936 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2937
2938 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2939
2940 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2941 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2942 conn_state);
2943 } else {
2944 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2945
2946 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2947 conn_state);
2948
2949 /* FIXME precompute everything properly */
2950 /* FIXME how do we turn infoframes off again? */
2951 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
2952 dig_port->set_infoframes(encoder,
2953 crtc_state->has_infoframe,
2954 crtc_state, conn_state);
2955 }
2956}
2957
2958static void
2959mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
2960{
2961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2962 enum port port = encoder->port;
2963 i915_reg_t reg;
2964 u32 clr_bits, wait_bits;
2965
2966 if (DISPLAY_VER(dev_priv) >= 20) {
2967 reg = DDI_BUF_CTL(port);
2968 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
2969 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
2970 } else {
2971 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
2972 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
2973 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
2974 }
2975
2976 intel_de_rmw(dev_priv, reg, clr_bits, 0);
2977 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
2978 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
2979 port_name(port));
2980}
2981
2982static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
2983 const struct intel_crtc_state *crtc_state)
2984{
2985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2986 enum port port = encoder->port;
2987 u32 val;
2988
2989 /* 3.b Clear DDI_CTL_DE Enable to 0. */
2990 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2991 if (val & DDI_BUF_CTL_ENABLE) {
2992 val &= ~DDI_BUF_CTL_ENABLE;
2993 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2994
2995 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */
2996 mtl_wait_ddi_buf_idle(dev_priv, port);
2997 }
2998
2999 /* 3.d Disable D2D Link */
3000 mtl_ddi_disable_d2d_link(encoder);
3001
3002 /* 3.e Disable DP_TP_CTL */
3003 if (intel_crtc_has_dp_encoder(crtc_state)) {
3004 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3005 DP_TP_CTL_ENABLE, 0);
3006 }
3007}
3008
3009static void disable_ddi_buf(struct intel_encoder *encoder,
3010 const struct intel_crtc_state *crtc_state)
3011{
3012 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3013 enum port port = encoder->port;
3014 bool wait = false;
3015 u32 val;
3016
3017 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3018 if (val & DDI_BUF_CTL_ENABLE) {
3019 val &= ~DDI_BUF_CTL_ENABLE;
3020 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3021 wait = true;
3022 }
3023
3024 if (intel_crtc_has_dp_encoder(crtc_state))
3025 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3026 DP_TP_CTL_ENABLE, 0);
3027
3028 intel_ddi_disable_fec(encoder, crtc_state);
3029
3030 if (wait)
3031 intel_wait_ddi_buf_idle(dev_priv, port);
3032}
3033
3034static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3035 const struct intel_crtc_state *crtc_state)
3036{
3037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3038
3039 if (DISPLAY_VER(dev_priv) >= 14) {
3040 mtl_disable_ddi_buf(encoder, crtc_state);
3041
3042 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */
3043 intel_ddi_disable_fec(encoder, crtc_state);
3044 } else {
3045 disable_ddi_buf(encoder, crtc_state);
3046 }
3047
3048 intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
3049}
3050
3051static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3052 struct intel_encoder *encoder,
3053 const struct intel_crtc_state *old_crtc_state,
3054 const struct drm_connector_state *old_conn_state)
3055{
3056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3057 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3058 struct intel_dp *intel_dp = &dig_port->dp;
3059 intel_wakeref_t wakeref;
3060 bool is_mst = intel_crtc_has_type(old_crtc_state,
3061 INTEL_OUTPUT_DP_MST);
3062
3063 if (!is_mst)
3064 intel_dp_set_infoframes(encoder, false,
3065 old_crtc_state, old_conn_state);
3066
3067 /*
3068 * Power down sink before disabling the port, otherwise we end
3069 * up getting interrupts from the sink on detecting link loss.
3070 */
3071 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3072
3073 if (DISPLAY_VER(dev_priv) >= 12) {
3074 if (is_mst) {
3075 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3076
3077 intel_de_rmw(dev_priv,
3078 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
3079 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
3080 0);
3081 }
3082 } else {
3083 if (!is_mst)
3084 intel_ddi_disable_transcoder_clock(old_crtc_state);
3085 }
3086
3087 intel_disable_ddi_buf(encoder, old_crtc_state);
3088
3089 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
3090
3091 /*
3092 * From TGL spec: "If single stream or multi-stream master transcoder:
3093 * Configure Transcoder Clock select to direct no clock to the
3094 * transcoder"
3095 */
3096 if (DISPLAY_VER(dev_priv) >= 12)
3097 intel_ddi_disable_transcoder_clock(old_crtc_state);
3098
3099 intel_pps_vdd_on(intel_dp);
3100 intel_pps_off(intel_dp);
3101
3102 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3103
3104 if (wakeref)
3105 intel_display_power_put(dev_priv,
3106 dig_port->ddi_io_power_domain,
3107 wakeref);
3108
3109 intel_ddi_disable_clock(encoder);
3110
3111 /* De-select Thunderbolt */
3112 if (DISPLAY_VER(dev_priv) >= 14)
3113 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),
3114 XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
3115}
3116
3117static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3118 struct intel_encoder *encoder,
3119 const struct intel_crtc_state *old_crtc_state,
3120 const struct drm_connector_state *old_conn_state)
3121{
3122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3123 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3124 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3125 intel_wakeref_t wakeref;
3126
3127 dig_port->set_infoframes(encoder, false,
3128 old_crtc_state, old_conn_state);
3129
3130 if (DISPLAY_VER(dev_priv) < 12)
3131 intel_ddi_disable_transcoder_clock(old_crtc_state);
3132
3133 intel_disable_ddi_buf(encoder, old_crtc_state);
3134
3135 if (DISPLAY_VER(dev_priv) >= 12)
3136 intel_ddi_disable_transcoder_clock(old_crtc_state);
3137
3138 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3139 if (wakeref)
3140 intel_display_power_put(dev_priv,
3141 dig_port->ddi_io_power_domain,
3142 wakeref);
3143
3144 intel_ddi_disable_clock(encoder);
3145
3146 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3147}
3148
3149static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
3150 struct intel_encoder *encoder,
3151 const struct intel_crtc_state *old_crtc_state,
3152 const struct drm_connector_state *old_conn_state)
3153{
3154 struct intel_display *display = to_intel_display(encoder);
3155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3156 struct intel_crtc *pipe_crtc;
3157 int i;
3158
3159 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3160 const struct intel_crtc_state *old_pipe_crtc_state =
3161 intel_atomic_get_old_crtc_state(state, pipe_crtc);
3162
3163 intel_crtc_vblank_off(old_pipe_crtc_state);
3164 }
3165
3166 intel_disable_transcoder(old_crtc_state);
3167
3168 intel_ddi_disable_transcoder_func(old_crtc_state);
3169
3170 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3171 const struct intel_crtc_state *old_pipe_crtc_state =
3172 intel_atomic_get_old_crtc_state(state, pipe_crtc);
3173
3174 intel_dsc_disable(old_pipe_crtc_state);
3175
3176 if (DISPLAY_VER(dev_priv) >= 9)
3177 skl_scaler_disable(old_pipe_crtc_state);
3178 else
3179 ilk_pfit_disable(old_pipe_crtc_state);
3180 }
3181}
3182
3183static void intel_ddi_post_disable(struct intel_atomic_state *state,
3184 struct intel_encoder *encoder,
3185 const struct intel_crtc_state *old_crtc_state,
3186 const struct drm_connector_state *old_conn_state)
3187{
3188 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
3189 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state,
3190 old_conn_state);
3191
3192 /*
3193 * When called from DP MST code:
3194 * - old_conn_state will be NULL
3195 * - encoder will be the main encoder (ie. mst->primary)
3196 * - the main connector associated with this port
3197 * won't be active or linked to a crtc
3198 * - old_crtc_state will be the state of the last stream to
3199 * be deactivated on this port, and it may not be the same
3200 * stream that was activated last, but each stream
3201 * should have a state that is identical when it comes to
3202 * the DP link parameteres
3203 */
3204
3205 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3206 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3207 old_conn_state);
3208 else
3209 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3210 old_conn_state);
3211}
3212
3213static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3214 struct intel_encoder *encoder,
3215 const struct intel_crtc_state *old_crtc_state,
3216 const struct drm_connector_state *old_conn_state)
3217{
3218 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3219
3220 main_link_aux_power_domain_put(dig_port, old_crtc_state);
3221
3222 if (intel_encoder_is_tc(encoder))
3223 intel_tc_port_put_link(dig_port);
3224}
3225
3226static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3227 struct intel_encoder *encoder,
3228 const struct intel_crtc_state *crtc_state)
3229{
3230 const struct drm_connector_state *conn_state;
3231 struct drm_connector *conn;
3232 int i;
3233
3234 if (!crtc_state->sync_mode_slaves_mask)
3235 return;
3236
3237 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3238 struct intel_encoder *slave_encoder =
3239 to_intel_encoder(conn_state->best_encoder);
3240 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3241 const struct intel_crtc_state *slave_crtc_state;
3242
3243 if (!slave_crtc)
3244 continue;
3245
3246 slave_crtc_state =
3247 intel_atomic_get_new_crtc_state(state, slave_crtc);
3248
3249 if (slave_crtc_state->master_transcoder !=
3250 crtc_state->cpu_transcoder)
3251 continue;
3252
3253 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3254 slave_crtc_state);
3255 }
3256
3257 usleep_range(200, 400);
3258
3259 intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3260 crtc_state);
3261}
3262
3263static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3264 struct intel_encoder *encoder,
3265 const struct intel_crtc_state *crtc_state,
3266 const struct drm_connector_state *conn_state)
3267{
3268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3269 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3270 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3271 enum port port = encoder->port;
3272
3273 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3274 intel_dp_stop_link_train(intel_dp, crtc_state);
3275
3276 drm_connector_update_privacy_screen(conn_state);
3277 intel_edp_backlight_on(crtc_state, conn_state);
3278
3279 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp))
3280 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3281
3282 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3283}
3284
3285/* FIXME bad home for this function */
3286i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915,
3287 enum transcoder cpu_transcoder)
3288{
3289 return DISPLAY_VER(i915) >= 14 ?
3290 MTL_CHICKEN_TRANS(cpu_transcoder) :
3291 CHICKEN_TRANS(cpu_transcoder);
3292}
3293
3294static i915_reg_t
3295gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3296 enum port port)
3297{
3298 static const enum transcoder trans[] = {
3299 [PORT_A] = TRANSCODER_EDP,
3300 [PORT_B] = TRANSCODER_A,
3301 [PORT_C] = TRANSCODER_B,
3302 [PORT_D] = TRANSCODER_C,
3303 [PORT_E] = TRANSCODER_A,
3304 };
3305
3306 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3307
3308 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3309 port = PORT_A;
3310
3311 return CHICKEN_TRANS(trans[port]);
3312}
3313
3314static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3315 struct intel_encoder *encoder,
3316 const struct intel_crtc_state *crtc_state,
3317 const struct drm_connector_state *conn_state)
3318{
3319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3320 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3321 struct drm_connector *connector = conn_state->connector;
3322 enum port port = encoder->port;
3323 u32 buf_ctl;
3324
3325 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3326 crtc_state->hdmi_high_tmds_clock_ratio,
3327 crtc_state->hdmi_scrambling))
3328 drm_dbg_kms(&dev_priv->drm,
3329 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3330 connector->base.id, connector->name);
3331
3332 if (has_buf_trans_select(dev_priv))
3333 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3334
3335 /* e. Enable D2D Link for C10/C20 Phy */
3336 if (DISPLAY_VER(dev_priv) >= 14)
3337 mtl_ddi_enable_d2d(encoder);
3338
3339 encoder->set_signal_levels(encoder, crtc_state);
3340
3341 /* Display WA #1143: skl,kbl,cfl */
3342 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3343 /*
3344 * For some reason these chicken bits have been
3345 * stuffed into a transcoder register, event though
3346 * the bits affect a specific DDI port rather than
3347 * a specific transcoder.
3348 */
3349 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3350 u32 val;
3351
3352 val = intel_de_read(dev_priv, reg);
3353
3354 if (port == PORT_E)
3355 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3356 DDIE_TRAINING_OVERRIDE_VALUE;
3357 else
3358 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3359 DDI_TRAINING_OVERRIDE_VALUE;
3360
3361 intel_de_write(dev_priv, reg, val);
3362 intel_de_posting_read(dev_priv, reg);
3363
3364 udelay(1);
3365
3366 if (port == PORT_E)
3367 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3368 DDIE_TRAINING_OVERRIDE_VALUE);
3369 else
3370 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3371 DDI_TRAINING_OVERRIDE_VALUE);
3372
3373 intel_de_write(dev_priv, reg, val);
3374 }
3375
3376 intel_ddi_power_up_lanes(encoder, crtc_state);
3377
3378 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3379 * are ignored so nothing special needs to be done besides
3380 * enabling the port.
3381 *
3382 * On ADL_P the PHY link rate and lane count must be programmed but
3383 * these are both 0 for HDMI.
3384 *
3385 * But MTL onwards HDMI2.1 is supported and in TMDS mode this
3386 * is filled with lane count, already set in the crtc_state.
3387 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3388 */
3389 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
3390 if (DISPLAY_VER(dev_priv) >= 14) {
3391 u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
3392 u32 port_buf = 0;
3393
3394 port_buf |= XELPDP_PORT_WIDTH(lane_count);
3395
3396 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
3397 port_buf |= XELPDP_PORT_REVERSAL;
3398
3399 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
3400 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
3401
3402 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
3403
3404 if (DISPLAY_VER(dev_priv) >= 20)
3405 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3406 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) {
3407 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
3408 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3409 }
3410
3411 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
3412
3413 intel_wait_ddi_buf_active(encoder);
3414}
3415
3416static void intel_enable_ddi(struct intel_atomic_state *state,
3417 struct intel_encoder *encoder,
3418 const struct intel_crtc_state *crtc_state,
3419 const struct drm_connector_state *conn_state)
3420{
3421 struct intel_display *display = to_intel_display(encoder);
3422 struct intel_crtc *pipe_crtc;
3423 int i;
3424
3425 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3426
3427 /* Enable/Disable DP2.0 SDP split config before transcoder */
3428 intel_audio_sdp_split_update(crtc_state);
3429
3430 intel_enable_transcoder(crtc_state);
3431
3432 intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
3433
3434 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {
3435 const struct intel_crtc_state *pipe_crtc_state =
3436 intel_atomic_get_new_crtc_state(state, pipe_crtc);
3437
3438 intel_crtc_vblank_on(pipe_crtc_state);
3439 }
3440
3441 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3442 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3443 else
3444 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3445
3446 intel_hdcp_enable(state, encoder, crtc_state, conn_state);
3447
3448}
3449
3450static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3451 struct intel_encoder *encoder,
3452 const struct intel_crtc_state *old_crtc_state,
3453 const struct drm_connector_state *old_conn_state)
3454{
3455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3456 struct intel_connector *connector =
3457 to_intel_connector(old_conn_state->connector);
3458
3459 intel_dp->link_trained = false;
3460
3461 intel_psr_disable(intel_dp, old_crtc_state);
3462 intel_edp_backlight_off(old_conn_state);
3463 /* Disable the decompression in DP Sink */
3464 intel_dp_sink_disable_decompression(state,
3465 connector, old_crtc_state);
3466 /* Disable Ignore_MSA bit in DP Sink */
3467 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3468 false);
3469}
3470
3471static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3472 struct intel_encoder *encoder,
3473 const struct intel_crtc_state *old_crtc_state,
3474 const struct drm_connector_state *old_conn_state)
3475{
3476 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3477 struct drm_connector *connector = old_conn_state->connector;
3478
3479 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3480 false, false))
3481 drm_dbg_kms(&i915->drm,
3482 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3483 connector->base.id, connector->name);
3484}
3485
3486static void intel_disable_ddi(struct intel_atomic_state *state,
3487 struct intel_encoder *encoder,
3488 const struct intel_crtc_state *old_crtc_state,
3489 const struct drm_connector_state *old_conn_state)
3490{
3491 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
3492
3493 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3494
3495 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3496 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3497 old_conn_state);
3498 else
3499 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3500 old_conn_state);
3501}
3502
3503static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3504 struct intel_encoder *encoder,
3505 const struct intel_crtc_state *crtc_state,
3506 const struct drm_connector_state *conn_state)
3507{
3508 intel_ddi_set_dp_msa(crtc_state, conn_state);
3509
3510 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3511
3512 intel_backlight_update(state, encoder, crtc_state, conn_state);
3513 drm_connector_update_privacy_screen(conn_state);
3514}
3515
3516static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder,
3517 const struct intel_crtc_state *crtc_state,
3518 const struct drm_connector_state *conn_state)
3519{
3520 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
3521}
3522
3523void intel_ddi_update_pipe(struct intel_atomic_state *state,
3524 struct intel_encoder *encoder,
3525 const struct intel_crtc_state *crtc_state,
3526 const struct drm_connector_state *conn_state)
3527{
3528
3529 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3530 !intel_encoder_is_mst(encoder))
3531 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3532 conn_state);
3533
3534 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3535 intel_ddi_update_pipe_hdmi(encoder, crtc_state,
3536 conn_state);
3537
3538 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3539}
3540
3541void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3542 struct intel_encoder *encoder,
3543 struct intel_crtc *crtc)
3544{
3545 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3546 const struct intel_crtc_state *crtc_state =
3547 intel_atomic_get_new_crtc_state(state, crtc);
3548 struct intel_crtc *pipe_crtc;
3549
3550 /* FIXME: Add MTL pll_mgr */
3551 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder))
3552 return;
3553
3554 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
3555 intel_crtc_joined_pipe_mask(crtc_state))
3556 intel_update_active_dpll(state, pipe_crtc, encoder);
3557}
3558
3559static void
3560intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3561 struct intel_encoder *encoder,
3562 const struct intel_crtc_state *crtc_state,
3563 const struct drm_connector_state *conn_state)
3564{
3565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3566 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3567 bool is_tc_port = intel_encoder_is_tc(encoder);
3568
3569 if (is_tc_port) {
3570 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3571
3572 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3573 intel_ddi_update_active_dpll(state, encoder, crtc);
3574 }
3575
3576 main_link_aux_power_domain_get(dig_port, crtc_state);
3577
3578 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3579 /*
3580 * Program the lane count for static/dynamic connections on
3581 * Type-C ports. Skip this step for TBT.
3582 */
3583 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3584 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3585 bxt_dpio_phy_set_lane_optim_mask(encoder,
3586 crtc_state->lane_lat_optim_mask);
3587}
3588
3589static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3590{
3591 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3592 enum tc_port tc_port = intel_encoder_to_tc(encoder);
3593 int ln;
3594
3595 for (ln = 0; ln < 2; ln++)
3596 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
3597}
3598
3599static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3600 const struct intel_crtc_state *crtc_state)
3601{
3602 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3603 struct intel_encoder *encoder = &dig_port->base;
3604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3605 enum port port = encoder->port;
3606 u32 dp_tp_ctl;
3607
3608 /*
3609 * TODO: To train with only a different voltage swing entry is not
3610 * necessary disable and enable port
3611 */
3612 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3613 if (dp_tp_ctl & DP_TP_CTL_ENABLE)
3614 mtl_disable_ddi_buf(encoder, crtc_state);
3615
3616 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3617 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3618 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3619 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3620 } else {
3621 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3622 if (crtc_state->enhanced_framing)
3623 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3624 }
3625 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3626 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3627
3628 /* 6.f Enable D2D Link */
3629 mtl_ddi_enable_d2d(encoder);
3630
3631 /* 6.g Configure voltage swing and related IO settings */
3632 encoder->set_signal_levels(encoder, crtc_state);
3633
3634 /* 6.h Configure PORT_BUF_CTL1 */
3635 mtl_port_buf_ctl_program(encoder, crtc_state);
3636
3637 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3638 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3639 if (DISPLAY_VER(dev_priv) >= 20)
3640 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3641
3642 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3643 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3644
3645 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
3646 intel_wait_ddi_buf_active(encoder);
3647}
3648
3649static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3650 const struct intel_crtc_state *crtc_state)
3651{
3652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3653 struct intel_encoder *encoder = &dig_port->base;
3654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3655 enum port port = encoder->port;
3656 u32 dp_tp_ctl, ddi_buf_ctl;
3657 bool wait = false;
3658
3659 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3660
3661 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3662 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3663 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3664 intel_de_write(dev_priv, DDI_BUF_CTL(port),
3665 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3666 wait = true;
3667 }
3668
3669 dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
3670 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3671 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3672
3673 if (wait)
3674 intel_wait_ddi_buf_idle(dev_priv, port);
3675 }
3676
3677 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3678 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3679 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3680 } else {
3681 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3682 if (crtc_state->enhanced_framing)
3683 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3684 }
3685 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3686 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3687
3688 if (IS_ALDERLAKE_P(dev_priv) &&
3689 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3690 adlp_tbt_to_dp_alt_switch_wa(encoder);
3691
3692 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3693 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3694 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3695
3696 intel_wait_ddi_buf_active(encoder);
3697}
3698
3699static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3700 const struct intel_crtc_state *crtc_state,
3701 u8 dp_train_pat)
3702{
3703 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3705 u32 temp;
3706
3707 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3708
3709 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3710 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3711 case DP_TRAINING_PATTERN_DISABLE:
3712 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3713 break;
3714 case DP_TRAINING_PATTERN_1:
3715 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3716 break;
3717 case DP_TRAINING_PATTERN_2:
3718 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3719 break;
3720 case DP_TRAINING_PATTERN_3:
3721 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3722 break;
3723 case DP_TRAINING_PATTERN_4:
3724 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3725 break;
3726 }
3727
3728 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3729}
3730
3731static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3732 const struct intel_crtc_state *crtc_state)
3733{
3734 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3735 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3736 enum port port = encoder->port;
3737
3738 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3739 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3740
3741 /*
3742 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3743 * reason we need to set idle transmission mode is to work around a HW
3744 * issue where we enable the pipe while not in idle link-training mode.
3745 * In this case there is requirement to wait for a minimum number of
3746 * idle patterns to be sent.
3747 */
3748 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3749 return;
3750
3751 if (intel_de_wait_for_set(dev_priv,
3752 dp_tp_status_reg(encoder, crtc_state),
3753 DP_TP_STATUS_IDLE_DONE, 2))
3754 drm_err(&dev_priv->drm,
3755 "Timed out waiting for DP idle patterns\n");
3756}
3757
3758static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3759 enum transcoder cpu_transcoder)
3760{
3761 if (cpu_transcoder == TRANSCODER_EDP)
3762 return false;
3763
3764 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3765 return false;
3766
3767 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3768 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3769}
3770
3771static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3772{
3773 if (crtc_state->port_clock > 594000)
3774 return 2;
3775 else
3776 return 0;
3777}
3778
3779static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3780{
3781 if (crtc_state->port_clock > 594000)
3782 return 3;
3783 else
3784 return 0;
3785}
3786
3787static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3788{
3789 if (crtc_state->port_clock > 594000)
3790 return 1;
3791 else
3792 return 0;
3793}
3794
3795void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
3796{
3797 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3798
3799 if (DISPLAY_VER(dev_priv) >= 14)
3800 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3801 else if (DISPLAY_VER(dev_priv) >= 12)
3802 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
3803 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
3804 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
3805 else if (DISPLAY_VER(dev_priv) >= 11)
3806 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3807}
3808
3809static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3810 enum transcoder cpu_transcoder)
3811{
3812 u32 master_select;
3813
3814 if (DISPLAY_VER(dev_priv) >= 11) {
3815 u32 ctl2 = intel_de_read(dev_priv,
3816 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder));
3817
3818 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3819 return INVALID_TRANSCODER;
3820
3821 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3822 } else {
3823 u32 ctl = intel_de_read(dev_priv,
3824 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3825
3826 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3827 return INVALID_TRANSCODER;
3828
3829 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3830 }
3831
3832 if (master_select == 0)
3833 return TRANSCODER_EDP;
3834 else
3835 return master_select - 1;
3836}
3837
3838static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3839{
3840 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3841 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3842 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3843 enum transcoder cpu_transcoder;
3844
3845 crtc_state->master_transcoder =
3846 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3847
3848 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3849 enum intel_display_power_domain power_domain;
3850 intel_wakeref_t trans_wakeref;
3851
3852 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3853 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3854 power_domain);
3855
3856 if (!trans_wakeref)
3857 continue;
3858
3859 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3860 crtc_state->cpu_transcoder)
3861 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3862
3863 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3864 }
3865
3866 drm_WARN_ON(&dev_priv->drm,
3867 crtc_state->master_transcoder != INVALID_TRANSCODER &&
3868 crtc_state->sync_mode_slaves_mask);
3869}
3870
3871static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3872 struct intel_crtc_state *pipe_config)
3873{
3874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3875 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3876 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3877 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3878 u32 temp, flags = 0;
3879
3880 temp = intel_de_read(dev_priv,
3881 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3882 if (temp & TRANS_DDI_PHSYNC)
3883 flags |= DRM_MODE_FLAG_PHSYNC;
3884 else
3885 flags |= DRM_MODE_FLAG_NHSYNC;
3886 if (temp & TRANS_DDI_PVSYNC)
3887 flags |= DRM_MODE_FLAG_PVSYNC;
3888 else
3889 flags |= DRM_MODE_FLAG_NVSYNC;
3890
3891 pipe_config->hw.adjusted_mode.flags |= flags;
3892
3893 switch (temp & TRANS_DDI_BPC_MASK) {
3894 case TRANS_DDI_BPC_6:
3895 pipe_config->pipe_bpp = 18;
3896 break;
3897 case TRANS_DDI_BPC_8:
3898 pipe_config->pipe_bpp = 24;
3899 break;
3900 case TRANS_DDI_BPC_10:
3901 pipe_config->pipe_bpp = 30;
3902 break;
3903 case TRANS_DDI_BPC_12:
3904 pipe_config->pipe_bpp = 36;
3905 break;
3906 default:
3907 break;
3908 }
3909
3910 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3911 case TRANS_DDI_MODE_SELECT_HDMI:
3912 pipe_config->has_hdmi_sink = true;
3913
3914 pipe_config->infoframes.enable |=
3915 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3916
3917 if (pipe_config->infoframes.enable)
3918 pipe_config->has_infoframe = true;
3919
3920 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3921 pipe_config->hdmi_scrambling = true;
3922 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3923 pipe_config->hdmi_high_tmds_clock_ratio = true;
3924 fallthrough;
3925 case TRANS_DDI_MODE_SELECT_DVI:
3926 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3927 if (DISPLAY_VER(dev_priv) >= 14)
3928 pipe_config->lane_count =
3929 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3930 else
3931 pipe_config->lane_count = 4;
3932 break;
3933 case TRANS_DDI_MODE_SELECT_DP_SST:
3934 if (encoder->type == INTEL_OUTPUT_EDP)
3935 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3936 else
3937 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3938 pipe_config->lane_count =
3939 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3940
3941 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3942 &pipe_config->dp_m_n);
3943 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3944 &pipe_config->dp_m2_n2);
3945
3946 pipe_config->enhanced_framing =
3947 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
3948 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3949
3950 if (DISPLAY_VER(dev_priv) >= 11)
3951 pipe_config->fec_enable =
3952 intel_de_read(dev_priv,
3953 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
3954
3955 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
3956 pipe_config->infoframes.enable |=
3957 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3958 else
3959 pipe_config->infoframes.enable |=
3960 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3961 break;
3962 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3963 if (!HAS_DP20(dev_priv)) {
3964 /* FDI */
3965 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3966 pipe_config->enhanced_framing =
3967 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
3968 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3969 break;
3970 }
3971 fallthrough; /* 128b/132b */
3972 case TRANS_DDI_MODE_SELECT_DP_MST:
3973 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3974 pipe_config->lane_count =
3975 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3976
3977 if (DISPLAY_VER(dev_priv) >= 12)
3978 pipe_config->mst_master_transcoder =
3979 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3980
3981 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3982 &pipe_config->dp_m_n);
3983
3984 if (DISPLAY_VER(dev_priv) >= 11)
3985 pipe_config->fec_enable =
3986 intel_de_read(dev_priv,
3987 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
3988
3989 pipe_config->infoframes.enable |=
3990 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3991 break;
3992 default:
3993 break;
3994 }
3995}
3996
3997static void intel_ddi_get_config(struct intel_encoder *encoder,
3998 struct intel_crtc_state *pipe_config)
3999{
4000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4001 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4002
4003 /* XXX: DSI transcoder paranoia */
4004 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4005 return;
4006
4007 intel_ddi_read_func_ctl(encoder, pipe_config);
4008
4009 intel_ddi_mso_get_config(encoder, pipe_config);
4010
4011 pipe_config->has_audio =
4012 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4013
4014 if (encoder->type == INTEL_OUTPUT_EDP)
4015 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
4016
4017 ddi_dotclock_get(pipe_config);
4018
4019 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4020 pipe_config->lane_lat_optim_mask =
4021 bxt_dpio_phy_get_lane_lat_optim_mask(encoder);
4022
4023 intel_ddi_compute_min_voltage_level(pipe_config);
4024
4025 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4026
4027 intel_read_infoframe(encoder, pipe_config,
4028 HDMI_INFOFRAME_TYPE_AVI,
4029 &pipe_config->infoframes.avi);
4030 intel_read_infoframe(encoder, pipe_config,
4031 HDMI_INFOFRAME_TYPE_SPD,
4032 &pipe_config->infoframes.spd);
4033 intel_read_infoframe(encoder, pipe_config,
4034 HDMI_INFOFRAME_TYPE_VENDOR,
4035 &pipe_config->infoframes.hdmi);
4036 intel_read_infoframe(encoder, pipe_config,
4037 HDMI_INFOFRAME_TYPE_DRM,
4038 &pipe_config->infoframes.drm);
4039
4040 if (DISPLAY_VER(dev_priv) >= 8)
4041 bdw_get_trans_port_sync_config(pipe_config);
4042
4043 intel_psr_get_config(encoder, pipe_config);
4044
4045 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4046 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4047 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
4048
4049 intel_audio_codec_get_config(encoder, pipe_config);
4050}
4051
4052void intel_ddi_get_clock(struct intel_encoder *encoder,
4053 struct intel_crtc_state *crtc_state,
4054 struct intel_shared_dpll *pll)
4055{
4056 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4057 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4058 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4059 bool pll_active;
4060
4061 if (drm_WARN_ON(&i915->drm, !pll))
4062 return;
4063
4064 port_dpll->pll = pll;
4065 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
4066 drm_WARN_ON(&i915->drm, !pll_active);
4067
4068 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4069
4070 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
4071 &crtc_state->dpll_hw_state);
4072}
4073
4074static void mtl_ddi_get_config(struct intel_encoder *encoder,
4075 struct intel_crtc_state *crtc_state)
4076{
4077 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
4078
4079 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
4080 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4081 else
4082 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
4083
4084 intel_ddi_get_config(encoder, crtc_state);
4085}
4086
4087static void dg2_ddi_get_config(struct intel_encoder *encoder,
4088 struct intel_crtc_state *crtc_state)
4089{
4090 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);
4091 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);
4092
4093 intel_ddi_get_config(encoder, crtc_state);
4094}
4095
4096static void adls_ddi_get_config(struct intel_encoder *encoder,
4097 struct intel_crtc_state *crtc_state)
4098{
4099 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
4100 intel_ddi_get_config(encoder, crtc_state);
4101}
4102
4103static void rkl_ddi_get_config(struct intel_encoder *encoder,
4104 struct intel_crtc_state *crtc_state)
4105{
4106 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
4107 intel_ddi_get_config(encoder, crtc_state);
4108}
4109
4110static void dg1_ddi_get_config(struct intel_encoder *encoder,
4111 struct intel_crtc_state *crtc_state)
4112{
4113 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
4114 intel_ddi_get_config(encoder, crtc_state);
4115}
4116
4117static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
4118 struct intel_crtc_state *crtc_state)
4119{
4120 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
4121 intel_ddi_get_config(encoder, crtc_state);
4122}
4123
4124static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
4125{
4126 return pll->info->id == DPLL_ID_ICL_TBTPLL;
4127}
4128
4129static enum icl_port_dpll_id
4130icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
4131 const struct intel_crtc_state *crtc_state)
4132{
4133 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4134 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
4135
4136 if (drm_WARN_ON(&i915->drm, !pll))
4137 return ICL_PORT_DPLL_DEFAULT;
4138
4139 if (icl_ddi_tc_pll_is_tbt(pll))
4140 return ICL_PORT_DPLL_DEFAULT;
4141 else
4142 return ICL_PORT_DPLL_MG_PHY;
4143}
4144
4145enum icl_port_dpll_id
4146intel_ddi_port_pll_type(struct intel_encoder *encoder,
4147 const struct intel_crtc_state *crtc_state)
4148{
4149 if (!encoder->port_pll_type)
4150 return ICL_PORT_DPLL_DEFAULT;
4151
4152 return encoder->port_pll_type(encoder, crtc_state);
4153}
4154
4155static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
4156 struct intel_crtc_state *crtc_state,
4157 struct intel_shared_dpll *pll)
4158{
4159 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4160 enum icl_port_dpll_id port_dpll_id;
4161 struct icl_port_dpll *port_dpll;
4162 bool pll_active;
4163
4164 if (drm_WARN_ON(&i915->drm, !pll))
4165 return;
4166
4167 if (icl_ddi_tc_pll_is_tbt(pll))
4168 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4169 else
4170 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
4171
4172 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4173
4174 port_dpll->pll = pll;
4175 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
4176 drm_WARN_ON(&i915->drm, !pll_active);
4177
4178 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4179
4180 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
4181 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
4182 else
4183 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
4184 &crtc_state->dpll_hw_state);
4185}
4186
4187static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
4188 struct intel_crtc_state *crtc_state)
4189{
4190 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
4191 intel_ddi_get_config(encoder, crtc_state);
4192}
4193
4194static void bxt_ddi_get_config(struct intel_encoder *encoder,
4195 struct intel_crtc_state *crtc_state)
4196{
4197 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
4198 intel_ddi_get_config(encoder, crtc_state);
4199}
4200
4201static void skl_ddi_get_config(struct intel_encoder *encoder,
4202 struct intel_crtc_state *crtc_state)
4203{
4204 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
4205 intel_ddi_get_config(encoder, crtc_state);
4206}
4207
4208void hsw_ddi_get_config(struct intel_encoder *encoder,
4209 struct intel_crtc_state *crtc_state)
4210{
4211 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
4212 intel_ddi_get_config(encoder, crtc_state);
4213}
4214
4215static void intel_ddi_sync_state(struct intel_encoder *encoder,
4216 const struct intel_crtc_state *crtc_state)
4217{
4218 if (intel_encoder_is_tc(encoder))
4219 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
4220 crtc_state);
4221
4222 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
4223 (!crtc_state && intel_encoder_is_dp(encoder)))
4224 intel_dp_sync_state(encoder, crtc_state);
4225}
4226
4227static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4228 struct intel_crtc_state *crtc_state)
4229{
4230 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4231 bool fastset = true;
4232
4233 if (intel_encoder_is_tc(encoder)) {
4234 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4235 encoder->base.base.id, encoder->base.name);
4236 crtc_state->uapi.mode_changed = true;
4237 fastset = false;
4238 }
4239
4240 if (intel_crtc_has_dp_encoder(crtc_state) &&
4241 !intel_dp_initial_fastset_check(encoder, crtc_state))
4242 fastset = false;
4243
4244 return fastset;
4245}
4246
4247static enum intel_output_type
4248intel_ddi_compute_output_type(struct intel_encoder *encoder,
4249 struct intel_crtc_state *crtc_state,
4250 struct drm_connector_state *conn_state)
4251{
4252 switch (conn_state->connector->connector_type) {
4253 case DRM_MODE_CONNECTOR_HDMIA:
4254 return INTEL_OUTPUT_HDMI;
4255 case DRM_MODE_CONNECTOR_eDP:
4256 return INTEL_OUTPUT_EDP;
4257 case DRM_MODE_CONNECTOR_DisplayPort:
4258 return INTEL_OUTPUT_DP;
4259 default:
4260 MISSING_CASE(conn_state->connector->connector_type);
4261 return INTEL_OUTPUT_UNUSED;
4262 }
4263}
4264
4265static int intel_ddi_compute_config(struct intel_encoder *encoder,
4266 struct intel_crtc_state *pipe_config,
4267 struct drm_connector_state *conn_state)
4268{
4269 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4271 enum port port = encoder->port;
4272 int ret;
4273
4274 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4275 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4276
4277 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4278 pipe_config->has_hdmi_sink =
4279 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state);
4280
4281 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4282 } else {
4283 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4284 }
4285
4286 if (ret)
4287 return ret;
4288
4289 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4290 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4291 pipe_config->pch_pfit.force_thru =
4292 pipe_config->pch_pfit.enabled ||
4293 pipe_config->crc_enabled;
4294
4295 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4296 pipe_config->lane_lat_optim_mask =
4297 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4298
4299 intel_ddi_compute_min_voltage_level(pipe_config);
4300
4301 return 0;
4302}
4303
4304static bool mode_equal(const struct drm_display_mode *mode1,
4305 const struct drm_display_mode *mode2)
4306{
4307 return drm_mode_match(mode1, mode2,
4308 DRM_MODE_MATCH_TIMINGS |
4309 DRM_MODE_MATCH_FLAGS |
4310 DRM_MODE_MATCH_3D_FLAGS) &&
4311 mode1->clock == mode2->clock; /* we want an exact match */
4312}
4313
4314static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4315 const struct intel_link_m_n *m_n_2)
4316{
4317 return m_n_1->tu == m_n_2->tu &&
4318 m_n_1->data_m == m_n_2->data_m &&
4319 m_n_1->data_n == m_n_2->data_n &&
4320 m_n_1->link_m == m_n_2->link_m &&
4321 m_n_1->link_n == m_n_2->link_n;
4322}
4323
4324static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4325 const struct intel_crtc_state *crtc_state2)
4326{
4327 /*
4328 * FIXME the modeset sequence is currently wrong and
4329 * can't deal with joiner + port sync at the same time.
4330 */
4331 return crtc_state1->hw.active && crtc_state2->hw.active &&
4332 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
4333 crtc_state1->output_types == crtc_state2->output_types &&
4334 crtc_state1->output_format == crtc_state2->output_format &&
4335 crtc_state1->lane_count == crtc_state2->lane_count &&
4336 crtc_state1->port_clock == crtc_state2->port_clock &&
4337 mode_equal(&crtc_state1->hw.adjusted_mode,
4338 &crtc_state2->hw.adjusted_mode) &&
4339 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4340}
4341
4342static u8
4343intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4344 int tile_group_id)
4345{
4346 struct drm_connector *connector;
4347 const struct drm_connector_state *conn_state;
4348 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4349 struct intel_atomic_state *state =
4350 to_intel_atomic_state(ref_crtc_state->uapi.state);
4351 u8 transcoders = 0;
4352 int i;
4353
4354 /*
4355 * We don't enable port sync on BDW due to missing w/as and
4356 * due to not having adjusted the modeset sequence appropriately.
4357 */
4358 if (DISPLAY_VER(dev_priv) < 9)
4359 return 0;
4360
4361 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4362 return 0;
4363
4364 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4365 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4366 const struct intel_crtc_state *crtc_state;
4367
4368 if (!crtc)
4369 continue;
4370
4371 if (!connector->has_tile ||
4372 connector->tile_group->id !=
4373 tile_group_id)
4374 continue;
4375 crtc_state = intel_atomic_get_new_crtc_state(state,
4376 crtc);
4377 if (!crtcs_port_sync_compatible(ref_crtc_state,
4378 crtc_state))
4379 continue;
4380 transcoders |= BIT(crtc_state->cpu_transcoder);
4381 }
4382
4383 return transcoders;
4384}
4385
4386static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4387 struct intel_crtc_state *crtc_state,
4388 struct drm_connector_state *conn_state)
4389{
4390 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4391 struct drm_connector *connector = conn_state->connector;
4392 u8 port_sync_transcoders = 0;
4393
4394 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
4395 encoder->base.base.id, encoder->base.name,
4396 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4397
4398 if (connector->has_tile)
4399 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4400 connector->tile_group->id);
4401
4402 /*
4403 * EDP Transcoders cannot be ensalved
4404 * make them a master always when present
4405 */
4406 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4407 crtc_state->master_transcoder = TRANSCODER_EDP;
4408 else
4409 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4410
4411 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4412 crtc_state->master_transcoder = INVALID_TRANSCODER;
4413 crtc_state->sync_mode_slaves_mask =
4414 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4415 }
4416
4417 return 0;
4418}
4419
4420static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4421{
4422 struct drm_i915_private *i915 = to_i915(encoder->dev);
4423 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4424
4425 intel_dp_encoder_flush_work(encoder);
4426 if (intel_encoder_is_tc(&dig_port->base))
4427 intel_tc_port_cleanup(dig_port);
4428 intel_display_power_flush_work(i915);
4429
4430 drm_encoder_cleanup(encoder);
4431 kfree(dig_port->hdcp_port_data.streams);
4432 kfree(dig_port);
4433}
4434
4435static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4436{
4437 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4438 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4439
4440 intel_dp->reset_link_params = true;
4441 intel_dp_invalidate_source_oui(intel_dp);
4442
4443 intel_pps_encoder_reset(intel_dp);
4444
4445 if (intel_encoder_is_tc(&dig_port->base))
4446 intel_tc_port_init_mode(dig_port);
4447}
4448
4449static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4450{
4451 struct intel_encoder *encoder = to_intel_encoder(_encoder);
4452
4453 intel_tc_port_link_reset(enc_to_dig_port(encoder));
4454
4455 return 0;
4456}
4457
4458static const struct drm_encoder_funcs intel_ddi_funcs = {
4459 .reset = intel_ddi_encoder_reset,
4460 .destroy = intel_ddi_encoder_destroy,
4461 .late_register = intel_ddi_encoder_late_register,
4462};
4463
4464static struct intel_connector *
4465intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4466{
4467 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4468 struct intel_connector *connector;
4469 enum port port = dig_port->base.port;
4470
4471 connector = intel_connector_alloc();
4472 if (!connector)
4473 return NULL;
4474
4475 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4476 if (DISPLAY_VER(i915) >= 14)
4477 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4478 else
4479 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4480 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4481 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4482
4483 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4484 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4485
4486 if (!intel_dp_init_connector(dig_port, connector)) {
4487 kfree(connector);
4488 return NULL;
4489 }
4490
4491 if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4492 struct drm_device *dev = dig_port->base.base.dev;
4493 struct drm_privacy_screen *privacy_screen;
4494
4495 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
4496 if (!IS_ERR(privacy_screen)) {
4497 drm_connector_attach_privacy_screen_provider(&connector->base,
4498 privacy_screen);
4499 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
4500 drm_warn(dev, "Error getting privacy-screen\n");
4501 }
4502 }
4503
4504 return connector;
4505}
4506
4507static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4508 struct drm_modeset_acquire_ctx *ctx)
4509{
4510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4511 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4512 struct intel_connector *connector = hdmi->attached_connector;
4513 struct i2c_adapter *ddc = connector->base.ddc;
4514 struct drm_connector_state *conn_state;
4515 struct intel_crtc_state *crtc_state;
4516 struct intel_crtc *crtc;
4517 u8 config;
4518 int ret;
4519
4520 if (connector->base.status != connector_status_connected)
4521 return 0;
4522
4523 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4524 ctx);
4525 if (ret)
4526 return ret;
4527
4528 conn_state = connector->base.state;
4529
4530 crtc = to_intel_crtc(conn_state->crtc);
4531 if (!crtc)
4532 return 0;
4533
4534 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4535 if (ret)
4536 return ret;
4537
4538 crtc_state = to_intel_crtc_state(crtc->base.state);
4539
4540 drm_WARN_ON(&dev_priv->drm,
4541 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4542
4543 if (!crtc_state->hw.active)
4544 return 0;
4545
4546 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4547 !crtc_state->hdmi_scrambling)
4548 return 0;
4549
4550 if (conn_state->commit &&
4551 !try_wait_for_completion(&conn_state->commit->hw_done))
4552 return 0;
4553
4554 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config);
4555 if (ret < 0) {
4556 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4557 connector->base.base.id, connector->base.name, ret);
4558 return 0;
4559 }
4560
4561 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4562 crtc_state->hdmi_high_tmds_clock_ratio &&
4563 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4564 crtc_state->hdmi_scrambling)
4565 return 0;
4566
4567 /*
4568 * HDMI 2.0 says that one should not send scrambled data
4569 * prior to configuring the sink scrambling, and that
4570 * TMDS clock/data transmission should be suspended when
4571 * changing the TMDS clock rate in the sink. So let's
4572 * just do a full modeset here, even though some sinks
4573 * would be perfectly happy if were to just reconfigure
4574 * the SCDC settings on the fly.
4575 */
4576 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx);
4577}
4578
4579static void intel_ddi_link_check(struct intel_encoder *encoder)
4580{
4581 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4582 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4583
4584 /* TODO: Move checking the HDMI link state here as well. */
4585 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector);
4586
4587 intel_dp_link_check(encoder);
4588}
4589
4590static enum intel_hotplug_state
4591intel_ddi_hotplug(struct intel_encoder *encoder,
4592 struct intel_connector *connector)
4593{
4594 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4595 struct intel_dp *intel_dp = &dig_port->dp;
4596 bool is_tc = intel_encoder_is_tc(encoder);
4597 struct drm_modeset_acquire_ctx ctx;
4598 enum intel_hotplug_state state;
4599 int ret;
4600
4601 if (intel_dp_test_phy(intel_dp))
4602 return INTEL_HOTPLUG_UNCHANGED;
4603
4604 state = intel_encoder_hotplug(encoder, connector);
4605
4606 if (!intel_tc_port_link_reset(dig_port)) {
4607 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
4608 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
4609 ret = intel_hdmi_reset_link(encoder, &ctx);
4610 drm_WARN_ON(encoder->base.dev, ret);
4611 } else {
4612 intel_dp_check_link_state(intel_dp);
4613 }
4614 }
4615
4616 /*
4617 * Unpowered type-c dongles can take some time to boot and be
4618 * responsible, so here giving some time to those dongles to power up
4619 * and then retrying the probe.
4620 *
4621 * On many platforms the HDMI live state signal is known to be
4622 * unreliable, so we can't use it to detect if a sink is connected or
4623 * not. Instead we detect if it's connected based on whether we can
4624 * read the EDID or not. That in turn has a problem during disconnect,
4625 * since the HPD interrupt may be raised before the DDC lines get
4626 * disconnected (due to how the required length of DDC vs. HPD
4627 * connector pins are specified) and so we'll still be able to get a
4628 * valid EDID. To solve this schedule another detection cycle if this
4629 * time around we didn't detect any change in the sink's connection
4630 * status.
4631 *
4632 * Type-c connectors which get their HPD signal deasserted then
4633 * reasserted, without unplugging/replugging the sink from the
4634 * connector, introduce a delay until the AUX channel communication
4635 * becomes functional. Retry the detection for 5 seconds on type-c
4636 * connectors to account for this delay.
4637 */
4638 if (state == INTEL_HOTPLUG_UNCHANGED &&
4639 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4640 !dig_port->dp.is_mst)
4641 state = INTEL_HOTPLUG_RETRY;
4642
4643 return state;
4644}
4645
4646static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4647{
4648 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4649 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
4650
4651 return intel_de_read(dev_priv, SDEISR) & bit;
4652}
4653
4654static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4655{
4656 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4657 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4658
4659 return intel_de_read(dev_priv, DEISR) & bit;
4660}
4661
4662static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4663{
4664 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4665 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4666
4667 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4668}
4669
4670static struct intel_connector *
4671intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4672{
4673 struct intel_connector *connector;
4674 enum port port = dig_port->base.port;
4675
4676 connector = intel_connector_alloc();
4677 if (!connector)
4678 return NULL;
4679
4680 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4681 intel_hdmi_init_connector(dig_port, connector);
4682
4683 return connector;
4684}
4685
4686static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4687{
4688 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4689
4690 if (dig_port->base.port != PORT_A)
4691 return false;
4692
4693 if (dig_port->saved_port_bits & DDI_A_4_LANES)
4694 return false;
4695
4696 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4697 * supported configuration
4698 */
4699 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4700 return true;
4701
4702 return false;
4703}
4704
4705static int
4706intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4707{
4708 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4709 enum port port = dig_port->base.port;
4710 int max_lanes = 4;
4711
4712 if (DISPLAY_VER(dev_priv) >= 11)
4713 return max_lanes;
4714
4715 if (port == PORT_A || port == PORT_E) {
4716 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4717 max_lanes = port == PORT_A ? 4 : 0;
4718 else
4719 /* Both A and E share 2 lanes */
4720 max_lanes = 2;
4721 }
4722
4723 /*
4724 * Some BIOS might fail to set this bit on port A if eDP
4725 * wasn't lit up at boot. Force this bit set when needed
4726 * so we use the proper lane count for our calculations.
4727 */
4728 if (intel_ddi_a_force_4_lanes(dig_port)) {
4729 drm_dbg_kms(&dev_priv->drm,
4730 "Forcing DDI_A_4_LANES for port A\n");
4731 dig_port->saved_port_bits |= DDI_A_4_LANES;
4732 max_lanes = 4;
4733 }
4734
4735 return max_lanes;
4736}
4737
4738static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4739 enum port port)
4740{
4741 if (port >= PORT_D_XELPD)
4742 return HPD_PORT_D + port - PORT_D_XELPD;
4743 else if (port >= PORT_TC1)
4744 return HPD_PORT_TC1 + port - PORT_TC1;
4745 else
4746 return HPD_PORT_A + port - PORT_A;
4747}
4748
4749static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4750 enum port port)
4751{
4752 if (port >= PORT_TC1)
4753 return HPD_PORT_C + port - PORT_TC1;
4754 else
4755 return HPD_PORT_A + port - PORT_A;
4756}
4757
4758static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4759 enum port port)
4760{
4761 if (port >= PORT_TC1)
4762 return HPD_PORT_TC1 + port - PORT_TC1;
4763 else
4764 return HPD_PORT_A + port - PORT_A;
4765}
4766
4767static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4768 enum port port)
4769{
4770 if (HAS_PCH_TGP(dev_priv))
4771 return tgl_hpd_pin(dev_priv, port);
4772
4773 if (port >= PORT_TC1)
4774 return HPD_PORT_C + port - PORT_TC1;
4775 else
4776 return HPD_PORT_A + port - PORT_A;
4777}
4778
4779static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4780 enum port port)
4781{
4782 if (port >= PORT_C)
4783 return HPD_PORT_TC1 + port - PORT_C;
4784 else
4785 return HPD_PORT_A + port - PORT_A;
4786}
4787
4788static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4789 enum port port)
4790{
4791 if (port == PORT_D)
4792 return HPD_PORT_A;
4793
4794 if (HAS_PCH_TGP(dev_priv))
4795 return icl_hpd_pin(dev_priv, port);
4796
4797 return HPD_PORT_A + port - PORT_A;
4798}
4799
4800static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4801{
4802 if (HAS_PCH_TGP(dev_priv))
4803 return icl_hpd_pin(dev_priv, port);
4804
4805 return HPD_PORT_A + port - PORT_A;
4806}
4807
4808static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4809{
4810 if (DISPLAY_VER(i915) >= 12)
4811 return port >= PORT_TC1;
4812 else if (DISPLAY_VER(i915) >= 11)
4813 return port >= PORT_C;
4814 else
4815 return false;
4816}
4817
4818static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4819{
4820 intel_dp_encoder_suspend(encoder);
4821}
4822
4823static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
4824{
4825 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4826 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4827
4828 /*
4829 * TODO: Move this to intel_dp_encoder_suspend(),
4830 * once modeset locking around that is removed.
4831 */
4832 intel_encoder_link_check_flush_work(encoder);
4833 intel_tc_port_suspend(dig_port);
4834}
4835
4836static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4837{
4838 intel_dp_encoder_shutdown(encoder);
4839 intel_hdmi_encoder_shutdown(encoder);
4840}
4841
4842static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
4843{
4844 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4845 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4846
4847 intel_tc_port_cleanup(dig_port);
4848}
4849
4850#define port_tc_name(port) ((port) - PORT_TC1 + '1')
4851#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4852
4853static bool port_strap_detected(struct drm_i915_private *i915, enum port port)
4854{
4855 /* straps not used on skl+ */
4856 if (DISPLAY_VER(i915) >= 9)
4857 return true;
4858
4859 switch (port) {
4860 case PORT_A:
4861 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
4862 case PORT_B:
4863 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
4864 case PORT_C:
4865 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
4866 case PORT_D:
4867 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
4868 case PORT_E:
4869 return true; /* no strap for DDI-E */
4870 default:
4871 MISSING_CASE(port);
4872 return false;
4873 }
4874}
4875
4876static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
4877{
4878 return init_dp || intel_encoder_is_tc(encoder);
4879}
4880
4881static bool assert_has_icl_dsi(struct drm_i915_private *i915)
4882{
4883 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) &&
4884 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11,
4885 "Platform does not support DSI\n");
4886}
4887
4888static bool port_in_use(struct drm_i915_private *i915, enum port port)
4889{
4890 struct intel_encoder *encoder;
4891
4892 for_each_intel_encoder(&i915->drm, encoder) {
4893 /* FIXME what about second port for dual link DSI? */
4894 if (encoder->port == port)
4895 return true;
4896 }
4897
4898 return false;
4899}
4900
4901void intel_ddi_init(struct intel_display *display,
4902 const struct intel_bios_encoder_data *devdata)
4903{
4904 struct drm_i915_private *dev_priv = to_i915(display->drm);
4905 struct intel_digital_port *dig_port;
4906 struct intel_encoder *encoder;
4907 bool init_hdmi, init_dp;
4908 enum port port;
4909 enum phy phy;
4910
4911 port = intel_bios_encoder_port(devdata);
4912 if (port == PORT_NONE)
4913 return;
4914
4915 if (!port_strap_detected(dev_priv, port)) {
4916 drm_dbg_kms(&dev_priv->drm,
4917 "Port %c strap not detected\n", port_name(port));
4918 return;
4919 }
4920
4921 if (!assert_port_valid(dev_priv, port))
4922 return;
4923
4924 if (port_in_use(dev_priv, port)) {
4925 drm_dbg_kms(&dev_priv->drm,
4926 "Port %c already claimed\n", port_name(port));
4927 return;
4928 }
4929
4930 if (intel_bios_encoder_supports_dsi(devdata)) {
4931 /* BXT/GLK handled elsewhere, for now at least */
4932 if (!assert_has_icl_dsi(dev_priv))
4933 return;
4934
4935 icl_dsi_init(display, devdata);
4936 return;
4937 }
4938
4939 phy = intel_port_to_phy(dev_priv, port);
4940
4941 /*
4942 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4943 * have taken over some of the PHYs and made them unavailable to the
4944 * driver. In that case we should skip initializing the corresponding
4945 * outputs.
4946 */
4947 if (intel_hti_uses_phy(display, phy)) {
4948 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4949 port_name(port), phy_name(phy));
4950 return;
4951 }
4952
4953 init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4954 intel_bios_encoder_supports_hdmi(devdata);
4955 init_dp = intel_bios_encoder_supports_dp(devdata);
4956
4957 if (intel_bios_encoder_is_lspcon(devdata)) {
4958 /*
4959 * Lspcon device needs to be driven with DP connector
4960 * with special detection sequence. So make sure DP
4961 * is initialized before lspcon.
4962 */
4963 init_dp = true;
4964 init_hdmi = false;
4965 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4966 port_name(port));
4967 }
4968
4969 if (!init_dp && !init_hdmi) {
4970 drm_dbg_kms(&dev_priv->drm,
4971 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4972 port_name(port));
4973 return;
4974 }
4975
4976 if (intel_phy_is_snps(dev_priv, phy) &&
4977 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
4978 drm_dbg_kms(&dev_priv->drm,
4979 "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4980 phy_name(phy));
4981 }
4982
4983 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4984 if (!dig_port)
4985 return;
4986
4987 dig_port->aux_ch = AUX_CH_NONE;
4988
4989 encoder = &dig_port->base;
4990 encoder->devdata = devdata;
4991
4992 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4993 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4994 DRM_MODE_ENCODER_TMDS,
4995 "DDI %c/PHY %c",
4996 port_name(port - PORT_D_XELPD + PORT_D),
4997 phy_name(phy));
4998 } else if (DISPLAY_VER(dev_priv) >= 12) {
4999 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5000
5001 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5002 DRM_MODE_ENCODER_TMDS,
5003 "DDI %s%c/PHY %s%c",
5004 port >= PORT_TC1 ? "TC" : "",
5005 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5006 tc_port != TC_PORT_NONE ? "TC" : "",
5007 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5008 } else if (DISPLAY_VER(dev_priv) >= 11) {
5009 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5010
5011 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5012 DRM_MODE_ENCODER_TMDS,
5013 "DDI %c%s/PHY %s%c",
5014 port_name(port),
5015 port >= PORT_C ? " (TC)" : "",
5016 tc_port != TC_PORT_NONE ? "TC" : "",
5017 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5018 } else {
5019 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5020 DRM_MODE_ENCODER_TMDS,
5021 "DDI %c/PHY %c", port_name(port), phy_name(phy));
5022 }
5023
5024 intel_encoder_link_check_init(encoder, intel_ddi_link_check);
5025
5026 mutex_init(&dig_port->hdcp_mutex);
5027 dig_port->num_hdcp_streams = 0;
5028
5029 encoder->hotplug = intel_ddi_hotplug;
5030 encoder->compute_output_type = intel_ddi_compute_output_type;
5031 encoder->compute_config = intel_ddi_compute_config;
5032 encoder->compute_config_late = intel_ddi_compute_config_late;
5033 encoder->enable = intel_enable_ddi;
5034 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5035 encoder->pre_enable = intel_ddi_pre_enable;
5036 encoder->disable = intel_disable_ddi;
5037 encoder->post_pll_disable = intel_ddi_post_pll_disable;
5038 encoder->post_disable = intel_ddi_post_disable;
5039 encoder->update_pipe = intel_ddi_update_pipe;
5040 encoder->audio_enable = intel_audio_codec_enable;
5041 encoder->audio_disable = intel_audio_codec_disable;
5042 encoder->get_hw_state = intel_ddi_get_hw_state;
5043 encoder->sync_state = intel_ddi_sync_state;
5044 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5045 encoder->suspend = intel_ddi_encoder_suspend;
5046 encoder->shutdown = intel_ddi_encoder_shutdown;
5047 encoder->get_power_domains = intel_ddi_get_power_domains;
5048
5049 encoder->type = INTEL_OUTPUT_DDI;
5050 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
5051 encoder->port = port;
5052 encoder->cloneable = 0;
5053 encoder->pipe_mask = ~0;
5054
5055 if (DISPLAY_VER(dev_priv) >= 14) {
5056 encoder->enable_clock = intel_mtl_pll_enable;
5057 encoder->disable_clock = intel_mtl_pll_disable;
5058 encoder->port_pll_type = intel_mtl_port_pll_type;
5059 encoder->get_config = mtl_ddi_get_config;
5060 } else if (IS_DG2(dev_priv)) {
5061 encoder->enable_clock = intel_mpllb_enable;
5062 encoder->disable_clock = intel_mpllb_disable;
5063 encoder->get_config = dg2_ddi_get_config;
5064 } else if (IS_ALDERLAKE_S(dev_priv)) {
5065 encoder->enable_clock = adls_ddi_enable_clock;
5066 encoder->disable_clock = adls_ddi_disable_clock;
5067 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
5068 encoder->get_config = adls_ddi_get_config;
5069 } else if (IS_ROCKETLAKE(dev_priv)) {
5070 encoder->enable_clock = rkl_ddi_enable_clock;
5071 encoder->disable_clock = rkl_ddi_disable_clock;
5072 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
5073 encoder->get_config = rkl_ddi_get_config;
5074 } else if (IS_DG1(dev_priv)) {
5075 encoder->enable_clock = dg1_ddi_enable_clock;
5076 encoder->disable_clock = dg1_ddi_disable_clock;
5077 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
5078 encoder->get_config = dg1_ddi_get_config;
5079 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
5080 if (intel_ddi_is_tc(dev_priv, port)) {
5081 encoder->enable_clock = jsl_ddi_tc_enable_clock;
5082 encoder->disable_clock = jsl_ddi_tc_disable_clock;
5083 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
5084 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5085 encoder->get_config = icl_ddi_combo_get_config;
5086 } else {
5087 encoder->enable_clock = icl_ddi_combo_enable_clock;
5088 encoder->disable_clock = icl_ddi_combo_disable_clock;
5089 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5090 encoder->get_config = icl_ddi_combo_get_config;
5091 }
5092 } else if (DISPLAY_VER(dev_priv) >= 11) {
5093 if (intel_ddi_is_tc(dev_priv, port)) {
5094 encoder->enable_clock = icl_ddi_tc_enable_clock;
5095 encoder->disable_clock = icl_ddi_tc_disable_clock;
5096 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
5097 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5098 encoder->get_config = icl_ddi_tc_get_config;
5099 } else {
5100 encoder->enable_clock = icl_ddi_combo_enable_clock;
5101 encoder->disable_clock = icl_ddi_combo_disable_clock;
5102 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5103 encoder->get_config = icl_ddi_combo_get_config;
5104 }
5105 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
5106 /* BXT/GLK have fixed PLL->port mapping */
5107 encoder->get_config = bxt_ddi_get_config;
5108 } else if (DISPLAY_VER(dev_priv) == 9) {
5109 encoder->enable_clock = skl_ddi_enable_clock;
5110 encoder->disable_clock = skl_ddi_disable_clock;
5111 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
5112 encoder->get_config = skl_ddi_get_config;
5113 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
5114 encoder->enable_clock = hsw_ddi_enable_clock;
5115 encoder->disable_clock = hsw_ddi_disable_clock;
5116 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
5117 encoder->get_config = hsw_ddi_get_config;
5118 }
5119
5120 if (DISPLAY_VER(dev_priv) >= 14) {
5121 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
5122 } else if (IS_DG2(dev_priv)) {
5123 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
5124 } else if (DISPLAY_VER(dev_priv) >= 12) {
5125 if (intel_encoder_is_combo(encoder))
5126 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5127 else
5128 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
5129 } else if (DISPLAY_VER(dev_priv) >= 11) {
5130 if (intel_encoder_is_combo(encoder))
5131 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5132 else
5133 encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
5134 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
5135 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;
5136 } else {
5137 encoder->set_signal_levels = hsw_set_signal_levels;
5138 }
5139
5140 intel_ddi_buf_trans_init(encoder);
5141
5142 if (DISPLAY_VER(dev_priv) >= 13)
5143 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
5144 else if (IS_DG1(dev_priv))
5145 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
5146 else if (IS_ROCKETLAKE(dev_priv))
5147 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
5148 else if (DISPLAY_VER(dev_priv) >= 12)
5149 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
5150 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
5151 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
5152 else if (DISPLAY_VER(dev_priv) == 11)
5153 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
5154 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
5155 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
5156 else
5157 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
5158
5159 if (DISPLAY_VER(dev_priv) >= 11)
5160 dig_port->saved_port_bits =
5161 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5162 & DDI_BUF_PORT_REVERSAL;
5163 else
5164 dig_port->saved_port_bits =
5165 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5166 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5167
5168 if (intel_bios_encoder_lane_reversal(devdata))
5169 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
5170
5171 dig_port->dp.output_reg = INVALID_MMIO_REG;
5172 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5173
5174 if (need_aux_ch(encoder, init_dp)) {
5175 dig_port->aux_ch = intel_dp_aux_ch(encoder);
5176 if (dig_port->aux_ch == AUX_CH_NONE)
5177 goto err;
5178 }
5179
5180 if (intel_encoder_is_tc(encoder)) {
5181 bool is_legacy =
5182 !intel_bios_encoder_supports_typec_usb(devdata) &&
5183 !intel_bios_encoder_supports_tbt(devdata);
5184
5185 if (!is_legacy && init_hdmi) {
5186 is_legacy = !init_dp;
5187
5188 drm_dbg_kms(&dev_priv->drm,
5189 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
5190 port_name(port),
5191 str_yes_no(init_dp),
5192 is_legacy ? "legacy" : "non-legacy");
5193 }
5194
5195 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
5196 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
5197
5198 dig_port->lock = intel_tc_port_lock;
5199 dig_port->unlock = intel_tc_port_unlock;
5200
5201 if (intel_tc_port_init(dig_port, is_legacy) < 0)
5202 goto err;
5203 }
5204
5205 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5206 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
5207
5208 if (DISPLAY_VER(dev_priv) >= 11) {
5209 if (intel_encoder_is_tc(encoder))
5210 dig_port->connected = intel_tc_port_connected;
5211 else
5212 dig_port->connected = lpt_digital_port_connected;
5213 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
5214 dig_port->connected = bdw_digital_port_connected;
5215 } else if (DISPLAY_VER(dev_priv) == 9) {
5216 dig_port->connected = lpt_digital_port_connected;
5217 } else if (IS_BROADWELL(dev_priv)) {
5218 if (port == PORT_A)
5219 dig_port->connected = bdw_digital_port_connected;
5220 else
5221 dig_port->connected = lpt_digital_port_connected;
5222 } else if (IS_HASWELL(dev_priv)) {
5223 if (port == PORT_A)
5224 dig_port->connected = hsw_digital_port_connected;
5225 else
5226 dig_port->connected = lpt_digital_port_connected;
5227 }
5228
5229 intel_infoframe_init(dig_port);
5230
5231 if (init_dp) {
5232 if (!intel_ddi_init_dp_connector(dig_port))
5233 goto err;
5234
5235 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5236
5237 if (dig_port->dp.mso_link_count)
5238 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
5239 }
5240
5241 /*
5242 * In theory we don't need the encoder->type check,
5243 * but leave it just in case we have some really bad VBTs...
5244 */
5245 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5246 if (!intel_ddi_init_hdmi_connector(dig_port))
5247 goto err;
5248 }
5249
5250 return;
5251
5252err:
5253 drm_encoder_cleanup(&encoder->base);
5254 kfree(dig_port);
5255}