Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2024, Intel Corporation.
4 */
5
6#include <linux/debugfs.h>
7
8#include "intel_alpm.h"
9#include "intel_crtc.h"
10#include "intel_de.h"
11#include "intel_display_types.h"
12#include "intel_dp.h"
13#include "intel_dp_aux.h"
14#include "intel_psr_regs.h"
15
16bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
17{
18 return intel_dp->alpm_dpcd & DP_ALPM_CAP;
19}
20
21bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
22{
23 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
24}
25
26void intel_alpm_init_dpcd(struct intel_dp *intel_dp)
27{
28 u8 dpcd;
29
30 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
31 return;
32
33 intel_dp->alpm_dpcd = dpcd;
34}
35
36/*
37 * See Bspec: 71632 for the table
38 *
39 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)
40 *
41 * Half cycle duration:
42 *
43 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
44 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
45 *
46 * Link rates 5.4 - 8.1
47 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
48 * LFPS Period chosen is the mid-point of the min:max values from the table
49 * FLOOR( LFPS Period in Symbol clocks /
50 * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )
51 */
52static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate,
53 int *silence_period,
54 int *lfps_half_cycle)
55{
56 switch (link_rate) {
57 case 162000:
58 *silence_period = 20;
59 *lfps_half_cycle = 5;
60 break;
61 case 216000:
62 *silence_period = 27;
63 *lfps_half_cycle = 7;
64 break;
65 case 243000:
66 *silence_period = 31;
67 *lfps_half_cycle = 8;
68 break;
69 case 270000:
70 *silence_period = 34;
71 *lfps_half_cycle = 9;
72 break;
73 case 324000:
74 *silence_period = 41;
75 *lfps_half_cycle = 11;
76 break;
77 case 432000:
78 *silence_period = 56;
79 *lfps_half_cycle = 15;
80 break;
81 case 540000:
82 *silence_period = 69;
83 *lfps_half_cycle = 12;
84 break;
85 case 648000:
86 *silence_period = 84;
87 *lfps_half_cycle = 15;
88 break;
89 case 675000:
90 *silence_period = 87;
91 *lfps_half_cycle = 15;
92 break;
93 case 810000:
94 *silence_period = 104;
95 *lfps_half_cycle = 19;
96 break;
97 default:
98 *silence_period = *lfps_half_cycle = -1;
99 return false;
100 }
101 return true;
102}
103
104/*
105 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
106 * tSilence, Max+ tPHY Establishment + tCDS) / tline)
107 * For the "PHY P2 to P0" latency see the PHY Power Control page
108 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965
109 * : 12 us
110 * The tLFPS_Period, Max term is 800ns
111 * The tSilence, Max term is 180ns
112 * The tPHY Establishment (a.k.a. t1) term is 50us
113 * The tCDS term is 1 or 2 times t2
114 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
115 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
116 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
117 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
118 * within the CDS period complete within the CDS period regardless of
119 * entry into the period
120 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
121 * TPS4 Length = 252 Symbols
122 */
123static int _lnl_compute_aux_less_wake_time(int port_clock)
124{
125 int tphy2_p2_to_p0 = 12 * 1000;
126 int tlfps_period_max = 800;
127 int tsilence_max = 180;
128 int t1 = 50 * 1000;
129 int tps4 = 252;
130 /* port_clock is link rate in 10kbit/s units */
131 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock;
132 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
133 int t2 = num_ml_phy_lock * tml_phy_lock;
134 int tcds = 1 * t2;
135
136 return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max +
137 t1 + tcds, 1000);
138}
139
140static int
141_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
142 const struct intel_crtc_state *crtc_state)
143{
144 struct intel_display *display = to_intel_display(intel_dp);
145 int aux_less_wake_time, aux_less_wake_lines, silence_period,
146 lfps_half_cycle;
147
148 aux_less_wake_time =
149 _lnl_compute_aux_less_wake_time(crtc_state->port_clock);
150 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
151 aux_less_wake_time);
152
153 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock,
154 &silence_period,
155 &lfps_half_cycle))
156 return false;
157
158 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
159 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
160 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
161 return false;
162
163 if (display->params.psr_safest_params)
164 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
165
166 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
167 intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;
168 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
169
170 return true;
171}
172
173static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
174 const struct intel_crtc_state *crtc_state)
175{
176 struct intel_display *display = to_intel_display(intel_dp);
177 int check_entry_lines;
178
179 if (DISPLAY_VER(display) < 20)
180 return true;
181
182 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
183 check_entry_lines = 2 +
184 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5);
185
186 if (check_entry_lines > 15)
187 return false;
188
189 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
190 return false;
191
192 if (display->params.psr_safest_params)
193 check_entry_lines = 15;
194
195 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
196
197 return true;
198}
199
200/*
201 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There
202 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are
203 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.
204 */
205static int skl_io_buffer_wake_time(void)
206{
207 return 18;
208}
209
210static int tgl_io_buffer_wake_time(void)
211{
212 return 10;
213}
214
215static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
216{
217 struct intel_display *display = to_intel_display(crtc_state);
218
219 if (DISPLAY_VER(display) >= 12)
220 return tgl_io_buffer_wake_time();
221 else
222 return skl_io_buffer_wake_time();
223}
224
225bool intel_alpm_compute_params(struct intel_dp *intel_dp,
226 const struct intel_crtc_state *crtc_state)
227{
228 struct intel_display *display = to_intel_display(intel_dp);
229 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
230 int tfw_exit_latency = 20; /* eDP spec */
231 int phy_wake = 4; /* eDP spec */
232 int preamble = 8; /* eDP spec */
233 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
234 u8 max_wake_lines;
235
236 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
237 preamble + phy_wake + tfw_exit_latency;
238 fast_wake_time = precharge + preamble + phy_wake +
239 tfw_exit_latency;
240
241 if (DISPLAY_VER(display) >= 20)
242 max_wake_lines = 68;
243 else if (DISPLAY_VER(display) >= 12)
244 max_wake_lines = 12;
245 else
246 max_wake_lines = 8;
247
248 io_wake_lines = intel_usecs_to_scanlines(
249 &crtc_state->hw.adjusted_mode, io_wake_time);
250 fast_wake_lines = intel_usecs_to_scanlines(
251 &crtc_state->hw.adjusted_mode, fast_wake_time);
252
253 if (io_wake_lines > max_wake_lines ||
254 fast_wake_lines > max_wake_lines)
255 return false;
256
257 if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
258 return false;
259
260 if (display->params.psr_safest_params)
261 io_wake_lines = fast_wake_lines = max_wake_lines;
262
263 /* According to Bspec lower limit should be set as 7 lines. */
264 intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
265 intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
266
267 return true;
268}
269
270void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
271 struct intel_crtc_state *crtc_state,
272 struct drm_connector_state *conn_state)
273{
274 struct intel_display *display = to_intel_display(intel_dp);
275 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
276 int waketime_in_lines, first_sdp_position;
277 int context_latency, guardband;
278
279 if (!intel_dp_is_edp(intel_dp))
280 return;
281
282 if (DISPLAY_VER(display) < 20)
283 return;
284
285 if (!intel_dp->as_sdp_supported)
286 return;
287
288 if (crtc_state->has_psr)
289 return;
290
291 if (!(intel_alpm_aux_wake_supported(intel_dp) ||
292 intel_alpm_aux_less_wake_supported(intel_dp)))
293 return;
294
295 if (!intel_alpm_compute_params(intel_dp, crtc_state))
296 return;
297
298 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
299 guardband = adjusted_mode->crtc_vtotal -
300 adjusted_mode->crtc_vdisplay - context_latency;
301 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
302 if (intel_alpm_aux_less_wake_supported(intel_dp))
303 waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
304 else
305 waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines;
306
307 crtc_state->has_lobf = (context_latency + guardband) >
308 (first_sdp_position + waketime_in_lines);
309}
310
311static void lnl_alpm_configure(struct intel_dp *intel_dp,
312 const struct intel_crtc_state *crtc_state)
313{
314 struct intel_display *display = to_intel_display(intel_dp);
315 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
316 enum port port = dp_to_dig_port(intel_dp)->base.port;
317 u32 alpm_ctl;
318
319 if (DISPLAY_VER(display) < 20 ||
320 (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp)))
321 return;
322
323 /*
324 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
325 * check panel support at this point.
326 */
327 if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) ||
328 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) {
329 alpm_ctl = ALPM_CTL_ALPM_ENABLE |
330 ALPM_CTL_ALPM_AUX_LESS_ENABLE |
331 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
332 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
333
334 intel_de_write(display,
335 PORT_ALPM_CTL(port),
336 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
337 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
338 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
339 PORT_ALPM_CTL_SILENCE_PERIOD(
340 intel_dp->alpm_parameters.silence_period_sym_clocks));
341
342 intel_de_write(display,
343 PORT_ALPM_LFPS_CTL(port),
344 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
345 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
346 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
347 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
348 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
349 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
350 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));
351 } else {
352 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
353 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
354 }
355
356 if (crtc_state->has_lobf)
357 alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
358
359 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
360
361 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
362}
363
364void intel_alpm_configure(struct intel_dp *intel_dp,
365 const struct intel_crtc_state *crtc_state)
366{
367 lnl_alpm_configure(intel_dp, crtc_state);
368}
369
370static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
371{
372 struct intel_connector *connector = m->private;
373 struct intel_display *display = to_intel_display(connector);
374 struct drm_crtc *crtc;
375 struct intel_crtc_state *crtc_state;
376 enum transcoder cpu_transcoder;
377 u32 alpm_ctl;
378 int ret;
379
380 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
381 if (ret)
382 return ret;
383
384 crtc = connector->base.state->crtc;
385 if (connector->base.status != connector_status_connected || !crtc) {
386 ret = -ENODEV;
387 goto out;
388 }
389
390 crtc_state = to_intel_crtc_state(crtc->state);
391 cpu_transcoder = crtc_state->cpu_transcoder;
392 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
393 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));
394 seq_printf(m, "Aux-wake alpm status: %s\n",
395 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
396 seq_printf(m, "Aux-less alpm status: %s\n",
397 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));
398out:
399 drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
400
401 return ret;
402}
403
404DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
405
406void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
407{
408 struct intel_display *display = to_intel_display(connector);
409 struct dentry *root = connector->base.debugfs_entry;
410
411 if (DISPLAY_VER(display) < 20 ||
412 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
413 return;
414
415 debugfs_create_file("i915_edp_lobf_info", 0444, root,
416 connector, &i915_edp_lobf_info_fops);
417}