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1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/backlight.h>
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/i2c.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/string_helpers.h>
33#include <linux/dynamic_debug.h>
34
35#include <drm/display/drm_dp_helper.h>
36#include <drm/display/drm_dp_mst_helper.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_fixed.h>
39#include <drm/drm_print.h>
40#include <drm/drm_vblank.h>
41#include <drm/drm_panel.h>
42
43#include "drm_dp_helper_internal.h"
44
45DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
46 "DRM_UT_CORE",
47 "DRM_UT_DRIVER",
48 "DRM_UT_KMS",
49 "DRM_UT_PRIME",
50 "DRM_UT_ATOMIC",
51 "DRM_UT_VBL",
52 "DRM_UT_STATE",
53 "DRM_UT_LEASE",
54 "DRM_UT_DP",
55 "DRM_UT_DRMRES");
56
57struct dp_aux_backlight {
58 struct backlight_device *base;
59 struct drm_dp_aux *aux;
60 struct drm_edp_backlight_info info;
61 bool enabled;
62};
63
64/**
65 * DOC: dp helpers
66 *
67 * These functions contain some common logic and helpers at various abstraction
68 * levels to deal with Display Port sink devices and related things like DP aux
69 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
70 * blocks, ...
71 */
72
73/* Helpers for DP link training */
74static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
75{
76 return link_status[r - DP_LANE0_1_STATUS];
77}
78
79static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
80 int lane)
81{
82 int i = DP_LANE0_1_STATUS + (lane >> 1);
83 int s = (lane & 1) * 4;
84 u8 l = dp_link_status(link_status, i);
85
86 return (l >> s) & 0xf;
87}
88
89bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
90 int lane_count)
91{
92 u8 lane_align;
93 u8 lane_status;
94 int lane;
95
96 lane_align = dp_link_status(link_status,
97 DP_LANE_ALIGN_STATUS_UPDATED);
98 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
99 return false;
100 for (lane = 0; lane < lane_count; lane++) {
101 lane_status = dp_get_lane_status(link_status, lane);
102 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
103 return false;
104 }
105 return true;
106}
107EXPORT_SYMBOL(drm_dp_channel_eq_ok);
108
109bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
110 int lane_count)
111{
112 int lane;
113 u8 lane_status;
114
115 for (lane = 0; lane < lane_count; lane++) {
116 lane_status = dp_get_lane_status(link_status, lane);
117 if ((lane_status & DP_LANE_CR_DONE) == 0)
118 return false;
119 }
120 return true;
121}
122EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
123
124u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
125 int lane)
126{
127 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
128 int s = ((lane & 1) ?
129 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
130 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
131 u8 l = dp_link_status(link_status, i);
132
133 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
134}
135EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
136
137u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
138 int lane)
139{
140 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
141 int s = ((lane & 1) ?
142 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
143 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
144 u8 l = dp_link_status(link_status, i);
145
146 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
147}
148EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
149
150/* DP 2.0 128b/132b */
151u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
152 int lane)
153{
154 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
155 int s = ((lane & 1) ?
156 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
157 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
158 u8 l = dp_link_status(link_status, i);
159
160 return (l >> s) & 0xf;
161}
162EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
163
164/* DP 2.0 errata for 128b/132b */
165bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
166 int lane_count)
167{
168 u8 lane_align, lane_status;
169 int lane;
170
171 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
172 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
173 return false;
174
175 for (lane = 0; lane < lane_count; lane++) {
176 lane_status = dp_get_lane_status(link_status, lane);
177 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
178 return false;
179 }
180 return true;
181}
182EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
183
184/* DP 2.0 errata for 128b/132b */
185bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
186 int lane_count)
187{
188 u8 lane_status;
189 int lane;
190
191 for (lane = 0; lane < lane_count; lane++) {
192 lane_status = dp_get_lane_status(link_status, lane);
193 if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
194 return false;
195 }
196 return true;
197}
198EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
199
200/* DP 2.0 errata for 128b/132b */
201bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
202{
203 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
204
205 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
206}
207EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
208
209/* DP 2.0 errata for 128b/132b */
210bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
211{
212 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
213
214 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
215}
216EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
217
218/* DP 2.0 errata for 128b/132b */
219bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
220{
221 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
222
223 return status & DP_128B132B_LT_FAILED;
224}
225EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
226
227static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
228{
229 if (rd_interval > 4)
230 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
231 aux->name, rd_interval);
232
233 if (rd_interval == 0)
234 return 100;
235
236 return rd_interval * 4 * USEC_PER_MSEC;
237}
238
239static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
240{
241 if (rd_interval > 4)
242 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
243 aux->name, rd_interval);
244
245 if (rd_interval == 0)
246 return 400;
247
248 return rd_interval * 4 * USEC_PER_MSEC;
249}
250
251static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
252{
253 switch (rd_interval) {
254 default:
255 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
256 aux->name, rd_interval);
257 fallthrough;
258 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
259 return 400;
260 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
261 return 4000;
262 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
263 return 8000;
264 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
265 return 12000;
266 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
267 return 16000;
268 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
269 return 32000;
270 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
271 return 64000;
272 }
273}
274
275/*
276 * The link training delays are different for:
277 *
278 * - Clock recovery vs. channel equalization
279 * - DPRX vs. LTTPR
280 * - 128b/132b vs. 8b/10b
281 * - DPCD rev 1.3 vs. later
282 *
283 * Get the correct delay in us, reading DPCD if necessary.
284 */
285static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
286 enum drm_dp_phy dp_phy, bool uhbr, bool cr)
287{
288 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
289 unsigned int offset;
290 u8 rd_interval, mask;
291
292 if (dp_phy == DP_PHY_DPRX) {
293 if (uhbr) {
294 if (cr)
295 return 100;
296
297 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
298 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
299 parse = __128b132b_channel_eq_delay_us;
300 } else {
301 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
302 return 100;
303
304 offset = DP_TRAINING_AUX_RD_INTERVAL;
305 mask = DP_TRAINING_AUX_RD_MASK;
306 if (cr)
307 parse = __8b10b_clock_recovery_delay_us;
308 else
309 parse = __8b10b_channel_eq_delay_us;
310 }
311 } else {
312 if (uhbr) {
313 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
314 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
315 parse = __128b132b_channel_eq_delay_us;
316 } else {
317 if (cr)
318 return 100;
319
320 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
321 mask = DP_TRAINING_AUX_RD_MASK;
322 parse = __8b10b_channel_eq_delay_us;
323 }
324 }
325
326 if (offset < DP_RECEIVER_CAP_SIZE) {
327 rd_interval = dpcd[offset];
328 } else {
329 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
330 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
331 aux->name);
332 /* arbitrary default delay */
333 return 400;
334 }
335 }
336
337 return parse(aux, rd_interval & mask);
338}
339
340int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
341 enum drm_dp_phy dp_phy, bool uhbr)
342{
343 return __read_delay(aux, dpcd, dp_phy, uhbr, true);
344}
345EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
346
347int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
348 enum drm_dp_phy dp_phy, bool uhbr)
349{
350 return __read_delay(aux, dpcd, dp_phy, uhbr, false);
351}
352EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
353
354/* Per DP 2.0 Errata */
355int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
356{
357 int unit;
358 u8 val;
359
360 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {
361 drm_err(aux->drm_dev, "%s: failed rd interval read\n",
362 aux->name);
363 /* default to max */
364 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
365 }
366
367 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
368 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
369
370 return (val + 1) * unit * 1000;
371}
372EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
373
374void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
375 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
376{
377 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
378 DP_TRAINING_AUX_RD_MASK;
379 int delay_us;
380
381 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
382 delay_us = 100;
383 else
384 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
385
386 usleep_range(delay_us, delay_us * 2);
387}
388EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
389
390static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
391 u8 rd_interval)
392{
393 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
394
395 usleep_range(delay_us, delay_us * 2);
396}
397
398void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
399 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
400{
401 __drm_dp_link_train_channel_eq_delay(aux,
402 dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
403 DP_TRAINING_AUX_RD_MASK);
404}
405EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
406
407/**
408 * drm_dp_phy_name() - Get the name of the given DP PHY
409 * @dp_phy: The DP PHY identifier
410 *
411 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
412 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
413 * non-NULL and valid.
414 *
415 * Returns: Name of the DP PHY.
416 */
417const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
418{
419 static const char * const phy_names[] = {
420 [DP_PHY_DPRX] = "DPRX",
421 [DP_PHY_LTTPR1] = "LTTPR 1",
422 [DP_PHY_LTTPR2] = "LTTPR 2",
423 [DP_PHY_LTTPR3] = "LTTPR 3",
424 [DP_PHY_LTTPR4] = "LTTPR 4",
425 [DP_PHY_LTTPR5] = "LTTPR 5",
426 [DP_PHY_LTTPR6] = "LTTPR 6",
427 [DP_PHY_LTTPR7] = "LTTPR 7",
428 [DP_PHY_LTTPR8] = "LTTPR 8",
429 };
430
431 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
432 WARN_ON(!phy_names[dp_phy]))
433 return "<INVALID DP PHY>";
434
435 return phy_names[dp_phy];
436}
437EXPORT_SYMBOL(drm_dp_phy_name);
438
439void drm_dp_lttpr_link_train_clock_recovery_delay(void)
440{
441 usleep_range(100, 200);
442}
443EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
444
445static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
446{
447 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
448}
449
450void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
451 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
452{
453 u8 interval = dp_lttpr_phy_cap(phy_cap,
454 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
455 DP_TRAINING_AUX_RD_MASK;
456
457 __drm_dp_link_train_channel_eq_delay(aux, interval);
458}
459EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
460
461u8 drm_dp_link_rate_to_bw_code(int link_rate)
462{
463 switch (link_rate) {
464 case 1000000:
465 return DP_LINK_BW_10;
466 case 1350000:
467 return DP_LINK_BW_13_5;
468 case 2000000:
469 return DP_LINK_BW_20;
470 default:
471 /* Spec says link_bw = link_rate / 0.27Gbps */
472 return link_rate / 27000;
473 }
474}
475EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
476
477int drm_dp_bw_code_to_link_rate(u8 link_bw)
478{
479 switch (link_bw) {
480 case DP_LINK_BW_10:
481 return 1000000;
482 case DP_LINK_BW_13_5:
483 return 1350000;
484 case DP_LINK_BW_20:
485 return 2000000;
486 default:
487 /* Spec says link_rate = link_bw * 0.27Gbps */
488 return link_bw * 27000;
489 }
490}
491EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
492
493#define AUX_RETRY_INTERVAL 500 /* us */
494
495static inline void
496drm_dp_dump_access(const struct drm_dp_aux *aux,
497 u8 request, uint offset, void *buffer, int ret)
498{
499 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
500
501 if (ret > 0)
502 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
503 aux->name, offset, arrow, ret, min(ret, 20), buffer);
504 else
505 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
506 aux->name, offset, arrow, ret);
507}
508
509/**
510 * DOC: dp helpers
511 *
512 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
513 * independent access to AUX functionality. Drivers can take advantage of
514 * this by filling in the fields of the drm_dp_aux structure.
515 *
516 * Transactions are described using a hardware-independent drm_dp_aux_msg
517 * structure, which is passed into a driver's .transfer() implementation.
518 * Both native and I2C-over-AUX transactions are supported.
519 */
520
521static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
522 unsigned int offset, void *buffer, size_t size)
523{
524 struct drm_dp_aux_msg msg;
525 unsigned int retry, native_reply;
526 int err = 0, ret = 0;
527
528 memset(&msg, 0, sizeof(msg));
529 msg.address = offset;
530 msg.request = request;
531 msg.buffer = buffer;
532 msg.size = size;
533
534 mutex_lock(&aux->hw_mutex);
535
536 /*
537 * If the device attached to the aux bus is powered down then there's
538 * no reason to attempt a transfer. Error out immediately.
539 */
540 if (aux->powered_down) {
541 ret = -EBUSY;
542 goto unlock;
543 }
544
545 /*
546 * The specification doesn't give any recommendation on how often to
547 * retry native transactions. We used to retry 7 times like for
548 * aux i2c transactions but real world devices this wasn't
549 * sufficient, bump to 32 which makes Dell 4k monitors happier.
550 */
551 for (retry = 0; retry < 32; retry++) {
552 if (ret != 0 && ret != -ETIMEDOUT) {
553 usleep_range(AUX_RETRY_INTERVAL,
554 AUX_RETRY_INTERVAL + 100);
555 }
556
557 ret = aux->transfer(aux, &msg);
558 if (ret >= 0) {
559 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
560 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
561 if (ret == size)
562 goto unlock;
563
564 ret = -EPROTO;
565 } else
566 ret = -EIO;
567 }
568
569 /*
570 * We want the error we return to be the error we received on
571 * the first transaction, since we may get a different error the
572 * next time we retry
573 */
574 if (!err)
575 err = ret;
576 }
577
578 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
579 aux->name, err);
580 ret = err;
581
582unlock:
583 mutex_unlock(&aux->hw_mutex);
584 return ret;
585}
586
587/**
588 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
589 * @aux: DisplayPort AUX channel (SST)
590 * @offset: address of the register to probe
591 *
592 * Probe the provided DPCD address by reading 1 byte from it. The function can
593 * be used to trigger some side-effect the read access has, like waking up the
594 * sink, without the need for the read-out value.
595 *
596 * Returns 0 if the read access suceeded, or a negative error code on failure.
597 */
598int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
599{
600 u8 buffer;
601 int ret;
602
603 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1);
604 WARN_ON(ret == 0);
605
606 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret);
607
608 return ret < 0 ? ret : 0;
609}
610EXPORT_SYMBOL(drm_dp_dpcd_probe);
611
612/**
613 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered
614 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here
615 * and the function will be a no-op.
616 * @powered: true if powered; false if not
617 *
618 * If the endpoint device on the DP AUX bus is known to be powered down
619 * then this function can be called to make future transfers fail immediately
620 * instead of needing to time out.
621 *
622 * If this function is never called then a device defaults to being powered.
623 */
624void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
625{
626 if (!aux)
627 return;
628
629 mutex_lock(&aux->hw_mutex);
630 aux->powered_down = !powered;
631 mutex_unlock(&aux->hw_mutex);
632}
633EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
634
635/**
636 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
637 * @aux: DisplayPort AUX channel (SST or MST)
638 * @offset: address of the (first) register to read
639 * @buffer: buffer to store the register values
640 * @size: number of bytes in @buffer
641 *
642 * Returns the number of bytes transferred on success, or a negative error
643 * code on failure. -EIO is returned if the request was NAKed by the sink or
644 * if the retry count was exceeded. If not all bytes were transferred, this
645 * function returns -EPROTO. Errors from the underlying AUX channel transfer
646 * function, with the exception of -EBUSY (which causes the transaction to
647 * be retried), are propagated to the caller.
648 */
649ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
650 void *buffer, size_t size)
651{
652 int ret;
653
654 /*
655 * HP ZR24w corrupts the first DPCD access after entering power save
656 * mode. Eg. on a read, the entire buffer will be filled with the same
657 * byte. Do a throw away read to avoid corrupting anything we care
658 * about. Afterwards things will work correctly until the monitor
659 * gets woken up and subsequently re-enters power save mode.
660 *
661 * The user pressing any button on the monitor is enough to wake it
662 * up, so there is no particularly good place to do the workaround.
663 * We just have to do it before any DPCD access and hope that the
664 * monitor doesn't power down exactly after the throw away read.
665 */
666 if (!aux->is_remote) {
667 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
668 if (ret < 0)
669 return ret;
670 }
671
672 if (aux->is_remote)
673 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
674 else
675 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
676 buffer, size);
677
678 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
679 return ret;
680}
681EXPORT_SYMBOL(drm_dp_dpcd_read);
682
683/**
684 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
685 * @aux: DisplayPort AUX channel (SST or MST)
686 * @offset: address of the (first) register to write
687 * @buffer: buffer containing the values to write
688 * @size: number of bytes in @buffer
689 *
690 * Returns the number of bytes transferred on success, or a negative error
691 * code on failure. -EIO is returned if the request was NAKed by the sink or
692 * if the retry count was exceeded. If not all bytes were transferred, this
693 * function returns -EPROTO. Errors from the underlying AUX channel transfer
694 * function, with the exception of -EBUSY (which causes the transaction to
695 * be retried), are propagated to the caller.
696 */
697ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
698 void *buffer, size_t size)
699{
700 int ret;
701
702 if (aux->is_remote)
703 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
704 else
705 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
706 buffer, size);
707
708 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
709 return ret;
710}
711EXPORT_SYMBOL(drm_dp_dpcd_write);
712
713/**
714 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
715 * @aux: DisplayPort AUX channel
716 * @status: buffer to store the link status in (must be at least 6 bytes)
717 *
718 * Returns the number of bytes transferred on success or a negative error
719 * code on failure.
720 */
721int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
722 u8 status[DP_LINK_STATUS_SIZE])
723{
724 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
725 DP_LINK_STATUS_SIZE);
726}
727EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
728
729/**
730 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
731 * @aux: DisplayPort AUX channel
732 * @dp_phy: the DP PHY to get the link status for
733 * @link_status: buffer to return the status in
734 *
735 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
736 * layout of the returned @link_status matches the DPCD register layout of the
737 * DPRX PHY link status.
738 *
739 * Returns 0 if the information was read successfully or a negative error code
740 * on failure.
741 */
742int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
743 enum drm_dp_phy dp_phy,
744 u8 link_status[DP_LINK_STATUS_SIZE])
745{
746 int ret;
747
748 if (dp_phy == DP_PHY_DPRX) {
749 ret = drm_dp_dpcd_read(aux,
750 DP_LANE0_1_STATUS,
751 link_status,
752 DP_LINK_STATUS_SIZE);
753
754 if (ret < 0)
755 return ret;
756
757 WARN_ON(ret != DP_LINK_STATUS_SIZE);
758
759 return 0;
760 }
761
762 ret = drm_dp_dpcd_read(aux,
763 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
764 link_status,
765 DP_LINK_STATUS_SIZE - 1);
766
767 if (ret < 0)
768 return ret;
769
770 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
771
772 /* Convert the LTTPR to the sink PHY link status layout */
773 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
774 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
775 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
776 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
777
778 return 0;
779}
780EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
781
782static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
783{
784 /* FIXME: get rid of drm_edid_raw() */
785 const struct edid *edid = drm_edid_raw(drm_edid);
786
787 return edid && edid->revision >= 4 &&
788 edid->input & DRM_EDID_INPUT_DIGITAL &&
789 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
790}
791
792/**
793 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
794 * @dpcd: DisplayPort configuration data
795 * @port_cap: port capabilities
796 * @type: port type to be checked. Can be:
797 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
798 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
799 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
800 *
801 * Caveat: Only works with DPCD 1.1+ port caps.
802 *
803 * Returns: whether the downstream facing port matches the type.
804 */
805bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
806 const u8 port_cap[4], u8 type)
807{
808 return drm_dp_is_branch(dpcd) &&
809 dpcd[DP_DPCD_REV] >= 0x11 &&
810 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
811}
812EXPORT_SYMBOL(drm_dp_downstream_is_type);
813
814/**
815 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
816 * @dpcd: DisplayPort configuration data
817 * @port_cap: port capabilities
818 * @drm_edid: EDID
819 *
820 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
821 */
822bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
823 const u8 port_cap[4],
824 const struct drm_edid *drm_edid)
825{
826 if (dpcd[DP_DPCD_REV] < 0x11) {
827 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
828 case DP_DWN_STRM_PORT_TYPE_TMDS:
829 return true;
830 default:
831 return false;
832 }
833 }
834
835 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
836 case DP_DS_PORT_TYPE_DP_DUALMODE:
837 if (is_edid_digital_input_dp(drm_edid))
838 return false;
839 fallthrough;
840 case DP_DS_PORT_TYPE_DVI:
841 case DP_DS_PORT_TYPE_HDMI:
842 return true;
843 default:
844 return false;
845 }
846}
847EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
848
849/**
850 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
851 * @aux: DisplayPort AUX channel
852 * @real_edid_checksum: real edid checksum for the last block
853 *
854 * Returns:
855 * True on success
856 */
857bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
858 u8 real_edid_checksum)
859{
860 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
861
862 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
863 &auto_test_req, 1) < 1) {
864 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
865 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
866 return false;
867 }
868 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
869
870 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
871 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
872 aux->name, DP_TEST_REQUEST);
873 return false;
874 }
875 link_edid_read &= DP_TEST_LINK_EDID_READ;
876
877 if (!auto_test_req || !link_edid_read) {
878 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
879 aux->name);
880 return false;
881 }
882
883 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
884 &auto_test_req, 1) < 1) {
885 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
886 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
887 return false;
888 }
889
890 /* send back checksum for the last edid extension block data */
891 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
892 &real_edid_checksum, 1) < 1) {
893 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
894 aux->name, DP_TEST_EDID_CHECKSUM);
895 return false;
896 }
897
898 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
899 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
900 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
901 aux->name, DP_TEST_RESPONSE);
902 return false;
903 }
904
905 return true;
906}
907EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
908
909static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
910{
911 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
912
913 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
914 port_count = 4;
915
916 return port_count;
917}
918
919static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
920 u8 dpcd[DP_RECEIVER_CAP_SIZE])
921{
922 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
923 int ret;
924
925 /*
926 * Prior to DP1.3 the bit represented by
927 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
928 * If it is set DP_DPCD_REV at 0000h could be at a value less than
929 * the true capability of the panel. The only way to check is to
930 * then compare 0000h and 2200h.
931 */
932 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
933 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
934 return 0;
935
936 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
937 sizeof(dpcd_ext));
938 if (ret < 0)
939 return ret;
940 if (ret != sizeof(dpcd_ext))
941 return -EIO;
942
943 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
944 drm_dbg_kms(aux->drm_dev,
945 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
946 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
947 return 0;
948 }
949
950 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
951 return 0;
952
953 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
954
955 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
956
957 return 0;
958}
959
960/**
961 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
962 * available
963 * @aux: DisplayPort AUX channel
964 * @dpcd: Buffer to store the resulting DPCD in
965 *
966 * Attempts to read the base DPCD caps for @aux. Additionally, this function
967 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
968 * present.
969 *
970 * Returns: %0 if the DPCD was read successfully, negative error code
971 * otherwise.
972 */
973int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
974 u8 dpcd[DP_RECEIVER_CAP_SIZE])
975{
976 int ret;
977
978 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
979 if (ret < 0)
980 return ret;
981 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
982 return -EIO;
983
984 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
985 if (ret < 0)
986 return ret;
987
988 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
989
990 return ret;
991}
992EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
993
994/**
995 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
996 * @aux: DisplayPort AUX channel
997 * @dpcd: A cached copy of the port's DPCD
998 * @downstream_ports: buffer to store the downstream port info in
999 *
1000 * See also:
1001 * drm_dp_downstream_max_clock()
1002 * drm_dp_downstream_max_bpc()
1003 *
1004 * Returns: 0 if either the downstream port info was read successfully or
1005 * there was no downstream info to read, or a negative error code otherwise.
1006 */
1007int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1008 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1009 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
1010{
1011 int ret;
1012 u8 len;
1013
1014 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
1015
1016 /* No downstream info to read */
1017 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
1018 return 0;
1019
1020 /* Some branches advertise having 0 downstream ports, despite also advertising they have a
1021 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
1022 * some branches do it we need to handle it regardless.
1023 */
1024 len = drm_dp_downstream_port_count(dpcd);
1025 if (!len)
1026 return 0;
1027
1028 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
1029 len *= 4;
1030
1031 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
1032 if (ret < 0)
1033 return ret;
1034 if (ret != len)
1035 return -EIO;
1036
1037 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1038
1039 return 0;
1040}
1041EXPORT_SYMBOL(drm_dp_read_downstream_info);
1042
1043/**
1044 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1045 * @dpcd: DisplayPort configuration data
1046 * @port_cap: port capabilities
1047 *
1048 * Returns: Downstream facing port max dot clock in kHz on success,
1049 * or 0 if max clock not defined
1050 */
1051int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1052 const u8 port_cap[4])
1053{
1054 if (!drm_dp_is_branch(dpcd))
1055 return 0;
1056
1057 if (dpcd[DP_DPCD_REV] < 0x11)
1058 return 0;
1059
1060 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1061 case DP_DS_PORT_TYPE_VGA:
1062 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1063 return 0;
1064 return port_cap[1] * 8000;
1065 default:
1066 return 0;
1067 }
1068}
1069EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1070
1071/**
1072 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1073 * @dpcd: DisplayPort configuration data
1074 * @port_cap: port capabilities
1075 * @drm_edid: EDID
1076 *
1077 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1078 * or 0 if max TMDS clock not defined
1079 */
1080int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1081 const u8 port_cap[4],
1082 const struct drm_edid *drm_edid)
1083{
1084 if (!drm_dp_is_branch(dpcd))
1085 return 0;
1086
1087 if (dpcd[DP_DPCD_REV] < 0x11) {
1088 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1089 case DP_DWN_STRM_PORT_TYPE_TMDS:
1090 return 165000;
1091 default:
1092 return 0;
1093 }
1094 }
1095
1096 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1097 case DP_DS_PORT_TYPE_DP_DUALMODE:
1098 if (is_edid_digital_input_dp(drm_edid))
1099 return 0;
1100 /*
1101 * It's left up to the driver to check the
1102 * DP dual mode adapter's max TMDS clock.
1103 *
1104 * Unfortunately it looks like branch devices
1105 * may not fordward that the DP dual mode i2c
1106 * access so we just usually get i2c nak :(
1107 */
1108 fallthrough;
1109 case DP_DS_PORT_TYPE_HDMI:
1110 /*
1111 * We should perhaps assume 165 MHz when detailed cap
1112 * info is not available. But looks like many typical
1113 * branch devices fall into that category and so we'd
1114 * probably end up with users complaining that they can't
1115 * get high resolution modes with their favorite dongle.
1116 *
1117 * So let's limit to 300 MHz instead since DPCD 1.4
1118 * HDMI 2.0 DFPs are required to have the detailed cap
1119 * info. So it's more likely we're dealing with a HDMI 1.4
1120 * compatible* device here.
1121 */
1122 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1123 return 300000;
1124 return port_cap[1] * 2500;
1125 case DP_DS_PORT_TYPE_DVI:
1126 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1127 return 165000;
1128 /* FIXME what to do about DVI dual link? */
1129 return port_cap[1] * 2500;
1130 default:
1131 return 0;
1132 }
1133}
1134EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1135
1136/**
1137 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1138 * @dpcd: DisplayPort configuration data
1139 * @port_cap: port capabilities
1140 * @drm_edid: EDID
1141 *
1142 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1143 * or 0 if max TMDS clock not defined
1144 */
1145int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1146 const u8 port_cap[4],
1147 const struct drm_edid *drm_edid)
1148{
1149 if (!drm_dp_is_branch(dpcd))
1150 return 0;
1151
1152 if (dpcd[DP_DPCD_REV] < 0x11) {
1153 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1154 case DP_DWN_STRM_PORT_TYPE_TMDS:
1155 return 25000;
1156 default:
1157 return 0;
1158 }
1159 }
1160
1161 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1162 case DP_DS_PORT_TYPE_DP_DUALMODE:
1163 if (is_edid_digital_input_dp(drm_edid))
1164 return 0;
1165 fallthrough;
1166 case DP_DS_PORT_TYPE_DVI:
1167 case DP_DS_PORT_TYPE_HDMI:
1168 /*
1169 * Unclear whether the protocol converter could
1170 * utilize pixel replication. Assume it won't.
1171 */
1172 return 25000;
1173 default:
1174 return 0;
1175 }
1176}
1177EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1178
1179/**
1180 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1181 * bits per component
1182 * @dpcd: DisplayPort configuration data
1183 * @port_cap: downstream facing port capabilities
1184 * @drm_edid: EDID
1185 *
1186 * Returns: Max bpc on success or 0 if max bpc not defined
1187 */
1188int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1189 const u8 port_cap[4],
1190 const struct drm_edid *drm_edid)
1191{
1192 if (!drm_dp_is_branch(dpcd))
1193 return 0;
1194
1195 if (dpcd[DP_DPCD_REV] < 0x11) {
1196 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1197 case DP_DWN_STRM_PORT_TYPE_DP:
1198 return 0;
1199 default:
1200 return 8;
1201 }
1202 }
1203
1204 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1205 case DP_DS_PORT_TYPE_DP:
1206 return 0;
1207 case DP_DS_PORT_TYPE_DP_DUALMODE:
1208 if (is_edid_digital_input_dp(drm_edid))
1209 return 0;
1210 fallthrough;
1211 case DP_DS_PORT_TYPE_HDMI:
1212 case DP_DS_PORT_TYPE_DVI:
1213 case DP_DS_PORT_TYPE_VGA:
1214 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1215 return 8;
1216
1217 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1218 case DP_DS_8BPC:
1219 return 8;
1220 case DP_DS_10BPC:
1221 return 10;
1222 case DP_DS_12BPC:
1223 return 12;
1224 case DP_DS_16BPC:
1225 return 16;
1226 default:
1227 return 8;
1228 }
1229 break;
1230 default:
1231 return 8;
1232 }
1233}
1234EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1235
1236/**
1237 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1238 * YCbCr 4:2:0 pass-through capability
1239 * @dpcd: DisplayPort configuration data
1240 * @port_cap: downstream facing port capabilities
1241 *
1242 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1243 */
1244bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1245 const u8 port_cap[4])
1246{
1247 if (!drm_dp_is_branch(dpcd))
1248 return false;
1249
1250 if (dpcd[DP_DPCD_REV] < 0x13)
1251 return false;
1252
1253 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1254 case DP_DS_PORT_TYPE_DP:
1255 return true;
1256 case DP_DS_PORT_TYPE_HDMI:
1257 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1258 return false;
1259
1260 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1261 default:
1262 return false;
1263 }
1264}
1265EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1266
1267/**
1268 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1269 * YCbCr 4:4:4->4:2:0 conversion capability
1270 * @dpcd: DisplayPort configuration data
1271 * @port_cap: downstream facing port capabilities
1272 *
1273 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1274 */
1275bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1276 const u8 port_cap[4])
1277{
1278 if (!drm_dp_is_branch(dpcd))
1279 return false;
1280
1281 if (dpcd[DP_DPCD_REV] < 0x13)
1282 return false;
1283
1284 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1285 case DP_DS_PORT_TYPE_HDMI:
1286 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1287 return false;
1288
1289 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1290 default:
1291 return false;
1292 }
1293}
1294EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1295
1296/**
1297 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1298 * RGB->YCbCr conversion capability
1299 * @dpcd: DisplayPort configuration data
1300 * @port_cap: downstream facing port capabilities
1301 * @color_spc: Colorspace for which conversion cap is sought
1302 *
1303 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1304 * colorspace.
1305 */
1306bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1307 const u8 port_cap[4],
1308 u8 color_spc)
1309{
1310 if (!drm_dp_is_branch(dpcd))
1311 return false;
1312
1313 if (dpcd[DP_DPCD_REV] < 0x13)
1314 return false;
1315
1316 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1317 case DP_DS_PORT_TYPE_HDMI:
1318 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1319 return false;
1320
1321 return port_cap[3] & color_spc;
1322 default:
1323 return false;
1324 }
1325}
1326EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1327
1328/**
1329 * drm_dp_downstream_mode() - return a mode for downstream facing port
1330 * @dev: DRM device
1331 * @dpcd: DisplayPort configuration data
1332 * @port_cap: port capabilities
1333 *
1334 * Provides a suitable mode for downstream facing ports without EDID.
1335 *
1336 * Returns: A new drm_display_mode on success or NULL on failure
1337 */
1338struct drm_display_mode *
1339drm_dp_downstream_mode(struct drm_device *dev,
1340 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1341 const u8 port_cap[4])
1342
1343{
1344 u8 vic;
1345
1346 if (!drm_dp_is_branch(dpcd))
1347 return NULL;
1348
1349 if (dpcd[DP_DPCD_REV] < 0x11)
1350 return NULL;
1351
1352 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1353 case DP_DS_PORT_TYPE_NON_EDID:
1354 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1355 case DP_DS_NON_EDID_720x480i_60:
1356 vic = 6;
1357 break;
1358 case DP_DS_NON_EDID_720x480i_50:
1359 vic = 21;
1360 break;
1361 case DP_DS_NON_EDID_1920x1080i_60:
1362 vic = 5;
1363 break;
1364 case DP_DS_NON_EDID_1920x1080i_50:
1365 vic = 20;
1366 break;
1367 case DP_DS_NON_EDID_1280x720_60:
1368 vic = 4;
1369 break;
1370 case DP_DS_NON_EDID_1280x720_50:
1371 vic = 19;
1372 break;
1373 default:
1374 return NULL;
1375 }
1376 return drm_display_mode_from_cea_vic(dev, vic);
1377 default:
1378 return NULL;
1379 }
1380}
1381EXPORT_SYMBOL(drm_dp_downstream_mode);
1382
1383/**
1384 * drm_dp_downstream_id() - identify branch device
1385 * @aux: DisplayPort AUX channel
1386 * @id: DisplayPort branch device id
1387 *
1388 * Returns branch device id on success or NULL on failure
1389 */
1390int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1391{
1392 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1393}
1394EXPORT_SYMBOL(drm_dp_downstream_id);
1395
1396/**
1397 * drm_dp_downstream_debug() - debug DP branch devices
1398 * @m: pointer for debugfs file
1399 * @dpcd: DisplayPort configuration data
1400 * @port_cap: port capabilities
1401 * @drm_edid: EDID
1402 * @aux: DisplayPort AUX channel
1403 *
1404 */
1405void drm_dp_downstream_debug(struct seq_file *m,
1406 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1407 const u8 port_cap[4],
1408 const struct drm_edid *drm_edid,
1409 struct drm_dp_aux *aux)
1410{
1411 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1412 DP_DETAILED_CAP_INFO_AVAILABLE;
1413 int clk;
1414 int bpc;
1415 char id[7];
1416 int len;
1417 uint8_t rev[2];
1418 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1419 bool branch_device = drm_dp_is_branch(dpcd);
1420
1421 seq_printf(m, "\tDP branch device present: %s\n",
1422 str_yes_no(branch_device));
1423
1424 if (!branch_device)
1425 return;
1426
1427 switch (type) {
1428 case DP_DS_PORT_TYPE_DP:
1429 seq_puts(m, "\t\tType: DisplayPort\n");
1430 break;
1431 case DP_DS_PORT_TYPE_VGA:
1432 seq_puts(m, "\t\tType: VGA\n");
1433 break;
1434 case DP_DS_PORT_TYPE_DVI:
1435 seq_puts(m, "\t\tType: DVI\n");
1436 break;
1437 case DP_DS_PORT_TYPE_HDMI:
1438 seq_puts(m, "\t\tType: HDMI\n");
1439 break;
1440 case DP_DS_PORT_TYPE_NON_EDID:
1441 seq_puts(m, "\t\tType: others without EDID support\n");
1442 break;
1443 case DP_DS_PORT_TYPE_DP_DUALMODE:
1444 seq_puts(m, "\t\tType: DP++\n");
1445 break;
1446 case DP_DS_PORT_TYPE_WIRELESS:
1447 seq_puts(m, "\t\tType: Wireless\n");
1448 break;
1449 default:
1450 seq_puts(m, "\t\tType: N/A\n");
1451 }
1452
1453 memset(id, 0, sizeof(id));
1454 drm_dp_downstream_id(aux, id);
1455 seq_printf(m, "\t\tID: %s\n", id);
1456
1457 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1458 if (len > 0)
1459 seq_printf(m, "\t\tHW: %d.%d\n",
1460 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1461
1462 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1463 if (len > 0)
1464 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1465
1466 if (detailed_cap_info) {
1467 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1468 if (clk > 0)
1469 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1470
1471 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1472 if (clk > 0)
1473 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1474
1475 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1476 if (clk > 0)
1477 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1478
1479 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1480
1481 if (bpc > 0)
1482 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1483 }
1484}
1485EXPORT_SYMBOL(drm_dp_downstream_debug);
1486
1487/**
1488 * drm_dp_subconnector_type() - get DP branch device type
1489 * @dpcd: DisplayPort configuration data
1490 * @port_cap: port capabilities
1491 */
1492enum drm_mode_subconnector
1493drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1494 const u8 port_cap[4])
1495{
1496 int type;
1497 if (!drm_dp_is_branch(dpcd))
1498 return DRM_MODE_SUBCONNECTOR_Native;
1499 /* DP 1.0 approach */
1500 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1501 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1502 DP_DWN_STRM_PORT_TYPE_MASK;
1503
1504 switch (type) {
1505 case DP_DWN_STRM_PORT_TYPE_TMDS:
1506 /* Can be HDMI or DVI-D, DVI-D is a safer option */
1507 return DRM_MODE_SUBCONNECTOR_DVID;
1508 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1509 /* Can be VGA or DVI-A, VGA is more popular */
1510 return DRM_MODE_SUBCONNECTOR_VGA;
1511 case DP_DWN_STRM_PORT_TYPE_DP:
1512 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1513 case DP_DWN_STRM_PORT_TYPE_OTHER:
1514 default:
1515 return DRM_MODE_SUBCONNECTOR_Unknown;
1516 }
1517 }
1518 type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1519
1520 switch (type) {
1521 case DP_DS_PORT_TYPE_DP:
1522 case DP_DS_PORT_TYPE_DP_DUALMODE:
1523 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1524 case DP_DS_PORT_TYPE_VGA:
1525 return DRM_MODE_SUBCONNECTOR_VGA;
1526 case DP_DS_PORT_TYPE_DVI:
1527 return DRM_MODE_SUBCONNECTOR_DVID;
1528 case DP_DS_PORT_TYPE_HDMI:
1529 return DRM_MODE_SUBCONNECTOR_HDMIA;
1530 case DP_DS_PORT_TYPE_WIRELESS:
1531 return DRM_MODE_SUBCONNECTOR_Wireless;
1532 case DP_DS_PORT_TYPE_NON_EDID:
1533 default:
1534 return DRM_MODE_SUBCONNECTOR_Unknown;
1535 }
1536}
1537EXPORT_SYMBOL(drm_dp_subconnector_type);
1538
1539/**
1540 * drm_dp_set_subconnector_property - set subconnector for DP connector
1541 * @connector: connector to set property on
1542 * @status: connector status
1543 * @dpcd: DisplayPort configuration data
1544 * @port_cap: port capabilities
1545 *
1546 * Called by a driver on every detect event.
1547 */
1548void drm_dp_set_subconnector_property(struct drm_connector *connector,
1549 enum drm_connector_status status,
1550 const u8 *dpcd,
1551 const u8 port_cap[4])
1552{
1553 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1554
1555 if (status == connector_status_connected)
1556 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1557 drm_object_property_set_value(&connector->base,
1558 connector->dev->mode_config.dp_subconnector_property,
1559 subconnector);
1560}
1561EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1562
1563/**
1564 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1565 * count
1566 * @connector: The DRM connector to check
1567 * @dpcd: A cached copy of the connector's DPCD RX capabilities
1568 * @desc: A cached copy of the connector's DP descriptor
1569 *
1570 * See also: drm_dp_read_sink_count()
1571 *
1572 * Returns: %True if the (e)DP connector has a valid sink count that should
1573 * be probed, %false otherwise.
1574 */
1575bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1576 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1577 const struct drm_dp_desc *desc)
1578{
1579 /* Some eDP panels don't set a valid value for the sink count */
1580 return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1581 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1582 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1583 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1584}
1585EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1586
1587/**
1588 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1589 * @aux: The DP AUX channel to use
1590 *
1591 * See also: drm_dp_read_sink_count_cap()
1592 *
1593 * Returns: The current sink count reported by @aux, or a negative error code
1594 * otherwise.
1595 */
1596int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1597{
1598 u8 count;
1599 int ret;
1600
1601 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1602 if (ret < 0)
1603 return ret;
1604 if (ret != 1)
1605 return -EIO;
1606
1607 return DP_GET_SINK_COUNT(count);
1608}
1609EXPORT_SYMBOL(drm_dp_read_sink_count);
1610
1611/*
1612 * I2C-over-AUX implementation
1613 */
1614
1615static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1616{
1617 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1618 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1619 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1620 I2C_FUNC_10BIT_ADDR;
1621}
1622
1623static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1624{
1625 /*
1626 * In case of i2c defer or short i2c ack reply to a write,
1627 * we need to switch to WRITE_STATUS_UPDATE to drain the
1628 * rest of the message
1629 */
1630 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1631 msg->request &= DP_AUX_I2C_MOT;
1632 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1633 }
1634}
1635
1636#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1637#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1638#define AUX_STOP_LEN 4
1639#define AUX_CMD_LEN 4
1640#define AUX_ADDRESS_LEN 20
1641#define AUX_REPLY_PAD_LEN 4
1642#define AUX_LENGTH_LEN 8
1643
1644/*
1645 * Calculate the duration of the AUX request/reply in usec. Gives the
1646 * "best" case estimate, ie. successful while as short as possible.
1647 */
1648static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1649{
1650 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1651 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1652
1653 if ((msg->request & DP_AUX_I2C_READ) == 0)
1654 len += msg->size * 8;
1655
1656 return len;
1657}
1658
1659static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1660{
1661 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1662 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1663
1664 /*
1665 * For read we expect what was asked. For writes there will
1666 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1667 */
1668 if (msg->request & DP_AUX_I2C_READ)
1669 len += msg->size * 8;
1670
1671 return len;
1672}
1673
1674#define I2C_START_LEN 1
1675#define I2C_STOP_LEN 1
1676#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1677#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1678
1679/*
1680 * Calculate the length of the i2c transfer in usec, assuming
1681 * the i2c bus speed is as specified. Gives the "worst"
1682 * case estimate, ie. successful while as long as possible.
1683 * Doesn't account the "MOT" bit, and instead assumes each
1684 * message includes a START, ADDRESS and STOP. Neither does it
1685 * account for additional random variables such as clock stretching.
1686 */
1687static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1688 int i2c_speed_khz)
1689{
1690 /* AUX bitrate is 1MHz, i2c bitrate as specified */
1691 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1692 msg->size * I2C_DATA_LEN +
1693 I2C_STOP_LEN) * 1000, i2c_speed_khz);
1694}
1695
1696/*
1697 * Determine how many retries should be attempted to successfully transfer
1698 * the specified message, based on the estimated durations of the
1699 * i2c and AUX transfers.
1700 */
1701static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1702 int i2c_speed_khz)
1703{
1704 int aux_time_us = drm_dp_aux_req_duration(msg) +
1705 drm_dp_aux_reply_duration(msg);
1706 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1707
1708 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1709}
1710
1711/*
1712 * FIXME currently assumes 10 kHz as some real world devices seem
1713 * to require it. We should query/set the speed via DPCD if supported.
1714 */
1715static int dp_aux_i2c_speed_khz __read_mostly = 10;
1716module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1717MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1718 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1719
1720/*
1721 * Transfer a single I2C-over-AUX message and handle various error conditions,
1722 * retrying the transaction as appropriate. It is assumed that the
1723 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1724 * reply field.
1725 *
1726 * Returns bytes transferred on success, or a negative error code on failure.
1727 */
1728static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1729{
1730 unsigned int retry, defer_i2c;
1731 int ret;
1732 /*
1733 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1734 * is required to retry at least seven times upon receiving AUX_DEFER
1735 * before giving up the AUX transaction.
1736 *
1737 * We also try to account for the i2c bus speed.
1738 */
1739 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1740
1741 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1742 ret = aux->transfer(aux, msg);
1743 if (ret < 0) {
1744 if (ret == -EBUSY)
1745 continue;
1746
1747 /*
1748 * While timeouts can be errors, they're usually normal
1749 * behavior (for instance, when a driver tries to
1750 * communicate with a non-existent DisplayPort device).
1751 * Avoid spamming the kernel log with timeout errors.
1752 */
1753 if (ret == -ETIMEDOUT)
1754 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1755 aux->name);
1756 else
1757 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1758 aux->name, ret);
1759 return ret;
1760 }
1761
1762
1763 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1764 case DP_AUX_NATIVE_REPLY_ACK:
1765 /*
1766 * For I2C-over-AUX transactions this isn't enough, we
1767 * need to check for the I2C ACK reply.
1768 */
1769 break;
1770
1771 case DP_AUX_NATIVE_REPLY_NACK:
1772 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1773 aux->name, ret, msg->size);
1774 return -EREMOTEIO;
1775
1776 case DP_AUX_NATIVE_REPLY_DEFER:
1777 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1778 /*
1779 * We could check for I2C bit rate capabilities and if
1780 * available adjust this interval. We could also be
1781 * more careful with DP-to-legacy adapters where a
1782 * long legacy cable may force very low I2C bit rates.
1783 *
1784 * For now just defer for long enough to hopefully be
1785 * safe for all use-cases.
1786 */
1787 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1788 continue;
1789
1790 default:
1791 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1792 aux->name, msg->reply);
1793 return -EREMOTEIO;
1794 }
1795
1796 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1797 case DP_AUX_I2C_REPLY_ACK:
1798 /*
1799 * Both native ACK and I2C ACK replies received. We
1800 * can assume the transfer was successful.
1801 */
1802 if (ret != msg->size)
1803 drm_dp_i2c_msg_write_status_update(msg);
1804 return ret;
1805
1806 case DP_AUX_I2C_REPLY_NACK:
1807 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1808 aux->name, ret, msg->size);
1809 aux->i2c_nack_count++;
1810 return -EREMOTEIO;
1811
1812 case DP_AUX_I2C_REPLY_DEFER:
1813 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1814 /* DP Compliance Test 4.2.2.5 Requirement:
1815 * Must have at least 7 retries for I2C defers on the
1816 * transaction to pass this test
1817 */
1818 aux->i2c_defer_count++;
1819 if (defer_i2c < 7)
1820 defer_i2c++;
1821 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1822 drm_dp_i2c_msg_write_status_update(msg);
1823
1824 continue;
1825
1826 default:
1827 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1828 aux->name, msg->reply);
1829 return -EREMOTEIO;
1830 }
1831 }
1832
1833 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1834 return -EREMOTEIO;
1835}
1836
1837static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1838 const struct i2c_msg *i2c_msg)
1839{
1840 msg->request = (i2c_msg->flags & I2C_M_RD) ?
1841 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1842 if (!(i2c_msg->flags & I2C_M_STOP))
1843 msg->request |= DP_AUX_I2C_MOT;
1844}
1845
1846/*
1847 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1848 *
1849 * Returns an error code on failure, or a recommended transfer size on success.
1850 */
1851static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1852{
1853 int err, ret = orig_msg->size;
1854 struct drm_dp_aux_msg msg = *orig_msg;
1855
1856 while (msg.size > 0) {
1857 err = drm_dp_i2c_do_msg(aux, &msg);
1858 if (err <= 0)
1859 return err == 0 ? -EPROTO : err;
1860
1861 if (err < msg.size && err < ret) {
1862 drm_dbg_kms(aux->drm_dev,
1863 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1864 aux->name, msg.size, err);
1865 ret = err;
1866 }
1867
1868 msg.size -= err;
1869 msg.buffer += err;
1870 }
1871
1872 return ret;
1873}
1874
1875/*
1876 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1877 * packets to be as large as possible. If not, the I2C transactions never
1878 * succeed. Hence the default is maximum.
1879 */
1880static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1881module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1882MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1883 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1884
1885static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1886 int num)
1887{
1888 struct drm_dp_aux *aux = adapter->algo_data;
1889 unsigned int i, j;
1890 unsigned transfer_size;
1891 struct drm_dp_aux_msg msg;
1892 int err = 0;
1893
1894 if (aux->powered_down)
1895 return -EBUSY;
1896
1897 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1898
1899 memset(&msg, 0, sizeof(msg));
1900
1901 for (i = 0; i < num; i++) {
1902 msg.address = msgs[i].addr;
1903 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1904 /* Send a bare address packet to start the transaction.
1905 * Zero sized messages specify an address only (bare
1906 * address) transaction.
1907 */
1908 msg.buffer = NULL;
1909 msg.size = 0;
1910 err = drm_dp_i2c_do_msg(aux, &msg);
1911
1912 /*
1913 * Reset msg.request in case in case it got
1914 * changed into a WRITE_STATUS_UPDATE.
1915 */
1916 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1917
1918 if (err < 0)
1919 break;
1920 /* We want each transaction to be as large as possible, but
1921 * we'll go to smaller sizes if the hardware gives us a
1922 * short reply.
1923 */
1924 transfer_size = dp_aux_i2c_transfer_size;
1925 for (j = 0; j < msgs[i].len; j += msg.size) {
1926 msg.buffer = msgs[i].buf + j;
1927 msg.size = min(transfer_size, msgs[i].len - j);
1928
1929 err = drm_dp_i2c_drain_msg(aux, &msg);
1930
1931 /*
1932 * Reset msg.request in case in case it got
1933 * changed into a WRITE_STATUS_UPDATE.
1934 */
1935 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1936
1937 if (err < 0)
1938 break;
1939 transfer_size = err;
1940 }
1941 if (err < 0)
1942 break;
1943 }
1944 if (err >= 0)
1945 err = num;
1946 /* Send a bare address packet to close out the transaction.
1947 * Zero sized messages specify an address only (bare
1948 * address) transaction.
1949 */
1950 msg.request &= ~DP_AUX_I2C_MOT;
1951 msg.buffer = NULL;
1952 msg.size = 0;
1953 (void)drm_dp_i2c_do_msg(aux, &msg);
1954
1955 return err;
1956}
1957
1958static const struct i2c_algorithm drm_dp_i2c_algo = {
1959 .functionality = drm_dp_i2c_functionality,
1960 .master_xfer = drm_dp_i2c_xfer,
1961};
1962
1963static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1964{
1965 return container_of(i2c, struct drm_dp_aux, ddc);
1966}
1967
1968static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1969{
1970 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1971}
1972
1973static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1974{
1975 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1976}
1977
1978static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1979{
1980 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1981}
1982
1983static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1984 .lock_bus = lock_bus,
1985 .trylock_bus = trylock_bus,
1986 .unlock_bus = unlock_bus,
1987};
1988
1989static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1990{
1991 u8 buf, count;
1992 int ret;
1993
1994 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1995 if (ret < 0)
1996 return ret;
1997
1998 WARN_ON(!(buf & DP_TEST_SINK_START));
1999
2000 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
2001 if (ret < 0)
2002 return ret;
2003
2004 count = buf & DP_TEST_COUNT_MASK;
2005 if (count == aux->crc_count)
2006 return -EAGAIN; /* No CRC yet */
2007
2008 aux->crc_count = count;
2009
2010 /*
2011 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
2012 * per component (RGB or CrYCb).
2013 */
2014 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
2015 if (ret < 0)
2016 return ret;
2017
2018 return 0;
2019}
2020
2021static void drm_dp_aux_crc_work(struct work_struct *work)
2022{
2023 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
2024 crc_work);
2025 struct drm_crtc *crtc;
2026 u8 crc_bytes[6];
2027 uint32_t crcs[3];
2028 int ret;
2029
2030 if (WARN_ON(!aux->crtc))
2031 return;
2032
2033 crtc = aux->crtc;
2034 while (crtc->crc.opened) {
2035 drm_crtc_wait_one_vblank(crtc);
2036 if (!crtc->crc.opened)
2037 break;
2038
2039 ret = drm_dp_aux_get_crc(aux, crc_bytes);
2040 if (ret == -EAGAIN) {
2041 usleep_range(1000, 2000);
2042 ret = drm_dp_aux_get_crc(aux, crc_bytes);
2043 }
2044
2045 if (ret == -EAGAIN) {
2046 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2047 aux->name, ret);
2048 continue;
2049 } else if (ret) {
2050 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2051 continue;
2052 }
2053
2054 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2055 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2056 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2057 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
2058 }
2059}
2060
2061/**
2062 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2063 * @aux: DisplayPort AUX channel
2064 *
2065 * Used for remote aux channel in general. Merely initialize the crc work
2066 * struct.
2067 */
2068void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2069{
2070 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2071}
2072EXPORT_SYMBOL(drm_dp_remote_aux_init);
2073
2074/**
2075 * drm_dp_aux_init() - minimally initialise an aux channel
2076 * @aux: DisplayPort AUX channel
2077 *
2078 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2079 * the outside world, call drm_dp_aux_init() first. For drivers which are
2080 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2081 * &drm_connector), you must still call drm_dp_aux_register() once the connector
2082 * has been registered to allow userspace access to the auxiliary DP channel.
2083 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2084 * early as possible so that the &drm_device that corresponds to the AUX adapter
2085 * may be mentioned in debugging output from the DRM DP helpers.
2086 *
2087 * For devices which use a separate platform device for their AUX adapters, this
2088 * may be called as early as required by the driver.
2089 *
2090 */
2091void drm_dp_aux_init(struct drm_dp_aux *aux)
2092{
2093 mutex_init(&aux->hw_mutex);
2094 mutex_init(&aux->cec.lock);
2095 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2096
2097 aux->ddc.algo = &drm_dp_i2c_algo;
2098 aux->ddc.algo_data = aux;
2099 aux->ddc.retries = 3;
2100
2101 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2102}
2103EXPORT_SYMBOL(drm_dp_aux_init);
2104
2105/**
2106 * drm_dp_aux_register() - initialise and register aux channel
2107 * @aux: DisplayPort AUX channel
2108 *
2109 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2110 * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2111 * initialized. For devices which are grandparents of their AUX channels,
2112 * &drm_dp_aux.dev will typically be the &drm_connector &device which
2113 * corresponds to @aux. For these devices, it's advised to call
2114 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2115 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2116 * Functions which don't follow this will likely Oops when
2117 * %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled.
2118 *
2119 * For devices where the AUX channel is a device that exists independently of
2120 * the &drm_device that uses it, such as SoCs and bridge devices, it is
2121 * recommended to call drm_dp_aux_register() after a &drm_device has been
2122 * assigned to &drm_dp_aux.drm_dev, and likewise to call
2123 * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2124 * with the AUX channel (e.g. on bridge detach).
2125 *
2126 * Drivers which need to use the aux channel before either of the two points
2127 * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2128 * channel before registration.
2129 *
2130 * Returns 0 on success or a negative error code on failure.
2131 */
2132int drm_dp_aux_register(struct drm_dp_aux *aux)
2133{
2134 int ret;
2135
2136 WARN_ON_ONCE(!aux->drm_dev);
2137
2138 if (!aux->ddc.algo)
2139 drm_dp_aux_init(aux);
2140
2141 aux->ddc.owner = THIS_MODULE;
2142 aux->ddc.dev.parent = aux->dev;
2143
2144 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2145 sizeof(aux->ddc.name));
2146
2147 ret = drm_dp_aux_register_devnode(aux);
2148 if (ret)
2149 return ret;
2150
2151 ret = i2c_add_adapter(&aux->ddc);
2152 if (ret) {
2153 drm_dp_aux_unregister_devnode(aux);
2154 return ret;
2155 }
2156
2157 return 0;
2158}
2159EXPORT_SYMBOL(drm_dp_aux_register);
2160
2161/**
2162 * drm_dp_aux_unregister() - unregister an AUX adapter
2163 * @aux: DisplayPort AUX channel
2164 */
2165void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2166{
2167 drm_dp_aux_unregister_devnode(aux);
2168 i2c_del_adapter(&aux->ddc);
2169}
2170EXPORT_SYMBOL(drm_dp_aux_unregister);
2171
2172#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2173
2174/**
2175 * drm_dp_psr_setup_time() - PSR setup in time usec
2176 * @psr_cap: PSR capabilities from DPCD
2177 *
2178 * Returns:
2179 * PSR setup time for the panel in microseconds, negative
2180 * error code on failure.
2181 */
2182int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2183{
2184 static const u16 psr_setup_time_us[] = {
2185 PSR_SETUP_TIME(330),
2186 PSR_SETUP_TIME(275),
2187 PSR_SETUP_TIME(220),
2188 PSR_SETUP_TIME(165),
2189 PSR_SETUP_TIME(110),
2190 PSR_SETUP_TIME(55),
2191 PSR_SETUP_TIME(0),
2192 };
2193 int i;
2194
2195 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2196 if (i >= ARRAY_SIZE(psr_setup_time_us))
2197 return -EINVAL;
2198
2199 return psr_setup_time_us[i];
2200}
2201EXPORT_SYMBOL(drm_dp_psr_setup_time);
2202
2203#undef PSR_SETUP_TIME
2204
2205/**
2206 * drm_dp_start_crc() - start capture of frame CRCs
2207 * @aux: DisplayPort AUX channel
2208 * @crtc: CRTC displaying the frames whose CRCs are to be captured
2209 *
2210 * Returns 0 on success or a negative error code on failure.
2211 */
2212int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2213{
2214 u8 buf;
2215 int ret;
2216
2217 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2218 if (ret < 0)
2219 return ret;
2220
2221 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
2222 if (ret < 0)
2223 return ret;
2224
2225 aux->crc_count = 0;
2226 aux->crtc = crtc;
2227 schedule_work(&aux->crc_work);
2228
2229 return 0;
2230}
2231EXPORT_SYMBOL(drm_dp_start_crc);
2232
2233/**
2234 * drm_dp_stop_crc() - stop capture of frame CRCs
2235 * @aux: DisplayPort AUX channel
2236 *
2237 * Returns 0 on success or a negative error code on failure.
2238 */
2239int drm_dp_stop_crc(struct drm_dp_aux *aux)
2240{
2241 u8 buf;
2242 int ret;
2243
2244 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2245 if (ret < 0)
2246 return ret;
2247
2248 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
2249 if (ret < 0)
2250 return ret;
2251
2252 flush_work(&aux->crc_work);
2253 aux->crtc = NULL;
2254
2255 return 0;
2256}
2257EXPORT_SYMBOL(drm_dp_stop_crc);
2258
2259struct dpcd_quirk {
2260 u8 oui[3];
2261 u8 device_id[6];
2262 bool is_branch;
2263 u32 quirks;
2264};
2265
2266#define OUI(first, second, third) { (first), (second), (third) }
2267#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2268 { (first), (second), (third), (fourth), (fifth), (sixth) }
2269
2270#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
2271
2272static const struct dpcd_quirk dpcd_quirk_list[] = {
2273 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
2274 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2275 /* LG LP140WF6-SPM1 eDP panel */
2276 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2277 /* Apple panels need some additional handling to support PSR */
2278 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2279 /* CH7511 seems to leave SINK_COUNT zeroed */
2280 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2281 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2282 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2283 /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
2284 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2285 /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */
2286 { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2287 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2288 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2289};
2290
2291#undef OUI
2292
2293/*
2294 * Get a bit mask of DPCD quirks for the sink/branch device identified by
2295 * ident. The quirk data is shared but it's up to the drivers to act on the
2296 * data.
2297 *
2298 * For now, only the OUI (first three bytes) is used, but this may be extended
2299 * to device identification string and hardware/firmware revisions later.
2300 */
2301static u32
2302drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2303{
2304 const struct dpcd_quirk *quirk;
2305 u32 quirks = 0;
2306 int i;
2307 u8 any_device[] = DEVICE_ID_ANY;
2308
2309 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2310 quirk = &dpcd_quirk_list[i];
2311
2312 if (quirk->is_branch != is_branch)
2313 continue;
2314
2315 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
2316 continue;
2317
2318 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
2319 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
2320 continue;
2321
2322 quirks |= quirk->quirks;
2323 }
2324
2325 return quirks;
2326}
2327
2328#undef DEVICE_ID_ANY
2329#undef DEVICE_ID
2330
2331static int drm_dp_read_ident(struct drm_dp_aux *aux, unsigned int offset,
2332 struct drm_dp_dpcd_ident *ident)
2333{
2334 int ret;
2335
2336 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2337
2338 return ret < 0 ? ret : 0;
2339}
2340
2341static void drm_dp_dump_desc(struct drm_dp_aux *aux,
2342 const char *device_name, const struct drm_dp_desc *desc)
2343{
2344 const struct drm_dp_dpcd_ident *ident = &desc->ident;
2345
2346 drm_dbg_kms(aux->drm_dev,
2347 "%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2348 aux->name, device_name,
2349 (int)sizeof(ident->oui), ident->oui,
2350 (int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id,
2351 ident->hw_rev >> 4, ident->hw_rev & 0xf,
2352 ident->sw_major_rev, ident->sw_minor_rev,
2353 desc->quirks);
2354}
2355
2356/**
2357 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2358 * @aux: DisplayPort AUX channel
2359 * @desc: Device descriptor to fill from DPCD
2360 * @is_branch: true for branch devices, false for sink devices
2361 *
2362 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2363 * identification.
2364 *
2365 * Returns 0 on success or a negative error code on failure.
2366 */
2367int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2368 bool is_branch)
2369{
2370 struct drm_dp_dpcd_ident *ident = &desc->ident;
2371 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2372 int ret;
2373
2374 ret = drm_dp_read_ident(aux, offset, ident);
2375 if (ret < 0)
2376 return ret;
2377
2378 desc->quirks = drm_dp_get_quirks(ident, is_branch);
2379
2380 drm_dp_dump_desc(aux, is_branch ? "DP branch" : "DP sink", desc);
2381
2382 return 0;
2383}
2384EXPORT_SYMBOL(drm_dp_read_desc);
2385
2386/**
2387 * drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY
2388 * @aux: DisplayPort AUX channel
2389 * @dp_phy: LTTPR PHY instance
2390 *
2391 * Read the DPCD LTTPR PHY descriptor for @dp_phy and print a debug message
2392 * with its details to dmesg.
2393 *
2394 * Returns 0 on success or a negative error code on failure.
2395 */
2396int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy)
2397{
2398 struct drm_dp_desc desc = {};
2399 int ret;
2400
2401 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT))
2402 return -EINVAL;
2403
2404 ret = drm_dp_read_ident(aux, DP_OUI_PHY_REPEATER(dp_phy), &desc.ident);
2405 if (ret < 0)
2406 return ret;
2407
2408 drm_dp_dump_desc(aux, drm_dp_phy_name(dp_phy), &desc);
2409
2410 return 0;
2411}
2412EXPORT_SYMBOL(drm_dp_dump_lttpr_desc);
2413
2414/**
2415 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2416 * @dsc_dpcd: DSC capabilities from DPCD
2417 *
2418 * Returns the bpp precision supported by the DP sink.
2419 */
2420u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2421{
2422 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
2423
2424 switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) {
2425 case DP_DSC_BITS_PER_PIXEL_1_16:
2426 return 16;
2427 case DP_DSC_BITS_PER_PIXEL_1_8:
2428 return 8;
2429 case DP_DSC_BITS_PER_PIXEL_1_4:
2430 return 4;
2431 case DP_DSC_BITS_PER_PIXEL_1_2:
2432 return 2;
2433 case DP_DSC_BITS_PER_PIXEL_1_1:
2434 return 1;
2435 }
2436
2437 return 0;
2438}
2439EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
2440
2441/**
2442 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2443 * supported by the DSC sink.
2444 * @dsc_dpcd: DSC capabilities from DPCD
2445 * @is_edp: true if its eDP, false for DP
2446 *
2447 * Read the slice capabilities DPCD register from DSC sink to get
2448 * the maximum slice count supported. This is used to populate
2449 * the DSC parameters in the &struct drm_dsc_config by the driver.
2450 * Driver creates an infoframe using these parameters to populate
2451 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2452 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2453 *
2454 * Returns:
2455 * Maximum slice count supported by DSC sink or 0 its invalid
2456 */
2457u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2458 bool is_edp)
2459{
2460 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2461
2462 if (is_edp) {
2463 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2464 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2465 return 4;
2466 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2467 return 2;
2468 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2469 return 1;
2470 } else {
2471 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2472 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2473
2474 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2475 return 24;
2476 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2477 return 20;
2478 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2479 return 16;
2480 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2481 return 12;
2482 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2483 return 10;
2484 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2485 return 8;
2486 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2487 return 6;
2488 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2489 return 4;
2490 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2491 return 2;
2492 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2493 return 1;
2494 }
2495
2496 return 0;
2497}
2498EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2499
2500/**
2501 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2502 * @dsc_dpcd: DSC capabilities from DPCD
2503 *
2504 * Read the DSC DPCD register to parse the line buffer depth in bits which is
2505 * number of bits of precision within the decoder line buffer supported by
2506 * the DSC sink. This is used to populate the DSC parameters in the
2507 * &struct drm_dsc_config by the driver.
2508 * Driver creates an infoframe using these parameters to populate
2509 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2510 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2511 *
2512 * Returns:
2513 * Line buffer depth supported by DSC panel or 0 its invalid
2514 */
2515u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2516{
2517 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2518
2519 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2520 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2521 return 9;
2522 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2523 return 10;
2524 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2525 return 11;
2526 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2527 return 12;
2528 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2529 return 13;
2530 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2531 return 14;
2532 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2533 return 15;
2534 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2535 return 16;
2536 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2537 return 8;
2538 }
2539
2540 return 0;
2541}
2542EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2543
2544/**
2545 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2546 * values supported by the DSC sink.
2547 * @dsc_dpcd: DSC capabilities from DPCD
2548 * @dsc_bpc: An array to be filled by this helper with supported
2549 * input bpcs.
2550 *
2551 * Read the DSC DPCD from the sink device to parse the supported bits per
2552 * component values. This is used to populate the DSC parameters
2553 * in the &struct drm_dsc_config by the driver.
2554 * Driver creates an infoframe using these parameters to populate
2555 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2556 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2557 *
2558 * Returns:
2559 * Number of input BPC values parsed from the DPCD
2560 */
2561int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2562 u8 dsc_bpc[3])
2563{
2564 int num_bpc = 0;
2565 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2566
2567 if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2568 return 0;
2569
2570 if (color_depth & DP_DSC_12_BPC)
2571 dsc_bpc[num_bpc++] = 12;
2572 if (color_depth & DP_DSC_10_BPC)
2573 dsc_bpc[num_bpc++] = 10;
2574
2575 /* A DP DSC Sink device shall support 8 bpc. */
2576 dsc_bpc[num_bpc++] = 8;
2577
2578 return num_bpc;
2579}
2580EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2581
2582static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2583 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2584 u8 *buf, int buf_size)
2585{
2586 /*
2587 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2588 * corrupted values when reading from the 0xF0000- range with a block
2589 * size bigger than 1.
2590 */
2591 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2592 int offset;
2593 int ret;
2594
2595 for (offset = 0; offset < buf_size; offset += block_size) {
2596 ret = drm_dp_dpcd_read(aux,
2597 address + offset,
2598 &buf[offset], block_size);
2599 if (ret < 0)
2600 return ret;
2601
2602 WARN_ON(ret != block_size);
2603 }
2604
2605 return 0;
2606}
2607
2608/**
2609 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2610 * @aux: DisplayPort AUX channel
2611 * @dpcd: DisplayPort configuration data
2612 * @caps: buffer to return the capability info in
2613 *
2614 * Read capabilities common to all LTTPRs.
2615 *
2616 * Returns 0 on success or a negative error code on failure.
2617 */
2618int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2619 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2620 u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2621{
2622 return drm_dp_read_lttpr_regs(aux, dpcd,
2623 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2624 caps, DP_LTTPR_COMMON_CAP_SIZE);
2625}
2626EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2627
2628/**
2629 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2630 * @aux: DisplayPort AUX channel
2631 * @dpcd: DisplayPort configuration data
2632 * @dp_phy: LTTPR PHY to read the capabilities for
2633 * @caps: buffer to return the capability info in
2634 *
2635 * Read the capabilities for the given LTTPR PHY.
2636 *
2637 * Returns 0 on success or a negative error code on failure.
2638 */
2639int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2640 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2641 enum drm_dp_phy dp_phy,
2642 u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2643{
2644 return drm_dp_read_lttpr_regs(aux, dpcd,
2645 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2646 caps, DP_LTTPR_PHY_CAP_SIZE);
2647}
2648EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2649
2650static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2651{
2652 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2653}
2654
2655/**
2656 * drm_dp_lttpr_count - get the number of detected LTTPRs
2657 * @caps: LTTPR common capabilities
2658 *
2659 * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2660 *
2661 * Returns:
2662 * -ERANGE if more than supported number (8) of LTTPRs are detected
2663 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2664 * otherwise the number of detected LTTPRs
2665 */
2666int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2667{
2668 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2669
2670 switch (hweight8(count)) {
2671 case 0:
2672 return 0;
2673 case 1:
2674 return 8 - ilog2(count);
2675 case 8:
2676 return -ERANGE;
2677 default:
2678 return -EINVAL;
2679 }
2680}
2681EXPORT_SYMBOL(drm_dp_lttpr_count);
2682
2683/**
2684 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2685 * @caps: LTTPR common capabilities
2686 *
2687 * Returns the maximum link rate supported by all detected LTTPRs.
2688 */
2689int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2690{
2691 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2692
2693 return drm_dp_bw_code_to_link_rate(rate);
2694}
2695EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2696
2697/**
2698 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2699 * @caps: LTTPR common capabilities
2700 *
2701 * Returns the maximum lane count supported by all detected LTTPRs.
2702 */
2703int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2704{
2705 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2706
2707 return max_lanes & DP_MAX_LANE_COUNT_MASK;
2708}
2709EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2710
2711/**
2712 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2713 * @caps: LTTPR PHY capabilities
2714 *
2715 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2716 * voltage swing level 3.
2717 */
2718bool
2719drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2720{
2721 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2722
2723 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2724}
2725EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2726
2727/**
2728 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2729 * @caps: LTTPR PHY capabilities
2730 *
2731 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2732 * pre-emphasis level 3.
2733 */
2734bool
2735drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2736{
2737 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2738
2739 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2740}
2741EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2742
2743/**
2744 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2745 * @aux: DisplayPort AUX channel
2746 * @data: DP phy compliance test parameters.
2747 *
2748 * Returns 0 on success or a negative error code on failure.
2749 */
2750int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2751 struct drm_dp_phy_test_params *data)
2752{
2753 int err;
2754 u8 rate, lanes;
2755
2756 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2757 if (err < 0)
2758 return err;
2759 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2760
2761 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2762 if (err < 0)
2763 return err;
2764 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2765
2766 if (lanes & DP_ENHANCED_FRAME_CAP)
2767 data->enhanced_frame_cap = true;
2768
2769 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2770 if (err < 0)
2771 return err;
2772
2773 switch (data->phy_pattern) {
2774 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2775 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2776 &data->custom80, sizeof(data->custom80));
2777 if (err < 0)
2778 return err;
2779
2780 break;
2781 case DP_PHY_TEST_PATTERN_CP2520:
2782 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2783 &data->hbr2_reset,
2784 sizeof(data->hbr2_reset));
2785 if (err < 0)
2786 return err;
2787 }
2788
2789 return 0;
2790}
2791EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2792
2793/**
2794 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2795 * @aux: DisplayPort AUX channel
2796 * @data: DP phy compliance test parameters.
2797 * @dp_rev: DP revision to use for compliance testing
2798 *
2799 * Returns 0 on success or a negative error code on failure.
2800 */
2801int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2802 struct drm_dp_phy_test_params *data, u8 dp_rev)
2803{
2804 int err, i;
2805 u8 test_pattern;
2806
2807 test_pattern = data->phy_pattern;
2808 if (dp_rev < 0x12) {
2809 test_pattern = (test_pattern << 2) &
2810 DP_LINK_QUAL_PATTERN_11_MASK;
2811 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2812 test_pattern);
2813 if (err < 0)
2814 return err;
2815 } else {
2816 for (i = 0; i < data->num_lanes; i++) {
2817 err = drm_dp_dpcd_writeb(aux,
2818 DP_LINK_QUAL_LANE0_SET + i,
2819 test_pattern);
2820 if (err < 0)
2821 return err;
2822 }
2823 }
2824
2825 return 0;
2826}
2827EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2828
2829static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2830{
2831 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2832 return "Invalid";
2833
2834 switch (pixelformat) {
2835 case DP_PIXELFORMAT_RGB:
2836 return "RGB";
2837 case DP_PIXELFORMAT_YUV444:
2838 return "YUV444";
2839 case DP_PIXELFORMAT_YUV422:
2840 return "YUV422";
2841 case DP_PIXELFORMAT_YUV420:
2842 return "YUV420";
2843 case DP_PIXELFORMAT_Y_ONLY:
2844 return "Y_ONLY";
2845 case DP_PIXELFORMAT_RAW:
2846 return "RAW";
2847 default:
2848 return "Reserved";
2849 }
2850}
2851
2852static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2853 enum dp_colorimetry colorimetry)
2854{
2855 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2856 return "Invalid";
2857
2858 switch (colorimetry) {
2859 case DP_COLORIMETRY_DEFAULT:
2860 switch (pixelformat) {
2861 case DP_PIXELFORMAT_RGB:
2862 return "sRGB";
2863 case DP_PIXELFORMAT_YUV444:
2864 case DP_PIXELFORMAT_YUV422:
2865 case DP_PIXELFORMAT_YUV420:
2866 return "BT.601";
2867 case DP_PIXELFORMAT_Y_ONLY:
2868 return "DICOM PS3.14";
2869 case DP_PIXELFORMAT_RAW:
2870 return "Custom Color Profile";
2871 default:
2872 return "Reserved";
2873 }
2874 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2875 switch (pixelformat) {
2876 case DP_PIXELFORMAT_RGB:
2877 return "Wide Fixed";
2878 case DP_PIXELFORMAT_YUV444:
2879 case DP_PIXELFORMAT_YUV422:
2880 case DP_PIXELFORMAT_YUV420:
2881 return "BT.709";
2882 default:
2883 return "Reserved";
2884 }
2885 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2886 switch (pixelformat) {
2887 case DP_PIXELFORMAT_RGB:
2888 return "Wide Float";
2889 case DP_PIXELFORMAT_YUV444:
2890 case DP_PIXELFORMAT_YUV422:
2891 case DP_PIXELFORMAT_YUV420:
2892 return "xvYCC 601";
2893 default:
2894 return "Reserved";
2895 }
2896 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2897 switch (pixelformat) {
2898 case DP_PIXELFORMAT_RGB:
2899 return "OpRGB";
2900 case DP_PIXELFORMAT_YUV444:
2901 case DP_PIXELFORMAT_YUV422:
2902 case DP_PIXELFORMAT_YUV420:
2903 return "xvYCC 709";
2904 default:
2905 return "Reserved";
2906 }
2907 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2908 switch (pixelformat) {
2909 case DP_PIXELFORMAT_RGB:
2910 return "DCI-P3";
2911 case DP_PIXELFORMAT_YUV444:
2912 case DP_PIXELFORMAT_YUV422:
2913 case DP_PIXELFORMAT_YUV420:
2914 return "sYCC 601";
2915 default:
2916 return "Reserved";
2917 }
2918 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2919 switch (pixelformat) {
2920 case DP_PIXELFORMAT_RGB:
2921 return "Custom Profile";
2922 case DP_PIXELFORMAT_YUV444:
2923 case DP_PIXELFORMAT_YUV422:
2924 case DP_PIXELFORMAT_YUV420:
2925 return "OpYCC 601";
2926 default:
2927 return "Reserved";
2928 }
2929 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2930 switch (pixelformat) {
2931 case DP_PIXELFORMAT_RGB:
2932 return "BT.2020 RGB";
2933 case DP_PIXELFORMAT_YUV444:
2934 case DP_PIXELFORMAT_YUV422:
2935 case DP_PIXELFORMAT_YUV420:
2936 return "BT.2020 CYCC";
2937 default:
2938 return "Reserved";
2939 }
2940 case DP_COLORIMETRY_BT2020_YCC:
2941 switch (pixelformat) {
2942 case DP_PIXELFORMAT_YUV444:
2943 case DP_PIXELFORMAT_YUV422:
2944 case DP_PIXELFORMAT_YUV420:
2945 return "BT.2020 YCC";
2946 default:
2947 return "Reserved";
2948 }
2949 default:
2950 return "Invalid";
2951 }
2952}
2953
2954static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2955{
2956 switch (dynamic_range) {
2957 case DP_DYNAMIC_RANGE_VESA:
2958 return "VESA range";
2959 case DP_DYNAMIC_RANGE_CTA:
2960 return "CTA range";
2961 default:
2962 return "Invalid";
2963 }
2964}
2965
2966static const char *dp_content_type_get_name(enum dp_content_type content_type)
2967{
2968 switch (content_type) {
2969 case DP_CONTENT_TYPE_NOT_DEFINED:
2970 return "Not defined";
2971 case DP_CONTENT_TYPE_GRAPHICS:
2972 return "Graphics";
2973 case DP_CONTENT_TYPE_PHOTO:
2974 return "Photo";
2975 case DP_CONTENT_TYPE_VIDEO:
2976 return "Video";
2977 case DP_CONTENT_TYPE_GAME:
2978 return "Game";
2979 default:
2980 return "Reserved";
2981 }
2982}
2983
2984void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
2985{
2986 drm_printf(p, "DP SDP: VSC, revision %u, length %u\n",
2987 vsc->revision, vsc->length);
2988 drm_printf(p, " pixelformat: %s\n",
2989 dp_pixelformat_get_name(vsc->pixelformat));
2990 drm_printf(p, " colorimetry: %s\n",
2991 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2992 drm_printf(p, " bpc: %u\n", vsc->bpc);
2993 drm_printf(p, " dynamic range: %s\n",
2994 dp_dynamic_range_get_name(vsc->dynamic_range));
2995 drm_printf(p, " content type: %s\n",
2996 dp_content_type_get_name(vsc->content_type));
2997}
2998EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2999
3000void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
3001{
3002 drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
3003 as_sdp->revision, as_sdp->length);
3004 drm_printf(p, " vtotal: %d\n", as_sdp->vtotal);
3005 drm_printf(p, " target_rr: %d\n", as_sdp->target_rr);
3006 drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
3007 drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
3008 drm_printf(p, " operation_mode: %d\n", as_sdp->mode);
3009}
3010EXPORT_SYMBOL(drm_dp_as_sdp_log);
3011
3012/**
3013 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
3014 * @aux: DisplayPort AUX channel
3015 * @dpcd: DisplayPort configuration data
3016 *
3017 * Returns true if adaptive sync sdp is supported, else returns false
3018 */
3019bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3020{
3021 u8 rx_feature;
3022
3023 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3024 return false;
3025
3026 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
3027 &rx_feature) != 1) {
3028 drm_dbg_dp(aux->drm_dev,
3029 "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
3030 return false;
3031 }
3032
3033 return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
3034}
3035EXPORT_SYMBOL(drm_dp_as_sdp_supported);
3036
3037/**
3038 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
3039 * @aux: DisplayPort AUX channel
3040 * @dpcd: DisplayPort configuration data
3041 *
3042 * Returns true if vsc sdp is supported, else returns false
3043 */
3044bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3045{
3046 u8 rx_feature;
3047
3048 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3049 return false;
3050
3051 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) != 1) {
3052 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
3053 return false;
3054 }
3055
3056 return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
3057}
3058EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
3059
3060/**
3061 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
3062 * @vsc: vsc sdp initialized according to its purpose as defined in
3063 * table 2-118 - table 2-120 in DP 1.4a specification
3064 * @sdp: valid handle to the generic dp_sdp which will be packed
3065 *
3066 * Returns length of sdp on success and error code on failure
3067 */
3068ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3069 struct dp_sdp *sdp)
3070{
3071 size_t length = sizeof(struct dp_sdp);
3072
3073 memset(sdp, 0, sizeof(struct dp_sdp));
3074
3075 /*
3076 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3077 * VSC SDP Header Bytes
3078 */
3079 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3080 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3081 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3082 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3083
3084 if (vsc->revision == 0x6) {
3085 sdp->db[0] = 1;
3086 sdp->db[3] = 1;
3087 }
3088
3089 /*
3090 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
3091 * Format as per DP 1.4a spec and DP 2.0 respectively.
3092 */
3093 if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
3094 goto out;
3095
3096 /* VSC SDP Payload for DB16 through DB18 */
3097 /* Pixel Encoding and Colorimetry Formats */
3098 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3099 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3100
3101 switch (vsc->bpc) {
3102 case 6:
3103 /* 6bpc: 0x0 */
3104 break;
3105 case 8:
3106 sdp->db[17] = 0x1; /* DB17[3:0] */
3107 break;
3108 case 10:
3109 sdp->db[17] = 0x2;
3110 break;
3111 case 12:
3112 sdp->db[17] = 0x3;
3113 break;
3114 case 16:
3115 sdp->db[17] = 0x4;
3116 break;
3117 default:
3118 WARN(1, "Missing case %d\n", vsc->bpc);
3119 return -EINVAL;
3120 }
3121
3122 /* Dynamic Range and Component Bit Depth */
3123 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3124 sdp->db[17] |= 0x80; /* DB17[7] */
3125
3126 /* Content Type */
3127 sdp->db[18] = vsc->content_type & 0x7;
3128
3129out:
3130 return length;
3131}
3132EXPORT_SYMBOL(drm_dp_vsc_sdp_pack);
3133
3134/**
3135 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
3136 * @dpcd: DisplayPort configuration data
3137 * @port_cap: port capabilities
3138 *
3139 * Returns maximum frl bandwidth supported by PCON in GBPS,
3140 * returns 0 if not supported.
3141 */
3142int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3143 const u8 port_cap[4])
3144{
3145 int bw;
3146 u8 buf;
3147
3148 buf = port_cap[2];
3149 bw = buf & DP_PCON_MAX_FRL_BW;
3150
3151 switch (bw) {
3152 case DP_PCON_MAX_9GBPS:
3153 return 9;
3154 case DP_PCON_MAX_18GBPS:
3155 return 18;
3156 case DP_PCON_MAX_24GBPS:
3157 return 24;
3158 case DP_PCON_MAX_32GBPS:
3159 return 32;
3160 case DP_PCON_MAX_40GBPS:
3161 return 40;
3162 case DP_PCON_MAX_48GBPS:
3163 return 48;
3164 case DP_PCON_MAX_0GBPS:
3165 default:
3166 return 0;
3167 }
3168
3169 return 0;
3170}
3171EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
3172
3173/**
3174 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
3175 * @aux: DisplayPort AUX channel
3176 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
3177 *
3178 * Returns 0 if success, else returns negative error code.
3179 */
3180int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
3181{
3182 int ret;
3183 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
3184 DP_PCON_ENABLE_LINK_FRL_MODE;
3185
3186 if (enable_frl_ready_hpd)
3187 buf |= DP_PCON_ENABLE_HPD_READY;
3188
3189 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3190
3191 return ret;
3192}
3193EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
3194
3195/**
3196 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3197 * @aux: DisplayPort AUX channel
3198 *
3199 * Returns true if success, else returns false.
3200 */
3201bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
3202{
3203 int ret;
3204 u8 buf;
3205
3206 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3207 if (ret < 0)
3208 return false;
3209
3210 if (buf & DP_PCON_FRL_READY)
3211 return true;
3212
3213 return false;
3214}
3215EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
3216
3217/**
3218 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3219 * @aux: DisplayPort AUX channel
3220 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
3221 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
3222 * In Concurrent Mode, the FRL link bring up can be done along with
3223 * DP Link training. In Sequential mode, the FRL link bring up is done prior to
3224 * the DP Link training.
3225 *
3226 * Returns 0 if success, else returns negative error code.
3227 */
3228
3229int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
3230 u8 frl_mode)
3231{
3232 int ret;
3233 u8 buf;
3234
3235 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3236 if (ret < 0)
3237 return ret;
3238
3239 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
3240 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
3241 else
3242 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
3243
3244 switch (max_frl_gbps) {
3245 case 9:
3246 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS;
3247 break;
3248 case 18:
3249 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS;
3250 break;
3251 case 24:
3252 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS;
3253 break;
3254 case 32:
3255 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS;
3256 break;
3257 case 40:
3258 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS;
3259 break;
3260 case 48:
3261 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS;
3262 break;
3263 case 0:
3264 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS;
3265 break;
3266 default:
3267 return -EINVAL;
3268 }
3269
3270 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3271 if (ret < 0)
3272 return ret;
3273
3274 return 0;
3275}
3276EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3277
3278/**
3279 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3280 * @aux: DisplayPort AUX channel
3281 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3282 * @frl_type : FRL training type, can be Extended, or Normal.
3283 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3284 * starting from min, and stops when link training is successful. In Extended
3285 * FRL training, all frl bw selected in the mask are trained by the PCON.
3286 *
3287 * Returns 0 if success, else returns negative error code.
3288 */
3289int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3290 u8 frl_type)
3291{
3292 int ret;
3293 u8 buf = max_frl_mask;
3294
3295 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3296 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3297 else
3298 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3299
3300 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
3301 if (ret < 0)
3302 return ret;
3303
3304 return 0;
3305}
3306EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3307
3308/**
3309 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3310 * @aux: DisplayPort AUX channel
3311 *
3312 * Returns 0 if success, else returns negative error code.
3313 */
3314int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3315{
3316 int ret;
3317
3318 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
3319 if (ret < 0)
3320 return ret;
3321
3322 return 0;
3323}
3324EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3325
3326/**
3327 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3328 * @aux: DisplayPort AUX channel
3329 *
3330 * Returns 0 if success, else returns negative error code.
3331 */
3332int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3333{
3334 int ret;
3335 u8 buf = 0;
3336
3337 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3338 if (ret < 0)
3339 return ret;
3340 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3341 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3342 aux->name);
3343 return -EINVAL;
3344 }
3345 buf |= DP_PCON_ENABLE_HDMI_LINK;
3346 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3347 if (ret < 0)
3348 return ret;
3349
3350 return 0;
3351}
3352EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3353
3354/**
3355 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3356 * @aux: DisplayPort AUX channel
3357 *
3358 * Returns true if link is active else returns false.
3359 */
3360bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3361{
3362 u8 buf;
3363 int ret;
3364
3365 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3366 if (ret < 0)
3367 return false;
3368
3369 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3370}
3371EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3372
3373/**
3374 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3375 * @aux: DisplayPort AUX channel
3376 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3377 * Valid only if the MODE returned is FRL. For Normal Link training mode
3378 * only 1 of the bits will be set, but in case of Extended mode, more than
3379 * one bits can be set.
3380 *
3381 * Returns the link mode : TMDS or FRL on success, else returns negative error
3382 * code.
3383 */
3384int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3385{
3386 u8 buf;
3387 int mode;
3388 int ret;
3389
3390 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
3391 if (ret < 0)
3392 return ret;
3393
3394 mode = buf & DP_PCON_HDMI_LINK_MODE;
3395
3396 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3397 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3398
3399 return mode;
3400}
3401EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3402
3403/**
3404 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3405 * during link failure between PCON and HDMI sink
3406 * @aux: DisplayPort AUX channel
3407 * @connector: DRM connector
3408 * code.
3409 **/
3410
3411void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3412 struct drm_connector *connector)
3413{
3414 u8 buf, error_count;
3415 int i, num_error;
3416 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3417
3418 for (i = 0; i < hdmi->max_lanes; i++) {
3419 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
3420 return;
3421
3422 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3423 switch (error_count) {
3424 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3425 num_error = 100;
3426 break;
3427 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3428 num_error = 10;
3429 break;
3430 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3431 num_error = 3;
3432 break;
3433 default:
3434 num_error = 0;
3435 }
3436
3437 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3438 aux->name, num_error, i);
3439 }
3440}
3441EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3442
3443/*
3444 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3445 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3446 *
3447 * Returns true is PCON encoder is DSC 1.2 else returns false.
3448 */
3449bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3450{
3451 u8 buf;
3452 u8 major_v, minor_v;
3453
3454 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3455 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3456 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3457
3458 if (major_v == 1 && minor_v == 2)
3459 return true;
3460
3461 return false;
3462}
3463EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3464
3465/*
3466 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3467 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3468 *
3469 * Returns maximum no. of slices supported by the PCON DSC Encoder.
3470 */
3471int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3472{
3473 u8 slice_cap1, slice_cap2;
3474
3475 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3476 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3477
3478 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3479 return 24;
3480 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3481 return 20;
3482 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3483 return 16;
3484 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3485 return 12;
3486 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3487 return 10;
3488 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3489 return 8;
3490 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3491 return 6;
3492 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3493 return 4;
3494 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3495 return 2;
3496 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3497 return 1;
3498
3499 return 0;
3500}
3501EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3502
3503/*
3504 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3505 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3506 *
3507 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3508 */
3509int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3510{
3511 u8 buf;
3512
3513 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3514
3515 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3516}
3517EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3518
3519/*
3520 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3521 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3522 *
3523 * Returns the bpp precision supported by the PCON encoder.
3524 */
3525int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3526{
3527 u8 buf;
3528
3529 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3530
3531 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3532 case DP_PCON_DSC_ONE_16TH_BPP:
3533 return 16;
3534 case DP_PCON_DSC_ONE_8TH_BPP:
3535 return 8;
3536 case DP_PCON_DSC_ONE_4TH_BPP:
3537 return 4;
3538 case DP_PCON_DSC_ONE_HALF_BPP:
3539 return 2;
3540 case DP_PCON_DSC_ONE_BPP:
3541 return 1;
3542 }
3543
3544 return 0;
3545}
3546EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3547
3548static
3549int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3550{
3551 u8 buf;
3552 int ret;
3553
3554 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3555 if (ret < 0)
3556 return ret;
3557
3558 buf |= DP_PCON_ENABLE_DSC_ENCODER;
3559
3560 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3561 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3562 buf |= pps_buf_config << 2;
3563 }
3564
3565 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3566 if (ret < 0)
3567 return ret;
3568
3569 return 0;
3570}
3571
3572/**
3573 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3574 * for DSC1.2 between PCON & HDMI2.1 sink
3575 * @aux: DisplayPort AUX channel
3576 *
3577 * Returns 0 on success, else returns negative error code.
3578 */
3579int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3580{
3581 int ret;
3582
3583 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3584 if (ret < 0)
3585 return ret;
3586
3587 return 0;
3588}
3589EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3590
3591/**
3592 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3593 * HDMI sink
3594 * @aux: DisplayPort AUX channel
3595 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3596 *
3597 * Returns 0 on success, else returns negative error code.
3598 */
3599int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3600{
3601 int ret;
3602
3603 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3604 if (ret < 0)
3605 return ret;
3606
3607 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3608 if (ret < 0)
3609 return ret;
3610
3611 return 0;
3612}
3613EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3614
3615/*
3616 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3617 * override registers
3618 * @aux: DisplayPort AUX channel
3619 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3620 * bits_per_pixel.
3621 *
3622 * Returns 0 on success, else returns negative error code.
3623 */
3624int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3625{
3626 int ret;
3627
3628 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3629 if (ret < 0)
3630 return ret;
3631 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3632 if (ret < 0)
3633 return ret;
3634 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3635 if (ret < 0)
3636 return ret;
3637
3638 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3639 if (ret < 0)
3640 return ret;
3641
3642 return 0;
3643}
3644EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3645
3646/*
3647 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3648 * @aux: displayPort AUX channel
3649 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3650 *
3651 * Returns 0 on success, else returns negative error code.
3652 */
3653int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3654{
3655 int ret;
3656 u8 buf;
3657
3658 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3659 if (ret < 0)
3660 return ret;
3661
3662 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3663 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3664 else
3665 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3666
3667 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3668 if (ret < 0)
3669 return ret;
3670
3671 return 0;
3672}
3673EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3674
3675/**
3676 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3677 * @aux: The DP AUX channel to use
3678 * @bl: Backlight capability info from drm_edp_backlight_init()
3679 * @level: The brightness level to set
3680 *
3681 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3682 * already have been enabled by the driver by calling drm_edp_backlight_enable().
3683 *
3684 * Returns: %0 on success, negative error code on failure
3685 */
3686int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3687 u16 level)
3688{
3689 int ret;
3690 u8 buf[2] = { 0 };
3691
3692 /* The panel uses the PWM for controlling brightness levels */
3693 if (!bl->aux_set)
3694 return 0;
3695
3696 if (bl->lsb_reg_used) {
3697 buf[0] = (level & 0xff00) >> 8;
3698 buf[1] = (level & 0x00ff);
3699 } else {
3700 buf[0] = level;
3701 }
3702
3703 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3704 if (ret != sizeof(buf)) {
3705 drm_err(aux->drm_dev,
3706 "%s: Failed to write aux backlight level: %d\n",
3707 aux->name, ret);
3708 return ret < 0 ? ret : -EIO;
3709 }
3710
3711 return 0;
3712}
3713EXPORT_SYMBOL(drm_edp_backlight_set_level);
3714
3715static int
3716drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3717 bool enable)
3718{
3719 int ret;
3720 u8 buf;
3721
3722 /* This panel uses the EDP_BL_PWR GPIO for enablement */
3723 if (!bl->aux_enable)
3724 return 0;
3725
3726 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3727 if (ret != 1) {
3728 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3729 aux->name, ret);
3730 return ret < 0 ? ret : -EIO;
3731 }
3732 if (enable)
3733 buf |= DP_EDP_BACKLIGHT_ENABLE;
3734 else
3735 buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3736
3737 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3738 if (ret != 1) {
3739 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3740 aux->name, ret);
3741 return ret < 0 ? ret : -EIO;
3742 }
3743
3744 return 0;
3745}
3746
3747/**
3748 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3749 * @aux: The DP AUX channel to use
3750 * @bl: Backlight capability info from drm_edp_backlight_init()
3751 * @level: The initial backlight level to set via AUX, if there is one
3752 *
3753 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
3754 * restoring any important backlight state such as the given backlight level, the brightness byte
3755 * count, backlight frequency, etc.
3756 *
3757 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3758 * that the driver handle enabling/disabling the panel through implementation-specific means using
3759 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3760 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3761 * the EDP_BL_PWR GPIO.
3762 *
3763 * Returns: %0 on success, negative error code on failure.
3764 */
3765int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3766 const u16 level)
3767{
3768 int ret;
3769 u8 dpcd_buf;
3770
3771 if (bl->aux_set)
3772 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3773 else
3774 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
3775
3776 if (bl->pwmgen_bit_count) {
3777 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3778 if (ret != 1)
3779 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3780 aux->name, ret);
3781 }
3782
3783 if (bl->pwm_freq_pre_divider) {
3784 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3785 if (ret != 1)
3786 drm_dbg_kms(aux->drm_dev,
3787 "%s: Failed to write aux backlight frequency: %d\n",
3788 aux->name, ret);
3789 else
3790 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3791 }
3792
3793 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);
3794 if (ret != 1) {
3795 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3796 aux->name, ret);
3797 return ret < 0 ? ret : -EIO;
3798 }
3799
3800 ret = drm_edp_backlight_set_level(aux, bl, level);
3801 if (ret < 0)
3802 return ret;
3803 ret = drm_edp_backlight_set_enable(aux, bl, true);
3804 if (ret < 0)
3805 return ret;
3806
3807 return 0;
3808}
3809EXPORT_SYMBOL(drm_edp_backlight_enable);
3810
3811/**
3812 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3813 * @aux: The DP AUX channel to use
3814 * @bl: Backlight capability info from drm_edp_backlight_init()
3815 *
3816 * This function handles disabling DPCD backlight controls on a panel over AUX.
3817 *
3818 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3819 * that the driver handle enabling/disabling the panel through implementation-specific means using
3820 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3821 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3822 * the EDP_BL_PWR GPIO.
3823 *
3824 * Returns: %0 on success or no-op, negative error code on failure.
3825 */
3826int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3827{
3828 int ret;
3829
3830 ret = drm_edp_backlight_set_enable(aux, bl, false);
3831 if (ret < 0)
3832 return ret;
3833
3834 return 0;
3835}
3836EXPORT_SYMBOL(drm_edp_backlight_disable);
3837
3838static inline int
3839drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3840 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3841{
3842 int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3843 int ret;
3844 u8 pn, pn_min, pn_max;
3845
3846 if (!bl->aux_set)
3847 return 0;
3848
3849 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3850 if (ret != 1) {
3851 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3852 aux->name, ret);
3853 return -ENODEV;
3854 }
3855
3856 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3857 bl->max = (1 << pn) - 1;
3858 if (!driver_pwm_freq_hz)
3859 return 0;
3860
3861 /*
3862 * Set PWM Frequency divider to match desired frequency provided by the driver.
3863 * The PWM Frequency is calculated as 27Mhz / (F x P).
3864 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
3865 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
3866 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
3867 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
3868 */
3869
3870 /* Find desired value of (F x P)
3871 * Note that, if F x P is out of supported range, the maximum value or minimum value will
3872 * applied automatically. So no need to check that.
3873 */
3874 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3875
3876 /* Use highest possible value of Pn for more granularity of brightness adjustment while
3877 * satisfying the conditions below.
3878 * - Pn is in the range of Pn_min and Pn_max
3879 * - F is in the range of 1 and 255
3880 * - FxP is within 25% of desired value.
3881 * Note: 25% is arbitrary value and may need some tweak.
3882 */
3883 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3884 if (ret != 1) {
3885 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3886 aux->name, ret);
3887 return 0;
3888 }
3889 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3890 if (ret != 1) {
3891 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3892 aux->name, ret);
3893 return 0;
3894 }
3895 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3896 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3897
3898 /* Ensure frequency is within 25% of desired value */
3899 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3900 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3901 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3902 drm_dbg_kms(aux->drm_dev,
3903 "%s: Driver defined backlight frequency (%d) out of range\n",
3904 aux->name, driver_pwm_freq_hz);
3905 return 0;
3906 }
3907
3908 for (pn = pn_max; pn >= pn_min; pn--) {
3909 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3910 fxp_actual = f << pn;
3911 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3912 break;
3913 }
3914
3915 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3916 if (ret != 1) {
3917 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3918 aux->name, ret);
3919 return 0;
3920 }
3921 bl->pwmgen_bit_count = pn;
3922 bl->max = (1 << pn) - 1;
3923
3924 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3925 bl->pwm_freq_pre_divider = f;
3926 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3927 aux->name, driver_pwm_freq_hz);
3928 }
3929
3930 return 0;
3931}
3932
3933static inline int
3934drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3935 u8 *current_mode)
3936{
3937 int ret;
3938 u8 buf[2];
3939 u8 mode_reg;
3940
3941 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3942 if (ret != 1) {
3943 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3944 aux->name, ret);
3945 return ret < 0 ? ret : -EIO;
3946 }
3947
3948 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3949 if (!bl->aux_set)
3950 return 0;
3951
3952 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3953 int size = 1 + bl->lsb_reg_used;
3954
3955 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3956 if (ret != size) {
3957 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3958 aux->name, ret);
3959 return ret < 0 ? ret : -EIO;
3960 }
3961
3962 if (bl->lsb_reg_used)
3963 return (buf[0] << 8) | buf[1];
3964 else
3965 return buf[0];
3966 }
3967
3968 /*
3969 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
3970 * the driver should assume max brightness
3971 */
3972 return bl->max;
3973}
3974
3975/**
3976 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3977 * interface.
3978 * @aux: The DP aux device to use for probing
3979 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
3980 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
3981 * @edp_dpcd: A cached copy of the eDP DPCD
3982 * @current_level: Where to store the probed brightness level, if any
3983 * @current_mode: Where to store the currently set backlight control mode
3984 *
3985 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3986 * along with also probing the current and maximum supported brightness levels.
3987 *
3988 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3989 * default frequency from the panel is used.
3990 *
3991 * Returns: %0 on success, negative error code on failure.
3992 */
3993int
3994drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3995 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3996 u16 *current_level, u8 *current_mode)
3997{
3998 int ret;
3999
4000 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
4001 bl->aux_enable = true;
4002 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
4003 bl->aux_set = true;
4004 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
4005 bl->lsb_reg_used = true;
4006
4007 /* Sanity check caps */
4008 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
4009 drm_dbg_kms(aux->drm_dev,
4010 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
4011 aux->name);
4012 return -EINVAL;
4013 }
4014
4015 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
4016 if (ret < 0)
4017 return ret;
4018
4019 ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
4020 if (ret < 0)
4021 return ret;
4022 *current_level = ret;
4023
4024 drm_dbg_kms(aux->drm_dev,
4025 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
4026 aux->name, bl->aux_set, bl->aux_enable, *current_mode);
4027 if (bl->aux_set) {
4028 drm_dbg_kms(aux->drm_dev,
4029 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
4030 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
4031 bl->lsb_reg_used);
4032 }
4033
4034 return 0;
4035}
4036EXPORT_SYMBOL(drm_edp_backlight_init);
4037
4038#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
4039 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
4040
4041static int dp_aux_backlight_update_status(struct backlight_device *bd)
4042{
4043 struct dp_aux_backlight *bl = bl_get_data(bd);
4044 u16 brightness = backlight_get_brightness(bd);
4045 int ret = 0;
4046
4047 if (!backlight_is_blank(bd)) {
4048 if (!bl->enabled) {
4049 drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
4050 bl->enabled = true;
4051 return 0;
4052 }
4053 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
4054 } else {
4055 if (bl->enabled) {
4056 drm_edp_backlight_disable(bl->aux, &bl->info);
4057 bl->enabled = false;
4058 }
4059 }
4060
4061 return ret;
4062}
4063
4064static const struct backlight_ops dp_aux_bl_ops = {
4065 .update_status = dp_aux_backlight_update_status,
4066};
4067
4068/**
4069 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
4070 * @panel: DRM panel
4071 * @aux: The DP AUX channel to use
4072 *
4073 * Use this function to create and handle backlight if your panel
4074 * supports backlight control over DP AUX channel using DPCD
4075 * registers as per VESA's standard backlight control interface.
4076 *
4077 * When the panel is enabled backlight will be enabled after a
4078 * successful call to &drm_panel_funcs.enable()
4079 *
4080 * When the panel is disabled backlight will be disabled before the
4081 * call to &drm_panel_funcs.disable().
4082 *
4083 * A typical implementation for a panel driver supporting backlight
4084 * control over DP AUX will call this function at probe time.
4085 * Backlight will then be handled transparently without requiring
4086 * any intervention from the driver.
4087 *
4088 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
4089 *
4090 * Return: 0 on success or a negative error code on failure.
4091 */
4092int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
4093{
4094 struct dp_aux_backlight *bl;
4095 struct backlight_properties props = { 0 };
4096 u16 current_level;
4097 u8 current_mode;
4098 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
4099 int ret;
4100
4101 if (!panel || !panel->dev || !aux)
4102 return -EINVAL;
4103
4104 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
4105 EDP_DISPLAY_CTL_CAP_SIZE);
4106 if (ret < 0)
4107 return ret;
4108
4109 if (!drm_edp_backlight_supported(edp_dpcd)) {
4110 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
4111 return 0;
4112 }
4113
4114 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
4115 if (!bl)
4116 return -ENOMEM;
4117
4118 bl->aux = aux;
4119
4120 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
4121 ¤t_level, ¤t_mode);
4122 if (ret < 0)
4123 return ret;
4124
4125 props.type = BACKLIGHT_RAW;
4126 props.brightness = current_level;
4127 props.max_brightness = bl->info.max;
4128
4129 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
4130 panel->dev, bl,
4131 &dp_aux_bl_ops, &props);
4132 if (IS_ERR(bl->base))
4133 return PTR_ERR(bl->base);
4134
4135 backlight_disable(bl->base);
4136
4137 panel->backlight = bl->base;
4138
4139 return 0;
4140}
4141EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
4142
4143#endif
4144
4145/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
4146static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
4147 int symbol_size, bool is_mst)
4148{
4149 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
4150 int align = is_mst ? 4 / lane_count : 1;
4151
4152 return ALIGN(cycles, align);
4153}
4154
4155static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
4156 int bpp_x16, int symbol_size, bool is_mst)
4157{
4158 int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
4159 int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
4160 bpp_x16, symbol_size, is_mst);
4161 int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
4162
4163 return slice_count * (slice_data_cycles + slice_eoc_cycles);
4164}
4165
4166/**
4167 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
4168 * @lane_count: DP link lane count
4169 * @hactive: pixel count of the active period in one scanline of the stream
4170 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
4171 * @bpp_x16: bits per pixel in .4 binary fixed point
4172 * @flags: DRM_DP_OVERHEAD_x flags
4173 *
4174 * Calculate the BW allocation overhead of a DP link stream, depending
4175 * on the link's
4176 * - @lane_count
4177 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
4178 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
4179 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
4180 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
4181 * as well as the stream's
4182 * - @hactive timing
4183 * - @bpp_x16 color depth
4184 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
4185 * Note that this overhead doesn't account for the 8b/10b, 128b/132b
4186 * channel coding efficiency, for that see
4187 * @drm_dp_link_bw_channel_coding_efficiency().
4188 *
4189 * Returns the overhead as 100% + overhead% in 1ppm units.
4190 */
4191int drm_dp_bw_overhead(int lane_count, int hactive,
4192 int dsc_slice_count,
4193 int bpp_x16, unsigned long flags)
4194{
4195 int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
4196 bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
4197 u32 overhead = 1000000;
4198 int symbol_cycles;
4199
4200 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
4201 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 " FXP_Q4_FMT "\n",
4202 lane_count, hactive,
4203 FXP_Q4_ARGS(bpp_x16));
4204 return 0;
4205 }
4206
4207 /*
4208 * DP Standard v2.1 2.6.4.1
4209 * SSC downspread and ref clock variation margin:
4210 * 5300ppm + 300ppm ~ 0.6%
4211 */
4212 if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
4213 overhead += 6000;
4214
4215 /*
4216 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
4217 * FEC symbol insertions for 8b/10b channel coding:
4218 * After each 250 data symbols on 2-4 lanes:
4219 * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
4220 * After each 2 x 250 data symbols on 1 lane:
4221 * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
4222 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
4223 * 256 * 256 bytes + 1 FEC_PM
4224 * or
4225 * 128 * 512 bytes + 1 FEC_PM
4226 * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
4227 */
4228 if (flags & DRM_DP_BW_OVERHEAD_FEC)
4229 overhead += 24016;
4230
4231 /*
4232 * DP Standard v2.1 2.7.9, 5.9.7
4233 * The FEC overhead for UHBR is accounted for in its 96.71% channel
4234 * coding efficiency.
4235 */
4236 WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
4237 (flags & DRM_DP_BW_OVERHEAD_FEC));
4238
4239 if (flags & DRM_DP_BW_OVERHEAD_DSC)
4240 symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
4241 dsc_slice_count,
4242 bpp_x16, symbol_size,
4243 is_mst);
4244 else
4245 symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
4246 bpp_x16, symbol_size,
4247 is_mst);
4248
4249 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4250 overhead * 16),
4251 hactive * bpp_x16);
4252}
4253EXPORT_SYMBOL(drm_dp_bw_overhead);
4254
4255/**
4256 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4257 * @is_uhbr: Whether the link has a 128b/132b channel coding
4258 *
4259 * Return the channel coding efficiency of the given DP link type, which is
4260 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
4261 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4262 * and for 128b/132b any link or PHY level control symbol insertion overhead
4263 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4264 * corresponding FEC overhead is BW allocation specific, included in the value
4265 * returned by drm_dp_bw_overhead().
4266 *
4267 * Returns the efficiency in the 100%/coding-overhead% ratio in
4268 * 1ppm units.
4269 */
4270int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
4271{
4272 if (is_uhbr)
4273 return 967100;
4274 else
4275 /*
4276 * Note that on 8b/10b MST the efficiency is only
4277 * 78.75% due to the 1 out of 64 MTPH packet overhead,
4278 * not accounted for here.
4279 */
4280 return 800000;
4281}
4282EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
4283
4284/**
4285 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
4286 * @max_link_rate: max DPRX link rate in 10kbps units
4287 * @max_lanes: max DPRX lane count
4288 *
4289 * Given a link rate and lanes, get the data bandwidth.
4290 *
4291 * Data bandwidth is the actual payload rate, which depends on the data
4292 * bandwidth efficiency and the link rate.
4293 *
4294 * Note that protocol layers above the DPRX link level considered here can
4295 * further limit the maximum data rate. Such layers are the MST topology (with
4296 * limits on the link between the source and first branch device as well as on
4297 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
4298 * which in turn can encapsulate an MST link with its own limit - with each
4299 * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
4300 *
4301 * Returns the maximum data rate in kBps units.
4302 */
4303int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
4304{
4305 int ch_coding_efficiency =
4306 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
4307
4308 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
4309 ch_coding_efficiency),
4310 1000000 * 8);
4311}
4312EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);