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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7#include <linux/atomic.h>
8#include <linux/auxiliary_bus.h>
9#include <linux/bitfield.h>
10#include <linux/bits.h>
11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/gpio/consumer.h>
14#include <linux/gpio/driver.h>
15#include <linux/i2c.h>
16#include <linux/iopoll.h>
17#include <linux/module.h>
18#include <linux/of_graph.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23
24#include <linux/unaligned.h>
25
26#include <drm/display/drm_dp_aux_bus.h>
27#include <drm/display/drm_dp_helper.h>
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_bridge.h>
31#include <drm/drm_bridge_connector.h>
32#include <drm/drm_edid.h>
33#include <drm/drm_mipi_dsi.h>
34#include <drm/drm_of.h>
35#include <drm/drm_panel.h>
36#include <drm/drm_print.h>
37#include <drm/drm_probe_helper.h>
38
39#define SN_DEVICE_REV_REG 0x08
40#define SN_DPPLL_SRC_REG 0x0A
41#define DPPLL_CLK_SRC_DSICLK BIT(0)
42#define REFCLK_FREQ_MASK GENMASK(3, 1)
43#define REFCLK_FREQ(x) ((x) << 1)
44#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45#define SN_PLL_ENABLE_REG 0x0D
46#define SN_DSI_LANES_REG 0x10
47#define CHA_DSI_LANES_MASK GENMASK(4, 3)
48#define CHA_DSI_LANES(x) ((x) << 3)
49#define SN_DSIA_CLK_FREQ_REG 0x12
50#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54#define CHA_HSYNC_POLARITY BIT(7)
55#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57#define CHA_VSYNC_POLARITY BIT(7)
58#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62#define SN_LN_ASSIGN_REG 0x59
63#define LN_ASSIGN_WIDTH 2
64#define SN_ENH_FRAME_REG 0x5A
65#define VSTREAM_ENABLE BIT(3)
66#define LN_POLRS_OFFSET 4
67#define LN_POLRS_MASK 0xf0
68#define SN_DATA_FORMAT_REG 0x5B
69#define BPP_18_RGB BIT(0)
70#define SN_HPD_DISABLE_REG 0x5C
71#define HPD_DISABLE BIT(0)
72#define HPD_DEBOUNCED_STATE BIT(4)
73#define SN_GPIO_IO_REG 0x5E
74#define SN_GPIO_INPUT_SHIFT 4
75#define SN_GPIO_OUTPUT_SHIFT 0
76#define SN_GPIO_CTRL_REG 0x5F
77#define SN_GPIO_MUX_INPUT 0
78#define SN_GPIO_MUX_OUTPUT 1
79#define SN_GPIO_MUX_SPECIAL 2
80#define SN_GPIO_MUX_MASK 0x3
81#define SN_AUX_WDATA_REG(x) (0x64 + (x))
82#define SN_AUX_ADDR_19_16_REG 0x74
83#define SN_AUX_ADDR_15_8_REG 0x75
84#define SN_AUX_ADDR_7_0_REG 0x76
85#define SN_AUX_ADDR_MASK GENMASK(19, 0)
86#define SN_AUX_LENGTH_REG 0x77
87#define SN_AUX_CMD_REG 0x78
88#define AUX_CMD_SEND BIT(0)
89#define AUX_CMD_REQ(x) ((x) << 4)
90#define SN_AUX_RDATA_REG(x) (0x79 + (x))
91#define SN_SSC_CONFIG_REG 0x93
92#define DP_NUM_LANES_MASK GENMASK(5, 4)
93#define DP_NUM_LANES(x) ((x) << 4)
94#define SN_DATARATE_CONFIG_REG 0x94
95#define DP_DATARATE_MASK GENMASK(7, 5)
96#define DP_DATARATE(x) ((x) << 5)
97#define SN_TRAINING_SETTING_REG 0x95
98#define SCRAMBLE_DISABLE BIT(4)
99#define SN_ML_TX_MODE_REG 0x96
100#define ML_TX_MAIN_LINK_OFF 0
101#define ML_TX_NORMAL_MODE BIT(0)
102#define SN_PWM_PRE_DIV_REG 0xA0
103#define SN_BACKLIGHT_SCALE_REG 0xA1
104#define BACKLIGHT_SCALE_MAX 0xFFFF
105#define SN_BACKLIGHT_REG 0xA3
106#define SN_PWM_EN_INV_REG 0xA5
107#define SN_PWM_INV_MASK BIT(0)
108#define SN_PWM_EN_MASK BIT(1)
109#define SN_AUX_CMD_STATUS_REG 0xF4
110#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111#define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
113
114#define MIN_DSI_CLK_FREQ_MHZ 40
115
116/* fudge factor required to account for 8b/10b encoding */
117#define DP_CLK_FUDGE_NUM 10
118#define DP_CLK_FUDGE_DEN 8
119
120/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121#define SN_AUX_MAX_PAYLOAD_BYTES 16
122
123#define SN_REGULATOR_SUPPLY_NUM 4
124
125#define SN_MAX_DP_LANES 4
126#define SN_NUM_GPIOS 4
127#define SN_GPIO_PHYSICAL_OFFSET 1
128
129#define SN_LINK_TRAINING_TRIES 10
130
131#define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
132
133/**
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
139 *
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
156 *
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
166 *
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
171 */
172struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
177
178 struct device *dev;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
185 struct clk *refclk;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
189 int dp_lanes;
190 u8 ln_assign;
191 u8 ln_polrs;
192 bool comms_enabled;
193 struct mutex comms_mutex;
194
195#if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
198#endif
199#if defined(CONFIG_PWM)
200 struct pwm_chip *pchip;
201 bool pwm_enabled;
202 atomic_t pwm_pin_busy;
203#endif
204 unsigned int pwm_refclk_freq;
205};
206
207static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
209};
210
211static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
214};
215
216static const struct regmap_config ti_sn65dsi86_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
222};
223
224static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
226{
227 u8 buf[2];
228 int ret;
229
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
231 if (ret)
232 return ret;
233
234 *val = buf[0] | (buf[1] << 8);
235
236 return 0;
237}
238
239static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
241{
242 u8 buf[2] = { val & 0xff, val >> 8 };
243
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
245}
246
247static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
248{
249 u32 bit_rate_khz, clk_freq_khz;
250 struct drm_display_mode *mode =
251 &pdata->bridge.encoder->crtc->state->adjusted_mode;
252
253 bit_rate_khz = mode->clock *
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
256
257 return clk_freq_khz;
258}
259
260/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
261static const u32 ti_sn_bridge_refclk_lut[] = {
262 12000000,
263 19200000,
264 26000000,
265 27000000,
266 38400000,
267};
268
269/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
270static const u32 ti_sn_bridge_dsiclk_lut[] = {
271 468000000,
272 384000000,
273 416000000,
274 486000000,
275 460800000,
276};
277
278static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
279{
280 int i;
281 u32 refclk_rate;
282 const u32 *refclk_lut;
283 size_t refclk_lut_size;
284
285 if (pdata->refclk) {
286 refclk_rate = clk_get_rate(pdata->refclk);
287 refclk_lut = ti_sn_bridge_refclk_lut;
288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
289 clk_prepare_enable(pdata->refclk);
290 } else {
291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
292 refclk_lut = ti_sn_bridge_dsiclk_lut;
293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
294 }
295
296 /* for i equals to refclk_lut_size means default frequency */
297 for (i = 0; i < refclk_lut_size; i++)
298 if (refclk_lut[i] == refclk_rate)
299 break;
300
301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
302 if (i >= refclk_lut_size)
303 i = 1;
304
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
306 REFCLK_FREQ(i));
307
308 /*
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
310 * regardless of its actual sourcing.
311 */
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
313}
314
315static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
316{
317 mutex_lock(&pdata->comms_mutex);
318
319 /* configure bridge ref_clk */
320 ti_sn_bridge_set_refclk_freq(pdata);
321
322 /*
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge
324 * so the HPD is an internal signal that's only there to signal that
325 * the panel is done powering up. ...but the bridge chip debounces
326 * this signal by between 100 ms and 400 ms (depending on process,
327 * voltage, and temperate--I measured it at about 200 ms). One
328 * particular panel asserted HPD 84 ms after it was powered on meaning
329 * that we saw HPD 284 ms after power on. ...but the same panel said
330 * that instead of looking at HPD you could just hardcode a delay of
331 * 200 ms. We'll assume that the panel driver will have the hardcoded
332 * delay in its prepare and always disable HPD.
333 *
334 * If HPD somehow makes sense on some future panel we'll have to
335 * change this to be conditional on someone specifying that HPD should
336 * be used.
337 */
338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
339 HPD_DISABLE);
340
341 pdata->comms_enabled = true;
342
343 mutex_unlock(&pdata->comms_mutex);
344}
345
346static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
347{
348 mutex_lock(&pdata->comms_mutex);
349
350 pdata->comms_enabled = false;
351 clk_disable_unprepare(pdata->refclk);
352
353 mutex_unlock(&pdata->comms_mutex);
354}
355
356static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
357{
358 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
359 int ret;
360
361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
362 if (ret) {
363 DRM_ERROR("failed to enable supplies %d\n", ret);
364 return ret;
365 }
366
367 /* td2: min 100 us after regulators before enabling the GPIO */
368 usleep_range(100, 110);
369
370 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
371
372 /*
373 * If we have a reference clock we can enable communication w/ the
374 * panel (including the aux channel) w/out any need for an input clock
375 * so we can do it in resume which lets us read the EDID before
376 * pre_enable(). Without a reference clock we need the MIPI reference
377 * clock so reading early doesn't work.
378 */
379 if (pdata->refclk)
380 ti_sn65dsi86_enable_comms(pdata);
381
382 return ret;
383}
384
385static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
386{
387 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
388 int ret;
389
390 if (pdata->refclk)
391 ti_sn65dsi86_disable_comms(pdata);
392
393 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
394
395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
396 if (ret)
397 DRM_ERROR("failed to disable supplies %d\n", ret);
398
399 return ret;
400}
401
402static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
403 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
404 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
405 pm_runtime_force_resume)
406};
407
408static int status_show(struct seq_file *s, void *data)
409{
410 struct ti_sn65dsi86 *pdata = s->private;
411 unsigned int reg, val;
412
413 seq_puts(s, "STATUS REGISTERS:\n");
414
415 pm_runtime_get_sync(pdata->dev);
416
417 /* IRQ Status Registers, see Table 31 in datasheet */
418 for (reg = 0xf0; reg <= 0xf8; reg++) {
419 regmap_read(pdata->regmap, reg, &val);
420 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
421 }
422
423 pm_runtime_put_autosuspend(pdata->dev);
424
425 return 0;
426}
427
428DEFINE_SHOW_ATTRIBUTE(status);
429
430static void ti_sn65dsi86_debugfs_remove(void *data)
431{
432 debugfs_remove_recursive(data);
433}
434
435static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
436{
437 struct device *dev = pdata->dev;
438 struct dentry *debugfs;
439 int ret;
440
441 debugfs = debugfs_create_dir(dev_name(dev), NULL);
442
443 /*
444 * We might get an error back if debugfs wasn't enabled in the kernel
445 * so let's just silently return upon failure.
446 */
447 if (IS_ERR_OR_NULL(debugfs))
448 return;
449
450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
451 if (ret)
452 return;
453
454 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
455}
456
457/* -----------------------------------------------------------------------------
458 * Auxiliary Devices (*not* AUX)
459 */
460
461static void ti_sn65dsi86_uninit_aux(void *data)
462{
463 auxiliary_device_uninit(data);
464}
465
466static void ti_sn65dsi86_delete_aux(void *data)
467{
468 auxiliary_device_delete(data);
469}
470
471static void ti_sn65dsi86_aux_device_release(struct device *dev)
472{
473 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
474
475 kfree(aux);
476}
477
478static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
479 struct auxiliary_device **aux_out,
480 const char *name)
481{
482 struct device *dev = pdata->dev;
483 struct auxiliary_device *aux;
484 int ret;
485
486 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
487 if (!aux)
488 return -ENOMEM;
489
490 aux->name = name;
491 aux->dev.parent = dev;
492 aux->dev.release = ti_sn65dsi86_aux_device_release;
493 device_set_of_node_from_dev(&aux->dev, dev);
494 ret = auxiliary_device_init(aux);
495 if (ret) {
496 kfree(aux);
497 return ret;
498 }
499 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
500 if (ret)
501 return ret;
502
503 ret = auxiliary_device_add(aux);
504 if (ret)
505 return ret;
506 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
507 if (!ret)
508 *aux_out = aux;
509
510 return ret;
511}
512
513/* -----------------------------------------------------------------------------
514 * AUX Adapter
515 */
516
517static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
518{
519 return container_of(aux, struct ti_sn65dsi86, aux);
520}
521
522static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
523 struct drm_dp_aux_msg *msg)
524{
525 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
526 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
527 u32 request_val = AUX_CMD_REQ(msg->request);
528 u8 *buf = msg->buffer;
529 unsigned int len = msg->size;
530 unsigned int short_len;
531 unsigned int val;
532 int ret;
533 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
534
535 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
536 return -EINVAL;
537
538 pm_runtime_get_sync(pdata->dev);
539 mutex_lock(&pdata->comms_mutex);
540
541 /*
542 * If someone tries to do a DDC over AUX transaction before pre_enable()
543 * on a device without a dedicated reference clock then we just can't
544 * do it. Fail right away. This prevents non-refclk users from reading
545 * the EDID before enabling the panel but such is life.
546 */
547 if (!pdata->comms_enabled) {
548 ret = -EIO;
549 goto exit;
550 }
551
552 switch (request) {
553 case DP_AUX_NATIVE_WRITE:
554 case DP_AUX_I2C_WRITE:
555 case DP_AUX_NATIVE_READ:
556 case DP_AUX_I2C_READ:
557 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
558 /* Assume it's good */
559 msg->reply = 0;
560 break;
561 default:
562 ret = -EINVAL;
563 goto exit;
564 }
565
566 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
567 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
568 addr_len);
569 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
570 ARRAY_SIZE(addr_len));
571
572 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
573 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
574
575 /* Clear old status bits before start so we don't get confused */
576 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
577 AUX_IRQ_STATUS_NAT_I2C_FAIL |
578 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
579 AUX_IRQ_STATUS_AUX_SHORT);
580
581 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
582
583 /* Zero delay loop because i2c transactions are slow already */
584 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
585 !(val & AUX_CMD_SEND), 0, 50 * 1000);
586 if (ret)
587 goto exit;
588
589 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
590 if (ret)
591 goto exit;
592
593 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
594 /*
595 * The hardware tried the message seven times per the DP spec
596 * but it hit a timeout. We ignore defers here because they're
597 * handled in hardware.
598 */
599 ret = -ETIMEDOUT;
600 goto exit;
601 }
602
603 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
604 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
605 len = min(len, short_len);
606 if (ret)
607 goto exit;
608 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
609 switch (request) {
610 case DP_AUX_I2C_WRITE:
611 case DP_AUX_I2C_READ:
612 msg->reply |= DP_AUX_I2C_REPLY_NACK;
613 break;
614 case DP_AUX_NATIVE_READ:
615 case DP_AUX_NATIVE_WRITE:
616 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
617 break;
618 }
619 len = 0;
620 goto exit;
621 }
622
623 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
624 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
625
626exit:
627 mutex_unlock(&pdata->comms_mutex);
628 pm_runtime_mark_last_busy(pdata->dev);
629 pm_runtime_put_autosuspend(pdata->dev);
630
631 if (ret)
632 return ret;
633 return len;
634}
635
636static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
637{
638 /*
639 * The HPD in this chip is a bit useless (See comment in
640 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
641 * for HPD, we just assume it's asserted after the wait_us delay.
642 *
643 * In case we are asked to wait forever (wait_us=0) take conservative
644 * 500ms delay.
645 */
646 if (wait_us == 0)
647 wait_us = 500000;
648
649 usleep_range(wait_us, wait_us + 1000);
650
651 return 0;
652}
653
654static int ti_sn_aux_probe(struct auxiliary_device *adev,
655 const struct auxiliary_device_id *id)
656{
657 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
658 int ret;
659
660 pdata->aux.name = "ti-sn65dsi86-aux";
661 pdata->aux.dev = &adev->dev;
662 pdata->aux.transfer = ti_sn_aux_transfer;
663 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
664 drm_dp_aux_init(&pdata->aux);
665
666 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
667 if (ret)
668 return ret;
669
670 /*
671 * The eDP to MIPI bridge parts don't work until the AUX channel is
672 * setup so we don't add it in the main driver probe, we add it now.
673 */
674 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
675}
676
677static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
678 { .name = "ti_sn65dsi86.aux", },
679 {},
680};
681
682static struct auxiliary_driver ti_sn_aux_driver = {
683 .name = "aux",
684 .probe = ti_sn_aux_probe,
685 .id_table = ti_sn_aux_id_table,
686};
687
688/*------------------------------------------------------------------------------
689 * DRM Bridge
690 */
691
692static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
693{
694 return container_of(bridge, struct ti_sn65dsi86, bridge);
695}
696
697static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
698{
699 int val;
700 struct mipi_dsi_host *host;
701 struct mipi_dsi_device *dsi;
702 struct device *dev = pdata->dev;
703 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
704 .channel = 0,
705 .node = NULL,
706 };
707
708 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
709 if (!host)
710 return -EPROBE_DEFER;
711
712 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
713 if (IS_ERR(dsi))
714 return PTR_ERR(dsi);
715
716 /* TODO: setting to 4 MIPI lanes always for now */
717 dsi->lanes = 4;
718 dsi->format = MIPI_DSI_FMT_RGB888;
719 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
720
721 /* check if continuous dsi clock is required or not */
722 pm_runtime_get_sync(dev);
723 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
724 pm_runtime_put_autosuspend(dev);
725 if (!(val & DPPLL_CLK_SRC_DSICLK))
726 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
727
728 pdata->dsi = dsi;
729
730 return devm_mipi_dsi_attach(&adev->dev, dsi);
731}
732
733static int ti_sn_bridge_attach(struct drm_bridge *bridge,
734 enum drm_bridge_attach_flags flags)
735{
736 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
737 int ret;
738
739 pdata->aux.drm_dev = bridge->dev;
740 ret = drm_dp_aux_register(&pdata->aux);
741 if (ret < 0) {
742 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
743 return ret;
744 }
745
746 /*
747 * Attach the next bridge.
748 * We never want the next bridge to *also* create a connector.
749 */
750 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
751 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
752 if (ret < 0)
753 goto err_initted_aux;
754
755 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
756 return 0;
757
758 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
759 pdata->bridge.encoder);
760 if (IS_ERR(pdata->connector)) {
761 ret = PTR_ERR(pdata->connector);
762 goto err_initted_aux;
763 }
764
765 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
766
767 return 0;
768
769err_initted_aux:
770 drm_dp_aux_unregister(&pdata->aux);
771 return ret;
772}
773
774static void ti_sn_bridge_detach(struct drm_bridge *bridge)
775{
776 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
777}
778
779static enum drm_mode_status
780ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
781 const struct drm_display_info *info,
782 const struct drm_display_mode *mode)
783{
784 /* maximum supported resolution is 4K at 60 fps */
785 if (mode->clock > 594000)
786 return MODE_CLOCK_HIGH;
787
788 /*
789 * The front and back porch registers are 8 bits, and pulse width
790 * registers are 15 bits, so reject any modes with larger periods.
791 */
792
793 if ((mode->hsync_start - mode->hdisplay) > 0xff)
794 return MODE_HBLANK_WIDE;
795
796 if ((mode->vsync_start - mode->vdisplay) > 0xff)
797 return MODE_VBLANK_WIDE;
798
799 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
800 return MODE_HSYNC_WIDE;
801
802 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
803 return MODE_VSYNC_WIDE;
804
805 if ((mode->htotal - mode->hsync_end) > 0xff)
806 return MODE_HBLANK_WIDE;
807
808 if ((mode->vtotal - mode->vsync_end) > 0xff)
809 return MODE_VBLANK_WIDE;
810
811 return MODE_OK;
812}
813
814static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
815 struct drm_bridge_state *old_bridge_state)
816{
817 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
818
819 /* disable video stream */
820 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
821}
822
823static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
824{
825 unsigned int bit_rate_mhz, clk_freq_mhz;
826 unsigned int val;
827 struct drm_display_mode *mode =
828 &pdata->bridge.encoder->crtc->state->adjusted_mode;
829
830 /* set DSIA clk frequency */
831 bit_rate_mhz = (mode->clock / 1000) *
832 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
833 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
834
835 /* for each increment in val, frequency increases by 5MHz */
836 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
837 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
838 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
839}
840
841static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
842{
843 if (connector->display_info.bpc <= 6)
844 return 18;
845 else
846 return 24;
847}
848
849/*
850 * LUT index corresponds to register value and
851 * LUT values corresponds to dp data rate supported
852 * by the bridge in Mbps unit.
853 */
854static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
855 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
856};
857
858static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
859{
860 unsigned int bit_rate_khz, dp_rate_mhz;
861 unsigned int i;
862 struct drm_display_mode *mode =
863 &pdata->bridge.encoder->crtc->state->adjusted_mode;
864
865 /* Calculate minimum bit rate based on our pixel clock. */
866 bit_rate_khz = mode->clock * bpp;
867
868 /* Calculate minimum DP data rate, taking 80% as per DP spec */
869 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
870 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
871
872 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
873 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
874 break;
875
876 return i;
877}
878
879static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
880{
881 unsigned int valid_rates = 0;
882 unsigned int rate_per_200khz;
883 unsigned int rate_mhz;
884 u8 dpcd_val;
885 int ret;
886 int i, j;
887
888 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
889 if (ret != 1) {
890 DRM_DEV_ERROR(pdata->dev,
891 "Can't read eDP rev (%d), assuming 1.1\n", ret);
892 dpcd_val = DP_EDP_11;
893 }
894
895 if (dpcd_val >= DP_EDP_14) {
896 /* eDP 1.4 devices must provide a custom table */
897 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
898
899 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
900 sink_rates, sizeof(sink_rates));
901
902 if (ret != sizeof(sink_rates)) {
903 DRM_DEV_ERROR(pdata->dev,
904 "Can't read supported rate table (%d)\n", ret);
905
906 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
907 memset(sink_rates, 0, sizeof(sink_rates));
908 }
909
910 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
911 rate_per_200khz = le16_to_cpu(sink_rates[i]);
912
913 if (!rate_per_200khz)
914 break;
915
916 rate_mhz = rate_per_200khz * 200 / 1000;
917 for (j = 0;
918 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
919 j++) {
920 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
921 valid_rates |= BIT(j);
922 }
923 }
924
925 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
926 if (valid_rates & BIT(i))
927 return valid_rates;
928 }
929 DRM_DEV_ERROR(pdata->dev,
930 "No matching eDP rates in table; falling back\n");
931 }
932
933 /* On older versions best we can do is use DP_MAX_LINK_RATE */
934 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
935 if (ret != 1) {
936 DRM_DEV_ERROR(pdata->dev,
937 "Can't read max rate (%d); assuming 5.4 GHz\n",
938 ret);
939 dpcd_val = DP_LINK_BW_5_4;
940 }
941
942 switch (dpcd_val) {
943 default:
944 DRM_DEV_ERROR(pdata->dev,
945 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
946 (int)dpcd_val);
947 fallthrough;
948 case DP_LINK_BW_5_4:
949 valid_rates |= BIT(7);
950 fallthrough;
951 case DP_LINK_BW_2_7:
952 valid_rates |= BIT(4);
953 fallthrough;
954 case DP_LINK_BW_1_62:
955 valid_rates |= BIT(1);
956 break;
957 }
958
959 return valid_rates;
960}
961
962static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
963{
964 struct drm_display_mode *mode =
965 &pdata->bridge.encoder->crtc->state->adjusted_mode;
966 u8 hsync_polarity = 0, vsync_polarity = 0;
967
968 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
969 hsync_polarity = CHA_HSYNC_POLARITY;
970 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
971 vsync_polarity = CHA_VSYNC_POLARITY;
972
973 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
974 mode->hdisplay);
975 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
976 mode->vdisplay);
977 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
978 (mode->hsync_end - mode->hsync_start) & 0xFF);
979 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
980 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
981 hsync_polarity);
982 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
983 (mode->vsync_end - mode->vsync_start) & 0xFF);
984 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
985 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
986 vsync_polarity);
987
988 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
989 (mode->htotal - mode->hsync_end) & 0xFF);
990 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
991 (mode->vtotal - mode->vsync_end) & 0xFF);
992
993 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
994 (mode->hsync_start - mode->hdisplay) & 0xFF);
995 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
996 (mode->vsync_start - mode->vdisplay) & 0xFF);
997
998 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
999}
1000
1001static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1002{
1003 u8 data;
1004 int ret;
1005
1006 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1007 if (ret != 1) {
1008 DRM_DEV_ERROR(pdata->dev,
1009 "Can't read lane count (%d); assuming 4\n", ret);
1010 return 4;
1011 }
1012
1013 return data & DP_LANE_COUNT_MASK;
1014}
1015
1016static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1017 const char **last_err_str)
1018{
1019 unsigned int val;
1020 int ret;
1021 int i;
1022
1023 /* set dp clk frequency value */
1024 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1025 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1026
1027 /* enable DP PLL */
1028 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1029
1030 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1031 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1032 50 * 1000);
1033 if (ret) {
1034 *last_err_str = "DP_PLL_LOCK polling failed";
1035 goto exit;
1036 }
1037
1038 /*
1039 * We'll try to link train several times. As part of link training
1040 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1041 * the panel isn't ready quite it might respond NAK here which means
1042 * we need to try again.
1043 */
1044 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1045 /* Semi auto link training mode */
1046 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1047 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1048 val == ML_TX_MAIN_LINK_OFF ||
1049 val == ML_TX_NORMAL_MODE, 1000,
1050 500 * 1000);
1051 if (ret) {
1052 *last_err_str = "Training complete polling failed";
1053 } else if (val == ML_TX_MAIN_LINK_OFF) {
1054 *last_err_str = "Link training failed, link is off";
1055 ret = -EIO;
1056 continue;
1057 }
1058
1059 break;
1060 }
1061
1062 /* If we saw quite a few retries, add a note about it */
1063 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1064 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1065
1066exit:
1067 /* Disable the PLL if we failed */
1068 if (ret)
1069 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1070
1071 return ret;
1072}
1073
1074static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1075 struct drm_bridge_state *old_bridge_state)
1076{
1077 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1078 struct drm_connector *connector;
1079 const char *last_err_str = "No supported DP rate";
1080 unsigned int valid_rates;
1081 int dp_rate_idx;
1082 unsigned int val;
1083 int ret = -EINVAL;
1084 int max_dp_lanes;
1085 unsigned int bpp;
1086
1087 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1088 bridge->encoder);
1089 if (!connector) {
1090 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1091 return;
1092 }
1093
1094 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1095 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1096
1097 /* DSI_A lane config */
1098 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1099 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1100 CHA_DSI_LANES_MASK, val);
1101
1102 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1103 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1104 pdata->ln_polrs << LN_POLRS_OFFSET);
1105
1106 /* set dsi clk frequency value */
1107 ti_sn_bridge_set_dsi_rate(pdata);
1108
1109 /*
1110 * The SN65DSI86 only supports ASSR Display Authentication method and
1111 * this method is enabled for eDP panels. An eDP panel must support this
1112 * authentication method. We need to enable this method in the eDP panel
1113 * at DisplayPort address 0x0010A prior to link training.
1114 *
1115 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1116 * we need to disable the scrambler.
1117 */
1118 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1119 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1120 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1121
1122 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1123 SCRAMBLE_DISABLE, 0);
1124 } else {
1125 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1126 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1127 }
1128
1129 bpp = ti_sn_bridge_get_bpp(connector);
1130 /* Set the DP output format (18 bpp or 24 bpp) */
1131 val = bpp == 18 ? BPP_18_RGB : 0;
1132 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1133
1134 /* DP lane config */
1135 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1136 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1137 val);
1138
1139 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1140
1141 /* Train until we run out of rates */
1142 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1143 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1144 dp_rate_idx++) {
1145 if (!(valid_rates & BIT(dp_rate_idx)))
1146 continue;
1147
1148 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1149 if (!ret)
1150 break;
1151 }
1152 if (ret) {
1153 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1154 return;
1155 }
1156
1157 /* config video parameters */
1158 ti_sn_bridge_set_video_timings(pdata);
1159
1160 /* enable video stream */
1161 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1162 VSTREAM_ENABLE);
1163}
1164
1165static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1166 struct drm_bridge_state *old_bridge_state)
1167{
1168 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1169
1170 pm_runtime_get_sync(pdata->dev);
1171
1172 if (!pdata->refclk)
1173 ti_sn65dsi86_enable_comms(pdata);
1174
1175 /* td7: min 100 us after enable before DSI data */
1176 usleep_range(100, 110);
1177}
1178
1179static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1180 struct drm_bridge_state *old_bridge_state)
1181{
1182 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1183
1184 /* semi auto link training mode OFF */
1185 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1186 /* Num lanes to 0 as per power sequencing in data sheet */
1187 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1188 /* disable DP PLL */
1189 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1190
1191 if (!pdata->refclk)
1192 ti_sn65dsi86_disable_comms(pdata);
1193
1194 pm_runtime_put_sync(pdata->dev);
1195}
1196
1197static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1198{
1199 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1200 int val = 0;
1201
1202 pm_runtime_get_sync(pdata->dev);
1203 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1204 pm_runtime_put_autosuspend(pdata->dev);
1205
1206 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1207 : connector_status_disconnected;
1208}
1209
1210static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge,
1211 struct drm_connector *connector)
1212{
1213 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1214
1215 return drm_edid_read_ddc(connector, &pdata->aux.ddc);
1216}
1217
1218static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1219 .attach = ti_sn_bridge_attach,
1220 .detach = ti_sn_bridge_detach,
1221 .mode_valid = ti_sn_bridge_mode_valid,
1222 .edid_read = ti_sn_bridge_edid_read,
1223 .detect = ti_sn_bridge_detect,
1224 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1225 .atomic_enable = ti_sn_bridge_atomic_enable,
1226 .atomic_disable = ti_sn_bridge_atomic_disable,
1227 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1228 .atomic_reset = drm_atomic_helper_bridge_reset,
1229 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1230 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1231};
1232
1233static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1234 struct device_node *np)
1235{
1236 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1237 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1238 struct device_node *endpoint;
1239 u8 ln_assign = 0;
1240 u8 ln_polrs = 0;
1241 int dp_lanes;
1242 int i;
1243
1244 /*
1245 * Read config from the device tree about lane remapping and lane
1246 * polarities. These are optional and we assume identity map and
1247 * normal polarity if nothing is specified. It's OK to specify just
1248 * data-lanes but not lane-polarities but not vice versa.
1249 *
1250 * Error checking is light (we just make sure we don't crash or
1251 * buffer overrun) and we assume dts is well formed and specifying
1252 * mappings that the hardware supports.
1253 */
1254 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1255 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1256 if (dp_lanes > 0) {
1257 of_property_read_u32_array(endpoint, "data-lanes",
1258 lane_assignments, dp_lanes);
1259 of_property_read_u32_array(endpoint, "lane-polarities",
1260 lane_polarities, dp_lanes);
1261 } else {
1262 dp_lanes = SN_MAX_DP_LANES;
1263 }
1264 of_node_put(endpoint);
1265
1266 /*
1267 * Convert into register format. Loop over all lanes even if
1268 * data-lanes had fewer elements so that we nicely initialize
1269 * the LN_ASSIGN register.
1270 */
1271 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1272 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1273 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1274 }
1275
1276 /* Stash in our struct for when we power on */
1277 pdata->dp_lanes = dp_lanes;
1278 pdata->ln_assign = ln_assign;
1279 pdata->ln_polrs = ln_polrs;
1280}
1281
1282static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1283{
1284 struct device_node *np = pdata->dev->of_node;
1285
1286 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1287
1288 if (!pdata->host_node) {
1289 DRM_ERROR("remote dsi host node not found\n");
1290 return -ENODEV;
1291 }
1292
1293 return 0;
1294}
1295
1296static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1297 const struct auxiliary_device_id *id)
1298{
1299 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1300 struct device_node *np = pdata->dev->of_node;
1301 int ret;
1302
1303 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1304 if (IS_ERR(pdata->next_bridge))
1305 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1306 "failed to create panel bridge\n");
1307
1308 ti_sn_bridge_parse_lanes(pdata, np);
1309
1310 ret = ti_sn_bridge_parse_dsi_host(pdata);
1311 if (ret)
1312 return ret;
1313
1314 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1315 pdata->bridge.of_node = np;
1316 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1317 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1318
1319 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)
1320 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
1321
1322 drm_bridge_add(&pdata->bridge);
1323
1324 ret = ti_sn_attach_host(adev, pdata);
1325 if (ret) {
1326 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1327 goto err_remove_bridge;
1328 }
1329
1330 return 0;
1331
1332err_remove_bridge:
1333 drm_bridge_remove(&pdata->bridge);
1334 return ret;
1335}
1336
1337static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1338{
1339 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1340
1341 if (!pdata)
1342 return;
1343
1344 drm_bridge_remove(&pdata->bridge);
1345
1346 of_node_put(pdata->host_node);
1347}
1348
1349static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1350 { .name = "ti_sn65dsi86.bridge", },
1351 {},
1352};
1353
1354static struct auxiliary_driver ti_sn_bridge_driver = {
1355 .name = "bridge",
1356 .probe = ti_sn_bridge_probe,
1357 .remove = ti_sn_bridge_remove,
1358 .id_table = ti_sn_bridge_id_table,
1359};
1360
1361/* -----------------------------------------------------------------------------
1362 * PWM Controller
1363 */
1364#if defined(CONFIG_PWM)
1365static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1366{
1367 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1368}
1369
1370static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1371{
1372 atomic_set(&pdata->pwm_pin_busy, 0);
1373}
1374
1375static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1376{
1377 return pwmchip_get_drvdata(chip);
1378}
1379
1380static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1381{
1382 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1383
1384 return ti_sn_pwm_pin_request(pdata);
1385}
1386
1387static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1388{
1389 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1390
1391 ti_sn_pwm_pin_release(pdata);
1392}
1393
1394/*
1395 * Limitations:
1396 * - The PWM signal is not driven when the chip is powered down, or in its
1397 * reset state and the driver does not implement the "suspend state"
1398 * described in the documentation. In order to save power, state->enabled is
1399 * interpreted as denoting if the signal is expected to be valid, and is used
1400 * to determine if the chip needs to be kept powered.
1401 * - Changing both period and duty_cycle is not done atomically, neither is the
1402 * multi-byte register updates, so the output might briefly be undefined
1403 * during update.
1404 */
1405static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1406 const struct pwm_state *state)
1407{
1408 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1409 unsigned int pwm_en_inv;
1410 unsigned int backlight;
1411 unsigned int pre_div;
1412 unsigned int scale;
1413 u64 period_max;
1414 u64 period;
1415 int ret;
1416
1417 if (!pdata->pwm_enabled) {
1418 ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
1419 if (ret < 0)
1420 return ret;
1421 }
1422
1423 if (state->enabled) {
1424 if (!pdata->pwm_enabled) {
1425 /*
1426 * The chip might have been powered down while we
1427 * didn't hold a PM runtime reference, so mux in the
1428 * PWM function on the GPIO pin again.
1429 */
1430 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1431 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1432 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1433 if (ret) {
1434 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n");
1435 goto out;
1436 }
1437 }
1438
1439 /*
1440 * Per the datasheet the PWM frequency is given by:
1441 *
1442 * REFCLK_FREQ
1443 * PWM_FREQ = -----------------------------------
1444 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1445 *
1446 * However, after careful review the author is convinced that
1447 * the documentation has lost some parenthesis around
1448 * "BACKLIGHT_SCALE + 1".
1449 *
1450 * With the period T_pwm = 1/PWM_FREQ this can be written:
1451 *
1452 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1453 *
1454 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1455 * PWM_PRE_DIV must be:
1456 *
1457 * T_pwm * REFCLK_FREQ
1458 * PWM_PRE_DIV >= -------------------------
1459 * BACKLIGHT_SCALE_MAX + 1
1460 *
1461 * To simplify the search and to favour higher resolution of
1462 * the duty cycle over accuracy of the period, the lowest
1463 * possible PWM_PRE_DIV is used. Finally the scale is
1464 * calculated as:
1465 *
1466 * T_pwm * REFCLK_FREQ
1467 * BACKLIGHT_SCALE = ---------------------- - 1
1468 * PWM_PRE_DIV
1469 *
1470 * Here T_pwm is represented in seconds, so appropriate scaling
1471 * to nanoseconds is necessary.
1472 */
1473
1474 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1475 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1476 ret = -EINVAL;
1477 goto out;
1478 }
1479
1480 /*
1481 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1482 * Limit period to this to avoid overflows
1483 */
1484 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1485 pdata->pwm_refclk_freq);
1486 period = min(state->period, period_max);
1487
1488 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1489 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1490 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1491
1492 /*
1493 * The documentation has the duty ratio given as:
1494 *
1495 * duty BACKLIGHT
1496 * ------- = ---------------------
1497 * period BACKLIGHT_SCALE + 1
1498 *
1499 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1500 * to definition above and adjusting for nanosecond
1501 * representation of duty cycle gives us:
1502 */
1503 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1504 (u64)NSEC_PER_SEC * pre_div);
1505 if (backlight > scale)
1506 backlight = scale;
1507
1508 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1509 if (ret) {
1510 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n");
1511 goto out;
1512 }
1513
1514 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1515 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1516 }
1517
1518 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1519 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1520 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1521 if (ret) {
1522 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n");
1523 goto out;
1524 }
1525
1526 pdata->pwm_enabled = state->enabled;
1527out:
1528
1529 if (!pdata->pwm_enabled)
1530 pm_runtime_put_sync(pwmchip_parent(chip));
1531
1532 return ret;
1533}
1534
1535static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1536 struct pwm_state *state)
1537{
1538 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1539 unsigned int pwm_en_inv;
1540 unsigned int pre_div;
1541 u16 backlight;
1542 u16 scale;
1543 int ret;
1544
1545 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1546 if (ret)
1547 return ret;
1548
1549 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1550 if (ret)
1551 return ret;
1552
1553 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1554 if (ret)
1555 return ret;
1556
1557 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1558 if (ret)
1559 return ret;
1560
1561 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1562 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1563 state->polarity = PWM_POLARITY_INVERSED;
1564 else
1565 state->polarity = PWM_POLARITY_NORMAL;
1566
1567 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1568 pdata->pwm_refclk_freq);
1569 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1570 pdata->pwm_refclk_freq);
1571
1572 if (state->duty_cycle > state->period)
1573 state->duty_cycle = state->period;
1574
1575 return 0;
1576}
1577
1578static const struct pwm_ops ti_sn_pwm_ops = {
1579 .request = ti_sn_pwm_request,
1580 .free = ti_sn_pwm_free,
1581 .apply = ti_sn_pwm_apply,
1582 .get_state = ti_sn_pwm_get_state,
1583};
1584
1585static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1586 const struct auxiliary_device_id *id)
1587{
1588 struct pwm_chip *chip;
1589 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1590
1591 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0);
1592 if (IS_ERR(chip))
1593 return PTR_ERR(chip);
1594
1595 pwmchip_set_drvdata(chip, pdata);
1596
1597 chip->ops = &ti_sn_pwm_ops;
1598 chip->of_xlate = of_pwm_single_xlate;
1599
1600 devm_pm_runtime_enable(&adev->dev);
1601
1602 return pwmchip_add(chip);
1603}
1604
1605static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1606{
1607 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1608
1609 pwmchip_remove(pdata->pchip);
1610
1611 if (pdata->pwm_enabled)
1612 pm_runtime_put_sync(&adev->dev);
1613}
1614
1615static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1616 { .name = "ti_sn65dsi86.pwm", },
1617 {},
1618};
1619
1620static struct auxiliary_driver ti_sn_pwm_driver = {
1621 .name = "pwm",
1622 .probe = ti_sn_pwm_probe,
1623 .remove = ti_sn_pwm_remove,
1624 .id_table = ti_sn_pwm_id_table,
1625};
1626
1627static int __init ti_sn_pwm_register(void)
1628{
1629 return auxiliary_driver_register(&ti_sn_pwm_driver);
1630}
1631
1632static void ti_sn_pwm_unregister(void)
1633{
1634 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1635}
1636
1637#else
1638static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1639static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1640
1641static inline int ti_sn_pwm_register(void) { return 0; }
1642static inline void ti_sn_pwm_unregister(void) {}
1643#endif
1644
1645/* -----------------------------------------------------------------------------
1646 * GPIO Controller
1647 */
1648#if defined(CONFIG_OF_GPIO)
1649
1650static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1651 const struct of_phandle_args *gpiospec,
1652 u32 *flags)
1653{
1654 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1655 return -EINVAL;
1656
1657 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1658 return -EINVAL;
1659
1660 if (flags)
1661 *flags = gpiospec->args[1];
1662
1663 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1664}
1665
1666static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1667 unsigned int offset)
1668{
1669 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1670
1671 /*
1672 * We already have to keep track of the direction because we use
1673 * that to figure out whether we've powered the device. We can
1674 * just return that rather than (maybe) powering up the device
1675 * to ask its direction.
1676 */
1677 return test_bit(offset, pdata->gchip_output) ?
1678 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1679}
1680
1681static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1682{
1683 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1684 unsigned int val;
1685 int ret;
1686
1687 /*
1688 * When the pin is an input we don't forcibly keep the bridge
1689 * powered--we just power it on to read the pin. NOTE: part of
1690 * the reason this works is that the bridge defaults (when
1691 * powered back on) to all 4 GPIOs being configured as GPIO input.
1692 * Also note that if something else is keeping the chip powered the
1693 * pm_runtime functions are lightweight increments of a refcount.
1694 */
1695 pm_runtime_get_sync(pdata->dev);
1696 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1697 pm_runtime_put_autosuspend(pdata->dev);
1698
1699 if (ret)
1700 return ret;
1701
1702 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1703}
1704
1705static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1706 int val)
1707{
1708 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1709 int ret;
1710
1711 if (!test_bit(offset, pdata->gchip_output)) {
1712 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1713 return;
1714 }
1715
1716 val &= 1;
1717 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1718 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1719 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1720 if (ret)
1721 dev_warn(pdata->dev,
1722 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1723}
1724
1725static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1726 unsigned int offset)
1727{
1728 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1729 int shift = offset * 2;
1730 int ret;
1731
1732 if (!test_and_clear_bit(offset, pdata->gchip_output))
1733 return 0;
1734
1735 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1736 SN_GPIO_MUX_MASK << shift,
1737 SN_GPIO_MUX_INPUT << shift);
1738 if (ret) {
1739 set_bit(offset, pdata->gchip_output);
1740 return ret;
1741 }
1742
1743 /*
1744 * NOTE: if nobody else is powering the device this may fully power
1745 * it off and when it comes back it will have lost all state, but
1746 * that's OK because the default is input and we're now an input.
1747 */
1748 pm_runtime_put_autosuspend(pdata->dev);
1749
1750 return 0;
1751}
1752
1753static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1754 unsigned int offset, int val)
1755{
1756 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1757 int shift = offset * 2;
1758 int ret;
1759
1760 if (test_and_set_bit(offset, pdata->gchip_output))
1761 return 0;
1762
1763 pm_runtime_get_sync(pdata->dev);
1764
1765 /* Set value first to avoid glitching */
1766 ti_sn_bridge_gpio_set(chip, offset, val);
1767
1768 /* Set direction */
1769 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1770 SN_GPIO_MUX_MASK << shift,
1771 SN_GPIO_MUX_OUTPUT << shift);
1772 if (ret) {
1773 clear_bit(offset, pdata->gchip_output);
1774 pm_runtime_put_autosuspend(pdata->dev);
1775 }
1776
1777 return ret;
1778}
1779
1780static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1781{
1782 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1783
1784 if (offset == SN_PWM_GPIO_IDX)
1785 return ti_sn_pwm_pin_request(pdata);
1786
1787 return 0;
1788}
1789
1790static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1791{
1792 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1793
1794 /* We won't keep pm_runtime if we're input, so switch there on free */
1795 ti_sn_bridge_gpio_direction_input(chip, offset);
1796
1797 if (offset == SN_PWM_GPIO_IDX)
1798 ti_sn_pwm_pin_release(pdata);
1799}
1800
1801static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1802 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1803};
1804
1805static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1806 const struct auxiliary_device_id *id)
1807{
1808 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1809 int ret;
1810
1811 /* Only init if someone is going to use us as a GPIO controller */
1812 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1813 return 0;
1814
1815 pdata->gchip.label = dev_name(pdata->dev);
1816 pdata->gchip.parent = pdata->dev;
1817 pdata->gchip.owner = THIS_MODULE;
1818 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1819 pdata->gchip.of_gpio_n_cells = 2;
1820 pdata->gchip.request = ti_sn_bridge_gpio_request;
1821 pdata->gchip.free = ti_sn_bridge_gpio_free;
1822 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1823 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1824 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1825 pdata->gchip.get = ti_sn_bridge_gpio_get;
1826 pdata->gchip.set = ti_sn_bridge_gpio_set;
1827 pdata->gchip.can_sleep = true;
1828 pdata->gchip.names = ti_sn_bridge_gpio_names;
1829 pdata->gchip.ngpio = SN_NUM_GPIOS;
1830 pdata->gchip.base = -1;
1831 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1832 if (ret)
1833 dev_err(pdata->dev, "can't add gpio chip\n");
1834
1835 return ret;
1836}
1837
1838static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1839 { .name = "ti_sn65dsi86.gpio", },
1840 {},
1841};
1842
1843MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1844
1845static struct auxiliary_driver ti_sn_gpio_driver = {
1846 .name = "gpio",
1847 .probe = ti_sn_gpio_probe,
1848 .id_table = ti_sn_gpio_id_table,
1849};
1850
1851static int __init ti_sn_gpio_register(void)
1852{
1853 return auxiliary_driver_register(&ti_sn_gpio_driver);
1854}
1855
1856static void ti_sn_gpio_unregister(void)
1857{
1858 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1859}
1860
1861#else
1862
1863static inline int ti_sn_gpio_register(void) { return 0; }
1864static inline void ti_sn_gpio_unregister(void) {}
1865
1866#endif
1867
1868/* -----------------------------------------------------------------------------
1869 * Probe & Remove
1870 */
1871
1872static void ti_sn65dsi86_runtime_disable(void *data)
1873{
1874 pm_runtime_dont_use_autosuspend(data);
1875 pm_runtime_disable(data);
1876}
1877
1878static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1879{
1880 unsigned int i;
1881 const char * const ti_sn_bridge_supply_names[] = {
1882 "vcca", "vcc", "vccio", "vpll",
1883 };
1884
1885 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1886 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1887
1888 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1889 pdata->supplies);
1890}
1891
1892static int ti_sn65dsi86_probe(struct i2c_client *client)
1893{
1894 struct device *dev = &client->dev;
1895 struct ti_sn65dsi86 *pdata;
1896 int ret;
1897
1898 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1899 DRM_ERROR("device doesn't support I2C\n");
1900 return -ENODEV;
1901 }
1902
1903 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1904 if (!pdata)
1905 return -ENOMEM;
1906 dev_set_drvdata(dev, pdata);
1907 pdata->dev = dev;
1908
1909 mutex_init(&pdata->comms_mutex);
1910
1911 pdata->regmap = devm_regmap_init_i2c(client,
1912 &ti_sn65dsi86_regmap_config);
1913 if (IS_ERR(pdata->regmap))
1914 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1915 "regmap i2c init failed\n");
1916
1917 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1918 GPIOD_OUT_LOW);
1919 if (IS_ERR(pdata->enable_gpio))
1920 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1921 "failed to get enable gpio from DT\n");
1922
1923 ret = ti_sn65dsi86_parse_regulators(pdata);
1924 if (ret)
1925 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1926
1927 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1928 if (IS_ERR(pdata->refclk))
1929 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1930 "failed to get reference clock\n");
1931
1932 pm_runtime_enable(dev);
1933 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1934 pm_runtime_use_autosuspend(pdata->dev);
1935 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1936 if (ret)
1937 return ret;
1938
1939 ti_sn65dsi86_debugfs_init(pdata);
1940
1941 /*
1942 * Break ourselves up into a collection of aux devices. The only real
1943 * motiviation here is to solve the chicken-and-egg problem of probe
1944 * ordering. The bridge wants the panel to be there when it probes.
1945 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1946 * when it probes. The panel and maybe backlight might want the DDC
1947 * bus or the pwm_chip. Having sub-devices allows the some sub devices
1948 * to finish probing even if others return -EPROBE_DEFER and gets us
1949 * around the problems.
1950 */
1951
1952 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1953 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1954 if (ret)
1955 return ret;
1956 }
1957
1958 if (IS_ENABLED(CONFIG_PWM)) {
1959 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1960 if (ret)
1961 return ret;
1962 }
1963
1964 /*
1965 * NOTE: At the end of the AUX channel probe we'll add the aux device
1966 * for the bridge. This is because the bridge can't be used until the
1967 * AUX channel is there and this is a very simple solution to the
1968 * dependency problem.
1969 */
1970 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1971}
1972
1973static struct i2c_device_id ti_sn65dsi86_id[] = {
1974 { "ti,sn65dsi86", 0},
1975 {},
1976};
1977MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1978
1979static const struct of_device_id ti_sn65dsi86_match_table[] = {
1980 {.compatible = "ti,sn65dsi86"},
1981 {},
1982};
1983MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1984
1985static struct i2c_driver ti_sn65dsi86_driver = {
1986 .driver = {
1987 .name = "ti_sn65dsi86",
1988 .of_match_table = ti_sn65dsi86_match_table,
1989 .pm = &ti_sn65dsi86_pm_ops,
1990 },
1991 .probe = ti_sn65dsi86_probe,
1992 .id_table = ti_sn65dsi86_id,
1993};
1994
1995static int __init ti_sn65dsi86_init(void)
1996{
1997 int ret;
1998
1999 ret = i2c_add_driver(&ti_sn65dsi86_driver);
2000 if (ret)
2001 return ret;
2002
2003 ret = ti_sn_gpio_register();
2004 if (ret)
2005 goto err_main_was_registered;
2006
2007 ret = ti_sn_pwm_register();
2008 if (ret)
2009 goto err_gpio_was_registered;
2010
2011 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2012 if (ret)
2013 goto err_pwm_was_registered;
2014
2015 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2016 if (ret)
2017 goto err_aux_was_registered;
2018
2019 return 0;
2020
2021err_aux_was_registered:
2022 auxiliary_driver_unregister(&ti_sn_aux_driver);
2023err_pwm_was_registered:
2024 ti_sn_pwm_unregister();
2025err_gpio_was_registered:
2026 ti_sn_gpio_unregister();
2027err_main_was_registered:
2028 i2c_del_driver(&ti_sn65dsi86_driver);
2029
2030 return ret;
2031}
2032module_init(ti_sn65dsi86_init);
2033
2034static void __exit ti_sn65dsi86_exit(void)
2035{
2036 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2037 auxiliary_driver_unregister(&ti_sn_aux_driver);
2038 ti_sn_pwm_unregister();
2039 ti_sn_gpio_unregister();
2040 i2c_del_driver(&ti_sn65dsi86_driver);
2041}
2042module_exit(ti_sn65dsi86_exit);
2043
2044MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2045MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2046MODULE_LICENSE("GPL v2");