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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5#include <linux/bits.h>
6#include <linux/debugfs.h>
7#include <linux/delay.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/extcon.h>
11#include <linux/fs.h>
12#include <linux/gpio/consumer.h>
13#include <linux/i2c.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pm_runtime.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/types.h>
21#include <linux/wait.h>
22
23#include <crypto/hash.h>
24
25#include <drm/display/drm_dp_helper.h>
26#include <drm/display/drm_hdcp_helper.h>
27#include <drm/drm_atomic_helper.h>
28#include <drm/drm_bridge.h>
29#include <drm/drm_crtc.h>
30#include <drm/drm_edid.h>
31#include <drm/drm_print.h>
32#include <drm/drm_probe_helper.h>
33
34#include <sound/hdmi-codec.h>
35
36#define REG_IC_VER 0x04
37
38#define REG_RESET_CTRL 0x05
39#define VIDEO_RESET BIT(0)
40#define AUDIO_RESET BIT(1)
41#define ALL_LOGIC_RESET BIT(2)
42#define AUX_RESET BIT(3)
43#define HDCP_RESET BIT(4)
44
45#define INT_STATUS_01 0x06
46#define INT_MASK_01 0x09
47#define INT_HPD_CHANGE 0
48#define INT_RECEIVE_HPD_IRQ 1
49#define INT_SCDT_CHANGE 2
50#define INT_HDCP_FAIL 3
51#define INT_HDCP_DONE 4
52#define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
53#define BIT_INT_HPD INT_HPD_CHANGE
54#define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
55#define BIT_INT_SCDT INT_SCDT_CHANGE
56#define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
57#define BIT_INT_HDCP_DONE INT_HDCP_DONE
58
59#define INT_STATUS_02 0x07
60#define INT_MASK_02 0x0A
61#define INT_AUX_CMD_FAIL 0
62#define INT_HDCP_KSV_CHECK 1
63#define INT_AUDIO_FIFO_ERROR 2
64#define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
65#define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
66#define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
67
68#define INT_STATUS_03 0x08
69#define INT_MASK_03 0x0B
70#define INT_LINK_TRAIN_FAIL 4
71#define INT_VID_FIFO_ERROR 5
72#define INT_IO_LATCH_FIFO_OVERFLOW 7
73#define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
74#define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
75#define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
76
77#define REG_SYSTEM_STS 0x0D
78#define INT_STS BIT(0)
79#define HPD_STS BIT(1)
80#define VIDEO_STB BIT(2)
81
82#define REG_LINK_TRAIN_STS 0x0E
83#define LINK_STATE_CR BIT(2)
84#define LINK_STATE_EQ BIT(3)
85#define LINK_STATE_NORP BIT(4)
86
87#define REG_BANK_SEL 0x0F
88#define REG_CLK_CTRL0 0x10
89#define M_PCLK_DELAY 0x03
90
91#define REG_AUX_OPT 0x11
92#define AUX_AUTO_RST BIT(0)
93#define AUX_FIX_FREQ BIT(3)
94
95#define REG_DATA_CTRL0 0x12
96#define VIDEO_LATCH_EDGE BIT(4)
97#define ENABLE_PCLK_COUNTER BIT(7)
98
99#define REG_PCLK_COUNTER_VALUE 0x13
100
101#define REG_501_FIFO_CTRL 0x15
102#define RST_501_FIFO BIT(1)
103
104#define REG_TRAIN_CTRL0 0x16
105#define FORCE_LBR BIT(0)
106#define LANE_COUNT_MASK 0x06
107#define LANE_SWAP BIT(3)
108#define SPREAD_AMP_5 BIT(4)
109#define FORCE_CR_DONE BIT(5)
110#define FORCE_EQ_DONE BIT(6)
111
112#define REG_TRAIN_CTRL1 0x17
113#define AUTO_TRAIN BIT(0)
114#define MANUAL_TRAIN BIT(1)
115#define FORCE_RETRAIN BIT(2)
116
117#define REG_AUX_CTRL 0x23
118#define CLR_EDID_FIFO BIT(0)
119#define AUX_USER_MODE BIT(1)
120#define AUX_NO_SEGMENT_WR BIT(6)
121#define AUX_EN_FIFO_READ BIT(7)
122
123#define REG_AUX_ADR_0_7 0x24
124#define REG_AUX_ADR_8_15 0x25
125#define REG_AUX_ADR_16_19 0x26
126#define REG_AUX_OUT_DATA0 0x27
127
128#define REG_AUX_CMD_REQ 0x2B
129#define AUX_BUSY BIT(5)
130
131#define REG_AUX_DATA_0_7 0x2C
132#define REG_AUX_DATA_8_15 0x2D
133#define REG_AUX_DATA_16_23 0x2E
134#define REG_AUX_DATA_24_31 0x2F
135
136#define REG_AUX_DATA_FIFO 0x2F
137
138#define REG_AUX_ERROR_STS 0x9F
139#define M_AUX_REQ_FAIL 0x03
140
141#define REG_HDCP_CTRL1 0x38
142#define HDCP_CP_ENABLE BIT(0)
143
144#define REG_HDCP_TRIGGER 0x39
145#define HDCP_TRIGGER_START BIT(0)
146#define HDCP_TRIGGER_CPIRQ BIT(1)
147#define HDCP_TRIGGER_KSV_DONE BIT(4)
148#define HDCP_TRIGGER_KSV_FAIL BIT(5)
149
150#define REG_HDCP_CTRL2 0x3A
151#define HDCP_AN_SEL BIT(0)
152#define HDCP_AN_GEN BIT(1)
153#define HDCP_HW_HPDIRQ_ACT BIT(2)
154#define HDCP_EN_M0_READ BIT(5)
155
156#define REG_M0_0_7 0x4C
157#define REG_AN_0_7 0x4C
158#define REG_SP_CTRL0 0x58
159#define REG_IP_CTRL1 0x59
160#define REG_IP_CTRL2 0x5A
161
162#define REG_LINK_DRV 0x5C
163#define DRV_HS BIT(1)
164
165#define REG_DRV_LN_DATA_SEL 0x5D
166
167#define REG_AUX 0x5E
168
169#define REG_VID_BUS_CTRL0 0x60
170#define IN_DDR BIT(2)
171#define DDR_CD (0x01 << 6)
172
173#define REG_VID_BUS_CTRL1 0x61
174#define TX_FIFO_RESET BIT(1)
175
176#define REG_INPUT_CTRL 0xA0
177#define INPUT_HSYNC_POL BIT(0)
178#define INPUT_VSYNC_POL BIT(2)
179#define INPUT_INTERLACED BIT(4)
180
181#define REG_INPUT_HTOTAL 0xA1
182#define REG_INPUT_HACTIVE_START 0xA3
183#define REG_INPUT_HACTIVE_WIDTH 0xA5
184#define REG_INPUT_HFRONT_PORCH 0xA7
185#define REG_INPUT_HSYNC_WIDTH 0xA9
186#define REG_INPUT_VTOTAL 0xAB
187#define REG_INPUT_VACTIVE_START 0xAD
188#define REG_INPUT_VACTIVE_WIDTH 0xAF
189#define REG_INPUT_VFRONT_PORCH 0xB1
190#define REG_INPUT_VSYNC_WIDTH 0xB3
191
192#define REG_AUDIO_SRC_CTRL 0xB8
193#define M_AUDIO_I2S_EN 0x0F
194#define EN_I2S0 BIT(0)
195#define EN_I2S1 BIT(1)
196#define EN_I2S2 BIT(2)
197#define EN_I2S3 BIT(3)
198#define AUDIO_FIFO_RESET BIT(7)
199
200#define REG_AUDIO_FMT 0xB9
201#define REG_AUDIO_FIFO_SEL 0xBA
202
203#define REG_AUDIO_CTRL0 0xBB
204#define AUDIO_FULL_PKT BIT(4)
205#define AUDIO_16B_BOUND BIT(5)
206
207#define REG_AUDIO_CTRL1 0xBC
208#define REG_AUDIO_INPUT_FREQ 0xBE
209
210#define REG_IEC958_STS0 0xBF
211#define REG_IEC958_STS1 0xC0
212#define REG_IEC958_STS2 0xC1
213#define REG_IEC958_STS3 0xC2
214#define REG_IEC958_STS4 0xC3
215
216#define REG_HPD_IRQ_TIME 0xC9
217#define REG_AUX_DEBUG_MODE 0xCA
218#define REG_AUX_OPT2 0xCB
219#define REG_HDCP_OPT 0xCE
220#define REG_USER_DRV_PRE 0xCF
221
222#define REG_DATA_MUTE_CTRL 0xD3
223#define ENABLE_ENHANCED_FRAME BIT(0)
224#define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
225#define EN_VID_MUTE BIT(4)
226#define EN_AUD_MUTE BIT(5)
227
228#define REG_TIME_STMP_CTRL 0xD4
229#define EN_ENHANCE_VID_STMP BIT(0)
230#define EN_ENHANCE_AUD_STMP BIT(2)
231#define M_STAMP_STEP 0x30
232#define EN_SSC_GAT BIT(6)
233
234#define REG_INFOFRAME_CTRL 0xE8
235#define EN_AVI_PKT BIT(0)
236#define EN_AUD_PKT BIT(1)
237#define EN_MPG_PKT BIT(2)
238#define EN_GEN_PKT BIT(3)
239#define EN_VID_TIME_STMP BIT(4)
240#define EN_AUD_TIME_STMP BIT(5)
241#define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
242#define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
243
244#define REG_AUDIO_N_0_7 0xDE
245#define REG_AUDIO_N_8_15 0xDF
246#define REG_AUDIO_N_16_23 0xE0
247
248#define REG_AVI_INFO_DB1 0xE9
249#define REG_AVI_INFO_DB2 0xEA
250#define REG_AVI_INFO_DB3 0xEB
251#define REG_AVI_INFO_DB4 0xEC
252#define REG_AVI_INFO_DB5 0xED
253#define REG_AVI_INFO_SUM 0xF6
254
255#define REG_AUD_INFOFRAM_DB1 0xF7
256#define REG_AUD_INFOFRAM_DB2 0xF8
257#define REG_AUD_INFOFRAM_DB3 0xF9
258#define REG_AUD_INFOFRAM_DB4 0xFA
259#define REG_AUD_INFOFRAM_SUM 0xFB
260
261/* the following six registers are in bank1 */
262#define REG_DRV_0_DB_800_MV 0x17E
263#define REG_PRE_0_DB_800_MV 0x17F
264#define REG_PRE_3P5_DB_800_MV 0x181
265#define REG_SSC_CTRL0 0x188
266#define REG_SSC_CTRL1 0x189
267#define REG_SSC_CTRL2 0x18A
268
269#define RBR DP_LINK_BW_1_62
270#define HBR DP_LINK_BW_2_7
271#define HBR2 DP_LINK_BW_5_4
272#define HBR3 DP_LINK_BW_8_1
273
274#define DPCD_V_1_1 0x11
275#define MISC_VERB 0xF0
276#define MISC_VERC 0x70
277#define I2S_INPUT_FORMAT_STANDARD 0
278#define I2S_INPUT_FORMAT_32BIT 1
279#define I2S_INPUT_LEFT_JUSTIFIED 0
280#define I2S_INPUT_RIGHT_JUSTIFIED 1
281#define I2S_DATA_1T_DELAY 0
282#define I2S_DATA_NO_DELAY 1
283#define I2S_WS_LEFT_CHANNEL 0
284#define I2S_WS_RIGHT_CHANNEL 1
285#define I2S_DATA_MSB_FIRST 0
286#define I2S_DATA_LSB_FIRST 1
287#define WORD_LENGTH_16BIT 0
288#define WORD_LENGTH_18BIT 1
289#define WORD_LENGTH_20BIT 2
290#define WORD_LENGTH_24BIT 3
291#define DEBUGFS_DIR_NAME "it6505-debugfs"
292#define READ_BUFFER_SIZE 400
293
294/* Vendor option */
295#define HDCP_DESIRED 1
296#define MAX_LANE_COUNT 4
297#define MAX_LINK_RATE HBR
298#define AUTO_TRAIN_RETRY 3
299#define MAX_HDCP_DOWN_STREAM_COUNT 127
300#define MAX_CR_LEVEL 0x03
301#define MAX_EQ_LEVEL 0x03
302#define AUX_WAIT_TIMEOUT_MS 15
303#define AUX_FIFO_MAX_SIZE 16
304#define PIXEL_CLK_DELAY 1
305#define PIXEL_CLK_INVERSE 0
306#define ADJUST_PHASE_THRESHOLD 80000
307#define DPI_PIXEL_CLK_MAX 95000
308#define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
309#define DEFAULT_PWR_ON 0
310#define DEFAULT_DRV_HOLD 0
311
312#define AUDIO_SELECT I2S
313#define AUDIO_TYPE LPCM
314#define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
315#define AUDIO_CHANNEL_COUNT 2
316#define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
317#define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
318#define I2S_DATA_DELAY I2S_DATA_1T_DELAY
319#define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
320#define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
321#define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
322
323enum aux_cmd_type {
324 CMD_AUX_NATIVE_READ = 0x0,
325 CMD_AUX_NATIVE_WRITE = 0x5,
326 CMD_AUX_I2C_EDID_READ = 0xB,
327};
328
329enum aux_cmd_reply {
330 REPLY_ACK,
331 REPLY_NACK,
332 REPLY_DEFER,
333};
334
335enum link_train_status {
336 LINK_IDLE,
337 LINK_BUSY,
338 LINK_OK,
339};
340
341enum hdcp_state {
342 HDCP_AUTH_IDLE,
343 HDCP_AUTH_GOING,
344 HDCP_AUTH_DONE,
345};
346
347struct it6505_platform_data {
348 struct regulator *pwr18;
349 struct regulator *ovdd;
350 struct gpio_desc *gpiod_reset;
351};
352
353enum it6505_audio_select {
354 I2S = 0,
355 SPDIF,
356};
357
358enum it6505_audio_sample_rate {
359 SAMPLE_RATE_24K = 0x6,
360 SAMPLE_RATE_32K = 0x3,
361 SAMPLE_RATE_48K = 0x2,
362 SAMPLE_RATE_96K = 0xA,
363 SAMPLE_RATE_192K = 0xE,
364 SAMPLE_RATE_44_1K = 0x0,
365 SAMPLE_RATE_88_2K = 0x8,
366 SAMPLE_RATE_176_4K = 0xC,
367};
368
369enum it6505_audio_type {
370 LPCM = 0,
371 NLPCM,
372 DSS,
373};
374
375struct it6505_audio_data {
376 enum it6505_audio_select select;
377 enum it6505_audio_sample_rate sample_rate;
378 enum it6505_audio_type type;
379 u8 word_length;
380 u8 channel_count;
381 u8 i2s_input_format;
382 u8 i2s_justified;
383 u8 i2s_data_delay;
384 u8 i2s_ws_channel;
385 u8 i2s_data_sequence;
386};
387
388struct it6505_audio_sample_rate_map {
389 enum it6505_audio_sample_rate rate;
390 int sample_rate_value;
391};
392
393struct it6505_drm_dp_link {
394 unsigned char revision;
395 unsigned int rate;
396 unsigned int num_lanes;
397 unsigned long capabilities;
398};
399
400struct debugfs_entries {
401 char *name;
402 const struct file_operations *fops;
403};
404
405struct it6505 {
406 struct drm_dp_aux aux;
407 struct drm_bridge bridge;
408 struct device *dev;
409 struct it6505_drm_dp_link link;
410 struct it6505_platform_data pdata;
411 /*
412 * Mutex protects extcon and interrupt functions from interfering
413 * each other.
414 */
415 struct mutex extcon_lock;
416 struct mutex mode_lock; /* used to bridge_detect */
417 struct mutex aux_lock; /* used to aux data transfers */
418 struct regmap *regmap;
419 struct drm_display_mode source_output_mode;
420 struct drm_display_mode video_info;
421 struct notifier_block event_nb;
422 struct extcon_dev *extcon;
423 struct work_struct extcon_wq;
424 int extcon_state;
425 enum drm_connector_status connector_status;
426 enum link_train_status link_state;
427 struct work_struct link_works;
428 u8 dpcd[DP_RECEIVER_CAP_SIZE];
429 u8 lane_count;
430 u8 link_rate_bw_code;
431 u8 sink_count;
432 bool step_train;
433 bool branch_device;
434 bool enable_ssc;
435 bool lane_swap_disabled;
436 bool lane_swap;
437 bool powered;
438 bool hpd_state;
439 u32 afe_setting;
440 u32 max_dpi_pixel_clock;
441 u32 max_lane_count;
442 enum hdcp_state hdcp_status;
443 struct delayed_work hdcp_work;
444 struct work_struct hdcp_wait_ksv_list;
445 struct completion extcon_completion;
446 u8 auto_train_retry;
447 bool hdcp_desired;
448 bool is_repeater;
449 u8 hdcp_down_stream_count;
450 u8 bksvs[DRM_HDCP_KSV_LEN];
451 u8 sha1_input[HDCP_SHA1_FIFO_LEN];
452 bool enable_enhanced_frame;
453 hdmi_codec_plugged_cb plugged_cb;
454 struct device *codec_dev;
455 struct delayed_work delayed_audio;
456 struct it6505_audio_data audio;
457 struct dentry *debugfs;
458
459 /* it6505 driver hold option */
460 bool enable_drv_hold;
461
462 const struct drm_edid *cached_edid;
463
464 int irq;
465};
466
467struct it6505_step_train_para {
468 u8 voltage_swing[MAX_LANE_COUNT];
469 u8 pre_emphasis[MAX_LANE_COUNT];
470};
471
472/*
473 * Vendor option afe settings for different platforms
474 * 0: without FPC cable
475 * 1: with FPC cable
476 */
477
478static const u8 afe_setting_table[][3] = {
479 {0x82, 0x00, 0x45},
480 {0x93, 0x2A, 0x85}
481};
482
483static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
484 {SAMPLE_RATE_24K, 24000},
485 {SAMPLE_RATE_32K, 32000},
486 {SAMPLE_RATE_48K, 48000},
487 {SAMPLE_RATE_96K, 96000},
488 {SAMPLE_RATE_192K, 192000},
489 {SAMPLE_RATE_44_1K, 44100},
490 {SAMPLE_RATE_88_2K, 88200},
491 {SAMPLE_RATE_176_4K, 176400},
492};
493
494static const struct regmap_range it6505_bridge_volatile_ranges[] = {
495 { .range_min = 0, .range_max = 0x1FF },
496};
497
498static const struct regmap_access_table it6505_bridge_volatile_table = {
499 .yes_ranges = it6505_bridge_volatile_ranges,
500 .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
501};
502
503static const struct regmap_range_cfg it6505_regmap_banks[] = {
504 {
505 .name = "it6505",
506 .range_min = 0x00,
507 .range_max = 0x1FF,
508 .selector_reg = REG_BANK_SEL,
509 .selector_mask = 0x1,
510 .selector_shift = 0,
511 .window_start = 0x00,
512 .window_len = 0x100,
513 },
514};
515
516static const struct regmap_config it6505_regmap_config = {
517 .reg_bits = 8,
518 .val_bits = 8,
519 .volatile_table = &it6505_bridge_volatile_table,
520 .cache_type = REGCACHE_NONE,
521 .ranges = it6505_regmap_banks,
522 .num_ranges = ARRAY_SIZE(it6505_regmap_banks),
523 .max_register = 0x1FF,
524};
525
526static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
527{
528 unsigned int value;
529 int err;
530 struct device *dev = it6505->dev;
531
532 if (!it6505->powered)
533 return -ENODEV;
534
535 err = regmap_read(it6505->regmap, reg_addr, &value);
536 if (err < 0) {
537 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
538 return err;
539 }
540
541 return value;
542}
543
544static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
545 unsigned int reg_val)
546{
547 int err;
548 struct device *dev = it6505->dev;
549
550 if (!it6505->powered)
551 return -ENODEV;
552
553 err = regmap_write(it6505->regmap, reg_addr, reg_val);
554
555 if (err < 0) {
556 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
557 reg_addr, reg_val, err);
558 return err;
559 }
560
561 return 0;
562}
563
564static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
565 unsigned int mask, unsigned int value)
566{
567 int err;
568 struct device *dev = it6505->dev;
569
570 if (!it6505->powered)
571 return -ENODEV;
572
573 err = regmap_update_bits(it6505->regmap, reg, mask, value);
574 if (err < 0) {
575 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
576 reg, value, mask, err);
577 return err;
578 }
579
580 return 0;
581}
582
583static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
584 const char *prefix)
585{
586 struct device *dev = it6505->dev;
587 int val;
588
589 if (!drm_debug_enabled(DRM_UT_DRIVER))
590 return;
591
592 val = it6505_read(it6505, reg);
593 if (val < 0)
594 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
595 prefix, reg, val);
596 else
597 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
598 val);
599}
600
601static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
602{
603 u8 value;
604 int ret;
605 struct device *dev = it6505->dev;
606
607 ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
608 if (ret < 0) {
609 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
610 return ret;
611 }
612 return value;
613}
614
615static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
616 u8 datain)
617{
618 int ret;
619 struct device *dev = it6505->dev;
620
621 ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
622 if (ret < 0) {
623 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
624 return ret;
625 }
626 return 0;
627}
628
629static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
630{
631 int ret;
632 struct device *dev = it6505->dev;
633
634 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
635
636 if (ret < 0)
637 return ret;
638
639 DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
640 num, dpcd);
641
642 return 0;
643}
644
645static void it6505_dump(struct it6505 *it6505)
646{
647 unsigned int i, j;
648 u8 regs[16];
649 struct device *dev = it6505->dev;
650
651 for (i = 0; i <= 0xff; i += 16) {
652 for (j = 0; j < 16; j++)
653 regs[j] = it6505_read(it6505, i + j);
654
655 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
656 }
657}
658
659static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
660{
661 int reg_0d;
662
663 reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
664
665 if (reg_0d < 0)
666 return false;
667
668 return reg_0d & HPD_STS;
669}
670
671static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
672{
673 int val0, val1;
674
675 val0 = it6505_read(it6505, reg);
676 if (val0 < 0)
677 return val0;
678
679 val1 = it6505_read(it6505, reg + 1);
680 if (val1 < 0)
681 return val1;
682
683 return (val1 << 8) | val0;
684}
685
686static void it6505_calc_video_info(struct it6505 *it6505)
687{
688 struct device *dev = it6505->dev;
689 int hsync_pol, vsync_pol, interlaced;
690 int htotal, hdes, hdew, hfph, hsyncw;
691 int vtotal, vdes, vdew, vfph, vsyncw;
692 int rddata, i, pclk, sum = 0;
693
694 usleep_range(10000, 15000);
695 rddata = it6505_read(it6505, REG_INPUT_CTRL);
696 hsync_pol = rddata & INPUT_HSYNC_POL;
697 vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
698 interlaced = (rddata & INPUT_INTERLACED) >> 4;
699
700 htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
701 hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
702 hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
703 hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
704 hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
705
706 vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
707 vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
708 vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
709 vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
710 vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
711
712 DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
713 hsync_pol, vsync_pol, interlaced);
714 DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
715 hdes, vdes);
716
717 for (i = 0; i < 3; i++) {
718 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
719 ENABLE_PCLK_COUNTER);
720 usleep_range(10000, 15000);
721 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
722 0x00);
723 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
724 0xFFF;
725
726 sum += rddata;
727 }
728
729 if (sum == 0) {
730 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
731 return;
732 }
733
734 sum /= 3;
735 pclk = 13500 * 2048 / sum;
736 it6505->video_info.clock = pclk;
737 it6505->video_info.hdisplay = hdew;
738 it6505->video_info.hsync_start = hdew + hfph;
739 it6505->video_info.hsync_end = hdew + hfph + hsyncw;
740 it6505->video_info.htotal = htotal;
741 it6505->video_info.vdisplay = vdew;
742 it6505->video_info.vsync_start = vdew + vfph;
743 it6505->video_info.vsync_end = vdew + vfph + vsyncw;
744 it6505->video_info.vtotal = vtotal;
745
746 DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
747 DRM_MODE_ARG(&it6505->video_info));
748}
749
750static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
751 struct it6505_drm_dp_link *link,
752 u8 mode)
753{
754 u8 value;
755 int err;
756
757 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
758 if (link->revision < DPCD_V_1_1)
759 return 0;
760
761 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
762 if (err < 0)
763 return err;
764
765 value &= ~DP_SET_POWER_MASK;
766 value |= mode;
767
768 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
769 if (err < 0)
770 return err;
771
772 if (mode == DP_SET_POWER_D0) {
773 /*
774 * According to the DP 1.1 specification, a "Sink Device must
775 * exit the power saving state within 1 ms" (Section 2.5.3.1,
776 * Table 5-52, "Sink Control Field" (register 0x600).
777 */
778 usleep_range(1000, 2000);
779 }
780
781 return 0;
782}
783
784static void it6505_clear_int(struct it6505 *it6505)
785{
786 it6505_write(it6505, INT_STATUS_01, 0xFF);
787 it6505_write(it6505, INT_STATUS_02, 0xFF);
788 it6505_write(it6505, INT_STATUS_03, 0xFF);
789}
790
791static void it6505_int_mask_enable(struct it6505 *it6505)
792{
793 it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
794 BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
795 BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
796
797 it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
798 BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
799
800 it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
801 BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
802}
803
804static void it6505_int_mask_disable(struct it6505 *it6505)
805{
806 it6505_write(it6505, INT_MASK_01, 0x00);
807 it6505_write(it6505, INT_MASK_02, 0x00);
808 it6505_write(it6505, INT_MASK_03, 0x00);
809}
810
811static void it6505_lane_termination_on(struct it6505 *it6505)
812{
813 int regcf;
814
815 regcf = it6505_read(it6505, REG_USER_DRV_PRE);
816
817 if (regcf == MISC_VERB)
818 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
819
820 if (regcf == MISC_VERC) {
821 if (it6505->lane_swap) {
822 switch (it6505->lane_count) {
823 case 1:
824 case 2:
825 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
826 0x0C, 0x08);
827 break;
828 default:
829 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
830 0x0C, 0x0C);
831 break;
832 }
833 } else {
834 switch (it6505->lane_count) {
835 case 1:
836 case 2:
837 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
838 0x0C, 0x04);
839 break;
840 default:
841 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
842 0x0C, 0x0C);
843 break;
844 }
845 }
846 }
847}
848
849static void it6505_lane_termination_off(struct it6505 *it6505)
850{
851 int regcf;
852
853 regcf = it6505_read(it6505, REG_USER_DRV_PRE);
854
855 if (regcf == MISC_VERB)
856 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
857
858 if (regcf == MISC_VERC)
859 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
860}
861
862static void it6505_lane_power_on(struct it6505 *it6505)
863{
864 it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
865 (it6505->lane_swap ?
866 GENMASK(7, 8 - it6505->lane_count) :
867 GENMASK(3 + it6505->lane_count, 4)) |
868 0x01);
869}
870
871static void it6505_lane_power_off(struct it6505 *it6505)
872{
873 it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
874}
875
876static void it6505_lane_off(struct it6505 *it6505)
877{
878 it6505_lane_power_off(it6505);
879 it6505_lane_termination_off(it6505);
880}
881
882static void it6505_aux_termination_on(struct it6505 *it6505)
883{
884 int regcf;
885
886 regcf = it6505_read(it6505, REG_USER_DRV_PRE);
887
888 if (regcf == MISC_VERB)
889 it6505_lane_termination_on(it6505);
890
891 if (regcf == MISC_VERC)
892 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
893}
894
895static void it6505_aux_power_on(struct it6505 *it6505)
896{
897 it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
898}
899
900static void it6505_aux_on(struct it6505 *it6505)
901{
902 it6505_aux_power_on(it6505);
903 it6505_aux_termination_on(it6505);
904}
905
906static void it6505_aux_reset(struct it6505 *it6505)
907{
908 it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
909 it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
910}
911
912static void it6505_reset_logic(struct it6505 *it6505)
913{
914 regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
915 usleep_range(1000, 1500);
916}
917
918static bool it6505_aux_op_finished(struct it6505 *it6505)
919{
920 int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
921
922 if (reg2b < 0)
923 return false;
924
925 return (reg2b & AUX_BUSY) == 0;
926}
927
928static int it6505_aux_wait(struct it6505 *it6505)
929{
930 int status;
931 unsigned long timeout;
932 struct device *dev = it6505->dev;
933
934 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
935
936 while (!it6505_aux_op_finished(it6505)) {
937 if (time_after(jiffies, timeout)) {
938 dev_err(dev, "Timed out waiting AUX to finish");
939 return -ETIMEDOUT;
940 }
941 usleep_range(1000, 2000);
942 }
943
944 status = it6505_read(it6505, REG_AUX_ERROR_STS);
945 if (status < 0) {
946 dev_err(dev, "Failed to read AUX channel: %d", status);
947 return status;
948 }
949
950 return 0;
951}
952
953static ssize_t it6505_aux_operation(struct it6505 *it6505,
954 enum aux_cmd_type cmd,
955 unsigned int address, u8 *buffer,
956 size_t size, enum aux_cmd_reply *reply)
957{
958 int i, ret;
959 bool aux_write_check = false;
960
961 if (!it6505_get_sink_hpd_status(it6505))
962 return -EIO;
963
964 /* set AUX user mode */
965 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
966
967aux_op_start:
968 if (cmd == CMD_AUX_I2C_EDID_READ) {
969 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
970 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
971 /* Enable AUX FIFO read back and clear FIFO */
972 it6505_set_bits(it6505, REG_AUX_CTRL,
973 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
974 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
975
976 it6505_set_bits(it6505, REG_AUX_CTRL,
977 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
978 AUX_EN_FIFO_READ);
979 } else {
980 /* The DP AUX transmit buffer has 4 bytes. */
981 size = min_t(size_t, size, 4);
982 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
983 AUX_NO_SEGMENT_WR);
984 }
985
986 /* Start Address[7:0] */
987 it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
988 /* Start Address[15:8] */
989 it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
990 /* WriteNum[3:0]+StartAdr[19:16] */
991 it6505_write(it6505, REG_AUX_ADR_16_19,
992 ((address >> 16) & 0x0F) | ((size - 1) << 4));
993
994 if (cmd == CMD_AUX_NATIVE_WRITE)
995 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
996 size);
997
998 /* Aux Fire */
999 it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
1000
1001 ret = it6505_aux_wait(it6505);
1002 if (ret < 0)
1003 goto aux_op_err;
1004
1005 ret = it6505_read(it6505, REG_AUX_ERROR_STS);
1006 if (ret < 0)
1007 goto aux_op_err;
1008
1009 switch ((ret >> 6) & 0x3) {
1010 case 0:
1011 *reply = REPLY_ACK;
1012 break;
1013 case 1:
1014 *reply = REPLY_DEFER;
1015 ret = -EAGAIN;
1016 goto aux_op_err;
1017 case 2:
1018 *reply = REPLY_NACK;
1019 ret = -EIO;
1020 goto aux_op_err;
1021 case 3:
1022 ret = -ETIMEDOUT;
1023 goto aux_op_err;
1024 }
1025
1026 /* Read back Native Write data */
1027 if (cmd == CMD_AUX_NATIVE_WRITE) {
1028 aux_write_check = true;
1029 cmd = CMD_AUX_NATIVE_READ;
1030 goto aux_op_start;
1031 }
1032
1033 if (cmd == CMD_AUX_I2C_EDID_READ) {
1034 for (i = 0; i < size; i++) {
1035 ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1036 if (ret < 0)
1037 goto aux_op_err;
1038 buffer[i] = ret;
1039 }
1040 } else {
1041 for (i = 0; i < size; i++) {
1042 ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1043 if (ret < 0)
1044 goto aux_op_err;
1045
1046 if (aux_write_check && buffer[size - 1 - i] != ret) {
1047 ret = -EINVAL;
1048 goto aux_op_err;
1049 }
1050
1051 buffer[size - 1 - i] = ret;
1052 }
1053 }
1054
1055 ret = i;
1056
1057aux_op_err:
1058 if (cmd == CMD_AUX_I2C_EDID_READ) {
1059 /* clear AUX FIFO */
1060 it6505_set_bits(it6505, REG_AUX_CTRL,
1061 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1062 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1063 it6505_set_bits(it6505, REG_AUX_CTRL,
1064 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1065 }
1066
1067 /* Leave AUX user mode */
1068 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1069
1070 return ret;
1071}
1072
1073static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1074 enum aux_cmd_type cmd,
1075 unsigned int address, u8 *buffer,
1076 size_t size, enum aux_cmd_reply *reply)
1077{
1078 int i, ret_size, ret = 0, request_size;
1079
1080 mutex_lock(&it6505->aux_lock);
1081 for (i = 0; i < size; i += 4) {
1082 request_size = min((int)size - i, 4);
1083 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1084 buffer + i, request_size,
1085 reply);
1086 if (ret_size < 0) {
1087 ret = ret_size;
1088 goto aux_op_err;
1089 }
1090
1091 ret += ret_size;
1092 }
1093
1094aux_op_err:
1095 mutex_unlock(&it6505->aux_lock);
1096 return ret;
1097}
1098
1099static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1100 struct drm_dp_aux_msg *msg)
1101{
1102 struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1103 u8 cmd;
1104 bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1105 int ret;
1106 enum aux_cmd_reply reply;
1107
1108 /* IT6505 doesn't support arbitrary I2C read / write. */
1109 if (is_i2c)
1110 return -EINVAL;
1111
1112 switch (msg->request) {
1113 case DP_AUX_NATIVE_READ:
1114 cmd = CMD_AUX_NATIVE_READ;
1115 break;
1116 case DP_AUX_NATIVE_WRITE:
1117 cmd = CMD_AUX_NATIVE_WRITE;
1118 break;
1119 default:
1120 return -EINVAL;
1121 }
1122
1123 ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1124 msg->size, &reply);
1125 if (ret < 0)
1126 return ret;
1127
1128 switch (reply) {
1129 case REPLY_ACK:
1130 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1131 break;
1132 case REPLY_NACK:
1133 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1134 break;
1135 case REPLY_DEFER:
1136 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1137 break;
1138 }
1139
1140 return ret;
1141}
1142
1143static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1144 size_t len)
1145{
1146 struct it6505 *it6505 = data;
1147 struct device *dev = it6505->dev;
1148 enum aux_cmd_reply reply;
1149 int offset, ret, aux_retry = 100;
1150
1151 it6505_aux_reset(it6505);
1152 DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1153
1154 for (offset = 0; offset < EDID_LENGTH;) {
1155 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1156 block * EDID_LENGTH + offset,
1157 buf + offset, 8, &reply);
1158
1159 if (ret < 0 && ret != -EAGAIN)
1160 return ret;
1161
1162 switch (reply) {
1163 case REPLY_ACK:
1164 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1165 buf + offset);
1166 offset += 8;
1167 aux_retry = 100;
1168 break;
1169 case REPLY_NACK:
1170 return -EIO;
1171 case REPLY_DEFER:
1172 msleep(20);
1173 if (!(--aux_retry))
1174 return -EIO;
1175 }
1176 }
1177
1178 return 0;
1179}
1180
1181static void it6505_variable_config(struct it6505 *it6505)
1182{
1183 it6505->link_rate_bw_code = HBR;
1184 it6505->lane_count = MAX_LANE_COUNT;
1185 it6505->link_state = LINK_IDLE;
1186 it6505->hdcp_desired = HDCP_DESIRED;
1187 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1188 it6505->audio.select = AUDIO_SELECT;
1189 it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1190 it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1191 it6505->audio.type = AUDIO_TYPE;
1192 it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1193 it6505->audio.i2s_justified = I2S_JUSTIFIED;
1194 it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1195 it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1196 it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1197 it6505->audio.word_length = AUDIO_WORD_LENGTH;
1198 memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1199 memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1200}
1201
1202static int it6505_send_video_infoframe(struct it6505 *it6505,
1203 struct hdmi_avi_infoframe *frame)
1204{
1205 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1206 int err;
1207 struct device *dev = it6505->dev;
1208
1209 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1210 if (err < 0) {
1211 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1212 return err;
1213 }
1214
1215 err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1216 if (err)
1217 return err;
1218
1219 err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1220 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1221 frame->length);
1222 if (err)
1223 return err;
1224
1225 err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1226 EN_AVI_PKT);
1227 if (err)
1228 return err;
1229
1230 return 0;
1231}
1232
1233static void it6505_get_extcon_property(struct it6505 *it6505)
1234{
1235 int err;
1236 union extcon_property_value property;
1237 struct device *dev = it6505->dev;
1238
1239 if (it6505->extcon && !it6505->lane_swap_disabled) {
1240 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1241 EXTCON_PROP_USB_TYPEC_POLARITY,
1242 &property);
1243 if (err) {
1244 dev_err(dev, "get property fail!");
1245 return;
1246 }
1247 it6505->lane_swap = property.intval;
1248 }
1249}
1250
1251static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1252 const struct drm_display_mode *mode)
1253{
1254 int clock = mode->clock;
1255
1256 it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1257 clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1258 it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1259 PIXEL_CLK_INVERSE << 4);
1260}
1261
1262static void it6505_link_reset_step_train(struct it6505 *it6505)
1263{
1264 it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1265 FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1266 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1267 DP_TRAINING_PATTERN_DISABLE);
1268}
1269
1270static void it6505_init(struct it6505 *it6505)
1271{
1272 it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1273 it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1274 it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1275 it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1276 it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1277 it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1278
1279 /* chip internal setting, don't modify */
1280 it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1281 it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1282 it6505_write(it6505, REG_AUX_OPT2, 0x17);
1283 it6505_write(it6505, REG_HDCP_OPT, 0x60);
1284 it6505_write(it6505, REG_DATA_MUTE_CTRL,
1285 EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1286 it6505_write(it6505, REG_TIME_STMP_CTRL,
1287 EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1288 it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1289 it6505_write(it6505, REG_DRV_0_DB_800_MV,
1290 afe_setting_table[it6505->afe_setting][0]);
1291 it6505_write(it6505, REG_PRE_0_DB_800_MV,
1292 afe_setting_table[it6505->afe_setting][1]);
1293 it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1294 afe_setting_table[it6505->afe_setting][2]);
1295 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1296 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1297 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1298}
1299
1300static void it6505_video_disable(struct it6505 *it6505)
1301{
1302 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1303 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1304 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1305}
1306
1307static void it6505_video_reset(struct it6505 *it6505)
1308{
1309 it6505_link_reset_step_train(it6505);
1310 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1311 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1312
1313 it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FIFO_RESET);
1314 it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00);
1315
1316 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1317 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1318
1319 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1320 usleep_range(1000, 2000);
1321 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1322}
1323
1324static void it6505_update_video_parameter(struct it6505 *it6505,
1325 const struct drm_display_mode *mode)
1326{
1327 it6505_clk_phase_adjustment(it6505, mode);
1328 it6505_video_disable(it6505);
1329}
1330
1331static bool it6505_audio_input(struct it6505 *it6505)
1332{
1333 int reg05, regbe;
1334
1335 reg05 = it6505_read(it6505, REG_RESET_CTRL);
1336 it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1337 usleep_range(3000, 4000);
1338 regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1339 it6505_write(it6505, REG_RESET_CTRL, reg05);
1340
1341 return regbe != 0xFF;
1342}
1343
1344static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1345{
1346 enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1347 u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1348
1349 /* Channel Status */
1350 it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1351 it6505_write(it6505, REG_IEC958_STS1, 0x00);
1352 it6505_write(it6505, REG_IEC958_STS2, 0x00);
1353 it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1354 it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1355 audio_word_length_map[it6505->audio.word_length]);
1356}
1357
1358static void it6505_setup_audio_format(struct it6505 *it6505)
1359{
1360 /* I2S MODE */
1361 it6505_write(it6505, REG_AUDIO_FMT,
1362 (it6505->audio.word_length << 5) |
1363 (it6505->audio.i2s_data_sequence << 4) |
1364 (it6505->audio.i2s_ws_channel << 3) |
1365 (it6505->audio.i2s_data_delay << 2) |
1366 (it6505->audio.i2s_justified << 1) |
1367 it6505->audio.i2s_input_format);
1368 if (it6505->audio.select == SPDIF) {
1369 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1370 /* 0x30 = 128*FS */
1371 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1372 } else {
1373 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1374 }
1375
1376 it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1377 it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1378}
1379
1380static void it6505_enable_audio_source(struct it6505 *it6505)
1381{
1382 unsigned int audio_source_count;
1383
1384 audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1385 - 1;
1386
1387 audio_source_count |= it6505->audio.select << 4;
1388
1389 it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1390}
1391
1392static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1393{
1394 struct device *dev = it6505->dev;
1395 u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1396
1397 DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1398 audio_info_ca[it6505->audio.channel_count - 1]);
1399
1400 it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1401 - 1);
1402 it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1403 it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1404 audio_info_ca[it6505->audio.channel_count - 1]);
1405 it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1406 it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1407
1408 /* Enable Audio InfoFrame */
1409 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1410 EN_AUD_CTRL_PKT);
1411}
1412
1413static void it6505_disable_audio(struct it6505 *it6505)
1414{
1415 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1416 it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1417 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1418 it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1419}
1420
1421static void it6505_enable_audio(struct it6505 *it6505)
1422{
1423 struct device *dev = it6505->dev;
1424 int regbe;
1425
1426 DRM_DEV_DEBUG_DRIVER(dev, "start");
1427 it6505_disable_audio(it6505);
1428
1429 it6505_setup_audio_channel_status(it6505);
1430 it6505_setup_audio_format(it6505);
1431 it6505_enable_audio_source(it6505);
1432 it6505_enable_audio_infoframe(it6505);
1433
1434 it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1435 it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1436 it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1437
1438 it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1439 AUDIO_FIFO_RESET);
1440 it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1441 it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1442 regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1443 DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1444 regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1445 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1446}
1447
1448static bool it6505_use_step_train_check(struct it6505 *it6505)
1449{
1450 if (it6505->link.revision >= 0x12)
1451 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1452
1453 return true;
1454}
1455
1456static void it6505_parse_link_capabilities(struct it6505 *it6505)
1457{
1458 struct device *dev = it6505->dev;
1459 struct it6505_drm_dp_link *link = &it6505->link;
1460 int bcaps;
1461
1462 if (it6505->dpcd[0] == 0) {
1463 dev_err(dev, "DPCD is not initialized");
1464 return;
1465 }
1466
1467 memset(link, 0, sizeof(*link));
1468
1469 link->revision = it6505->dpcd[0];
1470 link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1471 link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1472
1473 if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1474 link->capabilities = DP_ENHANCED_FRAME_CAP;
1475
1476 DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1477 link->revision >> 4, link->revision & 0x0F);
1478
1479 DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1480 link->rate / 100000, link->rate / 1000 % 100);
1481
1482 it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1483 DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1484 it6505->link_rate_bw_code);
1485 it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1486 MAX_LINK_RATE);
1487
1488 it6505->lane_count = link->num_lanes;
1489 DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1490 it6505->lane_count);
1491 it6505->lane_count = min_t(int, it6505->lane_count,
1492 it6505->max_lane_count);
1493
1494 it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1495 DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1496 it6505->branch_device ? "" : "Not ");
1497
1498 it6505->enable_enhanced_frame = link->capabilities;
1499 DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1500 it6505->enable_enhanced_frame ? "" : "Not ");
1501
1502 it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1503 DP_MAX_DOWNSPREAD_0_5);
1504 DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1505 it6505->enable_ssc ? "0.5" : "0",
1506 it6505->enable_ssc ? "" : "Not ");
1507
1508 it6505->step_train = it6505_use_step_train_check(it6505);
1509 if (it6505->step_train)
1510 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1511
1512 bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1513 DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1514 if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1515 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1516 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1517 it6505->is_repeater ? "repeater" :
1518 "receiver");
1519 } else {
1520 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1521 it6505->hdcp_desired = false;
1522 }
1523 DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1524 it6505->hdcp_desired ? "desired" : "undesired");
1525}
1526
1527static void it6505_setup_ssc(struct it6505 *it6505)
1528{
1529 it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1530 it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1531 if (it6505->enable_ssc) {
1532 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1533 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1534 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1535 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1536 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1537 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1538 /* Stamp Interrupt Step */
1539 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1540 0x10);
1541 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1542 DP_SPREAD_AMP_0_5);
1543 } else {
1544 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1545 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1546 0x00);
1547 }
1548}
1549
1550static inline void it6505_link_rate_setup(struct it6505 *it6505)
1551{
1552 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1553 (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1554 it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1555 (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1556}
1557
1558static void it6505_lane_count_setup(struct it6505 *it6505)
1559{
1560 it6505_get_extcon_property(it6505);
1561 it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1562 it6505->lane_swap ? LANE_SWAP : 0x00);
1563 it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1564 (it6505->lane_count - 1) << 1);
1565}
1566
1567static void it6505_link_training_setup(struct it6505 *it6505)
1568{
1569 struct device *dev = it6505->dev;
1570
1571 if (it6505->enable_enhanced_frame)
1572 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1573 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1574
1575 it6505_link_rate_setup(it6505);
1576 it6505_lane_count_setup(it6505);
1577 it6505_setup_ssc(it6505);
1578 DRM_DEV_DEBUG_DRIVER(dev,
1579 "%s, %d lanes, %sable ssc, %sable enhanced frame",
1580 it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1581 it6505->lane_count,
1582 it6505->enable_ssc ? "en" : "dis",
1583 it6505->enable_enhanced_frame ? "en" : "dis");
1584}
1585
1586static bool it6505_link_start_auto_train(struct it6505 *it6505)
1587{
1588 int timeout = 500, link_training_state;
1589 bool state = false;
1590
1591 mutex_lock(&it6505->aux_lock);
1592 it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1593 FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1594 it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1595 it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1596
1597 while (timeout > 0) {
1598 usleep_range(1000, 2000);
1599 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1600
1601 if (link_training_state > 0 &&
1602 (link_training_state & LINK_STATE_NORP)) {
1603 state = true;
1604 goto unlock;
1605 }
1606
1607 timeout--;
1608 }
1609unlock:
1610 mutex_unlock(&it6505->aux_lock);
1611
1612 return state;
1613}
1614
1615static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1616{
1617 u8 values[2];
1618 int err;
1619 struct drm_dp_aux *aux = &it6505->aux;
1620
1621 values[0] = it6505->link_rate_bw_code;
1622 values[1] = it6505->lane_count;
1623
1624 if (it6505->enable_enhanced_frame)
1625 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1626
1627 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1628 if (err < 0)
1629 return err;
1630
1631 return 0;
1632}
1633
1634static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1635{
1636 return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1637}
1638
1639static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1640{
1641 return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1642}
1643
1644static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1645 u8 lane_count)
1646{
1647 u8 i;
1648
1649 for (i = 0; i < lane_count; i++) {
1650 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1651 return true;
1652 }
1653
1654 return false;
1655}
1656
1657static bool
1658step_train_lane_voltage_para_set(struct it6505 *it6505,
1659 struct it6505_step_train_para
1660 *lane_voltage_pre_emphasis,
1661 u8 *lane_voltage_pre_emphasis_set)
1662{
1663 u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1664 u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1665 u8 i;
1666
1667 for (i = 0; i < it6505->lane_count; i++) {
1668 voltage_swing[i] &= 0x03;
1669 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1670 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1671 lane_voltage_pre_emphasis_set[i] |=
1672 DP_TRAIN_MAX_SWING_REACHED;
1673
1674 pre_emphasis[i] &= 0x03;
1675 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1676 << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1677 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1678 lane_voltage_pre_emphasis_set[i] |=
1679 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1680 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1681 lane_voltage_pre_emphasis_set[i]);
1682
1683 if (lane_voltage_pre_emphasis_set[i] !=
1684 it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1685 return false;
1686 }
1687
1688 return true;
1689}
1690
1691static bool
1692it6505_step_cr_train(struct it6505 *it6505,
1693 struct it6505_step_train_para *lane_voltage_pre_emphasis)
1694{
1695 u8 loop_count = 0, i = 0, j;
1696 u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1697 u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1698 int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1699 const struct drm_dp_aux *aux = &it6505->aux;
1700
1701 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1702 it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1703 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1704 DP_TRAINING_PATTERN_1);
1705
1706 while (loop_count < 5 && i < 10) {
1707 i++;
1708 if (!step_train_lane_voltage_para_set(it6505,
1709 lane_voltage_pre_emphasis,
1710 lane_level_config))
1711 continue;
1712 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1713 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1714
1715 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1716 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1717 FORCE_CR_DONE);
1718 return true;
1719 }
1720 DRM_DEV_DEBUG_DRIVER(it6505->dev, "cr not done");
1721
1722 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1723 it6505->lane_count))
1724 goto cr_train_fail;
1725
1726 for (j = 0; j < it6505->lane_count; j++) {
1727 lane_voltage_pre_emphasis->voltage_swing[j] =
1728 drm_dp_get_adjust_request_voltage(link_status,
1729 j) >>
1730 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1731 lane_voltage_pre_emphasis->pre_emphasis[j] =
1732 drm_dp_get_adjust_request_pre_emphasis(link_status,
1733 j) >>
1734 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1735 if (voltage_swing_adjust ==
1736 lane_voltage_pre_emphasis->voltage_swing[j] &&
1737 pre_emphasis_adjust ==
1738 lane_voltage_pre_emphasis->pre_emphasis[j]) {
1739 loop_count++;
1740 continue;
1741 }
1742
1743 voltage_swing_adjust =
1744 lane_voltage_pre_emphasis->voltage_swing[j];
1745 pre_emphasis_adjust =
1746 lane_voltage_pre_emphasis->pre_emphasis[j];
1747 loop_count = 0;
1748
1749 if (voltage_swing_adjust + pre_emphasis_adjust >
1750 MAX_EQ_LEVEL)
1751 lane_voltage_pre_emphasis->voltage_swing[j] =
1752 MAX_EQ_LEVEL -
1753 lane_voltage_pre_emphasis
1754 ->pre_emphasis[j];
1755 }
1756 }
1757
1758cr_train_fail:
1759 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1760 DP_TRAINING_PATTERN_DISABLE);
1761
1762 return false;
1763}
1764
1765static bool
1766it6505_step_eq_train(struct it6505 *it6505,
1767 struct it6505_step_train_para *lane_voltage_pre_emphasis)
1768{
1769 u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1770 u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1771 const struct drm_dp_aux *aux = &it6505->aux;
1772
1773 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1774 DP_TRAINING_PATTERN_2);
1775
1776 while (loop_count < 6) {
1777 loop_count++;
1778
1779 if (!step_train_lane_voltage_para_set(it6505,
1780 lane_voltage_pre_emphasis,
1781 lane_level_config))
1782 continue;
1783
1784 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1785 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1786
1787 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1788 goto eq_train_fail;
1789
1790 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1791 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1792 DP_TRAINING_PATTERN_DISABLE);
1793 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1794 FORCE_EQ_DONE);
1795 return true;
1796 }
1797 DRM_DEV_DEBUG_DRIVER(it6505->dev, "eq not done");
1798
1799 for (i = 0; i < it6505->lane_count; i++) {
1800 lane_voltage_pre_emphasis->voltage_swing[i] =
1801 drm_dp_get_adjust_request_voltage(link_status,
1802 i) >>
1803 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1804 lane_voltage_pre_emphasis->pre_emphasis[i] =
1805 drm_dp_get_adjust_request_pre_emphasis(link_status,
1806 i) >>
1807 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1808
1809 if (lane_voltage_pre_emphasis->voltage_swing[i] +
1810 lane_voltage_pre_emphasis->pre_emphasis[i] >
1811 MAX_EQ_LEVEL)
1812 lane_voltage_pre_emphasis->voltage_swing[i] =
1813 0x03 - lane_voltage_pre_emphasis
1814 ->pre_emphasis[i];
1815 }
1816 }
1817
1818eq_train_fail:
1819 it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1820 DP_TRAINING_PATTERN_DISABLE);
1821 return false;
1822}
1823
1824static bool it6505_link_start_step_train(struct it6505 *it6505)
1825{
1826 int err;
1827 struct it6505_step_train_para lane_voltage_pre_emphasis = {
1828 .voltage_swing = { 0 },
1829 .pre_emphasis = { 0 },
1830 };
1831
1832 DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
1833 err = it6505_drm_dp_link_configure(it6505);
1834
1835 if (err < 0)
1836 return false;
1837 if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1838 return false;
1839 if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1840 return false;
1841 return true;
1842}
1843
1844static bool it6505_get_video_status(struct it6505 *it6505)
1845{
1846 int reg_0d;
1847
1848 reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1849
1850 if (reg_0d < 0)
1851 return false;
1852
1853 return reg_0d & VIDEO_STB;
1854}
1855
1856static void it6505_reset_hdcp(struct it6505 *it6505)
1857{
1858 it6505->hdcp_status = HDCP_AUTH_IDLE;
1859 /* Disable CP_Desired */
1860 it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1861 it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1862}
1863
1864static void it6505_start_hdcp(struct it6505 *it6505)
1865{
1866 struct device *dev = it6505->dev;
1867
1868 DRM_DEV_DEBUG_DRIVER(dev, "start");
1869 it6505_reset_hdcp(it6505);
1870 queue_delayed_work(system_wq, &it6505->hdcp_work,
1871 msecs_to_jiffies(2400));
1872}
1873
1874static void it6505_stop_hdcp(struct it6505 *it6505)
1875{
1876 it6505_reset_hdcp(it6505);
1877 cancel_delayed_work(&it6505->hdcp_work);
1878}
1879
1880static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1881{
1882 int i, ones = 0;
1883
1884 /* KSV has 20 1's and 20 0's */
1885 for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1886 ones += hweight8(ksv[i]);
1887 if (ones != 20)
1888 return false;
1889 return true;
1890}
1891
1892static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1893{
1894 struct device *dev = it6505->dev;
1895 u8 hdcp_bcaps;
1896
1897 it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1898 /* Disable CP_Desired */
1899 it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1900
1901 usleep_range(1000, 1500);
1902 hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1903 DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1904 hdcp_bcaps);
1905
1906 if (!hdcp_bcaps)
1907 return;
1908
1909 /* clear the repeater List Chk Done and fail bit */
1910 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1911 HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1912 0x00);
1913
1914 /* Enable An Generator */
1915 it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1916 /* delay1ms(10);*/
1917 usleep_range(10000, 15000);
1918 /* Stop An Generator */
1919 it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1920
1921 it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1922
1923 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1924 HDCP_TRIGGER_START);
1925
1926 it6505->hdcp_status = HDCP_AUTH_GOING;
1927}
1928
1929static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1930 unsigned int size, u8 *output_av)
1931{
1932 struct shash_desc *desc;
1933 struct crypto_shash *tfm;
1934 int err;
1935 struct device *dev = it6505->dev;
1936
1937 tfm = crypto_alloc_shash("sha1", 0, 0);
1938 if (IS_ERR(tfm)) {
1939 dev_err(dev, "crypto_alloc_shash sha1 failed");
1940 return PTR_ERR(tfm);
1941 }
1942 desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1943 if (!desc) {
1944 crypto_free_shash(tfm);
1945 return -ENOMEM;
1946 }
1947
1948 desc->tfm = tfm;
1949 err = crypto_shash_digest(desc, sha1_input, size, output_av);
1950 if (err)
1951 dev_err(dev, "crypto_shash_digest sha1 failed");
1952
1953 crypto_free_shash(tfm);
1954 kfree(desc);
1955 return err;
1956}
1957
1958static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1959{
1960 struct device *dev = it6505->dev;
1961 u8 binfo[2];
1962 int down_stream_count, i, err, msg_count = 0;
1963
1964 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1965 ARRAY_SIZE(binfo));
1966
1967 if (err < 0) {
1968 dev_err(dev, "Read binfo value Fail");
1969 return err;
1970 }
1971
1972 down_stream_count = binfo[0] & 0x7F;
1973 DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1974 binfo);
1975
1976 if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1977 dev_err(dev, "HDCP max cascade device exceed");
1978 return 0;
1979 }
1980
1981 if (!down_stream_count ||
1982 down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1983 dev_err(dev, "HDCP down stream count Error %d",
1984 down_stream_count);
1985 return 0;
1986 }
1987
1988 for (i = 0; i < down_stream_count; i++) {
1989 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1990 (i % 3) * DRM_HDCP_KSV_LEN,
1991 sha1_input + msg_count,
1992 DRM_HDCP_KSV_LEN);
1993
1994 if (err < 0)
1995 return err;
1996
1997 msg_count += 5;
1998 }
1999
2000 it6505->hdcp_down_stream_count = down_stream_count;
2001 sha1_input[msg_count++] = binfo[0];
2002 sha1_input[msg_count++] = binfo[1];
2003
2004 it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
2005 HDCP_EN_M0_READ);
2006
2007 err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
2008 sha1_input + msg_count, 8);
2009
2010 it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
2011
2012 if (err < 0) {
2013 dev_err(dev, " Warning, Read M value Fail");
2014 return err;
2015 }
2016
2017 msg_count += 8;
2018
2019 return msg_count;
2020}
2021
2022static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2023{
2024 struct device *dev = it6505->dev;
2025 u8 av[5][4], bv[5][4];
2026 int i, err, retry;
2027
2028 i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2029 if (i <= 0) {
2030 dev_err(dev, "SHA-1 Input length error %d", i);
2031 return false;
2032 }
2033
2034 it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2035 /*1B-05 V' must retry 3 times */
2036 for (retry = 0; retry < 3; retry++) {
2037 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2038 sizeof(bv));
2039
2040 if (err < 0) {
2041 dev_err(dev, "Read V' value Fail %d", retry);
2042 continue;
2043 }
2044
2045 for (i = 0; i < 5; i++) {
2046 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2047 av[i][1] != av[i][2] || bv[i][0] != av[i][3])
2048 break;
2049
2050 DRM_DEV_DEBUG_DRIVER(dev, "V' all match!! %d, %d", retry, i);
2051 return true;
2052 }
2053 }
2054
2055 DRM_DEV_DEBUG_DRIVER(dev, "V' NOT match!! %d", retry);
2056 return false;
2057}
2058
2059static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2060{
2061 struct it6505 *it6505 = container_of(work, struct it6505,
2062 hdcp_wait_ksv_list);
2063 struct device *dev = it6505->dev;
2064 u8 bstatus;
2065 bool ksv_list_check;
2066 /* 1B-04 wait ksv list for 5s */
2067 unsigned long timeout = jiffies +
2068 msecs_to_jiffies(5000) + 1;
2069
2070 for (;;) {
2071 if (!it6505_get_sink_hpd_status(it6505))
2072 return;
2073
2074 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2075
2076 if (bstatus & DP_BSTATUS_READY)
2077 break;
2078
2079 if (time_after(jiffies, timeout)) {
2080 DRM_DEV_DEBUG_DRIVER(dev, "KSV list wait timeout");
2081 goto timeout;
2082 }
2083
2084 msleep(20);
2085 }
2086
2087 ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2088 DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2089 ksv_list_check ? "pass" : "fail");
2090
2091 if (ksv_list_check)
2092 return;
2093
2094timeout:
2095 it6505_start_hdcp(it6505);
2096}
2097
2098static void it6505_hdcp_work(struct work_struct *work)
2099{
2100 struct it6505 *it6505 = container_of(work, struct it6505,
2101 hdcp_work.work);
2102 struct device *dev = it6505->dev;
2103 int ret;
2104 u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2105
2106 DRM_DEV_DEBUG_DRIVER(dev, "start");
2107
2108 if (!it6505_get_sink_hpd_status(it6505))
2109 return;
2110
2111 ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2112 DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2113 (int)sizeof(link_status), link_status);
2114
2115 if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2116 !it6505_get_video_status(it6505)) {
2117 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2118 return;
2119 }
2120
2121 ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2122 ARRAY_SIZE(it6505->bksvs));
2123 if (ret < 0) {
2124 dev_err(dev, "fail to get bksv ret: %d", ret);
2125 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2126 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2127 }
2128
2129 DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2130 (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2131
2132 if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2133 dev_err(dev, "Display Port bksv not valid");
2134 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2135 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2136 }
2137
2138 it6505_hdcp_part1_auth(it6505);
2139}
2140
2141static void it6505_show_hdcp_info(struct it6505 *it6505)
2142{
2143 struct device *dev = it6505->dev;
2144 int i;
2145 u8 *sha1 = it6505->sha1_input;
2146
2147 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2148 it6505->hdcp_status, it6505->is_repeater);
2149 DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2150 (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2151
2152 if (it6505->is_repeater) {
2153 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2154 it6505->hdcp_down_stream_count);
2155 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2156 (int)ARRAY_SIZE(it6505->sha1_input),
2157 it6505->sha1_input);
2158 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2159 DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2160 DRM_HDCP_KSV_LEN, sha1);
2161 sha1 += DRM_HDCP_KSV_LEN;
2162 }
2163 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2164 sha1, sha1 + 2);
2165 }
2166}
2167
2168static void it6505_stop_link_train(struct it6505 *it6505)
2169{
2170 it6505->link_state = LINK_IDLE;
2171 cancel_work_sync(&it6505->link_works);
2172 it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2173}
2174
2175static void it6505_link_train_ok(struct it6505 *it6505)
2176{
2177 struct device *dev = it6505->dev;
2178
2179 it6505->link_state = LINK_OK;
2180 /* disalbe mute enable avi info frame */
2181 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2182 it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2183 EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2184
2185 if (it6505_audio_input(it6505)) {
2186 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2187 it6505_enable_audio(it6505);
2188 }
2189
2190 if (it6505->hdcp_desired)
2191 it6505_start_hdcp(it6505);
2192}
2193
2194static void it6505_link_step_train_process(struct it6505 *it6505)
2195{
2196 struct device *dev = it6505->dev;
2197 int ret, i, step_retry = 3;
2198
2199 DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2200
2201 if (it6505->sink_count == 0) {
2202 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2203 it6505->sink_count);
2204 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2205 FORCE_EQ_DONE);
2206 return;
2207 }
2208
2209 if (!it6505->step_train) {
2210 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2211 return;
2212 }
2213
2214 /* step training start here */
2215 for (i = 0; i < step_retry; i++) {
2216 it6505_link_reset_step_train(it6505);
2217 ret = it6505_link_start_step_train(it6505);
2218 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2219 ret ? "pass" : "failed", i + 1);
2220 if (ret) {
2221 it6505_link_train_ok(it6505);
2222 return;
2223 }
2224 }
2225
2226 DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2227 it6505->link_state = LINK_IDLE;
2228 it6505_video_reset(it6505);
2229}
2230
2231static void it6505_link_training_work(struct work_struct *work)
2232{
2233 struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2234 struct device *dev = it6505->dev;
2235 int ret;
2236
2237 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2238 it6505->sink_count);
2239
2240 if (!it6505_get_sink_hpd_status(it6505))
2241 return;
2242
2243 it6505_link_training_setup(it6505);
2244 it6505_reset_hdcp(it6505);
2245 it6505_aux_reset(it6505);
2246
2247 if (it6505->auto_train_retry < 1) {
2248 it6505_link_step_train_process(it6505);
2249 return;
2250 }
2251
2252 ret = it6505_link_start_auto_train(it6505);
2253 DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2254 ret ? "pass" : "failed", it6505->auto_train_retry);
2255
2256 if (ret) {
2257 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2258 it6505_link_train_ok(it6505);
2259 } else {
2260 it6505->auto_train_retry--;
2261 it6505_dump(it6505);
2262 }
2263
2264}
2265
2266static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2267{
2268 enum drm_connector_status status = it6505->connector_status;
2269
2270 if (it6505->plugged_cb && it6505->codec_dev)
2271 it6505->plugged_cb(it6505->codec_dev,
2272 status == connector_status_connected);
2273}
2274
2275static void it6505_remove_edid(struct it6505 *it6505)
2276{
2277 drm_edid_free(it6505->cached_edid);
2278 it6505->cached_edid = NULL;
2279}
2280
2281static int it6505_process_hpd_irq(struct it6505 *it6505)
2282{
2283 struct device *dev = it6505->dev;
2284 int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2285 u8 link_status[DP_LINK_STATUS_SIZE];
2286
2287 if (!it6505_get_sink_hpd_status(it6505)) {
2288 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2289 it6505->sink_count = 0;
2290 return 0;
2291 }
2292
2293 ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2294 if (ret < 0)
2295 return ret;
2296
2297 dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2298 DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2299 dpcd_sink_count, it6505->sink_count);
2300
2301 if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2302 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2303 it6505->sink_count = dpcd_sink_count;
2304 it6505_reset_logic(it6505);
2305 it6505_int_mask_enable(it6505);
2306 it6505_init(it6505);
2307 it6505_remove_edid(it6505);
2308 return 0;
2309 }
2310
2311 dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2312 if (dp_irq_vector < 0)
2313 return dp_irq_vector;
2314
2315 DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2316
2317 if (dp_irq_vector & DP_CP_IRQ) {
2318 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2319 if (bstatus < 0)
2320 return bstatus;
2321
2322 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2323
2324 /*Check BSTATUS when recive CP_IRQ */
2325 if (bstatus & DP_BSTATUS_R0_PRIME_READY &&
2326 it6505->hdcp_status == HDCP_AUTH_GOING)
2327 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2328 HDCP_TRIGGER_CPIRQ);
2329 else if (bstatus & (DP_BSTATUS_REAUTH_REQ | DP_BSTATUS_LINK_FAILURE) &&
2330 it6505->hdcp_status == HDCP_AUTH_DONE)
2331 it6505_start_hdcp(it6505);
2332 }
2333
2334 ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2335 if (ret < 0) {
2336 dev_err(dev, "Fail to read link status ret: %d", ret);
2337 return ret;
2338 }
2339
2340 DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2341 (int)ARRAY_SIZE(link_status), link_status);
2342
2343 if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2344 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2345 it6505_video_reset(it6505);
2346 }
2347
2348 return 0;
2349}
2350
2351static void it6505_irq_hpd(struct it6505 *it6505)
2352{
2353 struct device *dev = it6505->dev;
2354 int dp_sink_count;
2355
2356 it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2357 DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2358 it6505->hpd_state ? "high" : "low");
2359
2360 if (it6505->hpd_state) {
2361 wait_for_completion_timeout(&it6505->extcon_completion,
2362 msecs_to_jiffies(1000));
2363 it6505_aux_on(it6505);
2364 if (it6505->dpcd[0] == 0) {
2365 it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2366 ARRAY_SIZE(it6505->dpcd));
2367 it6505_variable_config(it6505);
2368 it6505_parse_link_capabilities(it6505);
2369 }
2370 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2371
2372 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2373 DP_SET_POWER_D0);
2374 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2375 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2376
2377 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2378 it6505->sink_count);
2379
2380 it6505_lane_termination_on(it6505);
2381 it6505_lane_power_on(it6505);
2382
2383 /*
2384 * for some dongle which issue HPD_irq
2385 * when sink count change from 0->1
2386 * it6505 not able to receive HPD_IRQ
2387 * if HW never go into trainig done
2388 */
2389
2390 if (it6505->branch_device && it6505->sink_count == 0)
2391 schedule_work(&it6505->link_works);
2392
2393 if (!it6505_get_video_status(it6505))
2394 it6505_video_reset(it6505);
2395 } else {
2396 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2397 it6505_remove_edid(it6505);
2398
2399 if (it6505->hdcp_desired)
2400 it6505_stop_hdcp(it6505);
2401
2402 it6505_video_disable(it6505);
2403 it6505_disable_audio(it6505);
2404 it6505_stop_link_train(it6505);
2405 it6505_lane_off(it6505);
2406 it6505_link_reset_step_train(it6505);
2407 }
2408
2409 if (it6505->bridge.dev)
2410 drm_helper_hpd_irq_event(it6505->bridge.dev);
2411}
2412
2413static void it6505_irq_hpd_irq(struct it6505 *it6505)
2414{
2415 struct device *dev = it6505->dev;
2416
2417 DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2418
2419 if (it6505_process_hpd_irq(it6505) < 0)
2420 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2421}
2422
2423static void it6505_irq_scdt(struct it6505 *it6505)
2424{
2425 struct device *dev = it6505->dev;
2426 bool data;
2427
2428 data = it6505_get_video_status(it6505);
2429 DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2430 data ? "stable" : "unstable");
2431 it6505_calc_video_info(it6505);
2432 it6505_link_reset_step_train(it6505);
2433
2434 if (data)
2435 schedule_work(&it6505->link_works);
2436}
2437
2438static void it6505_irq_hdcp_done(struct it6505 *it6505)
2439{
2440 struct device *dev = it6505->dev;
2441
2442 DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2443 it6505->hdcp_status = HDCP_AUTH_DONE;
2444 it6505_show_hdcp_info(it6505);
2445}
2446
2447static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2448{
2449 struct device *dev = it6505->dev;
2450
2451 DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2452 it6505->hdcp_status = HDCP_AUTH_IDLE;
2453 it6505_show_hdcp_info(it6505);
2454 it6505_start_hdcp(it6505);
2455}
2456
2457static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2458{
2459 struct device *dev = it6505->dev;
2460
2461 DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2462}
2463
2464static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2465{
2466 struct device *dev = it6505->dev;
2467
2468 DRM_DEV_DEBUG_DRIVER(dev, "HDCP repeater R0 event Interrupt");
2469 /* 1B01 HDCP encription should start when R0 is ready*/
2470 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2471 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2472
2473 schedule_work(&it6505->hdcp_wait_ksv_list);
2474}
2475
2476static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2477{
2478 struct device *dev = it6505->dev;
2479
2480 DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2481
2482 if (it6505_audio_input(it6505))
2483 it6505_enable_audio(it6505);
2484}
2485
2486static void it6505_irq_link_train_fail(struct it6505 *it6505)
2487{
2488 struct device *dev = it6505->dev;
2489
2490 DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2491 schedule_work(&it6505->link_works);
2492}
2493
2494static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2495{
2496 return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2497}
2498
2499static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status)
2500{
2501 struct device *dev = it6505->dev;
2502 int reg_0d, reg_int03;
2503
2504 /*
2505 * When video SCDT change with video not stable,
2506 * Or video FIFO error, need video reset
2507 */
2508
2509 if ((!it6505_get_video_status(it6505) &&
2510 (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))) ||
2511 (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW,
2512 (unsigned int *)int_status)) ||
2513 (it6505_test_bit(BIT_INT_VID_FIFO_ERROR,
2514 (unsigned int *)int_status))) {
2515 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2516 flush_work(&it6505->link_works);
2517 it6505_stop_hdcp(it6505);
2518 it6505_video_reset(it6505);
2519
2520 usleep_range(10000, 11000);
2521
2522 /*
2523 * Clear FIFO error IRQ to prevent fifo error -> reset loop
2524 * HW will trigger SCDT change IRQ again when video stable
2525 */
2526
2527 reg_int03 = it6505_read(it6505, INT_STATUS_03);
2528 reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
2529
2530 reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
2531 it6505_write(it6505, INT_STATUS_03, reg_int03);
2532
2533 DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03);
2534 DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d);
2535
2536 return;
2537 }
2538
2539 if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))
2540 it6505_irq_scdt(it6505);
2541}
2542
2543static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2544{
2545 struct it6505 *it6505 = data;
2546 struct device *dev = it6505->dev;
2547 static const struct {
2548 int bit;
2549 void (*handler)(struct it6505 *it6505);
2550 } irq_vec[] = {
2551 { BIT_INT_HPD, it6505_irq_hpd },
2552 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2553 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2554 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2555 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2556 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2557 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2558 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2559 };
2560 int int_status[3], i;
2561
2562 if (it6505->enable_drv_hold || !it6505->powered)
2563 return IRQ_HANDLED;
2564
2565 pm_runtime_get_sync(dev);
2566
2567 int_status[0] = it6505_read(it6505, INT_STATUS_01);
2568 int_status[1] = it6505_read(it6505, INT_STATUS_02);
2569 int_status[2] = it6505_read(it6505, INT_STATUS_03);
2570
2571 it6505_write(it6505, INT_STATUS_01, int_status[0]);
2572 it6505_write(it6505, INT_STATUS_02, int_status[1]);
2573 it6505_write(it6505, INT_STATUS_03, int_status[2]);
2574
2575 DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2576 DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2577 DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2578 it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2579
2580 if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2581 irq_vec[0].handler(it6505);
2582
2583 if (it6505->hpd_state) {
2584 for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2585 if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2586 irq_vec[i].handler(it6505);
2587 }
2588 it6505_irq_video_handler(it6505, (unsigned int *)int_status);
2589 }
2590
2591 pm_runtime_put_sync(dev);
2592
2593 return IRQ_HANDLED;
2594}
2595
2596static int it6505_poweron(struct it6505 *it6505)
2597{
2598 struct device *dev = it6505->dev;
2599 struct it6505_platform_data *pdata = &it6505->pdata;
2600 int err;
2601
2602 DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2603
2604 if (it6505->powered) {
2605 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2606 return 0;
2607 }
2608
2609 if (pdata->pwr18) {
2610 err = regulator_enable(pdata->pwr18);
2611 if (err) {
2612 DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2613 err);
2614 return err;
2615 }
2616 }
2617
2618 if (pdata->ovdd) {
2619 /* time interval between IVDD and OVDD at least be 1ms */
2620 usleep_range(1000, 2000);
2621 err = regulator_enable(pdata->ovdd);
2622 if (err) {
2623 regulator_disable(pdata->pwr18);
2624 return err;
2625 }
2626 }
2627 /* time interval between OVDD and SYSRSTN at least be 10ms */
2628 if (pdata->gpiod_reset) {
2629 usleep_range(10000, 20000);
2630 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2631 usleep_range(1000, 2000);
2632 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2633 usleep_range(25000, 35000);
2634 }
2635
2636 it6505->powered = true;
2637 it6505_reset_logic(it6505);
2638 it6505_int_mask_enable(it6505);
2639 it6505_init(it6505);
2640 it6505_lane_off(it6505);
2641
2642 enable_irq(it6505->irq);
2643
2644 return 0;
2645}
2646
2647static int it6505_poweroff(struct it6505 *it6505)
2648{
2649 struct device *dev = it6505->dev;
2650 struct it6505_platform_data *pdata = &it6505->pdata;
2651 int err;
2652
2653 DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2654
2655 if (!it6505->powered) {
2656 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2657 return 0;
2658 }
2659
2660 disable_irq_nosync(it6505->irq);
2661
2662 if (pdata->gpiod_reset)
2663 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2664
2665 if (pdata->pwr18) {
2666 err = regulator_disable(pdata->pwr18);
2667 if (err)
2668 return err;
2669 }
2670
2671 if (pdata->ovdd) {
2672 err = regulator_disable(pdata->ovdd);
2673 if (err)
2674 return err;
2675 }
2676
2677 it6505->powered = false;
2678 it6505->sink_count = 0;
2679
2680 return 0;
2681}
2682
2683static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2684{
2685 struct device *dev = it6505->dev;
2686 enum drm_connector_status status = connector_status_disconnected;
2687 int dp_sink_count;
2688
2689 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2690 it6505->sink_count, it6505->powered);
2691
2692 mutex_lock(&it6505->mode_lock);
2693
2694 if (!it6505->powered)
2695 goto unlock;
2696
2697 if (it6505->enable_drv_hold) {
2698 status = it6505->hpd_state ? connector_status_connected :
2699 connector_status_disconnected;
2700 goto unlock;
2701 }
2702
2703 if (it6505->hpd_state) {
2704 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2705 DP_SET_POWER_D0);
2706 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2707 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2708 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2709 it6505->sink_count, it6505->branch_device);
2710
2711 if (it6505->branch_device) {
2712 status = (it6505->sink_count != 0) ?
2713 connector_status_connected :
2714 connector_status_disconnected;
2715 } else {
2716 status = connector_status_connected;
2717 }
2718 } else {
2719 it6505->sink_count = 0;
2720 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2721 }
2722
2723unlock:
2724 if (it6505->connector_status != status) {
2725 it6505->connector_status = status;
2726 it6505_plugged_status_to_codec(it6505);
2727 }
2728
2729 mutex_unlock(&it6505->mode_lock);
2730
2731 return status;
2732}
2733
2734static int it6505_extcon_notifier(struct notifier_block *self,
2735 unsigned long event, void *ptr)
2736{
2737 struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2738
2739 schedule_work(&it6505->extcon_wq);
2740 return NOTIFY_DONE;
2741}
2742
2743static void it6505_extcon_work(struct work_struct *work)
2744{
2745 struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2746 struct device *dev = it6505->dev;
2747 int state, ret;
2748
2749 if (it6505->enable_drv_hold)
2750 return;
2751
2752 mutex_lock(&it6505->extcon_lock);
2753
2754 state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2755 DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2756
2757 if (state == it6505->extcon_state || unlikely(state < 0))
2758 goto unlock;
2759 it6505->extcon_state = state;
2760 if (state) {
2761 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2762 msleep(100);
2763 ret = pm_runtime_get_sync(dev);
2764
2765 /*
2766 * On system resume, extcon_work can be triggered before
2767 * pm_runtime_force_resume re-enables runtime power management.
2768 * Handling the error here to make sure the bridge is powered on.
2769 */
2770 if (ret < 0)
2771 it6505_poweron(it6505);
2772
2773 complete_all(&it6505->extcon_completion);
2774 } else {
2775 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2776 pm_runtime_put_sync(dev);
2777 reinit_completion(&it6505->extcon_completion);
2778
2779 drm_helper_hpd_irq_event(it6505->bridge.dev);
2780 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2781 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2782 }
2783
2784unlock:
2785 mutex_unlock(&it6505->extcon_lock);
2786}
2787
2788static int it6505_use_notifier_module(struct it6505 *it6505)
2789{
2790 int ret;
2791 struct device *dev = it6505->dev;
2792
2793 it6505->event_nb.notifier_call = it6505_extcon_notifier;
2794 INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2795 ret = devm_extcon_register_notifier(it6505->dev,
2796 it6505->extcon, EXTCON_DISP_DP,
2797 &it6505->event_nb);
2798 if (ret) {
2799 dev_err(dev, "failed to register notifier for DP");
2800 return ret;
2801 }
2802
2803 schedule_work(&it6505->extcon_wq);
2804
2805 return 0;
2806}
2807
2808static void it6505_remove_notifier_module(struct it6505 *it6505)
2809{
2810 if (it6505->extcon) {
2811 devm_extcon_unregister_notifier(it6505->dev,
2812 it6505->extcon, EXTCON_DISP_DP,
2813 &it6505->event_nb);
2814
2815 flush_work(&it6505->extcon_wq);
2816 }
2817}
2818
2819static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2820{
2821 struct it6505 *it6505 = container_of(work, struct it6505,
2822 delayed_audio.work);
2823
2824 DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2825
2826 if (!it6505->powered)
2827 return;
2828
2829 if (!it6505->enable_drv_hold)
2830 it6505_enable_audio(it6505);
2831}
2832
2833static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2834 struct hdmi_codec_params
2835 *params)
2836{
2837 struct device *dev = it6505->dev;
2838 int i = 0;
2839
2840 DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2841 params->sample_rate, params->sample_width,
2842 params->cea.channels);
2843
2844 if (!it6505->bridge.encoder)
2845 return -ENODEV;
2846
2847 if (params->cea.channels <= 1 || params->cea.channels > 8) {
2848 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2849 it6505->audio.channel_count);
2850 return -EINVAL;
2851 }
2852
2853 it6505->audio.channel_count = params->cea.channels;
2854
2855 while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2856 params->sample_rate !=
2857 audio_sample_rate_map[i].sample_rate_value) {
2858 i++;
2859 }
2860 if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2861 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2862 params->sample_rate);
2863 return -EINVAL;
2864 }
2865 it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2866
2867 switch (params->sample_width) {
2868 case 16:
2869 it6505->audio.word_length = WORD_LENGTH_16BIT;
2870 break;
2871 case 18:
2872 it6505->audio.word_length = WORD_LENGTH_18BIT;
2873 break;
2874 case 20:
2875 it6505->audio.word_length = WORD_LENGTH_20BIT;
2876 break;
2877 case 24:
2878 case 32:
2879 it6505->audio.word_length = WORD_LENGTH_24BIT;
2880 break;
2881 default:
2882 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2883 params->sample_width);
2884 return -EINVAL;
2885 }
2886
2887 return 0;
2888}
2889
2890static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2891{
2892 struct it6505 *it6505 = dev_get_drvdata(dev);
2893
2894 if (it6505->powered)
2895 it6505_disable_audio(it6505);
2896}
2897
2898static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2899 void *data,
2900 hdmi_codec_plugged_cb fn,
2901 struct device *codec_dev)
2902{
2903 struct it6505 *it6505 = data;
2904
2905 it6505->plugged_cb = fn;
2906 it6505->codec_dev = codec_dev;
2907 it6505_plugged_status_to_codec(it6505);
2908
2909 return 0;
2910}
2911
2912static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2913{
2914 return container_of(bridge, struct it6505, bridge);
2915}
2916
2917static int it6505_bridge_attach(struct drm_bridge *bridge,
2918 enum drm_bridge_attach_flags flags)
2919{
2920 struct it6505 *it6505 = bridge_to_it6505(bridge);
2921 struct device *dev = it6505->dev;
2922 int ret;
2923
2924 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2925 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2926 return -EINVAL;
2927 }
2928
2929 /* Register aux channel */
2930 it6505->aux.drm_dev = bridge->dev;
2931
2932 ret = drm_dp_aux_register(&it6505->aux);
2933
2934 if (ret < 0) {
2935 dev_err(dev, "Failed to register aux: %d", ret);
2936 return ret;
2937 }
2938
2939 if (it6505->extcon) {
2940 ret = it6505_use_notifier_module(it6505);
2941 if (ret < 0) {
2942 dev_err(dev, "use notifier module failed");
2943 return ret;
2944 }
2945 }
2946
2947 return 0;
2948}
2949
2950static void it6505_bridge_detach(struct drm_bridge *bridge)
2951{
2952 struct it6505 *it6505 = bridge_to_it6505(bridge);
2953
2954 flush_work(&it6505->link_works);
2955 it6505_remove_notifier_module(it6505);
2956}
2957
2958static enum drm_mode_status
2959it6505_bridge_mode_valid(struct drm_bridge *bridge,
2960 const struct drm_display_info *info,
2961 const struct drm_display_mode *mode)
2962{
2963 struct it6505 *it6505 = bridge_to_it6505(bridge);
2964
2965 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2966 return MODE_NO_INTERLACE;
2967
2968 if (mode->clock > it6505->max_dpi_pixel_clock)
2969 return MODE_CLOCK_HIGH;
2970
2971 it6505->video_info.clock = mode->clock;
2972
2973 return MODE_OK;
2974}
2975
2976static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2977 struct drm_bridge_state *old_state)
2978{
2979 struct it6505 *it6505 = bridge_to_it6505(bridge);
2980 struct device *dev = it6505->dev;
2981 struct drm_atomic_state *state = old_state->base.state;
2982 struct hdmi_avi_infoframe frame;
2983 struct drm_crtc_state *crtc_state;
2984 struct drm_connector_state *conn_state;
2985 struct drm_display_mode *mode;
2986 struct drm_connector *connector;
2987 int ret;
2988
2989 DRM_DEV_DEBUG_DRIVER(dev, "start");
2990
2991 connector = drm_atomic_get_new_connector_for_encoder(state,
2992 bridge->encoder);
2993
2994 if (WARN_ON(!connector))
2995 return;
2996
2997 conn_state = drm_atomic_get_new_connector_state(state, connector);
2998
2999 if (WARN_ON(!conn_state))
3000 return;
3001
3002 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
3003
3004 if (WARN_ON(!crtc_state))
3005 return;
3006
3007 mode = &crtc_state->adjusted_mode;
3008
3009 if (WARN_ON(!mode))
3010 return;
3011
3012 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
3013 connector,
3014 mode);
3015 if (ret)
3016 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
3017
3018 it6505_update_video_parameter(it6505, mode);
3019
3020 ret = it6505_send_video_infoframe(it6505, &frame);
3021
3022 if (ret)
3023 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
3024
3025 it6505_int_mask_enable(it6505);
3026 it6505_video_reset(it6505);
3027
3028 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
3029 DP_SET_POWER_D0);
3030}
3031
3032static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
3033 struct drm_bridge_state *old_state)
3034{
3035 struct it6505 *it6505 = bridge_to_it6505(bridge);
3036 struct device *dev = it6505->dev;
3037
3038 DRM_DEV_DEBUG_DRIVER(dev, "start");
3039
3040 if (it6505->powered) {
3041 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
3042 DP_SET_POWER_D3);
3043 it6505_video_disable(it6505);
3044 }
3045}
3046
3047static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
3048 struct drm_bridge_state *old_state)
3049{
3050 struct it6505 *it6505 = bridge_to_it6505(bridge);
3051 struct device *dev = it6505->dev;
3052
3053 DRM_DEV_DEBUG_DRIVER(dev, "start");
3054
3055 pm_runtime_get_sync(dev);
3056}
3057
3058static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3059 struct drm_bridge_state *old_state)
3060{
3061 struct it6505 *it6505 = bridge_to_it6505(bridge);
3062 struct device *dev = it6505->dev;
3063
3064 DRM_DEV_DEBUG_DRIVER(dev, "start");
3065
3066 pm_runtime_put_sync(dev);
3067}
3068
3069static enum drm_connector_status
3070it6505_bridge_detect(struct drm_bridge *bridge)
3071{
3072 struct it6505 *it6505 = bridge_to_it6505(bridge);
3073
3074 return it6505_detect(it6505);
3075}
3076
3077static const struct drm_edid *it6505_bridge_edid_read(struct drm_bridge *bridge,
3078 struct drm_connector *connector)
3079{
3080 struct it6505 *it6505 = bridge_to_it6505(bridge);
3081 struct device *dev = it6505->dev;
3082
3083 if (!it6505->cached_edid) {
3084 it6505->cached_edid = drm_edid_read_custom(connector,
3085 it6505_get_edid_block,
3086 it6505);
3087
3088 if (!it6505->cached_edid) {
3089 DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3090 return NULL;
3091 }
3092 }
3093
3094 return drm_edid_dup(it6505->cached_edid);
3095}
3096
3097static const struct drm_bridge_funcs it6505_bridge_funcs = {
3098 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3099 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3100 .atomic_reset = drm_atomic_helper_bridge_reset,
3101 .attach = it6505_bridge_attach,
3102 .detach = it6505_bridge_detach,
3103 .mode_valid = it6505_bridge_mode_valid,
3104 .atomic_enable = it6505_bridge_atomic_enable,
3105 .atomic_disable = it6505_bridge_atomic_disable,
3106 .atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3107 .atomic_post_disable = it6505_bridge_atomic_post_disable,
3108 .detect = it6505_bridge_detect,
3109 .edid_read = it6505_bridge_edid_read,
3110};
3111
3112static __maybe_unused int it6505_bridge_resume(struct device *dev)
3113{
3114 struct it6505 *it6505 = dev_get_drvdata(dev);
3115
3116 return it6505_poweron(it6505);
3117}
3118
3119static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3120{
3121 struct it6505 *it6505 = dev_get_drvdata(dev);
3122
3123 it6505_remove_edid(it6505);
3124
3125 return it6505_poweroff(it6505);
3126}
3127
3128static const struct dev_pm_ops it6505_bridge_pm_ops = {
3129 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3130 SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3131};
3132
3133static int it6505_init_pdata(struct it6505 *it6505)
3134{
3135 struct it6505_platform_data *pdata = &it6505->pdata;
3136 struct device *dev = it6505->dev;
3137
3138 /* 1.0V digital core power regulator */
3139 pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3140 if (IS_ERR(pdata->pwr18)) {
3141 dev_err(dev, "pwr18 regulator not found");
3142 return PTR_ERR(pdata->pwr18);
3143 }
3144
3145 pdata->ovdd = devm_regulator_get(dev, "ovdd");
3146 if (IS_ERR(pdata->ovdd)) {
3147 dev_err(dev, "ovdd regulator not found");
3148 return PTR_ERR(pdata->ovdd);
3149 }
3150
3151 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
3152 if (IS_ERR(pdata->gpiod_reset)) {
3153 dev_err(dev, "gpiod_reset gpio not found");
3154 return PTR_ERR(pdata->gpiod_reset);
3155 }
3156
3157 return 0;
3158}
3159
3160static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3161 const unsigned int min,
3162 const unsigned int max)
3163{
3164 int ret;
3165
3166 ret = of_property_count_u32_elems(endpoint, "data-lanes");
3167 if (ret < 0)
3168 return ret;
3169
3170 if (ret < min || ret > max)
3171 return -EINVAL;
3172
3173 return ret;
3174}
3175
3176static void it6505_parse_dt(struct it6505 *it6505)
3177{
3178 struct device *dev = it6505->dev;
3179 struct device_node *np = dev->of_node, *ep = NULL;
3180 int len;
3181 u64 link_frequencies;
3182 u32 data_lanes[4];
3183 u32 *afe_setting = &it6505->afe_setting;
3184 u32 *max_lane_count = &it6505->max_lane_count;
3185 u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3186
3187 it6505->lane_swap_disabled =
3188 device_property_read_bool(dev, "no-laneswap");
3189
3190 if (it6505->lane_swap_disabled)
3191 it6505->lane_swap = false;
3192
3193 if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3194 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3195 dev_err(dev, "afe setting error, use default");
3196 *afe_setting = 0;
3197 }
3198 } else {
3199 *afe_setting = 0;
3200 }
3201
3202 ep = of_graph_get_endpoint_by_regs(np, 1, 0);
3203 of_node_put(ep);
3204
3205 if (ep) {
3206 len = it6505_get_data_lanes_count(ep, 1, 4);
3207
3208 if (len > 0 && len != 3) {
3209 of_property_read_u32_array(ep, "data-lanes",
3210 data_lanes, len);
3211 *max_lane_count = len;
3212 } else {
3213 *max_lane_count = MAX_LANE_COUNT;
3214 dev_err(dev, "error data-lanes, use default");
3215 }
3216 } else {
3217 *max_lane_count = MAX_LANE_COUNT;
3218 dev_err(dev, "error endpoint, use default");
3219 }
3220
3221 ep = of_graph_get_endpoint_by_regs(np, 0, 0);
3222 of_node_put(ep);
3223
3224 if (ep) {
3225 len = of_property_read_variable_u64_array(ep,
3226 "link-frequencies",
3227 &link_frequencies, 0,
3228 1);
3229 if (len >= 0) {
3230 do_div(link_frequencies, 1000);
3231 if (link_frequencies > 297000) {
3232 dev_err(dev,
3233 "max pixel clock error, use default");
3234 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3235 } else {
3236 *max_dpi_pixel_clock = link_frequencies;
3237 }
3238 } else {
3239 dev_err(dev, "error link frequencies, use default");
3240 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3241 }
3242 } else {
3243 dev_err(dev, "error endpoint, use default");
3244 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3245 }
3246
3247 DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3248 it6505->afe_setting, it6505->max_lane_count);
3249 DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3250 it6505->max_dpi_pixel_clock);
3251}
3252
3253static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3254 size_t len, loff_t *ppos)
3255{
3256 struct it6505 *it6505 = file->private_data;
3257 struct drm_display_mode *vid;
3258 u8 read_buf[READ_BUFFER_SIZE];
3259 u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3260 ssize_t ret, count;
3261
3262 if (!it6505)
3263 return -ENODEV;
3264
3265 it6505_calc_video_info(it6505);
3266 vid = &it6505->video_info;
3267 str += scnprintf(str, end - str, "---video timing---\n");
3268 str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3269 vid->clock / 1000, vid->clock % 1000);
3270 str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3271 str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3272 str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3273 vid->hsync_start - vid->hdisplay);
3274 str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3275 vid->hsync_end - vid->hsync_start);
3276 str += scnprintf(str, end - str, "HBackPorch:%d\n",
3277 vid->htotal - vid->hsync_end);
3278 str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3279 str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3280 str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3281 vid->vsync_start - vid->vdisplay);
3282 str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3283 vid->vsync_end - vid->vsync_start);
3284 str += scnprintf(str, end - str, "VBackPorch:%d\n",
3285 vid->vtotal - vid->vsync_end);
3286
3287 count = str - read_buf;
3288 ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3289
3290 return ret;
3291}
3292
3293static int force_power_on_off_debugfs_write(void *data, u64 value)
3294{
3295 struct it6505 *it6505 = data;
3296
3297 if (!it6505)
3298 return -ENODEV;
3299
3300 if (value)
3301 it6505_poweron(it6505);
3302 else
3303 it6505_poweroff(it6505);
3304
3305 return 0;
3306}
3307
3308static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3309{
3310 struct it6505 *it6505 = data;
3311
3312 if (!it6505)
3313 return -ENODEV;
3314
3315 *buf = it6505->enable_drv_hold;
3316
3317 return 0;
3318}
3319
3320static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3321{
3322 struct it6505 *it6505 = data;
3323
3324 if (!it6505)
3325 return -ENODEV;
3326
3327 it6505->enable_drv_hold = drv_hold;
3328
3329 if (it6505->enable_drv_hold) {
3330 it6505_int_mask_disable(it6505);
3331 } else {
3332 it6505_clear_int(it6505);
3333 it6505_int_mask_enable(it6505);
3334
3335 if (it6505->powered) {
3336 it6505->connector_status =
3337 it6505_get_sink_hpd_status(it6505) ?
3338 connector_status_connected :
3339 connector_status_disconnected;
3340 } else {
3341 it6505->connector_status =
3342 connector_status_disconnected;
3343 }
3344 }
3345
3346 return 0;
3347}
3348
3349static const struct file_operations receive_timing_fops = {
3350 .owner = THIS_MODULE,
3351 .open = simple_open,
3352 .read = receive_timing_debugfs_show,
3353 .llseek = default_llseek,
3354};
3355
3356DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3357 force_power_on_off_debugfs_write, "%llu\n");
3358
3359DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3360 enable_drv_hold_debugfs_write, "%llu\n");
3361
3362static const struct debugfs_entries debugfs_entry[] = {
3363 { "receive_timing", &receive_timing_fops },
3364 { "force_power_on_off", &fops_force_power },
3365 { "enable_drv_hold", &fops_enable_drv_hold },
3366 { NULL, NULL },
3367};
3368
3369static void debugfs_create_files(struct it6505 *it6505)
3370{
3371 int i = 0;
3372
3373 while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3374 debugfs_create_file(debugfs_entry[i].name, 0644,
3375 it6505->debugfs, it6505,
3376 debugfs_entry[i].fops);
3377 i++;
3378 }
3379}
3380
3381static void debugfs_init(struct it6505 *it6505)
3382{
3383 struct device *dev = it6505->dev;
3384
3385 it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3386
3387 if (IS_ERR(it6505->debugfs)) {
3388 dev_err(dev, "failed to create debugfs root");
3389 return;
3390 }
3391
3392 debugfs_create_files(it6505);
3393}
3394
3395static void it6505_debugfs_remove(struct it6505 *it6505)
3396{
3397 debugfs_remove_recursive(it6505->debugfs);
3398}
3399
3400static void it6505_shutdown(struct i2c_client *client)
3401{
3402 struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3403
3404 if (it6505->powered)
3405 it6505_lane_off(it6505);
3406}
3407
3408static int it6505_i2c_probe(struct i2c_client *client)
3409{
3410 struct it6505 *it6505;
3411 struct device *dev = &client->dev;
3412 struct extcon_dev *extcon;
3413 int err;
3414
3415 it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3416 if (!it6505)
3417 return -ENOMEM;
3418
3419 mutex_init(&it6505->extcon_lock);
3420 mutex_init(&it6505->mode_lock);
3421 mutex_init(&it6505->aux_lock);
3422
3423 it6505->bridge.of_node = client->dev.of_node;
3424 it6505->connector_status = connector_status_disconnected;
3425 it6505->dev = &client->dev;
3426 i2c_set_clientdata(client, it6505);
3427
3428 /* get extcon device from DTS */
3429 extcon = extcon_get_edev_by_phandle(dev, 0);
3430 if (PTR_ERR(extcon) == -EPROBE_DEFER)
3431 return -EPROBE_DEFER;
3432 if (IS_ERR(extcon)) {
3433 dev_err(dev, "can not get extcon device!");
3434 return PTR_ERR(extcon);
3435 }
3436
3437 it6505->extcon = extcon;
3438
3439 it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3440 if (IS_ERR(it6505->regmap)) {
3441 dev_err(dev, "regmap i2c init failed");
3442 err = PTR_ERR(it6505->regmap);
3443 return err;
3444 }
3445
3446 err = it6505_init_pdata(it6505);
3447 if (err) {
3448 dev_err(dev, "Failed to initialize pdata: %d", err);
3449 return err;
3450 }
3451
3452 it6505_parse_dt(it6505);
3453
3454 it6505->irq = client->irq;
3455
3456 if (!it6505->irq) {
3457 dev_err(dev, "Failed to get INTP IRQ");
3458 err = -ENODEV;
3459 return err;
3460 }
3461
3462 err = devm_request_threaded_irq(&client->dev, it6505->irq, NULL,
3463 it6505_int_threaded_handler,
3464 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
3465 IRQF_NO_AUTOEN,
3466 "it6505-intp", it6505);
3467 if (err) {
3468 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3469 return err;
3470 }
3471
3472 INIT_WORK(&it6505->link_works, it6505_link_training_work);
3473 INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3474 INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3475 init_completion(&it6505->extcon_completion);
3476 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3477 it6505->powered = false;
3478 it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3479
3480 if (DEFAULT_PWR_ON)
3481 it6505_poweron(it6505);
3482
3483 DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3484 debugfs_init(it6505);
3485 pm_runtime_enable(dev);
3486
3487 it6505->aux.name = "DP-AUX";
3488 it6505->aux.dev = dev;
3489 it6505->aux.transfer = it6505_aux_transfer;
3490 drm_dp_aux_init(&it6505->aux);
3491
3492 it6505->bridge.funcs = &it6505_bridge_funcs;
3493 it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3494 it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3495 DRM_BRIDGE_OP_HPD;
3496 drm_bridge_add(&it6505->bridge);
3497
3498 return 0;
3499}
3500
3501static void it6505_i2c_remove(struct i2c_client *client)
3502{
3503 struct it6505 *it6505 = i2c_get_clientdata(client);
3504
3505 drm_bridge_remove(&it6505->bridge);
3506 drm_dp_aux_unregister(&it6505->aux);
3507 it6505_debugfs_remove(it6505);
3508 it6505_poweroff(it6505);
3509 it6505_remove_edid(it6505);
3510}
3511
3512static const struct i2c_device_id it6505_id[] = {
3513 { "it6505", 0 },
3514 { }
3515};
3516
3517MODULE_DEVICE_TABLE(i2c, it6505_id);
3518
3519static const struct of_device_id it6505_of_match[] = {
3520 { .compatible = "ite,it6505" },
3521 { }
3522};
3523MODULE_DEVICE_TABLE(of, it6505_of_match);
3524
3525static struct i2c_driver it6505_i2c_driver = {
3526 .driver = {
3527 .name = "it6505",
3528 .of_match_table = it6505_of_match,
3529 .pm = &it6505_bridge_pm_ops,
3530 },
3531 .probe = it6505_i2c_probe,
3532 .remove = it6505_i2c_remove,
3533 .shutdown = it6505_shutdown,
3534 .id_table = it6505_id,
3535};
3536
3537module_i2c_driver(it6505_i2c_driver);
3538
3539MODULE_AUTHOR("Allen Chen <allen.chen@ite.com.tw>");
3540MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3541MODULE_LICENSE("GPL v2");