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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2024 NXP
4 */
5
6#include <linux/bitfield.h>
7#include <linux/bits.h>
8#include <linux/delay.h>
9#include <linux/gpio/consumer.h>
10#include <linux/hdmi.h>
11#include <linux/i2c.h>
12#include <linux/media-bus-format.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/regmap.h>
16#include <linux/regulator/consumer.h>
17
18#include <drm/display/drm_hdmi_helper.h>
19#include <drm/display/drm_hdmi_state_helper.h>
20#include <drm/drm_atomic.h>
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_atomic_state_helper.h>
23#include <drm/drm_bridge.h>
24#include <drm/drm_bridge_connector.h>
25#include <drm/drm_connector.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_of.h>
29#include <drm/drm_probe_helper.h>
30
31/* -----------------------------------------------------------------------------
32 * LVDS registers
33 */
34
35/* LVDS software reset registers */
36#define LVDS_REG_05 0x05
37#define REG_SOFT_P_RST BIT(1)
38
39/* LVDS system configuration registers */
40/* 0x0b */
41#define LVDS_REG_0B 0x0b
42#define REG_SSC_PCLK_RF BIT(0)
43#define REG_LVDS_IN_SWAP BIT(1)
44
45/* LVDS test pattern gen control registers */
46/* 0x2c */
47#define LVDS_REG_2C 0x2c
48#define REG_COL_DEP GENMASK(1, 0)
49#define BIT8 FIELD_PREP(REG_COL_DEP, 1)
50#define OUT_MAP BIT(4)
51#define JEIDA 0
52#define REG_DESSC_ENB BIT(6)
53#define DMODE BIT(7)
54#define DISO BIT(7)
55#define SISO 0
56
57#define LVDS_REG_3C 0x3c
58#define LVDS_REG_3F 0x3f
59#define LVDS_REG_47 0x47
60#define LVDS_REG_48 0x48
61#define LVDS_REG_4F 0x4f
62#define LVDS_REG_52 0x52
63
64/* -----------------------------------------------------------------------------
65 * HDMI registers are separated into three banks:
66 * 1) HDMI register common bank: 0x00 ~ 0x2f
67 */
68
69/* HDMI genernal registers */
70#define HDMI_REG_SW_RST 0x04
71#define SOFTREF_RST BIT(5)
72#define SOFTA_RST BIT(4)
73#define SOFTV_RST BIT(3)
74#define AUD_RST BIT(2)
75#define HDCP_RST BIT(0)
76#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
77 AUD_RST | HDCP_RST)
78
79#define HDMI_REG_SYS_STATUS 0x0e
80#define HPDETECT BIT(6)
81#define TXVIDSTABLE BIT(4)
82
83#define HDMI_REG_BANK_CTRL 0x0f
84#define REG_BANK_SEL BIT(0)
85
86/* HDMI System DDC control registers */
87#define HDMI_REG_DDC_MASTER_CTRL 0x10
88#define MASTER_SEL_HOST BIT(0)
89
90#define HDMI_REG_DDC_HEADER 0x11
91
92#define HDMI_REG_DDC_REQOFF 0x12
93#define HDMI_REG_DDC_REQCOUNT 0x13
94#define HDMI_REG_DDC_EDIDSEG 0x14
95
96#define HDMI_REG_DDC_CMD 0x15
97#define DDC_CMD_EDID_READ 0x3
98#define DDC_CMD_FIFO_CLR 0x9
99
100#define HDMI_REG_DDC_STATUS 0x16
101#define DDC_DONE BIT(7)
102#define DDC_NOACK BIT(5)
103#define DDC_WAITBUS BIT(4)
104#define DDC_ARBILOSE BIT(3)
105#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
106
107#define HDMI_DDC_FIFO_BYTES 32
108#define HDMI_REG_DDC_READFIFO 0x17
109#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
110#define HDMI_REG_LVDS_PORT_EN 0x1e
111#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
112
113/* -----------------------------------------------------------------------------
114 * 2) HDMI register bank0: 0x30 ~ 0xff
115 */
116
117/* HDMI AFE registers */
118#define HDMI_REG_AFE_DRV_CTRL 0x61
119#define AFE_DRV_PWD BIT(5)
120#define AFE_DRV_RST BIT(4)
121
122#define HDMI_REG_AFE_XP_CTRL 0x62
123#define AFE_XP_GAINBIT BIT(7)
124#define AFE_XP_ER0 BIT(4)
125#define AFE_XP_RESETB BIT(3)
126
127#define HDMI_REG_AFE_ISW_CTRL 0x63
128
129#define HDMI_REG_AFE_IP_CTRL 0x64
130#define AFE_IP_GAINBIT BIT(7)
131#define AFE_IP_ER0 BIT(3)
132#define AFE_IP_RESETB BIT(2)
133
134/* HDMI input data format registers */
135#define HDMI_REG_INPUT_MODE 0x70
136#define IN_RGB 0x00
137
138/* HDMI general control registers */
139#define HDMI_REG_HDMI_MODE 0xc0
140#define TX_HDMI_MODE BIT(0)
141
142#define HDMI_REG_GCP 0xc1
143#define AVMUTE BIT(0)
144#define HDMI_COLOR_DEPTH GENMASK(6, 4)
145#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
146
147#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
148#define HDMI_REG_AVI_INFOFRM_CTRL 0xcd
149#define ENABLE_PKT BIT(0)
150#define REPEAT_PKT BIT(1)
151
152/* -----------------------------------------------------------------------------
153 * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
154 */
155
156/* AVI packet registers */
157#define HDMI_REG_AVI_DB1 0x158
158#define HDMI_REG_AVI_DB2 0x159
159#define HDMI_REG_AVI_DB3 0x15a
160#define HDMI_REG_AVI_DB4 0x15b
161#define HDMI_REG_AVI_DB5 0x15c
162#define HDMI_REG_AVI_CSUM 0x15d
163#define HDMI_REG_AVI_DB6 0x15e
164#define HDMI_REG_AVI_DB7 0x15f
165#define HDMI_REG_AVI_DB8 0x160
166#define HDMI_REG_AVI_DB9 0x161
167#define HDMI_REG_AVI_DB10 0x162
168#define HDMI_REG_AVI_DB11 0x163
169#define HDMI_REG_AVI_DB12 0x164
170#define HDMI_REG_AVI_DB13 0x165
171
172#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
173#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
174
175/* IT6263 data sheet Rev0.8: LVDS RX supports input clock rate up to 150MHz. */
176#define MAX_PIXEL_CLOCK_KHZ 150000
177
178/* IT6263 programming guide Ver0.90: PCLK_HIGH for TMDS clock over 80MHz. */
179#define HIGH_PIXEL_CLOCK_KHZ 80000
180
181/*
182 * IT6263 data sheet Rev0.8: HDMI TX supports link speeds of up to 2.25Gbps
183 * (link clock rate of 225MHz).
184 */
185#define MAX_HDMI_TMDS_CHAR_RATE_HZ 225000000
186
187struct it6263 {
188 struct device *dev;
189 struct i2c_client *hdmi_i2c;
190 struct i2c_client *lvds_i2c;
191 struct regmap *hdmi_regmap;
192 struct regmap *lvds_regmap;
193 struct drm_bridge bridge;
194 struct drm_bridge *next_bridge;
195 int lvds_data_mapping;
196 bool lvds_dual_link;
197 bool lvds_link12_swap;
198};
199
200static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
201{
202 return container_of(bridge, struct it6263, bridge);
203}
204
205static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
206{
207 switch (reg) {
208 case HDMI_REG_SW_RST:
209 case HDMI_REG_BANK_CTRL:
210 case HDMI_REG_DDC_MASTER_CTRL:
211 case HDMI_REG_DDC_HEADER:
212 case HDMI_REG_DDC_REQOFF:
213 case HDMI_REG_DDC_REQCOUNT:
214 case HDMI_REG_DDC_EDIDSEG:
215 case HDMI_REG_DDC_CMD:
216 case HDMI_REG_LVDS_PORT:
217 case HDMI_REG_LVDS_PORT_EN:
218 case HDMI_REG_AFE_DRV_CTRL:
219 case HDMI_REG_AFE_XP_CTRL:
220 case HDMI_REG_AFE_ISW_CTRL:
221 case HDMI_REG_AFE_IP_CTRL:
222 case HDMI_REG_INPUT_MODE:
223 case HDMI_REG_HDMI_MODE:
224 case HDMI_REG_GCP:
225 case HDMI_REG_PKT_GENERAL_CTRL:
226 case HDMI_REG_AVI_INFOFRM_CTRL:
227 case HDMI_REG_AVI_DB1:
228 case HDMI_REG_AVI_DB2:
229 case HDMI_REG_AVI_DB3:
230 case HDMI_REG_AVI_DB4:
231 case HDMI_REG_AVI_DB5:
232 case HDMI_REG_AVI_CSUM:
233 case HDMI_REG_AVI_DB6:
234 case HDMI_REG_AVI_DB7:
235 case HDMI_REG_AVI_DB8:
236 case HDMI_REG_AVI_DB9:
237 case HDMI_REG_AVI_DB10:
238 case HDMI_REG_AVI_DB11:
239 case HDMI_REG_AVI_DB12:
240 case HDMI_REG_AVI_DB13:
241 return true;
242 default:
243 return false;
244 }
245}
246
247static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
248{
249 if (it6263_hdmi_writeable_reg(dev, reg))
250 return true;
251
252 switch (reg) {
253 case HDMI_REG_SYS_STATUS:
254 case HDMI_REG_DDC_STATUS:
255 case HDMI_REG_DDC_READFIFO:
256 return true;
257 default:
258 return false;
259 }
260}
261
262static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
263{
264 switch (reg) {
265 case HDMI_REG_SW_RST:
266 case HDMI_REG_SYS_STATUS:
267 case HDMI_REG_DDC_STATUS:
268 case HDMI_REG_DDC_READFIFO:
269 return true;
270 default:
271 return false;
272 }
273}
274
275static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
276 .range_min = 0x00,
277 .range_max = HDMI_REG_AVI_DB13,
278 .selector_reg = HDMI_REG_BANK_CTRL,
279 .selector_mask = REG_BANK_SEL,
280 .selector_shift = 0,
281 .window_start = 0x00,
282 .window_len = 0x100,
283};
284
285static const struct regmap_config it6263_hdmi_regmap_config = {
286 .name = "it6263-hdmi",
287 .reg_bits = 8,
288 .val_bits = 8,
289 .writeable_reg = it6263_hdmi_writeable_reg,
290 .readable_reg = it6263_hdmi_readable_reg,
291 .volatile_reg = it6263_hdmi_volatile_reg,
292 .max_register = HDMI_REG_AVI_DB13,
293 .ranges = &it6263_hdmi_range_cfg,
294 .num_ranges = 1,
295 .cache_type = REGCACHE_MAPLE,
296};
297
298static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
299{
300 switch (reg) {
301 case LVDS_REG_05:
302 case LVDS_REG_0B:
303 case LVDS_REG_2C:
304 case LVDS_REG_3C:
305 case LVDS_REG_3F:
306 case LVDS_REG_47:
307 case LVDS_REG_48:
308 case LVDS_REG_4F:
309 case LVDS_REG_52:
310 return true;
311 default:
312 return false;
313 }
314}
315
316static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
317{
318 return it6263_lvds_writeable_reg(dev, reg);
319}
320
321static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
322{
323 return reg == LVDS_REG_05;
324}
325
326static const struct regmap_config it6263_lvds_regmap_config = {
327 .name = "it6263-lvds",
328 .reg_bits = 8,
329 .val_bits = 8,
330 .writeable_reg = it6263_lvds_writeable_reg,
331 .readable_reg = it6263_lvds_readable_reg,
332 .volatile_reg = it6263_lvds_volatile_reg,
333 .max_register = LVDS_REG_52,
334 .cache_type = REGCACHE_MAPLE,
335};
336
337static const char * const it6263_supplies[] = {
338 "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
339 "avcc", "anvdd", "apvdd"
340};
341
342static int it6263_parse_dt(struct it6263 *it)
343{
344 struct device *dev = it->dev;
345 struct device_node *port0, *port1;
346 int ret = 0;
347
348 it->lvds_data_mapping = drm_of_lvds_get_data_mapping(dev->of_node);
349 if (it->lvds_data_mapping < 0) {
350 dev_err(dev, "%pOF: invalid or missing %s DT property: %d\n",
351 dev->of_node, "data-mapping", it->lvds_data_mapping);
352 return it->lvds_data_mapping;
353 }
354
355 it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
356 if (IS_ERR(it->next_bridge))
357 return dev_err_probe(dev, PTR_ERR(it->next_bridge),
358 "failed to get next bridge\n");
359
360 port0 = of_graph_get_port_by_id(dev->of_node, 0);
361 port1 = of_graph_get_port_by_id(dev->of_node, 1);
362 if (port0 && port1) {
363 int order;
364
365 it->lvds_dual_link = true;
366 order = drm_of_lvds_get_dual_link_pixel_order_sink(port0, port1);
367 if (order < 0) {
368 dev_err(dev,
369 "failed to get dual link pixel order: %d\n",
370 order);
371 ret = order;
372 } else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
373 it->lvds_link12_swap = true;
374 }
375 } else if (port1) {
376 ret = -EINVAL;
377 dev_err(dev, "single input LVDS port1 is not supported\n");
378 } else if (!port0) {
379 ret = -EINVAL;
380 dev_err(dev, "no input LVDS port\n");
381 }
382
383 of_node_put(port0);
384 of_node_put(port1);
385
386 return ret;
387}
388
389static inline void it6263_hw_reset(struct gpio_desc *reset_gpio)
390{
391 if (!reset_gpio)
392 return;
393
394 gpiod_set_value_cansleep(reset_gpio, 0);
395 fsleep(1000);
396 gpiod_set_value_cansleep(reset_gpio, 1);
397 /* The chip maker says the low pulse should be at least 40ms. */
398 fsleep(40000);
399 gpiod_set_value_cansleep(reset_gpio, 0);
400 /* addtional time to wait the high voltage to be stable */
401 fsleep(5000);
402}
403
404static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
405{
406 int ret;
407
408 ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
409 LVDS_INPUT_CTRL_I2C_ADDR << 1);
410 if (ret)
411 return ret;
412
413 return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
414}
415
416static inline void it6263_lvds_reset(struct it6263 *it)
417{
418 /* AFE PLL reset */
419 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
420 fsleep(1000);
421 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
422
423 /* software pixel clock domain reset */
424 regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
425 REG_SOFT_P_RST);
426 fsleep(1000);
427 regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
428 fsleep(10000);
429}
430
431static inline void it6263_lvds_set_interface(struct it6263 *it)
432{
433 /* color depth */
434 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
435 /* output mapping */
436 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
437
438 if (it->lvds_dual_link) {
439 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
440 regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
441 } else {
442 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
443 regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
444 }
445}
446
447static inline void it6263_lvds_set_afe(struct it6263 *it)
448{
449 regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
450 regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
451 regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
452 regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
453 regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
454
455 regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
456 REG_SSC_PCLK_RF);
457 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
458 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
459 REG_DESSC_ENB);
460}
461
462static inline void it6263_lvds_sys_cfg(struct it6263 *it)
463{
464 regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
465 it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
466}
467
468static inline void it6263_lvds_config(struct it6263 *it)
469{
470 it6263_lvds_reset(it);
471 it6263_lvds_set_interface(it);
472 it6263_lvds_set_afe(it);
473 it6263_lvds_sys_cfg(it);
474}
475
476static inline void it6263_hdmi_config(struct it6263 *it)
477{
478 regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
479 regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
480 regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
481 HDMI_COLOR_DEPTH_24);
482}
483
484static enum drm_connector_status it6263_detect(struct it6263 *it)
485{
486 unsigned int val;
487
488 regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
489 if (val & HPDETECT)
490 return connector_status_connected;
491 else
492 return connector_status_disconnected;
493}
494
495static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
496{
497 struct it6263 *it = data;
498 struct regmap *regmap = it->hdmi_regmap;
499 unsigned int start = (block % 2) * EDID_LENGTH;
500 unsigned int segment = block >> 1;
501 unsigned int count, val;
502 int ret;
503
504 regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
505 regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
506 regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
507
508 while (len) {
509 /* clear DDC FIFO */
510 regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
511
512 ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
513 val, val & DDC_DONE,
514 2000, 10000);
515 if (ret) {
516 dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
517 return ret;
518 }
519
520 count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
521
522 /* fire the read command */
523 regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
524 regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
525 regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
526
527 start += count;
528 len -= count;
529
530 ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
531 val & (DDC_DONE | DDC_ERROR),
532 20000, 250000);
533 if (ret && !(val & DDC_ERROR)) {
534 dev_err(it->dev, "failed to read EDID:%d\n", ret);
535 return ret;
536 }
537
538 if (val & DDC_ERROR) {
539 dev_err(it->dev, "DDC error\n");
540 return -EIO;
541 }
542
543 /* cache to buffer */
544 for (; count > 0; count--) {
545 regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
546 *(buf++) = val;
547 }
548 }
549
550 return 0;
551}
552
553static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
554 struct drm_bridge_state *bridge_state,
555 struct drm_crtc_state *crtc_state,
556 struct drm_connector_state *conn_state)
557{
558 return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
559 conn_state->state);
560}
561
562static void
563it6263_bridge_atomic_disable(struct drm_bridge *bridge,
564 struct drm_bridge_state *old_bridge_state)
565{
566 struct it6263 *it = bridge_to_it6263(bridge);
567
568 regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
569 regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
570 regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
571 AFE_DRV_RST | AFE_DRV_PWD);
572}
573
574static void
575it6263_bridge_atomic_enable(struct drm_bridge *bridge,
576 struct drm_bridge_state *old_bridge_state)
577{
578 struct drm_atomic_state *state = old_bridge_state->base.state;
579 struct it6263 *it = bridge_to_it6263(bridge);
580 const struct drm_crtc_state *crtc_state;
581 struct regmap *regmap = it->hdmi_regmap;
582 const struct drm_display_mode *mode;
583 struct drm_connector *connector;
584 bool is_stable = false;
585 struct drm_crtc *crtc;
586 unsigned int val;
587 bool pclk_high;
588 int i, ret;
589
590 connector = drm_atomic_get_new_connector_for_encoder(state,
591 bridge->encoder);
592 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
593 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
594 mode = &crtc_state->adjusted_mode;
595
596 regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
597
598 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
599
600 /* HDMI AFE setup */
601 pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ;
602 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
603 if (pclk_high)
604 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
605 AFE_XP_GAINBIT | AFE_XP_RESETB);
606 else
607 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
608 AFE_XP_ER0 | AFE_XP_RESETB);
609 regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
610 if (pclk_high)
611 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
612 AFE_IP_GAINBIT | AFE_IP_RESETB);
613 else
614 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
615 AFE_IP_ER0 | AFE_IP_RESETB);
616
617 /* HDMI software video reset */
618 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
619 fsleep(1000);
620 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
621
622 /* reconfigure LVDS and retry several times in case video is instable */
623 for (i = 0; i < 3; i++) {
624 ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
625 val & TXVIDSTABLE,
626 20000, 500000);
627 if (!ret) {
628 is_stable = true;
629 break;
630 }
631
632 it6263_lvds_config(it);
633 }
634
635 if (!is_stable)
636 dev_warn(it->dev, "failed to wait for video stable\n");
637
638 /* HDMI AFE reset release and power up */
639 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
640
641 regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
642
643 regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
644}
645
646static enum drm_mode_status
647it6263_bridge_mode_valid(struct drm_bridge *bridge,
648 const struct drm_display_info *info,
649 const struct drm_display_mode *mode)
650{
651 unsigned long long rate;
652
653 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
654 if (rate == 0)
655 return MODE_NOCLOCK;
656
657 return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
658}
659
660static int it6263_bridge_attach(struct drm_bridge *bridge,
661 enum drm_bridge_attach_flags flags)
662{
663 struct it6263 *it = bridge_to_it6263(bridge);
664 struct drm_connector *connector;
665 int ret;
666
667 ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
668 flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
669 if (ret < 0)
670 return ret;
671
672 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
673 return 0;
674
675 connector = drm_bridge_connector_init(bridge->dev, bridge->encoder);
676 if (IS_ERR(connector)) {
677 ret = PTR_ERR(connector);
678 dev_err(it->dev, "failed to initialize bridge connector: %d\n",
679 ret);
680 return ret;
681 }
682
683 drm_connector_attach_encoder(connector, bridge->encoder);
684
685 return 0;
686}
687
688static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
689{
690 struct it6263 *it = bridge_to_it6263(bridge);
691
692 return it6263_detect(it);
693}
694
695static const struct drm_edid *
696it6263_bridge_edid_read(struct drm_bridge *bridge,
697 struct drm_connector *connector)
698{
699 struct it6263 *it = bridge_to_it6263(bridge);
700
701 return drm_edid_read_custom(connector, it6263_read_edid, it);
702}
703
704static u32 *
705it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
706 struct drm_bridge_state *bridge_state,
707 struct drm_crtc_state *crtc_state,
708 struct drm_connector_state *conn_state,
709 u32 output_fmt,
710 unsigned int *num_input_fmts)
711{
712 struct it6263 *it = bridge_to_it6263(bridge);
713 u32 *input_fmts;
714
715 *num_input_fmts = 0;
716
717 if (it->lvds_data_mapping != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA)
718 return NULL;
719
720 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
721 if (!input_fmts)
722 return NULL;
723
724 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
725 *num_input_fmts = 1;
726
727 return input_fmts;
728}
729
730static enum drm_mode_status
731it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
732 const struct drm_display_mode *mode,
733 unsigned long long tmds_rate)
734{
735 if (mode->clock > MAX_PIXEL_CLOCK_KHZ)
736 return MODE_CLOCK_HIGH;
737
738 if (tmds_rate > MAX_HDMI_TMDS_CHAR_RATE_HZ)
739 return MODE_CLOCK_HIGH;
740
741 return MODE_OK;
742}
743
744static int it6263_hdmi_clear_infoframe(struct drm_bridge *bridge,
745 enum hdmi_infoframe_type type)
746{
747 struct it6263 *it = bridge_to_it6263(bridge);
748
749 if (type == HDMI_INFOFRAME_TYPE_AVI)
750 regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0);
751 else
752 dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
753
754 return 0;
755}
756
757static int it6263_hdmi_write_infoframe(struct drm_bridge *bridge,
758 enum hdmi_infoframe_type type,
759 const u8 *buffer, size_t len)
760{
761 struct it6263 *it = bridge_to_it6263(bridge);
762 struct regmap *regmap = it->hdmi_regmap;
763
764 if (type != HDMI_INFOFRAME_TYPE_AVI) {
765 dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
766 return 0;
767 }
768
769 /* write the first AVI infoframe data byte chunk(DB1-DB5) */
770 regmap_bulk_write(regmap, HDMI_REG_AVI_DB1,
771 &buffer[HDMI_INFOFRAME_HEADER_SIZE],
772 HDMI_AVI_DB_CHUNK1_SIZE);
773
774 /* write the second AVI infoframe data byte chunk(DB6-DB13) */
775 regmap_bulk_write(regmap, HDMI_REG_AVI_DB6,
776 &buffer[HDMI_INFOFRAME_HEADER_SIZE +
777 HDMI_AVI_DB_CHUNK1_SIZE],
778 HDMI_AVI_DB_CHUNK2_SIZE);
779
780 /* write checksum */
781 regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]);
782
783 regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL, ENABLE_PKT | REPEAT_PKT);
784
785 return 0;
786}
787
788static const struct drm_bridge_funcs it6263_bridge_funcs = {
789 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
790 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
791 .atomic_reset = drm_atomic_helper_bridge_reset,
792 .attach = it6263_bridge_attach,
793 .mode_valid = it6263_bridge_mode_valid,
794 .atomic_disable = it6263_bridge_atomic_disable,
795 .atomic_enable = it6263_bridge_atomic_enable,
796 .atomic_check = it6263_bridge_atomic_check,
797 .detect = it6263_bridge_detect,
798 .edid_read = it6263_bridge_edid_read,
799 .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
800 .hdmi_tmds_char_rate_valid = it6263_hdmi_tmds_char_rate_valid,
801 .hdmi_clear_infoframe = it6263_hdmi_clear_infoframe,
802 .hdmi_write_infoframe = it6263_hdmi_write_infoframe,
803};
804
805static int it6263_probe(struct i2c_client *client)
806{
807 struct device *dev = &client->dev;
808 struct gpio_desc *reset_gpio;
809 struct it6263 *it;
810 int ret;
811
812 it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
813 if (!it)
814 return -ENOMEM;
815
816 it->dev = dev;
817 it->hdmi_i2c = client;
818
819 it->hdmi_regmap = devm_regmap_init_i2c(client,
820 &it6263_hdmi_regmap_config);
821 if (IS_ERR(it->hdmi_regmap))
822 return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
823 "failed to init I2C regmap for HDMI\n");
824
825 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
826 if (IS_ERR(reset_gpio))
827 return dev_err_probe(dev, PTR_ERR(reset_gpio),
828 "failed to get reset gpio\n");
829
830 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
831 it6263_supplies);
832 if (ret)
833 return dev_err_probe(dev, ret, "failed to get power supplies\n");
834
835 ret = it6263_parse_dt(it);
836 if (ret)
837 return ret;
838
839 it6263_hw_reset(reset_gpio);
840
841 ret = it6263_lvds_set_i2c_addr(it);
842 if (ret)
843 return dev_err_probe(dev, ret, "failed to set I2C addr\n");
844
845 it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
846 LVDS_INPUT_CTRL_I2C_ADDR);
847 if (IS_ERR(it->lvds_i2c))
848 return dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
849 "failed to allocate I2C device for LVDS\n");
850
851 it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
852 &it6263_lvds_regmap_config);
853 if (IS_ERR(it->lvds_regmap))
854 return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
855 "failed to init I2C regmap for LVDS\n");
856
857 it6263_lvds_config(it);
858 it6263_hdmi_config(it);
859
860 i2c_set_clientdata(client, it);
861
862 it->bridge.funcs = &it6263_bridge_funcs;
863 it->bridge.of_node = dev->of_node;
864 /* IT6263 chip doesn't support HPD interrupt. */
865 it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
866 DRM_BRIDGE_OP_HDMI;
867 it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
868 it->bridge.vendor = "ITE";
869 it->bridge.product = "IT6263";
870
871 return devm_drm_bridge_add(dev, &it->bridge);
872}
873
874static const struct of_device_id it6263_of_match[] = {
875 { .compatible = "ite,it6263", },
876 { }
877};
878MODULE_DEVICE_TABLE(of, it6263_of_match);
879
880static const struct i2c_device_id it6263_i2c_ids[] = {
881 { "it6263", 0 },
882 { }
883};
884MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
885
886static struct i2c_driver it6263_driver = {
887 .probe = it6263_probe,
888 .driver = {
889 .name = "it6263",
890 .of_match_table = it6263_of_match,
891 },
892 .id_table = it6263_i2c_ids,
893};
894module_i2c_driver(it6263_driver);
895
896MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
897MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
898MODULE_LICENSE("GPL");