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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AppliedMicro X-Gene SoC GPIO-Standby Driver
4 *
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
6 * Author: Tin Huynh <tnhuynh@apm.com>.
7 * Y Vo <yvo@apm.com>.
8 * Quan Nguyen <qnguyen@apm.com>.
9 */
10
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21#include <linux/types.h>
22
23#include <linux/gpio/driver.h>
24
25#include "gpiolib-acpi.h"
26
27#define XGENE_DFLT_MAX_NGPIO 22
28#define XGENE_DFLT_MAX_NIRQ 6
29#define XGENE_DFLT_IRQ_START_PIN 8
30#define GPIO_MASK(x) (1U << ((x) % 32))
31
32#define MPA_GPIO_INT_LVL 0x0290
33#define MPA_GPIO_OE_ADDR 0x029c
34#define MPA_GPIO_OUT_ADDR 0x02a0
35#define MPA_GPIO_IN_ADDR 0x02a4
36#define MPA_GPIO_SEL_LO 0x0294
37
38#define GPIO_INT_LEVEL_H 0x000001
39#define GPIO_INT_LEVEL_L 0x000000
40
41/**
42 * struct xgene_gpio_sb - GPIO-Standby private data structure.
43 * @gc: memory-mapped GPIO controllers.
44 * @regs: GPIO register base offset
45 * @irq_domain: GPIO interrupt domain
46 * @irq_start: GPIO pin that start support interrupt
47 * @nirq: Number of GPIO pins that supports interrupt
48 * @parent_irq_base: Start parent HWIRQ
49 */
50struct xgene_gpio_sb {
51 struct gpio_chip gc;
52 void __iomem *regs;
53 struct irq_domain *irq_domain;
54 u16 irq_start;
55 u16 nirq;
56 u16 parent_irq_base;
57};
58
59#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
60#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
61
62static void xgene_gpio_set_bit(struct gpio_chip *gc,
63 void __iomem *reg, u32 gpio, int val)
64{
65 u32 data;
66
67 data = gc->read_reg(reg);
68 if (val)
69 data |= GPIO_MASK(gpio);
70 else
71 data &= ~GPIO_MASK(gpio);
72 gc->write_reg(reg, data);
73}
74
75static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
76{
77 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
78 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
79 int lvl_type = GPIO_INT_LEVEL_H;
80
81 switch (type & IRQ_TYPE_SENSE_MASK) {
82 case IRQ_TYPE_EDGE_RISING:
83 case IRQ_TYPE_LEVEL_HIGH:
84 lvl_type = GPIO_INT_LEVEL_H;
85 break;
86 case IRQ_TYPE_EDGE_FALLING:
87 case IRQ_TYPE_LEVEL_LOW:
88 lvl_type = GPIO_INT_LEVEL_L;
89 break;
90 default:
91 break;
92 }
93
94 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
95 gpio * 2, 1);
96 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
97 d->hwirq, lvl_type);
98
99 /* Propagate IRQ type setting to parent */
100 if (type & IRQ_TYPE_EDGE_BOTH)
101 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
102 else
103 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
104}
105
106static struct irq_chip xgene_gpio_sb_irq_chip = {
107 .name = "sbgpio",
108 .irq_eoi = irq_chip_eoi_parent,
109 .irq_mask = irq_chip_mask_parent,
110 .irq_unmask = irq_chip_unmask_parent,
111 .irq_set_type = xgene_gpio_sb_irq_set_type,
112};
113
114static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
115{
116 struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
117 struct irq_fwspec fwspec;
118
119 if ((gpio < priv->irq_start) ||
120 (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
121 return -ENXIO;
122
123 fwspec.fwnode = gc->parent->fwnode;
124 fwspec.param_count = 2;
125 fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
126 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
127 return irq_create_fwspec_mapping(&fwspec);
128}
129
130static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
131 struct irq_data *irq_data,
132 bool reserve)
133{
134 struct xgene_gpio_sb *priv = d->host_data;
135 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
136 int ret;
137
138 ret = gpiochip_lock_as_irq(&priv->gc, gpio);
139 if (ret) {
140 dev_err(priv->gc.parent,
141 "Unable to configure XGene GPIO standby pin %d as IRQ\n",
142 gpio);
143 return ret;
144 }
145
146 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
147 gpio * 2, 1);
148 return 0;
149}
150
151static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
152 struct irq_data *irq_data)
153{
154 struct xgene_gpio_sb *priv = d->host_data;
155 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
156
157 gpiochip_unlock_as_irq(&priv->gc, gpio);
158 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
159 gpio * 2, 0);
160}
161
162static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
163 struct irq_fwspec *fwspec,
164 unsigned long *hwirq,
165 unsigned int *type)
166{
167 struct xgene_gpio_sb *priv = d->host_data;
168
169 if ((fwspec->param_count != 2) ||
170 (fwspec->param[0] >= priv->nirq))
171 return -EINVAL;
172 *hwirq = fwspec->param[0];
173 *type = fwspec->param[1];
174 return 0;
175}
176
177static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
178 unsigned int virq,
179 unsigned int nr_irqs, void *data)
180{
181 struct irq_fwspec *fwspec = data;
182 struct irq_fwspec parent_fwspec;
183 struct xgene_gpio_sb *priv = domain->host_data;
184 irq_hw_number_t hwirq;
185 unsigned int i;
186
187 hwirq = fwspec->param[0];
188 for (i = 0; i < nr_irqs; i++)
189 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
190 &xgene_gpio_sb_irq_chip, priv);
191
192 parent_fwspec.fwnode = domain->parent->fwnode;
193 if (is_of_node(parent_fwspec.fwnode)) {
194 parent_fwspec.param_count = 3;
195 parent_fwspec.param[0] = 0;/* SPI */
196 /* Skip SGIs and PPIs*/
197 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
198 parent_fwspec.param[2] = fwspec->param[1];
199 } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
200 parent_fwspec.param_count = 2;
201 parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
202 parent_fwspec.param[1] = fwspec->param[1];
203 } else
204 return -EINVAL;
205
206 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
207 &parent_fwspec);
208}
209
210static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
211 .translate = xgene_gpio_sb_domain_translate,
212 .alloc = xgene_gpio_sb_domain_alloc,
213 .free = irq_domain_free_irqs_common,
214 .activate = xgene_gpio_sb_domain_activate,
215 .deactivate = xgene_gpio_sb_domain_deactivate,
216};
217
218static int xgene_gpio_sb_probe(struct platform_device *pdev)
219{
220 struct xgene_gpio_sb *priv;
221 int ret;
222 void __iomem *regs;
223 struct irq_domain *parent_domain = NULL;
224 u32 val32;
225
226 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
227 if (!priv)
228 return -ENOMEM;
229
230 regs = devm_platform_ioremap_resource(pdev, 0);
231 if (IS_ERR(regs))
232 return PTR_ERR(regs);
233
234 priv->regs = regs;
235
236 ret = platform_get_irq(pdev, 0);
237 if (ret > 0) {
238 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
239 parent_domain = irq_get_irq_data(ret)->domain;
240 }
241 if (!parent_domain) {
242 dev_err(&pdev->dev, "unable to obtain parent domain\n");
243 return -ENODEV;
244 }
245
246 ret = bgpio_init(&priv->gc, &pdev->dev, 4,
247 regs + MPA_GPIO_IN_ADDR,
248 regs + MPA_GPIO_OUT_ADDR, NULL,
249 regs + MPA_GPIO_OE_ADDR, NULL, 0);
250 if (ret)
251 return ret;
252
253 priv->gc.to_irq = xgene_gpio_sb_to_irq;
254
255 /* Retrieve start irq pin, use default if property not found */
256 priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
257 if (!device_property_read_u32(&pdev->dev, "apm,irq-start", &val32))
258 priv->irq_start = val32;
259
260 /* Retrieve number irqs, use default if property not found */
261 priv->nirq = XGENE_DFLT_MAX_NIRQ;
262 if (!device_property_read_u32(&pdev->dev, "apm,nr-irqs", &val32))
263 priv->nirq = val32;
264
265 /* Retrieve number gpio, use default if property not found */
266 priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
267 if (!device_property_read_u32(&pdev->dev, "apm,nr-gpios", &val32))
268 priv->gc.ngpio = val32;
269
270 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
271 priv->gc.ngpio, priv->nirq, priv->irq_start);
272
273 platform_set_drvdata(pdev, priv);
274
275 priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
276 0, priv->nirq, pdev->dev.fwnode,
277 &xgene_gpio_sb_domain_ops, priv);
278 if (!priv->irq_domain)
279 return -ENODEV;
280
281 priv->gc.irq.domain = priv->irq_domain;
282
283 ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
284 if (ret) {
285 dev_err(&pdev->dev,
286 "failed to register X-Gene GPIO Standby driver\n");
287 irq_domain_remove(priv->irq_domain);
288 return ret;
289 }
290
291 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
292
293 /* Register interrupt handlers for GPIO signaled ACPI Events */
294 acpi_gpiochip_request_interrupts(&priv->gc);
295
296 return ret;
297}
298
299static void xgene_gpio_sb_remove(struct platform_device *pdev)
300{
301 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
302
303 acpi_gpiochip_free_interrupts(&priv->gc);
304
305 irq_domain_remove(priv->irq_domain);
306}
307
308static const struct of_device_id xgene_gpio_sb_of_match[] = {
309 { .compatible = "apm,xgene-gpio-sb" },
310 {}
311};
312MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
313
314static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
315 { "APMC0D15" },
316 {}
317};
318MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
319
320static struct platform_driver xgene_gpio_sb_driver = {
321 .driver = {
322 .name = "xgene-gpio-sb",
323 .of_match_table = xgene_gpio_sb_of_match,
324 .acpi_match_table = xgene_gpio_sb_acpi_match,
325 },
326 .probe = xgene_gpio_sb_probe,
327 .remove = xgene_gpio_sb_remove,
328};
329module_platform_driver(xgene_gpio_sb_driver);
330
331MODULE_AUTHOR("AppliedMicro");
332MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
333MODULE_LICENSE("GPL");