Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2015 IBM Corp.
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8#include <linux/clk.h>
9#include <linux/gpio/aspeed.h>
10#include <linux/gpio/driver.h>
11#include <linux/hashtable.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/seq_file.h>
19#include <linux/spinlock.h>
20#include <linux/string.h>
21
22#include <asm/div64.h>
23
24/*
25 * These two headers aren't meant to be used by GPIO drivers. We need
26 * them in order to access gpio_chip_hwgpio() which we need to implement
27 * the aspeed specific API which allows the coprocessor to request
28 * access to some GPIOs and to arbitrate between coprocessor and ARM.
29 */
30#include <linux/gpio/consumer.h>
31#include "gpiolib.h"
32
33/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
34#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
35#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
36
37#define GPIO_G7_IRQ_STS_BASE 0x100
38#define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4)
39#define GPIO_G7_CTRL_REG_BASE 0x180
40#define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4)
41#define GPIO_G7_CTRL_OUT_DATA BIT(0)
42#define GPIO_G7_CTRL_DIR BIT(1)
43#define GPIO_G7_CTRL_IRQ_EN BIT(2)
44#define GPIO_G7_CTRL_IRQ_TYPE0 BIT(3)
45#define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4)
46#define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5)
47#define GPIO_G7_CTRL_RST_TOLERANCE BIT(6)
48#define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7)
49#define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8)
50#define GPIO_G7_CTRL_INPUT_MASK BIT(9)
51#define GPIO_G7_CTRL_IRQ_STS BIT(12)
52#define GPIO_G7_CTRL_IN_DATA BIT(13)
53
54struct aspeed_bank_props {
55 unsigned int bank;
56 u32 input;
57 u32 output;
58};
59
60struct aspeed_gpio_config {
61 unsigned int nr_gpios;
62 const struct aspeed_bank_props *props;
63 const struct aspeed_gpio_llops *llops;
64 const int *debounce_timers_array;
65 int debounce_timers_num;
66 bool require_dcache;
67};
68
69/*
70 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
71 * @timer_users: Tracks the number of users for each timer
72 *
73 * The @timer_users has four elements but the first element is unused. This is
74 * to simplify accounting and indexing, as a zero value in @offset_timer
75 * represents disabled debouncing for the GPIO. Any other value for an element
76 * of @offset_timer is used as an index into @timer_users. This behaviour of
77 * the zero value aligns with the behaviour of zero built from the timer
78 * configuration registers (i.e. debouncing is disabled).
79 */
80struct aspeed_gpio {
81 struct gpio_chip chip;
82 struct device *dev;
83 raw_spinlock_t lock;
84 void __iomem *base;
85 int irq;
86 const struct aspeed_gpio_config *config;
87
88 u8 *offset_timer;
89 unsigned int timer_users[4];
90 struct clk *clk;
91
92 u32 *dcache;
93 u8 *cf_copro_bankmap;
94};
95
96struct aspeed_gpio_bank {
97 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
98 * +4: Rd/Wr: Direction (0=in, 1=out)
99 */
100 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
101 uint16_t irq_regs;
102 uint16_t debounce_regs;
103 uint16_t tolerance_regs;
104 uint16_t cmdsrc_regs;
105};
106
107/*
108 * Note: The "value" register returns the input value sampled on the
109 * line even when the GPIO is configured as an output. Since
110 * that input goes through synchronizers, writing, then reading
111 * back may not return the written value right away.
112 *
113 * The "rdata" register returns the content of the write latch
114 * and thus can be used to read back what was last written
115 * reliably.
116 */
117
118static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
119static const int g7_debounce_timers[4] = { 0x00, 0x00, 0x04, 0x08 };
120
121/*
122 * The debounce timers array is used to configure the debounce timer settings.Here’s how it works:
123 * Array Value: Indicates the offset for configuring the debounce timer.
124 * Array Index: Corresponds to the debounce setting register.
125 * The debounce timers array follows this pattern for configuring the debounce setting registers:
126 * Array Index 0: No debounce timer is set;
127 * Array Value is irrelevant (don’t care).
128 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0.
129 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00)
130 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1.
131 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04)
132 * Array Index 3: Debounce setting #2 is set to 1, and debounce setting #1 is set to 1.
133 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8)
134 */
135
136static const struct aspeed_gpio_copro_ops *copro_ops;
137static void *copro_data;
138
139static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
140 {
141 .val_regs = 0x0000,
142 .rdata_reg = 0x00c0,
143 .irq_regs = 0x0008,
144 .debounce_regs = 0x0040,
145 .tolerance_regs = 0x001c,
146 .cmdsrc_regs = 0x0060,
147 },
148 {
149 .val_regs = 0x0020,
150 .rdata_reg = 0x00c4,
151 .irq_regs = 0x0028,
152 .debounce_regs = 0x0048,
153 .tolerance_regs = 0x003c,
154 .cmdsrc_regs = 0x0068,
155 },
156 {
157 .val_regs = 0x0070,
158 .rdata_reg = 0x00c8,
159 .irq_regs = 0x0098,
160 .debounce_regs = 0x00b0,
161 .tolerance_regs = 0x00ac,
162 .cmdsrc_regs = 0x0090,
163 },
164 {
165 .val_regs = 0x0078,
166 .rdata_reg = 0x00cc,
167 .irq_regs = 0x00e8,
168 .debounce_regs = 0x0100,
169 .tolerance_regs = 0x00fc,
170 .cmdsrc_regs = 0x00e0,
171 },
172 {
173 .val_regs = 0x0080,
174 .rdata_reg = 0x00d0,
175 .irq_regs = 0x0118,
176 .debounce_regs = 0x0130,
177 .tolerance_regs = 0x012c,
178 .cmdsrc_regs = 0x0110,
179 },
180 {
181 .val_regs = 0x0088,
182 .rdata_reg = 0x00d4,
183 .irq_regs = 0x0148,
184 .debounce_regs = 0x0160,
185 .tolerance_regs = 0x015c,
186 .cmdsrc_regs = 0x0140,
187 },
188 {
189 .val_regs = 0x01E0,
190 .rdata_reg = 0x00d8,
191 .irq_regs = 0x0178,
192 .debounce_regs = 0x0190,
193 .tolerance_regs = 0x018c,
194 .cmdsrc_regs = 0x0170,
195 },
196 {
197 .val_regs = 0x01e8,
198 .rdata_reg = 0x00dc,
199 .irq_regs = 0x01a8,
200 .debounce_regs = 0x01c0,
201 .tolerance_regs = 0x01bc,
202 .cmdsrc_regs = 0x01a0,
203 },
204};
205
206enum aspeed_gpio_reg {
207 reg_val,
208 reg_rdata,
209 reg_dir,
210 reg_irq_enable,
211 reg_irq_type0,
212 reg_irq_type1,
213 reg_irq_type2,
214 reg_irq_status,
215 reg_debounce_sel1,
216 reg_debounce_sel2,
217 reg_tolerance,
218 reg_cmdsrc0,
219 reg_cmdsrc1,
220};
221
222struct aspeed_gpio_llops {
223 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset,
224 const enum aspeed_gpio_reg reg, bool val);
225 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset,
226 const enum aspeed_gpio_reg reg);
227 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset,
228 const enum aspeed_gpio_reg reg);
229 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner);
230 void (*privilege_init)(struct aspeed_gpio *gpio);
231 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset);
232 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset);
233};
234
235#define GPIO_VAL_VALUE 0x00
236#define GPIO_VAL_DIR 0x04
237
238#define GPIO_IRQ_ENABLE 0x00
239#define GPIO_IRQ_TYPE0 0x04
240#define GPIO_IRQ_TYPE1 0x08
241#define GPIO_IRQ_TYPE2 0x0c
242#define GPIO_IRQ_STATUS 0x10
243
244#define GPIO_DEBOUNCE_SEL1 0x00
245#define GPIO_DEBOUNCE_SEL2 0x04
246
247#define GPIO_CMDSRC_0 0x00
248#define GPIO_CMDSRC_1 0x04
249#define GPIO_CMDSRC_ARM 0
250#define GPIO_CMDSRC_LPC 1
251#define GPIO_CMDSRC_COLDFIRE 2
252#define GPIO_CMDSRC_RESERVED 3
253
254/* This will be resolved at compile time */
255static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio,
256 const struct aspeed_gpio_bank *bank,
257 const enum aspeed_gpio_reg reg)
258{
259 switch (reg) {
260 case reg_val:
261 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
262 case reg_rdata:
263 return gpio->base + bank->rdata_reg;
264 case reg_dir:
265 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
266 case reg_irq_enable:
267 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
268 case reg_irq_type0:
269 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
270 case reg_irq_type1:
271 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
272 case reg_irq_type2:
273 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
274 case reg_irq_status:
275 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
276 case reg_debounce_sel1:
277 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
278 case reg_debounce_sel2:
279 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
280 case reg_tolerance:
281 return gpio->base + bank->tolerance_regs;
282 case reg_cmdsrc0:
283 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
284 case reg_cmdsrc1:
285 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
286 }
287 BUG();
288}
289
290static u32 aspeed_gpio_g7_reg_mask(const enum aspeed_gpio_reg reg)
291{
292 switch (reg) {
293 case reg_val:
294 return GPIO_G7_CTRL_OUT_DATA;
295 case reg_dir:
296 return GPIO_G7_CTRL_DIR;
297 case reg_irq_enable:
298 return GPIO_G7_CTRL_IRQ_EN;
299 case reg_irq_type0:
300 return GPIO_G7_CTRL_IRQ_TYPE0;
301 case reg_irq_type1:
302 return GPIO_G7_CTRL_IRQ_TYPE1;
303 case reg_irq_type2:
304 return GPIO_G7_CTRL_IRQ_TYPE2;
305 case reg_tolerance:
306 return GPIO_G7_CTRL_RST_TOLERANCE;
307 case reg_debounce_sel1:
308 return GPIO_G7_CTRL_DEBOUNCE_SEL1;
309 case reg_debounce_sel2:
310 return GPIO_G7_CTRL_DEBOUNCE_SEL2;
311 case reg_rdata:
312 return GPIO_G7_CTRL_OUT_DATA;
313 case reg_irq_status:
314 return GPIO_G7_CTRL_IRQ_STS;
315 case reg_cmdsrc0:
316 case reg_cmdsrc1:
317 default:
318 WARN_ON_ONCE(1);
319 return 0;
320 }
321}
322
323#define GPIO_BANK(x) ((x) >> 5)
324#define GPIO_OFFSET(x) ((x) & 0x1f)
325#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
326
327static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
328{
329 unsigned int bank = GPIO_BANK(offset);
330
331 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
332 return &aspeed_gpio_banks[bank];
333}
334
335static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
336{
337 return !(props->input || props->output);
338}
339
340static inline const struct aspeed_bank_props *find_bank_props(
341 struct aspeed_gpio *gpio, unsigned int offset)
342{
343 const struct aspeed_bank_props *props = gpio->config->props;
344
345 while (!is_bank_props_sentinel(props)) {
346 if (props->bank == GPIO_BANK(offset))
347 return props;
348 props++;
349 }
350
351 return NULL;
352}
353
354static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
355{
356 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
357
358 if (offset >= gpio->chip.ngpio)
359 return false;
360
361 return (!props || ((props->input | props->output) & GPIO_BIT(offset)));
362}
363
364static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
365{
366 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
367
368 return !props || (props->input & GPIO_BIT(offset));
369}
370
371#define have_irq(g, o) have_input((g), (o))
372#define have_debounce(g, o) have_input((g), (o))
373
374static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
375{
376 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
377
378 return !props || (props->output & GPIO_BIT(offset));
379}
380
381static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc)
382{
383 if (gpio->config->llops->privilege_ctrl)
384 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc);
385}
386
387static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
388 unsigned int offset)
389{
390 if (gpio->config->llops->copro_request)
391 return gpio->config->llops->copro_request(gpio, offset);
392
393 return false;
394}
395
396static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
397 unsigned int offset)
398{
399 if (gpio->config->llops->copro_release)
400 gpio->config->llops->copro_release(gpio, offset);
401}
402
403static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio)
404{
405 return gpio->config->llops->copro_request && gpio->config->llops->copro_release &&
406 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init;
407}
408
409static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
410{
411 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
412
413 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val);
414}
415
416static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
417 int val)
418{
419 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
420
421 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val);
422 /* Flush write */
423 gpio->config->llops->reg_bit_get(gpio, offset, reg_val);
424}
425
426static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
427 int val)
428{
429 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
430 unsigned long flags;
431 bool copro = false;
432
433 raw_spin_lock_irqsave(&gpio->lock, flags);
434 copro = aspeed_gpio_copro_request(gpio, offset);
435
436 __aspeed_gpio_set(gc, offset, val);
437
438 if (copro)
439 aspeed_gpio_copro_release(gpio, offset);
440 raw_spin_unlock_irqrestore(&gpio->lock, flags);
441}
442
443static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
444{
445 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
446 unsigned long flags;
447 bool copro = false;
448
449 if (!have_input(gpio, offset))
450 return -ENOTSUPP;
451
452 raw_spin_lock_irqsave(&gpio->lock, flags);
453
454 copro = aspeed_gpio_copro_request(gpio, offset);
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0);
456 if (copro)
457 aspeed_gpio_copro_release(gpio, offset);
458
459 raw_spin_unlock_irqrestore(&gpio->lock, flags);
460
461 return 0;
462}
463
464static int aspeed_gpio_dir_out(struct gpio_chip *gc,
465 unsigned int offset, int val)
466{
467 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
468 unsigned long flags;
469 bool copro = false;
470
471 if (!have_output(gpio, offset))
472 return -ENOTSUPP;
473
474 raw_spin_lock_irqsave(&gpio->lock, flags);
475
476 copro = aspeed_gpio_copro_request(gpio, offset);
477 __aspeed_gpio_set(gc, offset, val);
478 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1);
479
480 if (copro)
481 aspeed_gpio_copro_release(gpio, offset);
482 raw_spin_unlock_irqrestore(&gpio->lock, flags);
483
484 return 0;
485}
486
487static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
488{
489 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
490 unsigned long flags;
491 u32 val;
492
493 if (!have_input(gpio, offset))
494 return GPIO_LINE_DIRECTION_OUT;
495
496 if (!have_output(gpio, offset))
497 return GPIO_LINE_DIRECTION_IN;
498
499 raw_spin_lock_irqsave(&gpio->lock, flags);
500
501 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir);
502
503 raw_spin_unlock_irqrestore(&gpio->lock, flags);
504
505 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
506}
507
508static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
509 struct aspeed_gpio **gpio,
510 int *offset)
511{
512 struct aspeed_gpio *internal;
513
514 *offset = irqd_to_hwirq(d);
515
516 internal = irq_data_get_irq_chip_data(d);
517
518 /* This might be a bit of a questionable place to check */
519 if (!have_irq(internal, *offset))
520 return -ENOTSUPP;
521
522 *gpio = internal;
523
524 return 0;
525}
526
527static void aspeed_gpio_irq_ack(struct irq_data *d)
528{
529 struct aspeed_gpio *gpio;
530 unsigned long flags;
531 int rc, offset;
532 bool copro = false;
533
534 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
535 if (rc)
536 return;
537
538 raw_spin_lock_irqsave(&gpio->lock, flags);
539 copro = aspeed_gpio_copro_request(gpio, offset);
540
541 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1);
542
543 if (copro)
544 aspeed_gpio_copro_release(gpio, offset);
545 raw_spin_unlock_irqrestore(&gpio->lock, flags);
546}
547
548static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
549{
550 struct aspeed_gpio *gpio;
551 unsigned long flags;
552 int rc, offset;
553 bool copro = false;
554
555 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
556 if (rc)
557 return;
558
559 /* Unmasking the IRQ */
560 if (set)
561 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d));
562
563 raw_spin_lock_irqsave(&gpio->lock, flags);
564 copro = aspeed_gpio_copro_request(gpio, offset);
565
566 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set);
567
568 if (copro)
569 aspeed_gpio_copro_release(gpio, offset);
570 raw_spin_unlock_irqrestore(&gpio->lock, flags);
571
572 /* Masking the IRQ */
573 if (!set)
574 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d));
575}
576
577static void aspeed_gpio_irq_mask(struct irq_data *d)
578{
579 aspeed_gpio_irq_set_mask(d, false);
580}
581
582static void aspeed_gpio_irq_unmask(struct irq_data *d)
583{
584 aspeed_gpio_irq_set_mask(d, true);
585}
586
587static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
588{
589 u32 type0 = 0;
590 u32 type1 = 0;
591 u32 type2 = 0;
592 irq_flow_handler_t handler;
593 struct aspeed_gpio *gpio;
594 unsigned long flags;
595 int rc, offset;
596 bool copro = false;
597
598 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
599 if (rc)
600 return -EINVAL;
601
602 switch (type & IRQ_TYPE_SENSE_MASK) {
603 case IRQ_TYPE_EDGE_BOTH:
604 type2 = 1;
605 fallthrough;
606 case IRQ_TYPE_EDGE_RISING:
607 type0 = 1;
608 fallthrough;
609 case IRQ_TYPE_EDGE_FALLING:
610 handler = handle_edge_irq;
611 break;
612 case IRQ_TYPE_LEVEL_HIGH:
613 type0 = 1;
614 fallthrough;
615 case IRQ_TYPE_LEVEL_LOW:
616 type1 = 1;
617 handler = handle_level_irq;
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 raw_spin_lock_irqsave(&gpio->lock, flags);
624 copro = aspeed_gpio_copro_request(gpio, offset);
625
626 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0);
627 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1);
628 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2);
629
630 if (copro)
631 aspeed_gpio_copro_release(gpio, offset);
632 raw_spin_unlock_irqrestore(&gpio->lock, flags);
633
634 irq_set_handler_locked(d, handler);
635
636 return 0;
637}
638
639static void aspeed_gpio_irq_handler(struct irq_desc *desc)
640{
641 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
642 struct irq_chip *ic = irq_desc_get_chip(desc);
643 unsigned int i, p, banks;
644 unsigned long reg;
645 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
646
647 chained_irq_enter(ic, desc);
648
649 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
650 for (i = 0; i < banks; i++) {
651 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status);
652
653 for_each_set_bit(p, ®, 32)
654 generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
655 }
656
657 chained_irq_exit(ic, desc);
658}
659
660static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
661 unsigned long *valid_mask,
662 unsigned int ngpios)
663{
664 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
665 const struct aspeed_bank_props *props = gpio->config->props;
666
667 while (!is_bank_props_sentinel(props)) {
668 unsigned int offset;
669 const unsigned long int input = props->input;
670
671 /* Pretty crummy approach, but similar to GPIO core */
672 for_each_clear_bit(offset, &input, 32) {
673 unsigned int i = props->bank * 32 + offset;
674
675 if (i >= gpio->chip.ngpio)
676 break;
677
678 clear_bit(i, valid_mask);
679 }
680
681 props++;
682 }
683}
684
685static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
686 unsigned int offset, bool enable)
687{
688 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
689 unsigned long flags;
690 bool copro = false;
691
692 raw_spin_lock_irqsave(&gpio->lock, flags);
693 copro = aspeed_gpio_copro_request(gpio, offset);
694
695 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable);
696
697 if (copro)
698 aspeed_gpio_copro_release(gpio, offset);
699 raw_spin_unlock_irqrestore(&gpio->lock, flags);
700
701 return 0;
702}
703
704static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
705{
706 if (!have_gpio(gpiochip_get_data(chip), offset))
707 return -ENODEV;
708
709 return pinctrl_gpio_request(chip, offset);
710}
711
712static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
713{
714 pinctrl_gpio_free(chip, offset);
715}
716
717static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
718 u32 *cycles)
719{
720 u64 rate;
721 u64 n;
722 u32 r;
723
724 rate = clk_get_rate(gpio->clk);
725 if (!rate)
726 return -ENOTSUPP;
727
728 n = rate * usecs;
729 r = do_div(n, 1000000);
730
731 if (n >= U32_MAX)
732 return -ERANGE;
733
734 /* At least as long as the requested time */
735 *cycles = n + (!!r);
736
737 return 0;
738}
739
740/* Call under gpio->lock */
741static int register_allocated_timer(struct aspeed_gpio *gpio,
742 unsigned int offset, unsigned int timer)
743{
744 if (WARN(gpio->offset_timer[offset] != 0,
745 "Offset %d already allocated timer %d\n",
746 offset, gpio->offset_timer[offset]))
747 return -EINVAL;
748
749 if (WARN(gpio->timer_users[timer] == UINT_MAX,
750 "Timer user count would overflow\n"))
751 return -EPERM;
752
753 gpio->offset_timer[offset] = timer;
754 gpio->timer_users[timer]++;
755
756 return 0;
757}
758
759/* Call under gpio->lock */
760static int unregister_allocated_timer(struct aspeed_gpio *gpio,
761 unsigned int offset)
762{
763 if (WARN(gpio->offset_timer[offset] == 0,
764 "No timer allocated to offset %d\n", offset))
765 return -EINVAL;
766
767 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
768 "No users recorded for timer %d\n",
769 gpio->offset_timer[offset]))
770 return -EINVAL;
771
772 gpio->timer_users[gpio->offset_timer[offset]]--;
773 gpio->offset_timer[offset] = 0;
774
775 return 0;
776}
777
778/* Call under gpio->lock */
779static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
780 unsigned int offset)
781{
782 return gpio->offset_timer[offset] > 0;
783}
784
785/* Call under gpio->lock */
786static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
787 unsigned int timer)
788{
789 /* Note: Debounce timer isn't under control of the command
790 * source registers, so no need to sync with the coprocessor
791 */
792 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1)));
793 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0)));
794}
795
796static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
797 unsigned long usecs)
798{
799 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
800 u32 requested_cycles;
801 unsigned long flags;
802 int rc;
803 int i;
804
805 if (!gpio->clk)
806 return -EINVAL;
807
808 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
809 if (rc < 0) {
810 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
811 usecs, clk_get_rate(gpio->clk), rc);
812 return rc;
813 }
814
815 raw_spin_lock_irqsave(&gpio->lock, flags);
816
817 if (timer_allocation_registered(gpio, offset)) {
818 rc = unregister_allocated_timer(gpio, offset);
819 if (rc < 0)
820 goto out;
821 }
822
823 /* Try to find a timer already configured for the debounce period */
824 for (i = 1; i < gpio->config->debounce_timers_num; i++) {
825 u32 cycles;
826
827 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]);
828 if (requested_cycles == cycles)
829 break;
830 }
831
832 if (i == gpio->config->debounce_timers_num) {
833 int j;
834
835 /*
836 * As there are no timers configured for the requested debounce
837 * period, find an unused timer instead
838 */
839 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
840 if (gpio->timer_users[j] == 0)
841 break;
842 }
843
844 if (j == ARRAY_SIZE(gpio->timer_users)) {
845 dev_warn(chip->parent,
846 "Debounce timers exhausted, cannot debounce for period %luus\n",
847 usecs);
848
849 rc = -EPERM;
850
851 /*
852 * We already adjusted the accounting to remove @offset
853 * as a user of its previous timer, so also configure
854 * the hardware so @offset has timers disabled for
855 * consistency.
856 */
857 configure_timer(gpio, offset, 0);
858 goto out;
859 }
860
861 i = j;
862
863 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]);
864 }
865
866 if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
867 rc = -EINVAL;
868 goto out;
869 }
870
871 register_allocated_timer(gpio, offset, i);
872 configure_timer(gpio, offset, i);
873
874out:
875 raw_spin_unlock_irqrestore(&gpio->lock, flags);
876
877 return rc;
878}
879
880static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
881{
882 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
883 unsigned long flags;
884 int rc;
885
886 raw_spin_lock_irqsave(&gpio->lock, flags);
887
888 rc = unregister_allocated_timer(gpio, offset);
889 if (!rc)
890 configure_timer(gpio, offset, 0);
891
892 raw_spin_unlock_irqrestore(&gpio->lock, flags);
893
894 return rc;
895}
896
897static int set_debounce(struct gpio_chip *chip, unsigned int offset,
898 unsigned long usecs)
899{
900 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
901
902 if (!have_debounce(gpio, offset))
903 return -ENOTSUPP;
904
905 if (usecs)
906 return enable_debounce(chip, offset, usecs);
907
908 return disable_debounce(chip, offset);
909}
910
911static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
912 unsigned long config)
913{
914 unsigned long param = pinconf_to_config_param(config);
915 u32 arg = pinconf_to_config_argument(config);
916
917 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
918 return set_debounce(chip, offset, arg);
919 else if (param == PIN_CONFIG_BIAS_DISABLE ||
920 param == PIN_CONFIG_BIAS_PULL_DOWN ||
921 param == PIN_CONFIG_DRIVE_STRENGTH)
922 return pinctrl_gpio_set_config(chip, offset, config);
923 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
924 param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
925 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
926 return -ENOTSUPP;
927 else if (param == PIN_CONFIG_PERSIST_STATE)
928 return aspeed_gpio_reset_tolerance(chip, offset, arg);
929
930 return -ENOTSUPP;
931}
932
933/**
934 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
935 * the coprocessor for shared GPIO banks
936 * @ops: The callbacks
937 * @data: Pointer passed back to the callbacks
938 */
939int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
940{
941 copro_data = data;
942 copro_ops = ops;
943
944 return 0;
945}
946EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
947
948/**
949 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
950 * bank gets marked and any access from the ARM will
951 * result in handshaking via callbacks.
952 * @desc: The GPIO to be marked
953 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
954 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
955 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
956 */
957int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
958 u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
959{
960 struct gpio_chip *chip = gpiod_to_chip(desc);
961 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
962 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
963 const struct aspeed_gpio_bank *bank = to_bank(offset);
964 unsigned long flags;
965
966 if (!aspeed_gpio_support_copro(gpio))
967 return -EOPNOTSUPP;
968
969 if (!gpio->cf_copro_bankmap)
970 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
971 if (!gpio->cf_copro_bankmap)
972 return -ENOMEM;
973 if (offset < 0 || offset > gpio->chip.ngpio)
974 return -EINVAL;
975 bindex = offset >> 3;
976
977 raw_spin_lock_irqsave(&gpio->lock, flags);
978
979 /* Sanity check, this shouldn't happen */
980 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
981 rc = -EIO;
982 goto bail;
983 }
984 gpio->cf_copro_bankmap[bindex]++;
985
986 /* Switch command source */
987 if (gpio->cf_copro_bankmap[bindex] == 1)
988 aspeed_gpio_change_cmd_source(gpio, offset,
989 GPIO_CMDSRC_COLDFIRE);
990
991 if (vreg_offset)
992 *vreg_offset = bank->val_regs;
993 if (dreg_offset)
994 *dreg_offset = bank->rdata_reg;
995 if (bit)
996 *bit = GPIO_OFFSET(offset);
997 bail:
998 raw_spin_unlock_irqrestore(&gpio->lock, flags);
999 return rc;
1000}
1001EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
1002
1003/**
1004 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1005 * @desc: The GPIO to be marked
1006 */
1007int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
1008{
1009 struct gpio_chip *chip = gpiod_to_chip(desc);
1010 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1011 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1012 unsigned long flags;
1013
1014 if (!aspeed_gpio_support_copro(gpio))
1015 return -EOPNOTSUPP;
1016
1017 if (!gpio->cf_copro_bankmap)
1018 return -ENXIO;
1019
1020 if (offset < 0 || offset > gpio->chip.ngpio)
1021 return -EINVAL;
1022 bindex = offset >> 3;
1023
1024 raw_spin_lock_irqsave(&gpio->lock, flags);
1025
1026 /* Sanity check, this shouldn't happen */
1027 if (gpio->cf_copro_bankmap[bindex] == 0) {
1028 rc = -EIO;
1029 goto bail;
1030 }
1031 gpio->cf_copro_bankmap[bindex]--;
1032
1033 /* Switch command source */
1034 if (gpio->cf_copro_bankmap[bindex] == 0)
1035 aspeed_gpio_change_cmd_source(gpio, offset,
1036 GPIO_CMDSRC_ARM);
1037 bail:
1038 raw_spin_unlock_irqrestore(&gpio->lock, flags);
1039 return rc;
1040}
1041EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
1042
1043static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
1044{
1045 struct aspeed_gpio *gpio;
1046 int rc, offset;
1047
1048 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset);
1049 if (rc)
1050 return;
1051
1052 seq_puts(p, dev_name(gpio->dev));
1053}
1054
1055static const struct irq_chip aspeed_gpio_irq_chip = {
1056 .irq_ack = aspeed_gpio_irq_ack,
1057 .irq_mask = aspeed_gpio_irq_mask,
1058 .irq_unmask = aspeed_gpio_irq_unmask,
1059 .irq_set_type = aspeed_gpio_set_type,
1060 .irq_print_chip = aspeed_gpio_irq_print_chip,
1061 .flags = IRQCHIP_IMMUTABLE,
1062 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1063};
1064
1065static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
1066 const enum aspeed_gpio_reg reg, bool val)
1067{
1068 const struct aspeed_gpio_bank *bank = to_bank(offset);
1069 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1070 u32 temp;
1071
1072 if (reg == reg_val)
1073 temp = gpio->dcache[GPIO_BANK(offset)];
1074 else
1075 temp = ioread32(addr);
1076
1077 if (val)
1078 temp |= GPIO_BIT(offset);
1079 else
1080 temp &= ~GPIO_BIT(offset);
1081
1082 if (reg == reg_val)
1083 gpio->dcache[GPIO_BANK(offset)] = temp;
1084 iowrite32(temp, addr);
1085}
1086
1087static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset,
1088 const enum aspeed_gpio_reg reg)
1089{
1090 const struct aspeed_gpio_bank *bank = to_bank(offset);
1091 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1092
1093 return !!(ioread32(addr) & GPIO_BIT(offset));
1094}
1095
1096static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset,
1097 const enum aspeed_gpio_reg reg)
1098{
1099 const struct aspeed_gpio_bank *bank = to_bank(offset);
1100 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
1101
1102 if (reg == reg_rdata || reg == reg_irq_status)
1103 return ioread32(addr);
1104 else
1105 return -EOPNOTSUPP;
1106}
1107
1108static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc)
1109{
1110 /*
1111 * The command source register is only valid in bits 0, 8, 16, and 24, so we use
1112 * (offset & ~(0x7)) to ensure that reg_bits_set always targets a valid bit.
1113 */
1114 /* Source 1 first to avoid illegal 11 combination */
1115 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1)));
1116 /* Then Source 0 */
1117 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0)));
1118}
1119
1120static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio)
1121{
1122 u32 i;
1123
1124 /* Switch all command sources to the ARM by default */
1125 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) {
1126 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM);
1127 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM);
1128 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM);
1129 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM);
1130 }
1131}
1132
1133static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset)
1134{
1135 if (!copro_ops || !gpio->cf_copro_bankmap)
1136 return false;
1137 if (!gpio->cf_copro_bankmap[offset >> 3])
1138 return false;
1139 if (!copro_ops->request_access)
1140 return false;
1141
1142 /* Pause the coprocessor */
1143 copro_ops->request_access(copro_data);
1144
1145 /* Change command source back to ARM */
1146 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM);
1147
1148 /* Update cache */
1149 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata);
1150
1151 return true;
1152}
1153
1154static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset)
1155{
1156 if (!copro_ops || !gpio->cf_copro_bankmap)
1157 return;
1158 if (!gpio->cf_copro_bankmap[offset >> 3])
1159 return;
1160 if (!copro_ops->release_access)
1161 return;
1162
1163 /* Change command source back to ColdFire */
1164 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE);
1165
1166 /* Restart the coprocessor */
1167 copro_ops->release_access(copro_data);
1168}
1169
1170static const struct aspeed_gpio_llops aspeed_g4_llops = {
1171 .reg_bit_set = aspeed_g4_reg_bit_set,
1172 .reg_bit_get = aspeed_g4_reg_bit_get,
1173 .reg_bank_get = aspeed_g4_reg_bank_get,
1174 .privilege_ctrl = aspeed_g4_privilege_ctrl,
1175 .privilege_init = aspeed_g4_privilege_init,
1176 .copro_request = aspeed_g4_copro_request,
1177 .copro_release = aspeed_g4_copro_release,
1178};
1179
1180static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
1181 const enum aspeed_gpio_reg reg, bool val)
1182{
1183 u32 mask = aspeed_gpio_g7_reg_mask(reg);
1184 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset);
1185 u32 write_val;
1186
1187 if (mask) {
1188 write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val);
1189 iowrite32(write_val, addr);
1190 }
1191}
1192
1193static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset,
1194 const enum aspeed_gpio_reg reg)
1195{
1196 u32 mask = aspeed_gpio_g7_reg_mask(reg);
1197 void __iomem *addr;
1198
1199 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset);
1200 if (reg == reg_val)
1201 mask = GPIO_G7_CTRL_IN_DATA;
1202
1203 if (mask)
1204 return field_get(mask, ioread32(addr));
1205 else
1206 return 0;
1207}
1208
1209static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset,
1210 const enum aspeed_gpio_reg reg)
1211{
1212 void __iomem *addr;
1213
1214 if (reg == reg_irq_status) {
1215 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5);
1216 return ioread32(addr);
1217 } else {
1218 return -EOPNOTSUPP;
1219 }
1220}
1221
1222static const struct aspeed_gpio_llops aspeed_g7_llops = {
1223 .reg_bit_set = aspeed_g7_reg_bit_set,
1224 .reg_bit_get = aspeed_g7_reg_bit_get,
1225 .reg_bank_get = aspeed_g7_reg_bank_get,
1226 .privilege_ctrl = NULL,
1227 .privilege_init = NULL,
1228 .copro_request = NULL,
1229 .copro_release = NULL,
1230};
1231
1232/*
1233 * Any banks not specified in a struct aspeed_bank_props array are assumed to
1234 * have the properties:
1235 *
1236 * { .input = 0xffffffff, .output = 0xffffffff }
1237 */
1238
1239static const struct aspeed_bank_props ast2400_bank_props[] = {
1240 /* input output */
1241 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1242 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1243 { },
1244};
1245
1246static const struct aspeed_gpio_config ast2400_config =
1247 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1248 {
1249 .nr_gpios = 220,
1250 .props = ast2400_bank_props,
1251 .llops = &aspeed_g4_llops,
1252 .debounce_timers_array = debounce_timers,
1253 .debounce_timers_num = ARRAY_SIZE(debounce_timers),
1254 .require_dcache = true,
1255 };
1256
1257static const struct aspeed_bank_props ast2500_bank_props[] = {
1258 /* input output */
1259 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1260 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1261 { 7, 0x000000ff, 0x000000ff }, /* AC */
1262 { },
1263};
1264
1265static const struct aspeed_gpio_config ast2500_config =
1266 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1267 {
1268 .nr_gpios = 232,
1269 .props = ast2500_bank_props,
1270 .llops = &aspeed_g4_llops,
1271 .debounce_timers_array = debounce_timers,
1272 .debounce_timers_num = ARRAY_SIZE(debounce_timers),
1273 .require_dcache = true,
1274 };
1275
1276static const struct aspeed_bank_props ast2600_bank_props[] = {
1277 /* input output */
1278 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
1279 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1280 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1281 { },
1282};
1283
1284static const struct aspeed_gpio_config ast2600_config =
1285 /*
1286 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1287 * We expect ngpio being set in the device tree and this is a fallback
1288 * option.
1289 */
1290 {
1291 .nr_gpios = 208,
1292 .props = ast2600_bank_props,
1293 .llops = &aspeed_g4_llops,
1294 .debounce_timers_array = debounce_timers,
1295 .debounce_timers_num = ARRAY_SIZE(debounce_timers),
1296 .require_dcache = true,
1297 };
1298
1299static const struct aspeed_bank_props ast2700_bank_props[] = {
1300 /* input output */
1301 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1302 { 6, 0x00ffffff, 0x00ff0000 }, /* Y/Z/AA */
1303 {},
1304};
1305
1306static const struct aspeed_gpio_config ast2700_config =
1307 /*
1308 * ast2700 has two controllers one with 212 GPIOs and one with 16 GPIOs.
1309 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1310 * We expect ngpio being set in the device tree and this is a fallback
1311 * option.
1312 */
1313 {
1314 .nr_gpios = 216,
1315 .props = ast2700_bank_props,
1316 .llops = &aspeed_g7_llops,
1317 .debounce_timers_array = g7_debounce_timers,
1318 .debounce_timers_num = ARRAY_SIZE(g7_debounce_timers),
1319 .require_dcache = false,
1320 };
1321
1322static const struct of_device_id aspeed_gpio_of_table[] = {
1323 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1324 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1325 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1326 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1327 {}
1328};
1329MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
1330
1331static int aspeed_gpio_probe(struct platform_device *pdev)
1332{
1333 const struct of_device_id *gpio_id;
1334 struct gpio_irq_chip *girq;
1335 struct aspeed_gpio *gpio;
1336 int rc, irq, i, banks, err;
1337 u32 ngpio;
1338
1339 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1340 if (!gpio)
1341 return -ENOMEM;
1342
1343 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1344 if (IS_ERR(gpio->base))
1345 return PTR_ERR(gpio->base);
1346
1347 gpio->dev = &pdev->dev;
1348
1349 raw_spin_lock_init(&gpio->lock);
1350
1351 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1352 if (!gpio_id)
1353 return -EINVAL;
1354
1355 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1356 if (IS_ERR(gpio->clk)) {
1357 dev_warn(&pdev->dev,
1358 "Failed to get clock from devicetree, debouncing disabled\n");
1359 gpio->clk = NULL;
1360 }
1361
1362 gpio->config = gpio_id->data;
1363
1364 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get ||
1365 !gpio->config->llops->reg_bank_get)
1366 return -EINVAL;
1367
1368 gpio->chip.parent = &pdev->dev;
1369 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1370 gpio->chip.ngpio = (u16) ngpio;
1371 if (err)
1372 gpio->chip.ngpio = gpio->config->nr_gpios;
1373 gpio->chip.direction_input = aspeed_gpio_dir_in;
1374 gpio->chip.direction_output = aspeed_gpio_dir_out;
1375 gpio->chip.get_direction = aspeed_gpio_get_direction;
1376 gpio->chip.request = aspeed_gpio_request;
1377 gpio->chip.free = aspeed_gpio_free;
1378 gpio->chip.get = aspeed_gpio_get;
1379 gpio->chip.set = aspeed_gpio_set;
1380 gpio->chip.set_config = aspeed_gpio_set_config;
1381 gpio->chip.label = dev_name(&pdev->dev);
1382 gpio->chip.base = -1;
1383
1384 if (gpio->config->require_dcache) {
1385 /* Allocate a cache of the output registers */
1386 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1387 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL);
1388 if (!gpio->dcache)
1389 return -ENOMEM;
1390 /*
1391 * Populate it with initial values read from the HW
1392 */
1393 for (i = 0; i < banks; i++)
1394 gpio->dcache[i] =
1395 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata);
1396 }
1397
1398 if (gpio->config->llops->privilege_init)
1399 gpio->config->llops->privilege_init(gpio);
1400
1401 /* Set up an irqchip */
1402 irq = platform_get_irq(pdev, 0);
1403 if (irq < 0)
1404 return irq;
1405 gpio->irq = irq;
1406 girq = &gpio->chip.irq;
1407 gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip);
1408
1409 girq->parent_handler = aspeed_gpio_irq_handler;
1410 girq->num_parents = 1;
1411 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
1412 if (!girq->parents)
1413 return -ENOMEM;
1414 girq->parents[0] = gpio->irq;
1415 girq->default_type = IRQ_TYPE_NONE;
1416 girq->handler = handle_bad_irq;
1417 girq->init_valid_mask = aspeed_init_irq_valid_mask;
1418
1419 gpio->offset_timer =
1420 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1421 if (!gpio->offset_timer)
1422 return -ENOMEM;
1423
1424 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1425 if (rc < 0)
1426 return rc;
1427
1428 return 0;
1429}
1430
1431static struct platform_driver aspeed_gpio_driver = {
1432 .probe = aspeed_gpio_probe,
1433 .driver = {
1434 .name = KBUILD_MODNAME,
1435 .of_match_table = aspeed_gpio_of_table,
1436 },
1437};
1438
1439module_platform_driver(aspeed_gpio_driver);
1440
1441MODULE_DESCRIPTION("Aspeed GPIO Driver");
1442MODULE_LICENSE("GPL");