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1// SPDX-License-Identifier: GPL-2.0-only
2
3#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4
5#include <linux/clk.h>
6#include <linux/clockchips.h>
7#include <linux/cpu.h>
8#include <linux/cpuhotplug.h>
9#include <linux/cpumask.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/jiffies.h>
13#include <linux/printk.h>
14#include <linux/sched_clock.h>
15#include "timer-of.h"
16
17#define RTTM_DATA 0x0
18#define RTTM_CNT 0x4
19#define RTTM_CTRL 0x8
20#define RTTM_INT 0xc
21
22#define RTTM_CTRL_ENABLE BIT(28)
23#define RTTM_INT_PENDING BIT(16)
24#define RTTM_INT_ENABLE BIT(20)
25
26/*
27 * The Otto platform provides multiple 28 bit timers/counters with the following
28 * operating logic. If enabled the timer counts up. Per timer one can set a
29 * maximum counter value as an end marker. If end marker is reached the timer
30 * fires an interrupt. If the timer "overflows" by reaching the end marker or
31 * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
32 * the timer is in operating mode COUNTER it stops. In mode TIMER it will
33 * continue to count up.
34 */
35#define RTTM_CTRL_COUNTER 0
36#define RTTM_CTRL_TIMER BIT(24)
37
38#define RTTM_BIT_COUNT 28
39#define RTTM_MIN_DELTA 8
40#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28)
41
42/*
43 * Timers are derived from the LXB clock frequency. Usually this is a fixed
44 * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
45 * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
46 * base. The only meaningful frequencies we can achieve from that are 175.000
47 * MHz and 153.125 MHz. The greatest common divisor of all explained possible
48 * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
49 */
50#define RTTM_TICKS_PER_SEC 3125000
51
52struct rttm_cs {
53 struct timer_of to;
54 struct clocksource cs;
55};
56
57/* Simple internal register functions */
58static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
59{
60 iowrite32(counter, base + RTTM_CNT);
61}
62
63static inline unsigned int rttm_get_counter(void __iomem *base)
64{
65 return ioread32(base + RTTM_CNT);
66}
67
68static inline void rttm_set_period(void __iomem *base, unsigned int period)
69{
70 iowrite32(period, base + RTTM_DATA);
71}
72
73static inline void rttm_disable_timer(void __iomem *base)
74{
75 iowrite32(0, base + RTTM_CTRL);
76}
77
78static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)
79{
80 iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);
81}
82
83static inline void rttm_ack_irq(void __iomem *base)
84{
85 iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);
86}
87
88static inline void rttm_enable_irq(void __iomem *base)
89{
90 iowrite32(RTTM_INT_ENABLE, base + RTTM_INT);
91}
92
93static inline void rttm_disable_irq(void __iomem *base)
94{
95 iowrite32(0, base + RTTM_INT);
96}
97
98/* Aggregated control functions for kernel clock framework */
99#define RTTM_DEBUG(base) \
100 pr_debug("------------- %d %p\n", \
101 smp_processor_id(), base)
102
103static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id)
104{
105 struct clock_event_device *clkevt = dev_id;
106 struct timer_of *to = to_timer_of(clkevt);
107
108 rttm_ack_irq(to->of_base.base);
109 RTTM_DEBUG(to->of_base.base);
110 clkevt->event_handler(clkevt);
111
112 return IRQ_HANDLED;
113}
114
115static void rttm_stop_timer(void __iomem *base)
116{
117 rttm_disable_timer(base);
118 rttm_ack_irq(base);
119}
120
121static void rttm_start_timer(struct timer_of *to, u32 mode)
122{
123 rttm_set_counter(to->of_base.base, 0);
124 rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC);
125}
126
127static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt)
128{
129 struct timer_of *to = to_timer_of(clkevt);
130
131 RTTM_DEBUG(to->of_base.base);
132 rttm_stop_timer(to->of_base.base);
133 rttm_set_period(to->of_base.base, delta);
134 rttm_start_timer(to, RTTM_CTRL_COUNTER);
135
136 return 0;
137}
138
139static int rttm_state_oneshot(struct clock_event_device *clkevt)
140{
141 struct timer_of *to = to_timer_of(clkevt);
142
143 RTTM_DEBUG(to->of_base.base);
144 rttm_stop_timer(to->of_base.base);
145 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
146 rttm_start_timer(to, RTTM_CTRL_COUNTER);
147
148 return 0;
149}
150
151static int rttm_state_periodic(struct clock_event_device *clkevt)
152{
153 struct timer_of *to = to_timer_of(clkevt);
154
155 RTTM_DEBUG(to->of_base.base);
156 rttm_stop_timer(to->of_base.base);
157 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
158 rttm_start_timer(to, RTTM_CTRL_TIMER);
159
160 return 0;
161}
162
163static int rttm_state_shutdown(struct clock_event_device *clkevt)
164{
165 struct timer_of *to = to_timer_of(clkevt);
166
167 RTTM_DEBUG(to->of_base.base);
168 rttm_stop_timer(to->of_base.base);
169
170 return 0;
171}
172
173static void rttm_setup_timer(void __iomem *base)
174{
175 RTTM_DEBUG(base);
176 rttm_stop_timer(base);
177 rttm_set_period(base, 0);
178}
179
180static u64 rttm_read_clocksource(struct clocksource *cs)
181{
182 struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
183
184 return rttm_get_counter(rcs->to.of_base.base);
185}
186
187/* Module initialization part. */
188static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
189 .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
190 .of_irq = {
191 .flags = IRQF_PERCPU | IRQF_TIMER,
192 .handler = rttm_timer_interrupt,
193 },
194 .clkevt = {
195 .rating = 400,
196 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
197 .set_state_periodic = rttm_state_periodic,
198 .set_state_shutdown = rttm_state_shutdown,
199 .set_state_oneshot = rttm_state_oneshot,
200 .set_next_event = rttm_next_event
201 },
202};
203
204static int rttm_enable_clocksource(struct clocksource *cs)
205{
206 struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
207
208 rttm_disable_irq(rcs->to.of_base.base);
209 rttm_setup_timer(rcs->to.of_base.base);
210 rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER,
211 rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC);
212
213 return 0;
214}
215
216struct rttm_cs rttm_cs = {
217 .to = {
218 .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
219 },
220 .cs = {
221 .name = "realtek_otto_timer",
222 .rating = 400,
223 .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT),
224 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
225 .read = rttm_read_clocksource,
226 }
227};
228
229static u64 notrace rttm_read_clock(void)
230{
231 return rttm_get_counter(rttm_cs.to.of_base.base);
232}
233
234static int rttm_cpu_starting(unsigned int cpu)
235{
236 struct timer_of *to = per_cpu_ptr(&rttm_to, cpu);
237
238 RTTM_DEBUG(to->of_base.base);
239 to->clkevt.cpumask = cpumask_of(cpu);
240 irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask);
241 clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC,
242 RTTM_MIN_DELTA, RTTM_MAX_DELTA);
243 rttm_enable_irq(to->of_base.base);
244
245 return 0;
246}
247
248static int __init rttm_probe(struct device_node *np)
249{
250 unsigned int cpu, cpu_rollback;
251 struct timer_of *to;
252 unsigned int clkidx = num_possible_cpus();
253
254 /* Use the first n timers as per CPU clock event generators */
255 for_each_possible_cpu(cpu) {
256 to = per_cpu_ptr(&rttm_to, cpu);
257 to->of_irq.index = to->of_base.index = cpu;
258 if (timer_of_init(np, to)) {
259 pr_err("setup of timer %d failed\n", cpu);
260 goto rollback;
261 }
262 rttm_setup_timer(to->of_base.base);
263 }
264
265 /* Activate the n'th + 1 timer as a stable CPU clocksource. */
266 to = &rttm_cs.to;
267 to->of_base.index = clkidx;
268 timer_of_init(np, to);
269 if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) {
270 rttm_enable_clocksource(&rttm_cs.cs);
271 clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC);
272 sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC);
273 } else
274 pr_err(" setup of timer %d as clocksource failed", clkidx);
275
276 return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING,
277 "timer/realtek:online",
278 rttm_cpu_starting, NULL);
279rollback:
280 pr_err("timer registration failed\n");
281 for_each_possible_cpu(cpu_rollback) {
282 if (cpu_rollback == cpu)
283 break;
284 to = per_cpu_ptr(&rttm_to, cpu_rollback);
285 timer_of_cleanup(to);
286 }
287
288 return -EINVAL;
289}
290
291TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe);