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1/*
2 * Atheros AR71XX/AR724X/AR913X SoC register definitions
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __ASM_MACH_AR71XX_REGS_H
15#define __ASM_MACH_AR71XX_REGS_H
16
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/bitops.h>
21
22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_SPI_BASE 0x1f000000
24#define AR71XX_SPI_SIZE 0x01000000
25
26#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
27#define AR71XX_DDR_CTRL_SIZE 0x100
28#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29#define AR71XX_UART_SIZE 0x100
30#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
31#define AR71XX_GPIO_SIZE 0x100
32#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
33#define AR71XX_PLL_SIZE 0x100
34#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
35#define AR71XX_RESET_SIZE 0x100
36
37#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
38#define AR913X_WMAC_SIZE 0x30000
39
40/*
41 * DDR_CTRL block
42 */
43#define AR71XX_DDR_REG_PCI_WIN0 0x7c
44#define AR71XX_DDR_REG_PCI_WIN1 0x80
45#define AR71XX_DDR_REG_PCI_WIN2 0x84
46#define AR71XX_DDR_REG_PCI_WIN3 0x88
47#define AR71XX_DDR_REG_PCI_WIN4 0x8c
48#define AR71XX_DDR_REG_PCI_WIN5 0x90
49#define AR71XX_DDR_REG_PCI_WIN6 0x94
50#define AR71XX_DDR_REG_PCI_WIN7 0x98
51#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
52#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
53#define AR71XX_DDR_REG_FLUSH_USB 0xa4
54#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
55
56#define AR724X_DDR_REG_FLUSH_GE0 0x7c
57#define AR724X_DDR_REG_FLUSH_GE1 0x80
58#define AR724X_DDR_REG_FLUSH_USB 0x84
59#define AR724X_DDR_REG_FLUSH_PCIE 0x88
60
61#define AR913X_DDR_REG_FLUSH_GE0 0x7c
62#define AR913X_DDR_REG_FLUSH_GE1 0x80
63#define AR913X_DDR_REG_FLUSH_USB 0x84
64#define AR913X_DDR_REG_FLUSH_WMAC 0x88
65
66/*
67 * PLL block
68 */
69#define AR71XX_PLL_REG_CPU_CONFIG 0x00
70#define AR71XX_PLL_REG_SEC_CONFIG 0x04
71#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
72#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
73
74#define AR71XX_PLL_DIV_SHIFT 3
75#define AR71XX_PLL_DIV_MASK 0x1f
76#define AR71XX_CPU_DIV_SHIFT 16
77#define AR71XX_CPU_DIV_MASK 0x3
78#define AR71XX_DDR_DIV_SHIFT 18
79#define AR71XX_DDR_DIV_MASK 0x3
80#define AR71XX_AHB_DIV_SHIFT 20
81#define AR71XX_AHB_DIV_MASK 0x7
82
83#define AR724X_PLL_REG_CPU_CONFIG 0x00
84#define AR724X_PLL_REG_PCIE_CONFIG 0x18
85
86#define AR724X_PLL_DIV_SHIFT 0
87#define AR724X_PLL_DIV_MASK 0x3ff
88#define AR724X_PLL_REF_DIV_SHIFT 10
89#define AR724X_PLL_REF_DIV_MASK 0xf
90#define AR724X_AHB_DIV_SHIFT 19
91#define AR724X_AHB_DIV_MASK 0x1
92#define AR724X_DDR_DIV_SHIFT 22
93#define AR724X_DDR_DIV_MASK 0x3
94
95#define AR913X_PLL_REG_CPU_CONFIG 0x00
96#define AR913X_PLL_REG_ETH_CONFIG 0x04
97#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
98#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
99
100#define AR913X_PLL_DIV_SHIFT 0
101#define AR913X_PLL_DIV_MASK 0x3ff
102#define AR913X_DDR_DIV_SHIFT 22
103#define AR913X_DDR_DIV_MASK 0x3
104#define AR913X_AHB_DIV_SHIFT 19
105#define AR913X_AHB_DIV_MASK 0x1
106
107/*
108 * RESET block
109 */
110#define AR71XX_RESET_REG_TIMER 0x00
111#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
112#define AR71XX_RESET_REG_WDOG_CTRL 0x08
113#define AR71XX_RESET_REG_WDOG 0x0c
114#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
115#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
116#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
117#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
118#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
119#define AR71XX_RESET_REG_RESET_MODULE 0x24
120#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
121#define AR71XX_RESET_REG_PERFC0 0x30
122#define AR71XX_RESET_REG_PERFC1 0x34
123#define AR71XX_RESET_REG_REV_ID 0x90
124
125#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
126#define AR913X_RESET_REG_RESET_MODULE 0x1c
127#define AR913X_RESET_REG_PERF_CTRL 0x20
128#define AR913X_RESET_REG_PERFC0 0x24
129#define AR913X_RESET_REG_PERFC1 0x28
130
131#define AR724X_RESET_REG_RESET_MODULE 0x1c
132
133#define MISC_INT_DMA BIT(7)
134#define MISC_INT_OHCI BIT(6)
135#define MISC_INT_PERFC BIT(5)
136#define MISC_INT_WDOG BIT(4)
137#define MISC_INT_UART BIT(3)
138#define MISC_INT_GPIO BIT(2)
139#define MISC_INT_ERROR BIT(1)
140#define MISC_INT_TIMER BIT(0)
141
142#define AR71XX_RESET_EXTERNAL BIT(28)
143#define AR71XX_RESET_FULL_CHIP BIT(24)
144#define AR71XX_RESET_CPU_NMI BIT(21)
145#define AR71XX_RESET_CPU_COLD BIT(20)
146#define AR71XX_RESET_DMA BIT(19)
147#define AR71XX_RESET_SLIC BIT(18)
148#define AR71XX_RESET_STEREO BIT(17)
149#define AR71XX_RESET_DDR BIT(16)
150#define AR71XX_RESET_GE1_MAC BIT(13)
151#define AR71XX_RESET_GE1_PHY BIT(12)
152#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
153#define AR71XX_RESET_GE0_MAC BIT(9)
154#define AR71XX_RESET_GE0_PHY BIT(8)
155#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
156#define AR71XX_RESET_USB_HOST BIT(5)
157#define AR71XX_RESET_USB_PHY BIT(4)
158#define AR71XX_RESET_PCI_BUS BIT(1)
159#define AR71XX_RESET_PCI_CORE BIT(0)
160
161#define AR724X_RESET_GE1_MDIO BIT(23)
162#define AR724X_RESET_GE0_MDIO BIT(22)
163#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
164#define AR724X_RESET_PCIE_PHY BIT(7)
165#define AR724X_RESET_PCIE BIT(6)
166#define AR724X_RESET_OHCI_DLL BIT(3)
167
168#define AR913X_RESET_AMBA2WMAC BIT(22)
169
170#define REV_ID_MAJOR_MASK 0xfff0
171#define REV_ID_MAJOR_AR71XX 0x00a0
172#define REV_ID_MAJOR_AR913X 0x00b0
173#define REV_ID_MAJOR_AR7240 0x00c0
174#define REV_ID_MAJOR_AR7241 0x0100
175#define REV_ID_MAJOR_AR7242 0x1100
176
177#define AR71XX_REV_ID_MINOR_MASK 0x3
178#define AR71XX_REV_ID_MINOR_AR7130 0x0
179#define AR71XX_REV_ID_MINOR_AR7141 0x1
180#define AR71XX_REV_ID_MINOR_AR7161 0x2
181#define AR71XX_REV_ID_REVISION_MASK 0x3
182#define AR71XX_REV_ID_REVISION_SHIFT 2
183
184#define AR913X_REV_ID_MINOR_MASK 0x3
185#define AR913X_REV_ID_MINOR_AR9130 0x0
186#define AR913X_REV_ID_MINOR_AR9132 0x1
187#define AR913X_REV_ID_REVISION_MASK 0x3
188#define AR913X_REV_ID_REVISION_SHIFT 2
189
190#define AR724X_REV_ID_REVISION_MASK 0x3
191
192/*
193 * SPI block
194 */
195#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
196#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
197#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
198#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
199
200#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
201
202#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
203#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
204
205#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
206#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
207#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
208#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
209#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
210#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
211#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
212 AR71XX_SPI_IOC_CS2)
213
214/*
215 * GPIO block
216 */
217#define AR71XX_GPIO_REG_OE 0x00
218#define AR71XX_GPIO_REG_IN 0x04
219#define AR71XX_GPIO_REG_OUT 0x08
220#define AR71XX_GPIO_REG_SET 0x0c
221#define AR71XX_GPIO_REG_CLEAR 0x10
222#define AR71XX_GPIO_REG_INT_MODE 0x14
223#define AR71XX_GPIO_REG_INT_TYPE 0x18
224#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
225#define AR71XX_GPIO_REG_INT_PENDING 0x20
226#define AR71XX_GPIO_REG_INT_ENABLE 0x24
227#define AR71XX_GPIO_REG_FUNC 0x28
228
229#define AR71XX_GPIO_COUNT 16
230#define AR724X_GPIO_COUNT 18
231#define AR913X_GPIO_COUNT 22
232
233#endif /* __ASM_MACH_AR71XX_REGS_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Atheros AR71XX/AR724X/AR913X SoC register definitions
4 *
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 *
9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 */
11
12#ifndef __ASM_MACH_AR71XX_REGS_H
13#define __ASM_MACH_AR71XX_REGS_H
14
15#include <linux/types.h>
16#include <linux/io.h>
17#include <linux/bitops.h>
18
19#define AR71XX_APB_BASE 0x18000000
20#define AR71XX_GE0_BASE 0x19000000
21#define AR71XX_GE0_SIZE 0x10000
22#define AR71XX_GE1_BASE 0x1a000000
23#define AR71XX_GE1_SIZE 0x10000
24#define AR71XX_EHCI_BASE 0x1b000000
25#define AR71XX_EHCI_SIZE 0x1000
26#define AR71XX_OHCI_BASE 0x1c000000
27#define AR71XX_OHCI_SIZE 0x1000
28#define AR71XX_SPI_BASE 0x1f000000
29#define AR71XX_SPI_SIZE 0x01000000
30
31#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
32#define AR71XX_DDR_CTRL_SIZE 0x100
33#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
34#define AR71XX_UART_SIZE 0x100
35#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
36#define AR71XX_USB_CTRL_SIZE 0x100
37#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
38#define AR71XX_GPIO_SIZE 0x100
39#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
40#define AR71XX_PLL_SIZE 0x100
41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42#define AR71XX_RESET_SIZE 0x100
43#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
44#define AR71XX_MII_SIZE 0x100
45
46#define AR71XX_PCI_MEM_BASE 0x10000000
47#define AR71XX_PCI_MEM_SIZE 0x07000000
48
49#define AR71XX_PCI_WIN0_OFFS 0x10000000
50#define AR71XX_PCI_WIN1_OFFS 0x11000000
51#define AR71XX_PCI_WIN2_OFFS 0x12000000
52#define AR71XX_PCI_WIN3_OFFS 0x13000000
53#define AR71XX_PCI_WIN4_OFFS 0x14000000
54#define AR71XX_PCI_WIN5_OFFS 0x15000000
55#define AR71XX_PCI_WIN6_OFFS 0x16000000
56#define AR71XX_PCI_WIN7_OFFS 0x07000000
57
58#define AR71XX_PCI_CFG_BASE \
59 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
60#define AR71XX_PCI_CFG_SIZE 0x100
61
62#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
63#define AR7240_USB_CTRL_SIZE 0x100
64#define AR7240_OHCI_BASE 0x1b000000
65#define AR7240_OHCI_SIZE 0x1000
66
67#define AR724X_PCI_MEM_BASE 0x10000000
68#define AR724X_PCI_MEM_SIZE 0x04000000
69
70#define AR724X_PCI_CFG_BASE 0x14000000
71#define AR724X_PCI_CFG_SIZE 0x1000
72#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
73#define AR724X_PCI_CRP_SIZE 0x1000
74#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
75#define AR724X_PCI_CTRL_SIZE 0x100
76
77#define AR724X_EHCI_BASE 0x1b000000
78#define AR724X_EHCI_SIZE 0x1000
79
80#define AR913X_EHCI_BASE 0x1b000000
81#define AR913X_EHCI_SIZE 0x1000
82#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
83#define AR913X_WMAC_SIZE 0x30000
84
85#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
86#define AR933X_UART_SIZE 0x14
87#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
88#define AR933X_GMAC_SIZE 0x04
89#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
90#define AR933X_WMAC_SIZE 0x20000
91#define AR933X_EHCI_BASE 0x1b000000
92#define AR933X_EHCI_SIZE 0x1000
93
94#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
95#define AR934X_GMAC_SIZE 0x14
96#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
97#define AR934X_WMAC_SIZE 0x20000
98#define AR934X_EHCI_BASE 0x1b000000
99#define AR934X_EHCI_SIZE 0x200
100#define AR934X_NFC_BASE 0x1b000200
101#define AR934X_NFC_SIZE 0xb8
102#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
103#define AR934X_SRIF_SIZE 0x1000
104
105#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
106#define QCA953X_GMAC_SIZE 0x14
107#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
108#define QCA953X_WMAC_SIZE 0x20000
109#define QCA953X_EHCI_BASE 0x1b000000
110#define QCA953X_EHCI_SIZE 0x200
111#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
112#define QCA953X_SRIF_SIZE 0x1000
113
114#define QCA953X_PCI_CFG_BASE0 0x14000000
115#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
116#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
117#define QCA953X_PCI_MEM_BASE0 0x10000000
118#define QCA953X_PCI_MEM_SIZE 0x02000000
119
120#define QCA955X_PCI_MEM_BASE0 0x10000000
121#define QCA955X_PCI_MEM_BASE1 0x12000000
122#define QCA955X_PCI_MEM_SIZE 0x02000000
123#define QCA955X_PCI_CFG_BASE0 0x14000000
124#define QCA955X_PCI_CFG_BASE1 0x16000000
125#define QCA955X_PCI_CFG_SIZE 0x1000
126#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
127#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
128#define QCA955X_PCI_CRP_SIZE 0x1000
129#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
130#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
131#define QCA955X_PCI_CTRL_SIZE 0x100
132
133#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
134#define QCA955X_GMAC_SIZE 0x40
135#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
136#define QCA955X_WMAC_SIZE 0x20000
137#define QCA955X_EHCI0_BASE 0x1b000000
138#define QCA955X_EHCI1_BASE 0x1b400000
139#define QCA955X_EHCI_SIZE 0x1000
140#define QCA955X_NFC_BASE 0x1b800200
141#define QCA955X_NFC_SIZE 0xb8
142
143#define QCA956X_PCI_MEM_BASE1 0x12000000
144#define QCA956X_PCI_MEM_SIZE 0x02000000
145#define QCA956X_PCI_CFG_BASE1 0x16000000
146#define QCA956X_PCI_CFG_SIZE 0x1000
147#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
148#define QCA956X_PCI_CRP_SIZE 0x1000
149#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
150#define QCA956X_PCI_CTRL_SIZE 0x100
151
152#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
153#define QCA956X_WMAC_SIZE 0x20000
154#define QCA956X_EHCI0_BASE 0x1b000000
155#define QCA956X_EHCI1_BASE 0x1b400000
156#define QCA956X_EHCI_SIZE 0x200
157#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
158#define QCA956X_GMAC_SGMII_SIZE 0x64
159#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
160#define QCA956X_PLL_SIZE 0x50
161#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
162#define QCA956X_GMAC_SIZE 0x64
163
164/*
165 * Hidden Registers
166 */
167#define QCA956X_MAC_CFG_BASE 0xb9000000
168#define QCA956X_MAC_CFG_SIZE 0x64
169
170#define QCA956X_MAC_CFG1_REG 0x00
171#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172#define QCA956X_MAC_CFG1_RX_RST BIT(19)
173#define QCA956X_MAC_CFG1_TX_RST BIT(18)
174#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175#define QCA956X_MAC_CFG1_RX_EN BIT(2)
176#define QCA956X_MAC_CFG1_TX_EN BIT(0)
177
178#define QCA956X_MAC_CFG2_REG 0x04
179#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
180#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
181#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
182#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
183#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
184#define QCA956X_MAC_CFG2_FDX BIT(0)
185
186#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
187#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
188
189#define QCA956X_MAC_FIFO_CFG0_REG 0x48
190#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
191#define QCA956X_MAC_FIFO_CFG2_REG 0x50
192#define QCA956X_MAC_FIFO_CFG3_REG 0x54
193#define QCA956X_MAC_FIFO_CFG4_REG 0x58
194#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
195
196#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
197#define QCA956X_DAM_RESET_SIZE 0x4
198#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
199
200/*
201 * DDR_CTRL block
202 */
203#define AR71XX_DDR_REG_PCI_WIN0 0x7c
204#define AR71XX_DDR_REG_PCI_WIN1 0x80
205#define AR71XX_DDR_REG_PCI_WIN2 0x84
206#define AR71XX_DDR_REG_PCI_WIN3 0x88
207#define AR71XX_DDR_REG_PCI_WIN4 0x8c
208#define AR71XX_DDR_REG_PCI_WIN5 0x90
209#define AR71XX_DDR_REG_PCI_WIN6 0x94
210#define AR71XX_DDR_REG_PCI_WIN7 0x98
211#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
212#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
213#define AR71XX_DDR_REG_FLUSH_USB 0xa4
214#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
215
216#define AR724X_DDR_REG_FLUSH_GE0 0x7c
217#define AR724X_DDR_REG_FLUSH_GE1 0x80
218#define AR724X_DDR_REG_FLUSH_USB 0x84
219#define AR724X_DDR_REG_FLUSH_PCIE 0x88
220
221#define AR913X_DDR_REG_FLUSH_GE0 0x7c
222#define AR913X_DDR_REG_FLUSH_GE1 0x80
223#define AR913X_DDR_REG_FLUSH_USB 0x84
224#define AR913X_DDR_REG_FLUSH_WMAC 0x88
225
226#define AR933X_DDR_REG_FLUSH_GE0 0x7c
227#define AR933X_DDR_REG_FLUSH_GE1 0x80
228#define AR933X_DDR_REG_FLUSH_USB 0x84
229#define AR933X_DDR_REG_FLUSH_WMAC 0x88
230
231#define AR934X_DDR_REG_FLUSH_GE0 0x9c
232#define AR934X_DDR_REG_FLUSH_GE1 0xa0
233#define AR934X_DDR_REG_FLUSH_USB 0xa4
234#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
235#define AR934X_DDR_REG_FLUSH_WMAC 0xac
236
237#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
238#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
239#define QCA953X_DDR_REG_FLUSH_USB 0xa4
240#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
241#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
242
243/*
244 * PLL block
245 */
246#define AR71XX_PLL_REG_CPU_CONFIG 0x00
247#define AR71XX_PLL_REG_SEC_CONFIG 0x04
248#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
249#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
250
251#define AR71XX_PLL_FB_SHIFT 3
252#define AR71XX_PLL_FB_MASK 0x1f
253#define AR71XX_CPU_DIV_SHIFT 16
254#define AR71XX_CPU_DIV_MASK 0x3
255#define AR71XX_DDR_DIV_SHIFT 18
256#define AR71XX_DDR_DIV_MASK 0x3
257#define AR71XX_AHB_DIV_SHIFT 20
258#define AR71XX_AHB_DIV_MASK 0x7
259
260#define AR71XX_ETH0_PLL_SHIFT 17
261#define AR71XX_ETH1_PLL_SHIFT 19
262
263#define AR724X_PLL_REG_CPU_CONFIG 0x00
264#define AR724X_PLL_REG_PCIE_CONFIG 0x10
265
266#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
267#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
268
269#define AR724X_PLL_FB_SHIFT 0
270#define AR724X_PLL_FB_MASK 0x3ff
271#define AR724X_PLL_REF_DIV_SHIFT 10
272#define AR724X_PLL_REF_DIV_MASK 0xf
273#define AR724X_AHB_DIV_SHIFT 19
274#define AR724X_AHB_DIV_MASK 0x1
275#define AR724X_DDR_DIV_SHIFT 22
276#define AR724X_DDR_DIV_MASK 0x3
277
278#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
279
280#define AR913X_PLL_REG_CPU_CONFIG 0x00
281#define AR913X_PLL_REG_ETH_CONFIG 0x04
282#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
283#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
284
285#define AR913X_PLL_FB_SHIFT 0
286#define AR913X_PLL_FB_MASK 0x3ff
287#define AR913X_DDR_DIV_SHIFT 22
288#define AR913X_DDR_DIV_MASK 0x3
289#define AR913X_AHB_DIV_SHIFT 19
290#define AR913X_AHB_DIV_MASK 0x1
291
292#define AR913X_ETH0_PLL_SHIFT 20
293#define AR913X_ETH1_PLL_SHIFT 22
294
295#define AR933X_PLL_CPU_CONFIG_REG 0x00
296#define AR933X_PLL_CLOCK_CTRL_REG 0x08
297
298#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
299#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
300#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
301#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
302#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
303#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
304
305#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
306#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
307#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
308#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
309#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
310#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
311#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
312
313#define AR934X_PLL_CPU_CONFIG_REG 0x00
314#define AR934X_PLL_DDR_CONFIG_REG 0x04
315#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
316#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
317#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
318
319#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
320#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
321#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
322#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
323#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
324#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
325#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
326#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
327
328#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
329#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
330#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
331#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
332#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
333#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
334#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
335#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
336
337#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
338#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
339#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
340#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
341#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
342#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
343#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
344#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
345#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
346#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
347#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
348#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
349
350#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
351
352#define QCA953X_PLL_CPU_CONFIG_REG 0x00
353#define QCA953X_PLL_DDR_CONFIG_REG 0x04
354#define QCA953X_PLL_CLK_CTRL_REG 0x08
355#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
356#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
357#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
358
359#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
360#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
361#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
362#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
363#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
364#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
365#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
366#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
367
368#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
369#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
370#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
371#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
372#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
373#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
374#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
375#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
376
377#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
378#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
379#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
380#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
381#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
382#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
383#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
384#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
385#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
386#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
387#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
388#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
389
390#define QCA955X_PLL_CPU_CONFIG_REG 0x00
391#define QCA955X_PLL_DDR_CONFIG_REG 0x04
392#define QCA955X_PLL_CLK_CTRL_REG 0x08
393#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
394#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
395#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
396
397#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
398#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
399#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
400#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
401#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
402#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
403#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
404#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
405
406#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
407#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
408#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
409#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
410#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
411#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
412#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
413#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
414
415#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
416#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
417#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
418#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
419#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
420#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
421#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
422#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
423#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
424#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
425#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
426#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
427
428#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
429#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
430#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
431
432#define QCA956X_PLL_CPU_CONFIG_REG 0x00
433#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
434#define QCA956X_PLL_DDR_CONFIG_REG 0x08
435#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
436#define QCA956X_PLL_CLK_CTRL_REG 0x10
437#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
438#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
439#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
440
441#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
442#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
443#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
444#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
445
446#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
447#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
448#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
449#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
450#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
451#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
452
453#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
454#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
455#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
456#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
457
458#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
459#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
460#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
461#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
462#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
463#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
464
465#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
466#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
467#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
468#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
469#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
470#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
471#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
472#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
473#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
474#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
475#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
476#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
477
478#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
479#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
480#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
481#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
482#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
483#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
484#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
485#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
486#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
487#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
488#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
489#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
490#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
491
492#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
493#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
494#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
495#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
496#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
497#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
498
499#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
500#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
501#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
502
503/*
504 * USB_CONFIG block
505 */
506#define AR71XX_USB_CTRL_REG_FLADJ 0x00
507#define AR71XX_USB_CTRL_REG_CONFIG 0x04
508
509/*
510 * RESET block
511 */
512#define AR71XX_RESET_REG_TIMER 0x00
513#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
514#define AR71XX_RESET_REG_WDOG_CTRL 0x08
515#define AR71XX_RESET_REG_WDOG 0x0c
516#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
517#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
518#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
519#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
520#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
521#define AR71XX_RESET_REG_RESET_MODULE 0x24
522#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
523#define AR71XX_RESET_REG_PERFC0 0x30
524#define AR71XX_RESET_REG_PERFC1 0x34
525#define AR71XX_RESET_REG_REV_ID 0x90
526
527#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
528#define AR913X_RESET_REG_RESET_MODULE 0x1c
529#define AR913X_RESET_REG_PERF_CTRL 0x20
530#define AR913X_RESET_REG_PERFC0 0x24
531#define AR913X_RESET_REG_PERFC1 0x28
532
533#define AR724X_RESET_REG_RESET_MODULE 0x1c
534
535#define AR933X_RESET_REG_RESET_MODULE 0x1c
536#define AR933X_RESET_REG_BOOTSTRAP 0xac
537
538#define AR934X_RESET_REG_RESET_MODULE 0x1c
539#define AR934X_RESET_REG_BOOTSTRAP 0xb0
540#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
541
542#define QCA953X_RESET_REG_RESET_MODULE 0x1c
543#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
544#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
545
546#define QCA955X_RESET_REG_RESET_MODULE 0x1c
547#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
548#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
549
550#define QCA956X_RESET_REG_RESET_MODULE 0x1c
551#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
552#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
553
554#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
555#define MISC_INT_ETHSW BIT(12)
556#define MISC_INT_TIMER4 BIT(10)
557#define MISC_INT_TIMER3 BIT(9)
558#define MISC_INT_TIMER2 BIT(8)
559#define MISC_INT_DMA BIT(7)
560#define MISC_INT_OHCI BIT(6)
561#define MISC_INT_PERFC BIT(5)
562#define MISC_INT_WDOG BIT(4)
563#define MISC_INT_UART BIT(3)
564#define MISC_INT_GPIO BIT(2)
565#define MISC_INT_ERROR BIT(1)
566#define MISC_INT_TIMER BIT(0)
567
568#define AR71XX_RESET_EXTERNAL BIT(28)
569#define AR71XX_RESET_FULL_CHIP BIT(24)
570#define AR71XX_RESET_CPU_NMI BIT(21)
571#define AR71XX_RESET_CPU_COLD BIT(20)
572#define AR71XX_RESET_DMA BIT(19)
573#define AR71XX_RESET_SLIC BIT(18)
574#define AR71XX_RESET_STEREO BIT(17)
575#define AR71XX_RESET_DDR BIT(16)
576#define AR71XX_RESET_GE1_MAC BIT(13)
577#define AR71XX_RESET_GE1_PHY BIT(12)
578#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
579#define AR71XX_RESET_GE0_MAC BIT(9)
580#define AR71XX_RESET_GE0_PHY BIT(8)
581#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
582#define AR71XX_RESET_USB_HOST BIT(5)
583#define AR71XX_RESET_USB_PHY BIT(4)
584#define AR71XX_RESET_PCI_BUS BIT(1)
585#define AR71XX_RESET_PCI_CORE BIT(0)
586
587#define AR7240_RESET_USB_HOST BIT(5)
588#define AR7240_RESET_OHCI_DLL BIT(3)
589
590#define AR724X_RESET_GE1_MDIO BIT(23)
591#define AR724X_RESET_GE0_MDIO BIT(22)
592#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
593#define AR724X_RESET_PCIE_PHY BIT(7)
594#define AR724X_RESET_PCIE BIT(6)
595#define AR724X_RESET_USB_HOST BIT(5)
596#define AR724X_RESET_USB_PHY BIT(4)
597#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
598
599#define AR913X_RESET_AMBA2WMAC BIT(22)
600#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
601#define AR913X_RESET_USB_HOST BIT(5)
602#define AR913X_RESET_USB_PHY BIT(4)
603
604#define AR933X_RESET_GE1_MDIO BIT(23)
605#define AR933X_RESET_GE0_MDIO BIT(22)
606#define AR933X_RESET_GE1_MAC BIT(13)
607#define AR933X_RESET_WMAC BIT(11)
608#define AR933X_RESET_GE0_MAC BIT(9)
609#define AR933X_RESET_USB_HOST BIT(5)
610#define AR933X_RESET_USB_PHY BIT(4)
611#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
612
613#define AR934X_RESET_HOST BIT(31)
614#define AR934X_RESET_SLIC BIT(30)
615#define AR934X_RESET_HDMA BIT(29)
616#define AR934X_RESET_EXTERNAL BIT(28)
617#define AR934X_RESET_RTC BIT(27)
618#define AR934X_RESET_PCIE_EP_INT BIT(26)
619#define AR934X_RESET_CHKSUM_ACC BIT(25)
620#define AR934X_RESET_FULL_CHIP BIT(24)
621#define AR934X_RESET_GE1_MDIO BIT(23)
622#define AR934X_RESET_GE0_MDIO BIT(22)
623#define AR934X_RESET_CPU_NMI BIT(21)
624#define AR934X_RESET_CPU_COLD BIT(20)
625#define AR934X_RESET_HOST_RESET_INT BIT(19)
626#define AR934X_RESET_PCIE_EP BIT(18)
627#define AR934X_RESET_UART1 BIT(17)
628#define AR934X_RESET_DDR BIT(16)
629#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
630#define AR934X_RESET_NANDF BIT(14)
631#define AR934X_RESET_GE1_MAC BIT(13)
632#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
633#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
634#define AR934X_RESET_HOST_DMA_INT BIT(10)
635#define AR934X_RESET_GE0_MAC BIT(9)
636#define AR934X_RESET_ETH_SWITCH BIT(8)
637#define AR934X_RESET_PCIE_PHY BIT(7)
638#define AR934X_RESET_PCIE BIT(6)
639#define AR934X_RESET_USB_HOST BIT(5)
640#define AR934X_RESET_USB_PHY BIT(4)
641#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
642#define AR934X_RESET_LUT BIT(2)
643#define AR934X_RESET_MBOX BIT(1)
644#define AR934X_RESET_I2S BIT(0)
645
646#define QCA953X_RESET_USB_EXT_PWR BIT(29)
647#define QCA953X_RESET_EXTERNAL BIT(28)
648#define QCA953X_RESET_RTC BIT(27)
649#define QCA953X_RESET_FULL_CHIP BIT(24)
650#define QCA953X_RESET_GE1_MDIO BIT(23)
651#define QCA953X_RESET_GE0_MDIO BIT(22)
652#define QCA953X_RESET_CPU_NMI BIT(21)
653#define QCA953X_RESET_CPU_COLD BIT(20)
654#define QCA953X_RESET_DDR BIT(16)
655#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
656#define QCA953X_RESET_GE1_MAC BIT(13)
657#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
658#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
659#define QCA953X_RESET_GE0_MAC BIT(9)
660#define QCA953X_RESET_ETH_SWITCH BIT(8)
661#define QCA953X_RESET_PCIE_PHY BIT(7)
662#define QCA953X_RESET_PCIE BIT(6)
663#define QCA953X_RESET_USB_HOST BIT(5)
664#define QCA953X_RESET_USB_PHY BIT(4)
665#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
666
667#define QCA955X_RESET_HOST BIT(31)
668#define QCA955X_RESET_SLIC BIT(30)
669#define QCA955X_RESET_HDMA BIT(29)
670#define QCA955X_RESET_EXTERNAL BIT(28)
671#define QCA955X_RESET_RTC BIT(27)
672#define QCA955X_RESET_PCIE_EP_INT BIT(26)
673#define QCA955X_RESET_CHKSUM_ACC BIT(25)
674#define QCA955X_RESET_FULL_CHIP BIT(24)
675#define QCA955X_RESET_GE1_MDIO BIT(23)
676#define QCA955X_RESET_GE0_MDIO BIT(22)
677#define QCA955X_RESET_CPU_NMI BIT(21)
678#define QCA955X_RESET_CPU_COLD BIT(20)
679#define QCA955X_RESET_HOST_RESET_INT BIT(19)
680#define QCA955X_RESET_PCIE_EP BIT(18)
681#define QCA955X_RESET_UART1 BIT(17)
682#define QCA955X_RESET_DDR BIT(16)
683#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
684#define QCA955X_RESET_NANDF BIT(14)
685#define QCA955X_RESET_GE1_MAC BIT(13)
686#define QCA955X_RESET_SGMII_ANALOG BIT(12)
687#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
688#define QCA955X_RESET_HOST_DMA_INT BIT(10)
689#define QCA955X_RESET_GE0_MAC BIT(9)
690#define QCA955X_RESET_SGMII BIT(8)
691#define QCA955X_RESET_PCIE_PHY BIT(7)
692#define QCA955X_RESET_PCIE BIT(6)
693#define QCA955X_RESET_USB_HOST BIT(5)
694#define QCA955X_RESET_USB_PHY BIT(4)
695#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
696#define QCA955X_RESET_LUT BIT(2)
697#define QCA955X_RESET_MBOX BIT(1)
698#define QCA955X_RESET_I2S BIT(0)
699
700#define QCA956X_RESET_EXTERNAL BIT(28)
701#define QCA956X_RESET_FULL_CHIP BIT(24)
702#define QCA956X_RESET_GE1_MDIO BIT(23)
703#define QCA956X_RESET_GE0_MDIO BIT(22)
704#define QCA956X_RESET_CPU_NMI BIT(21)
705#define QCA956X_RESET_CPU_COLD BIT(20)
706#define QCA956X_RESET_DMA BIT(19)
707#define QCA956X_RESET_DDR BIT(16)
708#define QCA956X_RESET_GE1_MAC BIT(13)
709#define QCA956X_RESET_SGMII_ANALOG BIT(12)
710#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
711#define QCA956X_RESET_GE0_MAC BIT(9)
712#define QCA956X_RESET_SGMII BIT(8)
713#define QCA956X_RESET_USB_HOST BIT(5)
714#define QCA956X_RESET_USB_PHY BIT(4)
715#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
716#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
717#define QCA956X_RESET_SWITCH BIT(0)
718
719#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
720#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
721#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
722
723#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
724#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
725#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
726#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
727#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
728#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
729#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
730#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
731#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
732#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
733#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
734#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
735#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
736#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
737#define AR934X_BOOTSTRAP_DDR1 BIT(0)
738
739#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
740#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
741#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
742#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
743#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
744#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
745
746#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
747
748#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
749
750#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
751#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
752#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
753#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
754#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
755#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
756#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
757#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
758#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
759#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
760 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
761 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
762
763#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
764 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
765 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
766 AR934X_PCIE_WMAC_INT_PCIE_RC3)
767
768#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
769#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
770#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
771#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
772#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
773#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
774#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
775#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
776#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
777#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
778 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
779 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
780
781#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
782 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
783 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
784 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
785
786#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
787#define QCA955X_EXT_INT_WMAC_TX BIT(1)
788#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
789#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
790#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
791#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
792#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
793#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
794#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
795#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
796#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
797#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
798#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
799#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
800#define QCA955X_EXT_INT_USB1 BIT(24)
801#define QCA955X_EXT_INT_USB2 BIT(28)
802
803#define QCA955X_EXT_INT_WMAC_ALL \
804 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
805 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
806
807#define QCA955X_EXT_INT_PCIE_RC1_ALL \
808 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
809 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
810 QCA955X_EXT_INT_PCIE_RC1_INT3)
811
812#define QCA955X_EXT_INT_PCIE_RC2_ALL \
813 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
814 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
815 QCA955X_EXT_INT_PCIE_RC2_INT3)
816
817#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
818#define QCA956X_EXT_INT_WMAC_TX BIT(1)
819#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
820#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
821#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
822#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
823#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
824#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
825#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
826#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
827#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
828#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
829#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
830#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
831#define QCA956X_EXT_INT_USB1 BIT(24)
832#define QCA956X_EXT_INT_USB2 BIT(28)
833
834#define QCA956X_EXT_INT_WMAC_ALL \
835 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
836 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
837
838#define QCA956X_EXT_INT_PCIE_RC1_ALL \
839 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
840 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
841 QCA956X_EXT_INT_PCIE_RC1_INT3)
842
843#define QCA956X_EXT_INT_PCIE_RC2_ALL \
844 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
845 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
846 QCA956X_EXT_INT_PCIE_RC2_INT3)
847
848#define REV_ID_MAJOR_MASK 0xfff0
849#define REV_ID_MAJOR_AR71XX 0x00a0
850#define REV_ID_MAJOR_AR913X 0x00b0
851#define REV_ID_MAJOR_AR7240 0x00c0
852#define REV_ID_MAJOR_AR7241 0x0100
853#define REV_ID_MAJOR_AR7242 0x1100
854#define REV_ID_MAJOR_AR9330 0x0110
855#define REV_ID_MAJOR_AR9331 0x1110
856#define REV_ID_MAJOR_AR9341 0x0120
857#define REV_ID_MAJOR_AR9342 0x1120
858#define REV_ID_MAJOR_AR9344 0x2120
859#define REV_ID_MAJOR_QCA9533 0x0140
860#define REV_ID_MAJOR_QCA9533_V2 0x0160
861#define REV_ID_MAJOR_QCA9556 0x0130
862#define REV_ID_MAJOR_QCA9558 0x1130
863#define REV_ID_MAJOR_TP9343 0x0150
864#define REV_ID_MAJOR_QCA956X 0x1150
865#define REV_ID_MAJOR_QCN550X 0x2170
866
867#define AR71XX_REV_ID_MINOR_MASK 0x3
868#define AR71XX_REV_ID_MINOR_AR7130 0x0
869#define AR71XX_REV_ID_MINOR_AR7141 0x1
870#define AR71XX_REV_ID_MINOR_AR7161 0x2
871#define AR71XX_REV_ID_REVISION_MASK 0x3
872#define AR71XX_REV_ID_REVISION_SHIFT 2
873
874#define AR913X_REV_ID_MINOR_MASK 0x3
875#define AR913X_REV_ID_MINOR_AR9130 0x0
876#define AR913X_REV_ID_MINOR_AR9132 0x1
877#define AR913X_REV_ID_REVISION_MASK 0x3
878#define AR913X_REV_ID_REVISION_SHIFT 2
879
880#define AR933X_REV_ID_REVISION_MASK 0x3
881
882#define AR724X_REV_ID_REVISION_MASK 0x3
883
884#define AR934X_REV_ID_REVISION_MASK 0xf
885
886#define QCA953X_REV_ID_REVISION_MASK 0xf
887
888#define QCA955X_REV_ID_REVISION_MASK 0xf
889
890#define QCA956X_REV_ID_REVISION_MASK 0xf
891
892/*
893 * SPI block
894 */
895#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
896#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
897#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
898#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
899
900#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
901
902#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
903#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
904
905#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
906#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
907#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
908#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
909#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
910#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
911#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
912 AR71XX_SPI_IOC_CS2)
913
914/*
915 * GPIO block
916 */
917#define AR71XX_GPIO_REG_OE 0x00
918#define AR71XX_GPIO_REG_IN 0x04
919#define AR71XX_GPIO_REG_OUT 0x08
920#define AR71XX_GPIO_REG_SET 0x0c
921#define AR71XX_GPIO_REG_CLEAR 0x10
922#define AR71XX_GPIO_REG_INT_MODE 0x14
923#define AR71XX_GPIO_REG_INT_TYPE 0x18
924#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
925#define AR71XX_GPIO_REG_INT_PENDING 0x20
926#define AR71XX_GPIO_REG_INT_ENABLE 0x24
927#define AR71XX_GPIO_REG_FUNC 0x28
928
929#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
930#define AR934X_GPIO_REG_OUT_FUNC1 0x30
931#define AR934X_GPIO_REG_OUT_FUNC2 0x34
932#define AR934X_GPIO_REG_OUT_FUNC3 0x38
933#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
934#define AR934X_GPIO_REG_OUT_FUNC5 0x40
935#define AR934X_GPIO_REG_FUNC 0x6c
936
937#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
938#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
939#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
940#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
941#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
942#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
943#define QCA953X_GPIO_REG_FUNC 0x6c
944
945#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
946#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
947#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
948#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
949#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
950#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
951#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
952#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
953#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
954#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
955
956#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
957#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
958#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
959#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
960#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
961#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
962#define QCA955X_GPIO_REG_FUNC 0x6c
963
964#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
965#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
966#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
967#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
968#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
969#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
970#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
971#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
972#define QCA956X_GPIO_REG_FUNC 0x6c
973
974#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
975#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
976
977#define AR71XX_GPIO_COUNT 16
978#define AR7240_GPIO_COUNT 18
979#define AR7241_GPIO_COUNT 20
980#define AR913X_GPIO_COUNT 22
981#define AR933X_GPIO_COUNT 30
982#define AR934X_GPIO_COUNT 23
983#define QCA953X_GPIO_COUNT 18
984#define QCA955X_GPIO_COUNT 24
985#define QCA956X_GPIO_COUNT 23
986
987/*
988 * SRIF block
989 */
990#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
991#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
992#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
993
994#define AR934X_SRIF_DDR_DPLL1_REG 0x240
995#define AR934X_SRIF_DDR_DPLL2_REG 0x244
996#define AR934X_SRIF_DDR_DPLL3_REG 0x248
997
998#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
999#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
1000#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
1001#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
1002#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1003
1004#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1005#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
1006#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
1007
1008#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
1009#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
1010#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
1011
1012#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
1013#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
1014#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
1015
1016#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
1017#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
1018#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
1019#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
1020#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1021
1022#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1023#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
1024#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
1025
1026#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
1027#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
1028#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
1029#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
1030#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
1031#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
1032#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
1033
1034#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
1035#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
1036#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1037#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1038#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
1039#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
1040#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
1041#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
1042#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
1043#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1044#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1045#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1046#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1047#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1048#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1049#define AR724X_GPIO_FUNC_UART_EN BIT(1)
1050#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1051
1052#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
1053#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
1054#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
1055#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
1056#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
1057#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
1058#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
1059#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
1060#define AR913X_GPIO_FUNC_UART_EN BIT(8)
1061#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
1062
1063#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
1064#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
1065#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
1066#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
1067#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
1068#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
1069#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
1070#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
1071#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
1072#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1073#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1074#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1075#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1076#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1077#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1078#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1079#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1080#define AR933X_GPIO_FUNC_UART_EN BIT(1)
1081#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1082
1083#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1084#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1085#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1086#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1087#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1088#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1089#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1090#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
1091#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1092
1093#define AR934X_GPIO_OUT_GPIO 0
1094#define AR934X_GPIO_OUT_SPI_CS1 7
1095#define AR934X_GPIO_OUT_LED_LINK0 41
1096#define AR934X_GPIO_OUT_LED_LINK1 42
1097#define AR934X_GPIO_OUT_LED_LINK2 43
1098#define AR934X_GPIO_OUT_LED_LINK3 44
1099#define AR934X_GPIO_OUT_LED_LINK4 45
1100#define AR934X_GPIO_OUT_EXT_LNA0 46
1101#define AR934X_GPIO_OUT_EXT_LNA1 47
1102
1103#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1104#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1105#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1106#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1107#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1108#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1109#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1110#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1111
1112#define QCA955X_GPIO_OUT_GPIO 0
1113#define QCA955X_MII_EXT_MDI 1
1114#define QCA955X_SLIC_DATA_OUT 3
1115#define QCA955X_SLIC_PCM_FS 4
1116#define QCA955X_SLIC_PCM_CLK 5
1117#define QCA955X_SPI_CLK 8
1118#define QCA955X_SPI_CS_0 9
1119#define QCA955X_SPI_CS_1 10
1120#define QCA955X_SPI_CS_2 11
1121#define QCA955X_SPI_MISO 12
1122#define QCA955X_I2S_CLK 13
1123#define QCA955X_I2S_WS 14
1124#define QCA955X_I2S_SD 15
1125#define QCA955X_I2S_MCK 16
1126#define QCA955X_SPDIF_OUT 17
1127#define QCA955X_UART1_TD 18
1128#define QCA955X_UART1_RTS 19
1129#define QCA955X_UART1_RD 20
1130#define QCA955X_UART1_CTS 21
1131#define QCA955X_UART0_SOUT 22
1132#define QCA955X_SPDIF2_OUT 23
1133#define QCA955X_LED_SGMII_SPEED0 24
1134#define QCA955X_LED_SGMII_SPEED1 25
1135#define QCA955X_LED_SGMII_DUPLEX 26
1136#define QCA955X_LED_SGMII_LINK_UP 27
1137#define QCA955X_SGMII_SPEED0_INVERT 28
1138#define QCA955X_SGMII_SPEED1_INVERT 29
1139#define QCA955X_SGMII_DUPLEX_INVERT 30
1140#define QCA955X_SGMII_LINK_UP_INVERT 31
1141#define QCA955X_GE1_MII_MDO 32
1142#define QCA955X_GE1_MII_MDC 33
1143#define QCA955X_SWCOM2 38
1144#define QCA955X_SWCOM3 39
1145#define QCA955X_MAC2_GPIO 40
1146#define QCA955X_MAC3_GPIO 41
1147#define QCA955X_ATT_LED 42
1148#define QCA955X_PWR_LED 43
1149#define QCA955X_TX_FRAME 44
1150#define QCA955X_RX_CLEAR_EXTERNAL 45
1151#define QCA955X_LED_NETWORK_EN 46
1152#define QCA955X_LED_POWER_EN 47
1153#define QCA955X_WMAC_GLUE_WOW 68
1154#define QCA955X_RX_CLEAR_EXTENSION 70
1155#define QCA955X_CP_NAND_CS1 73
1156#define QCA955X_USB_SUSPEND 74
1157#define QCA955X_ETH_TX_ERR 75
1158#define QCA955X_DDR_DQ_OE 76
1159#define QCA955X_CLKREQ_N_EP 77
1160#define QCA955X_CLKREQ_N_RC 78
1161#define QCA955X_CLK_OBS0 79
1162#define QCA955X_CLK_OBS1 80
1163#define QCA955X_CLK_OBS2 81
1164#define QCA955X_CLK_OBS3 82
1165#define QCA955X_CLK_OBS4 83
1166#define QCA955X_CLK_OBS5 84
1167
1168/*
1169 * MII_CTRL block
1170 */
1171#define AR71XX_MII_REG_MII0_CTRL 0x00
1172#define AR71XX_MII_REG_MII1_CTRL 0x04
1173
1174#define AR71XX_MII_CTRL_IF_MASK 3
1175#define AR71XX_MII_CTRL_SPEED_SHIFT 4
1176#define AR71XX_MII_CTRL_SPEED_MASK 3
1177#define AR71XX_MII_CTRL_SPEED_10 0
1178#define AR71XX_MII_CTRL_SPEED_100 1
1179#define AR71XX_MII_CTRL_SPEED_1000 2
1180
1181#define AR71XX_MII0_CTRL_IF_GMII 0
1182#define AR71XX_MII0_CTRL_IF_MII 1
1183#define AR71XX_MII0_CTRL_IF_RGMII 2
1184#define AR71XX_MII0_CTRL_IF_RMII 3
1185
1186#define AR71XX_MII1_CTRL_IF_RGMII 0
1187#define AR71XX_MII1_CTRL_IF_RMII 1
1188
1189/*
1190 * AR933X GMAC interface
1191 */
1192#define AR933X_GMAC_REG_ETH_CFG 0x00
1193
1194#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1195#define AR933X_ETH_CFG_MII_GE0 BIT(1)
1196#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
1197#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
1198#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1199#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
1200#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
1201#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
1202#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
1203#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
1204#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
1205
1206/*
1207 * AR934X GMAC Interface
1208 */
1209#define AR934X_GMAC_REG_ETH_CFG 0x00
1210
1211#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1212#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
1213#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
1214#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
1215#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
1216#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
1217#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
1218#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
1219#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
1220#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
1221#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1222#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1223#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1224#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
1225#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
1226#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
1227#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
1228#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
1229#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
1230
1231/*
1232 * QCA953X GMAC Interface
1233 */
1234#define QCA953X_GMAC_REG_ETH_CFG 0x00
1235
1236#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
1237#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
1238#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
1239#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1240
1241/*
1242 * QCA955X GMAC Interface
1243 */
1244
1245#define QCA955X_GMAC_REG_ETH_CFG 0x00
1246#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
1247
1248#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1249#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
1250#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
1251#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
1252#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1253#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
1254#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
1255#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
1256#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1257#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
1258#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
1259#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
1260#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
1261#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
1262#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
1263#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
1264#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
1265#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
1266#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
1267
1268#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1269#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1270#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1271/*
1272 * QCA956X GMAC Interface
1273 */
1274
1275#define QCA956X_GMAC_REG_ETH_CFG 0x00
1276#define QCA956X_GMAC_REG_SGMII_RESET 0x14
1277#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
1278#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
1279#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
1280#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
1281
1282#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
1283#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
1284#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
1285#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
1286#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
1287#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
1288#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1289#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
1290#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
1291#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
1292#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
1293
1294#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
1295#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
1296#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
1297#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
1298#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
1299#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
1300
1301#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
1302#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
1303#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
1304#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
1305#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
1306#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
1307#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
1308#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1309#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
1310#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
1311#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1312#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1313#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
1314#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
1315
1316#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
1317#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
1318
1319#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
1320#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
1321
1322#endif /* __ASM_MACH_AR71XX_REGS_H */