1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Board-level suspend/resume support.
  4 *
  5 * Copyright (C) 2014-2015 Marvell
  6 *
  7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  8 */
  9
 10#include <linux/delay.h>
 11#include <linux/err.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/of.h>
 16#include <linux/of_address.h>
 17#include <linux/slab.h>
 18#include "common.h"
 19
 20#define ARMADA_PIC_NR_GPIOS 3
 21
 22static void __iomem *gpio_ctrl;
 23static struct gpio_desc *pic_gpios[ARMADA_PIC_NR_GPIOS];
 24static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
 25
 26static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
 27{
 28	u32 reg, ackcmd;
 29	int i;
 30
 31	/* Put 001 as value on the GPIOs */
 32	reg = readl(gpio_ctrl);
 33	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
 34		reg &= ~BIT(pic_raw_gpios[i]);
 35	reg |= BIT(pic_raw_gpios[0]);
 36	writel(reg, gpio_ctrl);
 37
 38	/* Prepare writing 111 to the GPIOs */
 39	ackcmd = readl(gpio_ctrl);
 40	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
 41		ackcmd |= BIT(pic_raw_gpios[i]);
 42
 43	srcmd = cpu_to_le32(srcmd);
 44	ackcmd = cpu_to_le32(ackcmd);
 45
 46	/*
 47	 * Wait a while, the PIC needs quite a bit of time between the
 48	 * two GPIO commands.
 49	 */
 50	mdelay(3000);
 51
 52	asm volatile (
 53		/* Align to a cache line */
 54		".balign 32\n\t"
 55
 56		/* Enter self refresh */
 57		"str %[srcmd], [%[sdram_reg]]\n\t"
 58
 59		/*
 60		 * Wait 100 cycles for DDR to enter self refresh, by
 61		 * doing 50 times two instructions.
 62		 */
 63		"mov r1, #50\n\t"
 64		"1: subs r1, r1, #1\n\t"
 65		"bne 1b\n\t"
 66
 67		/* Issue the command ACK */
 68		"str %[ackcmd], [%[gpio_ctrl]]\n\t"
 69
 70		/* Trap the processor */
 71		"b .\n\t"
 72		: : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
 73		  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
 74}
 75
 76static int __init mvebu_armada_pm_init(void)
 77{
 78	struct device_node *np;
 79	struct device_node *gpio_ctrl_np = NULL;
 80	int ret = 0, i;
 81
 82	if (!of_machine_is_compatible("marvell,axp-gp"))
 83		return -ENODEV;
 84
 85	np = of_find_node_by_name(NULL, "pm_pic");
 86	if (!np)
 87		return -ENODEV;
 88
 89	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
 90		char *name;
 91		struct of_phandle_args args;
 92
 93		name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
 94		if (!name) {
 95			ret = -ENOMEM;
 96			goto out;
 97		}
 98
 99		pic_gpios[i] = fwnode_gpiod_get_index(of_fwnode_handle(np),
100						      "ctrl", i, GPIOD_OUT_HIGH,
101						      name);
102		ret = PTR_ERR_OR_ZERO(pic_gpios[i]);
103		if (ret) {
104			kfree(name);
105			goto out;
106		}
107
108		ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
109						       i, &args);
110		if (ret < 0) {
111			gpiod_put(pic_gpios[i]);
112			kfree(name);
113			goto out;
114		}
115
116		if (gpio_ctrl_np)
117			of_node_put(gpio_ctrl_np);
118		gpio_ctrl_np = args.np;
119		pic_raw_gpios[i] = args.args[0];
120	}
121
122	gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
123	if (!gpio_ctrl) {
124		ret = -ENOMEM;
125		goto out;
126	}
127
128	mvebu_pm_suspend_init(mvebu_armada_pm_enter);
129
130out:
131	of_node_put(np);
132	of_node_put(gpio_ctrl_np);
133	return ret;
134}
135
136/*
137 * Registering the mvebu_board_pm_enter callback must be done before
138 * the platform_suspend_ops will be registered. In the same time we
139 * also need to have the gpio devices registered. That's why we use a
140 * device_initcall_sync which is called after all the device_initcall
141 * (used by the gpio device) but before the late_initcall (used to
142 * register the platform_suspend_ops)
143 */
144device_initcall_sync(mvebu_armada_pm_init);