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1#ifndef __ALPHA_MCPCIA__H__
2#define __ALPHA_MCPCIA__H__
3
4/* Define to experiment with fitting everything into one 128MB HAE window.
5 One window per bus, that is. */
6#define MCPCIA_ONE_HAE_WINDOW 1
7
8#include <linux/types.h>
9#include <asm/compiler.h>
10
11/*
12 * MCPCIA is the internal name for a core logic chipset which provides
13 * PCI access for the RAWHIDE family of systems.
14 *
15 * This file is based on:
16 *
17 * RAWHIDE System Programmer's Manual
18 * 16-May-96
19 * Rev. 1.4
20 *
21 */
22
23/*------------------------------------------------------------------------**
24** **
25** I/O procedures **
26** **
27** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
28** inportbxt: 8 bits only **
29** inport: alias of inportw **
30** outport: alias of outportw **
31** **
32** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
33** inmembxt: 8 bits only **
34** inmem: alias of inmemw **
35** outmem: alias of outmemw **
36** **
37**------------------------------------------------------------------------*/
38
39
40/* MCPCIA ADDRESS BIT DEFINITIONS
41 *
42 * 3333 3333 3322 2222 2222 1111 1111 11
43 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
44 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
45 * 1 000
46 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
47 * | |\|
48 * | Byte Enable --+ |
49 * | Transfer Length --+
50 * +-- IO space, not cached
51 *
52 * Byte Transfer
53 * Enable Length Transfer Byte Address
54 * adr<6:5> adr<4:3> Length Enable Adder
55 * ---------------------------------------------
56 * 00 00 Byte 1110 0x000
57 * 01 00 Byte 1101 0x020
58 * 10 00 Byte 1011 0x040
59 * 11 00 Byte 0111 0x060
60 *
61 * 00 01 Word 1100 0x008
62 * 01 01 Word 1001 0x028 <= Not supported in this code.
63 * 10 01 Word 0011 0x048
64 *
65 * 00 10 Tribyte 1000 0x010
66 * 01 10 Tribyte 0001 0x030
67 *
68 * 10 11 Longword 0000 0x058
69 *
70 * Note that byte enables are asserted low.
71 *
72 */
73
74#define MCPCIA_MAX_HOSES 4
75
76#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
77
78/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
79 Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
80#define MCPCIA_HOSE2MID(h) ((h) + 4)
81
82#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
83
84/*
85 * Memory spaces:
86 */
87#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
88#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
89#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
90#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
91#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
92#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
93#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
94#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
95
96/*
97 * General Registers
98 */
99#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
100#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
101#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
102#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
103#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
104#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
105#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
106#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
107
108/*
109 * Interrupt Control registers
110 */
111#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
112#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
113#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
114#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
115#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
116#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
117#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
118#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
119#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
120
121/*
122 * Performance Monitor registers
123 */
124#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
125#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
126
127/*
128 * Diagnostic Registers
129 */
130#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
131#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
132
133/*
134 * Error registers
135 */
136#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
137#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
138#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
139#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
140#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
141#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
142#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
143#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
144#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
145#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
146
147/*
148 * PCI Address Translation Registers.
149 */
150#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
151#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
152
153#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
154#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
155#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
156
157#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
158#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
159#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
160
161#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
162#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
163#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
164
165#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
166#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
167#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
168
169/* Hack! Only words for bus 0. */
170
171#ifndef MCPCIA_ONE_HAE_WINDOW
172#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
173#endif
174#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
175
176/*
177 * The canonical non-remaped I/O and MEM addresses have these values
178 * subtracted out. This is arranged so that folks manipulating ISA
179 * devices can use their familiar numbers and have them map to bus 0.
180 */
181
182#define MCPCIA_IO_BIAS MCPCIA_IO(4)
183#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
184
185/* Offset between ram physical addresses and pci64 DAC bus addresses. */
186#define MCPCIA_DAC_OFFSET (1UL << 40)
187
188/*
189 * Data structure for handling MCPCIA machine checks:
190 */
191struct el_MCPCIA_uncorrected_frame_mcheck {
192 struct el_common header;
193 struct el_common_EV5_uncorrectable_mcheck procdata;
194};
195
196
197#ifdef __KERNEL__
198
199#ifndef __EXTERN_INLINE
200#define __EXTERN_INLINE extern inline
201#define __IO_EXTERN_INLINE
202#endif
203
204/*
205 * I/O functions:
206 *
207 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
208 * and EV56 (21164a) processors, can use either a sparse address mapping
209 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
210 * and I/O.
211 *
212 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
213 */
214
215/*
216 * Memory functions. 64-bit and 32-bit accesses are done through
217 * dense memory space, everything else through sparse space.
218 *
219 * For reading and writing 8 and 16 bit quantities we need to
220 * go through one of the three sparse address mapping regions
221 * and use the HAE_MEM CSR to provide some bits of the address.
222 * The following few routines use only sparse address region 1
223 * which gives 1Gbyte of accessible space which relates exactly
224 * to the amount of PCI memory mapping *into* system address space.
225 * See p 6-17 of the specification but it looks something like this:
226 *
227 * 21164 Address:
228 *
229 * 3 2 1
230 * 9876543210987654321098765432109876543210
231 * 1ZZZZ0.PCI.QW.Address............BBLL
232 *
233 * ZZ = SBZ
234 * BB = Byte offset
235 * LL = Transfer length
236 *
237 * PCI Address:
238 *
239 * 3 2 1
240 * 10987654321098765432109876543210
241 * HHH....PCI.QW.Address........ 00
242 *
243 * HHH = 31:29 HAE_MEM CSR
244 *
245 */
246
247#define vip volatile int __force *
248#define vuip volatile unsigned int __force *
249
250#ifndef MCPCIA_ONE_HAE_WINDOW
251#define MCPCIA_FROB_MMIO \
252 if (__mcpcia_is_mmio(hose)) { \
253 set_hae(hose & 0xffffffff); \
254 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
255 }
256#else
257#define MCPCIA_FROB_MMIO \
258 if (__mcpcia_is_mmio(hose)) { \
259 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
260 }
261#endif
262
263extern inline int __mcpcia_is_mmio(unsigned long addr)
264{
265 return (addr & 0x80000000UL) == 0;
266}
267
268__EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
269{
270 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
271 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
272 unsigned long result;
273
274 MCPCIA_FROB_MMIO;
275
276 result = *(vip) ((addr << 5) + hose + 0x00);
277 return __kernel_extbl(result, addr & 3);
278}
279
280__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
281{
282 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
283 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
284 unsigned long w;
285
286 MCPCIA_FROB_MMIO;
287
288 w = __kernel_insbl(b, addr & 3);
289 *(vuip) ((addr << 5) + hose + 0x00) = w;
290}
291
292__EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
293{
294 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
295 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
296 unsigned long result;
297
298 MCPCIA_FROB_MMIO;
299
300 result = *(vip) ((addr << 5) + hose + 0x08);
301 return __kernel_extwl(result, addr & 3);
302}
303
304__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
305{
306 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
307 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
308 unsigned long w;
309
310 MCPCIA_FROB_MMIO;
311
312 w = __kernel_inswl(b, addr & 3);
313 *(vuip) ((addr << 5) + hose + 0x08) = w;
314}
315
316__EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
317{
318 unsigned long addr = (unsigned long)xaddr;
319
320 if (!__mcpcia_is_mmio(addr))
321 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
322
323 return *(vuip)addr;
324}
325
326__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
327{
328 unsigned long addr = (unsigned long)xaddr;
329
330 if (!__mcpcia_is_mmio(addr))
331 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
332
333 *(vuip)addr = b;
334}
335
336
337__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
338{
339 return (void __iomem *)(addr + MCPCIA_IO_BIAS);
340}
341
342__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
343 unsigned long size)
344{
345 return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
346}
347
348__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
349{
350 return addr >= MCPCIA_SPARSE(0);
351}
352
353__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
354{
355 unsigned long addr = (unsigned long) xaddr;
356 return __mcpcia_is_mmio(addr);
357}
358
359#undef MCPCIA_FROB_MMIO
360
361#undef vip
362#undef vuip
363
364#undef __IO_PREFIX
365#define __IO_PREFIX mcpcia
366#define mcpcia_trivial_rw_bw 2
367#define mcpcia_trivial_rw_lq 1
368#define mcpcia_trivial_io_bw 0
369#define mcpcia_trivial_io_lq 0
370#define mcpcia_trivial_iounmap 1
371#include <asm/io_trivial.h>
372
373#ifdef __IO_EXTERN_INLINE
374#undef __EXTERN_INLINE
375#undef __IO_EXTERN_INLINE
376#endif
377
378#endif /* __KERNEL__ */
379
380#endif /* __ALPHA_MCPCIA__H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ALPHA_MCPCIA__H__
3#define __ALPHA_MCPCIA__H__
4
5/* Define to experiment with fitting everything into one 128MB HAE window.
6 One window per bus, that is. */
7#define MCPCIA_ONE_HAE_WINDOW 1
8
9#include <linux/types.h>
10#include <asm/compiler.h>
11#include <asm/mce.h>
12
13/*
14 * MCPCIA is the internal name for a core logic chipset which provides
15 * PCI access for the RAWHIDE family of systems.
16 *
17 * This file is based on:
18 *
19 * RAWHIDE System Programmer's Manual
20 * 16-May-96
21 * Rev. 1.4
22 *
23 */
24
25/*------------------------------------------------------------------------**
26** **
27** I/O procedures **
28** **
29** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
30** inportbxt: 8 bits only **
31** inport: alias of inportw **
32** outport: alias of outportw **
33** **
34** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
35** inmembxt: 8 bits only **
36** inmem: alias of inmemw **
37** outmem: alias of outmemw **
38** **
39**------------------------------------------------------------------------*/
40
41
42/* MCPCIA ADDRESS BIT DEFINITIONS
43 *
44 * 3333 3333 3322 2222 2222 1111 1111 11
45 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
46 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
47 * 1 000
48 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
49 * | |\|
50 * | Byte Enable --+ |
51 * | Transfer Length --+
52 * +-- IO space, not cached
53 *
54 * Byte Transfer
55 * Enable Length Transfer Byte Address
56 * adr<6:5> adr<4:3> Length Enable Adder
57 * ---------------------------------------------
58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
62 *
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
66 *
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
69 *
70 * 10 11 Longword 0000 0x058
71 *
72 * Note that byte enables are asserted low.
73 *
74 */
75
76#define MCPCIA_MAX_HOSES 4
77
78#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
79
80/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
81 Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
82#define MCPCIA_HOSE2MID(h) ((h) + 4)
83
84#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
85
86/*
87 * Memory spaces:
88 */
89#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
90#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
91#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
92#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
93#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
94#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
95#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
96#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
97
98/*
99 * General Registers
100 */
101#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
102#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
103#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
104#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
105#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
106#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
107#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
108#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
109
110/*
111 * Interrupt Control registers
112 */
113#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
114#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
115#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
116#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
117#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
118#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
119#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
120#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
121#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
122
123/*
124 * Performance Monitor registers
125 */
126#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
127#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
128
129/*
130 * Diagnostic Registers
131 */
132#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
133#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
134
135/*
136 * Error registers
137 */
138#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
139#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
140#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
141#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
142#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
143#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
144#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
145#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
146#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
147#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
148
149/*
150 * PCI Address Translation Registers.
151 */
152#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
153#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
154
155#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
156#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
157#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
158
159#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
160#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
161#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
162
163#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
164#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
165#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
166
167#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
168#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
169#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
170
171/* Hack! Only words for bus 0. */
172
173#ifndef MCPCIA_ONE_HAE_WINDOW
174#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
175#endif
176#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
177
178/*
179 * The canonical non-remaped I/O and MEM addresses have these values
180 * subtracted out. This is arranged so that folks manipulating ISA
181 * devices can use their familiar numbers and have them map to bus 0.
182 */
183
184#define MCPCIA_IO_BIAS MCPCIA_IO(4)
185#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
186
187/* Offset between ram physical addresses and pci64 DAC bus addresses. */
188#define MCPCIA_DAC_OFFSET (1UL << 40)
189
190/*
191 * Data structure for handling MCPCIA machine checks:
192 */
193struct el_MCPCIA_uncorrected_frame_mcheck {
194 struct el_common header;
195 struct el_common_EV5_uncorrectable_mcheck procdata;
196};
197
198
199#ifdef __KERNEL__
200
201#ifndef __EXTERN_INLINE
202#define __EXTERN_INLINE extern inline
203#define __IO_EXTERN_INLINE
204#endif
205
206/*
207 * I/O functions:
208 *
209 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
210 * and EV56 (21164a) processors, can use either a sparse address mapping
211 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
212 * and I/O.
213 *
214 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
215 */
216
217/*
218 * Memory functions. 64-bit and 32-bit accesses are done through
219 * dense memory space, everything else through sparse space.
220 *
221 * For reading and writing 8 and 16 bit quantities we need to
222 * go through one of the three sparse address mapping regions
223 * and use the HAE_MEM CSR to provide some bits of the address.
224 * The following few routines use only sparse address region 1
225 * which gives 1Gbyte of accessible space which relates exactly
226 * to the amount of PCI memory mapping *into* system address space.
227 * See p 6-17 of the specification but it looks something like this:
228 *
229 * 21164 Address:
230 *
231 * 3 2 1
232 * 9876543210987654321098765432109876543210
233 * 1ZZZZ0.PCI.QW.Address............BBLL
234 *
235 * ZZ = SBZ
236 * BB = Byte offset
237 * LL = Transfer length
238 *
239 * PCI Address:
240 *
241 * 3 2 1
242 * 10987654321098765432109876543210
243 * HHH....PCI.QW.Address........ 00
244 *
245 * HHH = 31:29 HAE_MEM CSR
246 *
247 */
248
249#define vip volatile int __force *
250#define vuip volatile unsigned int __force *
251#define vulp volatile unsigned long __force *
252
253#ifndef MCPCIA_ONE_HAE_WINDOW
254#define MCPCIA_FROB_MMIO \
255 if (__mcpcia_is_mmio(hose)) { \
256 set_hae(hose & 0xffffffff); \
257 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
258 }
259#else
260#define MCPCIA_FROB_MMIO \
261 if (__mcpcia_is_mmio(hose)) { \
262 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
263 }
264#endif
265
266extern inline int __mcpcia_is_mmio(unsigned long addr)
267{
268 return (addr & 0x80000000UL) == 0;
269}
270
271__EXTERN_INLINE u8 mcpcia_ioread8(const void __iomem *xaddr)
272{
273 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
274 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
275 unsigned long result;
276
277 MCPCIA_FROB_MMIO;
278
279 result = *(vip) ((addr << 5) + hose + 0x00);
280 return __kernel_extbl(result, addr & 3);
281}
282
283__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
284{
285 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
286 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
287 unsigned long w;
288
289 MCPCIA_FROB_MMIO;
290
291 w = __kernel_insbl(b, addr & 3);
292 *(vuip) ((addr << 5) + hose + 0x00) = w;
293}
294
295__EXTERN_INLINE u16 mcpcia_ioread16(const void __iomem *xaddr)
296{
297 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
298 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
299 unsigned long result;
300
301 MCPCIA_FROB_MMIO;
302
303 result = *(vip) ((addr << 5) + hose + 0x08);
304 return __kernel_extwl(result, addr & 3);
305}
306
307__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
308{
309 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
310 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
311 unsigned long w;
312
313 MCPCIA_FROB_MMIO;
314
315 w = __kernel_inswl(b, addr & 3);
316 *(vuip) ((addr << 5) + hose + 0x08) = w;
317}
318
319__EXTERN_INLINE u32 mcpcia_ioread32(const void __iomem *xaddr)
320{
321 unsigned long addr = (unsigned long)xaddr;
322
323 if (!__mcpcia_is_mmio(addr))
324 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
325
326 return *(vuip)addr;
327}
328
329__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
330{
331 unsigned long addr = (unsigned long)xaddr;
332
333 if (!__mcpcia_is_mmio(addr))
334 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
335
336 *(vuip)addr = b;
337}
338
339__EXTERN_INLINE u64 mcpcia_ioread64(const void __iomem *xaddr)
340{
341 unsigned long addr = (unsigned long)xaddr;
342
343 if (!__mcpcia_is_mmio(addr))
344 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
345
346 return *(vulp)addr;
347}
348
349__EXTERN_INLINE void mcpcia_iowrite64(u64 b, void __iomem *xaddr)
350{
351 unsigned long addr = (unsigned long)xaddr;
352
353 if (!__mcpcia_is_mmio(addr))
354 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
355
356 *(vulp)addr = b;
357}
358
359
360__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
361{
362 return (void __iomem *)(addr + MCPCIA_IO_BIAS);
363}
364
365__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
366 unsigned long size)
367{
368 return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
369}
370
371__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
372{
373 return addr >= MCPCIA_SPARSE(0);
374}
375
376__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
377{
378 unsigned long addr = (unsigned long) xaddr;
379 return __mcpcia_is_mmio(addr);
380}
381
382#undef MCPCIA_FROB_MMIO
383
384#undef vip
385#undef vuip
386#undef vulp
387
388#undef __IO_PREFIX
389#define __IO_PREFIX mcpcia
390#define mcpcia_trivial_rw_bw 2
391#define mcpcia_trivial_rw_lq 1
392#define mcpcia_trivial_io_bw 0
393#define mcpcia_trivial_io_lq 0
394#define mcpcia_trivial_iounmap 1
395#include <asm/io_trivial.h>
396
397#ifdef __IO_EXTERN_INLINE
398#undef __EXTERN_INLINE
399#undef __IO_EXTERN_INLINE
400#endif
401
402#endif /* __KERNEL__ */
403
404#endif /* __ALPHA_MCPCIA__H__ */