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1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
5 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
6 *
7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
18 * www.moxa.com.
19 * - Fixed x86_64 cleanness
20 */
21
22#include <linux/module.h>
23#include <linux/errno.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/timer.h>
27#include <linux/interrupt.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_reg.h>
32#include <linux/major.h>
33#include <linux/string.h>
34#include <linux/fcntl.h>
35#include <linux/ptrace.h>
36#include <linux/ioport.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39#include <linux/pci.h>
40#include <linux/bitops.h>
41#include <linux/slab.h>
42#include <linux/ratelimit.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/uaccess.h>
48
49#include "mxser.h"
50
51#define MXSER_VERSION "2.0.5" /* 1.14 */
52#define MXSERMAJOR 174
53
54#define MXSER_BOARDS 4 /* Max. boards */
55#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
56#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
57#define MXSER_ISR_PASS_LIMIT 100
58
59/*CheckIsMoxaMust return value*/
60#define MOXA_OTHER_UART 0x00
61#define MOXA_MUST_MU150_HWID 0x01
62#define MOXA_MUST_MU860_HWID 0x02
63
64#define WAKEUP_CHARS 256
65
66#define UART_MCR_AFE 0x20
67#define UART_LSR_SPECIAL 0x1E
68
69#define PCI_DEVICE_ID_POS104UL 0x1044
70#define PCI_DEVICE_ID_CB108 0x1080
71#define PCI_DEVICE_ID_CP102UF 0x1023
72#define PCI_DEVICE_ID_CP112UL 0x1120
73#define PCI_DEVICE_ID_CB114 0x1142
74#define PCI_DEVICE_ID_CP114UL 0x1143
75#define PCI_DEVICE_ID_CB134I 0x1341
76#define PCI_DEVICE_ID_CP138U 0x1380
77
78
79#define C168_ASIC_ID 1
80#define C104_ASIC_ID 2
81#define C102_ASIC_ID 0xB
82#define CI132_ASIC_ID 4
83#define CI134_ASIC_ID 3
84#define CI104J_ASIC_ID 5
85
86#define MXSER_HIGHBAUD 1
87#define MXSER_HAS2 2
88
89/* This is only for PCI */
90static const struct {
91 int type;
92 int tx_fifo;
93 int rx_fifo;
94 int xmit_fifo_size;
95 int rx_high_water;
96 int rx_trigger;
97 int rx_low_water;
98 long max_baud;
99} Gpci_uart_info[] = {
100 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
101 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
102 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
103};
104#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
105
106struct mxser_cardinfo {
107 char *name;
108 unsigned int nports;
109 unsigned int flags;
110};
111
112static const struct mxser_cardinfo mxser_cards[] = {
113/* 0*/ { "C168 series", 8, },
114 { "C104 series", 4, },
115 { "CI-104J series", 4, },
116 { "C168H/PCI series", 8, },
117 { "C104H/PCI series", 4, },
118/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
119 { "CI-132 series", 4, MXSER_HAS2 },
120 { "CI-134 series", 4, },
121 { "CP-132 series", 2, },
122 { "CP-114 series", 4, },
123/*10*/ { "CT-114 series", 4, },
124 { "CP-102 series", 2, MXSER_HIGHBAUD },
125 { "CP-104U series", 4, },
126 { "CP-168U series", 8, },
127 { "CP-132U series", 2, },
128/*15*/ { "CP-134U series", 4, },
129 { "CP-104JU series", 4, },
130 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
131 { "CP-118U series", 8, },
132 { "CP-102UL series", 2, },
133/*20*/ { "CP-102U series", 2, },
134 { "CP-118EL series", 8, },
135 { "CP-168EL series", 8, },
136 { "CP-104EL series", 4, },
137 { "CB-108 series", 8, },
138/*25*/ { "CB-114 series", 4, },
139 { "CB-134I series", 4, },
140 { "CP-138U series", 8, },
141 { "POS-104UL series", 4, },
142 { "CP-114UL series", 4, },
143/*30*/ { "CP-102UF series", 2, },
144 { "CP-112UL series", 2, },
145};
146
147/* driver_data correspond to the lines in the structure above
148 see also ISA probe function before you change something */
149static struct pci_device_id mxser_pcibrds[] = {
150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
172 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
173 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
174 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
175 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 31 },
176 { }
177};
178MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
179
180static unsigned long ioaddr[MXSER_BOARDS];
181static int ttymajor = MXSERMAJOR;
182
183/* Variables for insmod */
184
185MODULE_AUTHOR("Casper Yang");
186MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
187module_param_array(ioaddr, ulong, NULL, 0);
188MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
189module_param(ttymajor, int, 0);
190MODULE_LICENSE("GPL");
191
192struct mxser_log {
193 int tick;
194 unsigned long rxcnt[MXSER_PORTS];
195 unsigned long txcnt[MXSER_PORTS];
196};
197
198struct mxser_mon {
199 unsigned long rxcnt;
200 unsigned long txcnt;
201 unsigned long up_rxcnt;
202 unsigned long up_txcnt;
203 int modem_status;
204 unsigned char hold_reason;
205};
206
207struct mxser_mon_ext {
208 unsigned long rx_cnt[32];
209 unsigned long tx_cnt[32];
210 unsigned long up_rxcnt[32];
211 unsigned long up_txcnt[32];
212 int modem_status[32];
213
214 long baudrate[32];
215 int databits[32];
216 int stopbits[32];
217 int parity[32];
218 int flowctrl[32];
219 int fifo[32];
220 int iftype[32];
221};
222
223struct mxser_board;
224
225struct mxser_port {
226 struct tty_port port;
227 struct mxser_board *board;
228
229 unsigned long ioaddr;
230 unsigned long opmode_ioaddr;
231 int max_baud;
232
233 int rx_high_water;
234 int rx_trigger; /* Rx fifo trigger level */
235 int rx_low_water;
236 int baud_base; /* max. speed */
237 int type; /* UART type */
238
239 int x_char; /* xon/xoff character */
240 int IER; /* Interrupt Enable Register */
241 int MCR; /* Modem control register */
242
243 unsigned char stop_rx;
244 unsigned char ldisc_stop_rx;
245
246 int custom_divisor;
247 unsigned char err_shadow;
248
249 struct async_icount icount; /* kernel counters for 4 input interrupts */
250 int timeout;
251
252 int read_status_mask;
253 int ignore_status_mask;
254 int xmit_fifo_size;
255 int xmit_head;
256 int xmit_tail;
257 int xmit_cnt;
258
259 struct ktermios normal_termios;
260
261 struct mxser_mon mon_data;
262
263 spinlock_t slock;
264};
265
266struct mxser_board {
267 unsigned int idx;
268 int irq;
269 const struct mxser_cardinfo *info;
270 unsigned long vector;
271 unsigned long vector_mask;
272
273 int chip_flag;
274 int uart_type;
275
276 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
277};
278
279struct mxser_mstatus {
280 tcflag_t cflag;
281 int cts;
282 int dsr;
283 int ri;
284 int dcd;
285};
286
287static struct mxser_board mxser_boards[MXSER_BOARDS];
288static struct tty_driver *mxvar_sdriver;
289static struct mxser_log mxvar_log;
290static int mxser_set_baud_method[MXSER_PORTS + 1];
291
292static void mxser_enable_must_enchance_mode(unsigned long baseio)
293{
294 u8 oldlcr;
295 u8 efr;
296
297 oldlcr = inb(baseio + UART_LCR);
298 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
299
300 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
301 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
302
303 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
304 outb(oldlcr, baseio + UART_LCR);
305}
306
307#ifdef CONFIG_PCI
308static void mxser_disable_must_enchance_mode(unsigned long baseio)
309{
310 u8 oldlcr;
311 u8 efr;
312
313 oldlcr = inb(baseio + UART_LCR);
314 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
315
316 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
317 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
318
319 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
320 outb(oldlcr, baseio + UART_LCR);
321}
322#endif
323
324static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
325{
326 u8 oldlcr;
327 u8 efr;
328
329 oldlcr = inb(baseio + UART_LCR);
330 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
331
332 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
333 efr &= ~MOXA_MUST_EFR_BANK_MASK;
334 efr |= MOXA_MUST_EFR_BANK0;
335
336 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
337 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
338 outb(oldlcr, baseio + UART_LCR);
339}
340
341static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
342{
343 u8 oldlcr;
344 u8 efr;
345
346 oldlcr = inb(baseio + UART_LCR);
347 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
348
349 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
350 efr &= ~MOXA_MUST_EFR_BANK_MASK;
351 efr |= MOXA_MUST_EFR_BANK0;
352
353 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
354 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
355 outb(oldlcr, baseio + UART_LCR);
356}
357
358static void mxser_set_must_fifo_value(struct mxser_port *info)
359{
360 u8 oldlcr;
361 u8 efr;
362
363 oldlcr = inb(info->ioaddr + UART_LCR);
364 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
365
366 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
367 efr &= ~MOXA_MUST_EFR_BANK_MASK;
368 efr |= MOXA_MUST_EFR_BANK1;
369
370 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
371 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
372 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
373 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
374 outb(oldlcr, info->ioaddr + UART_LCR);
375}
376
377static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
378{
379 u8 oldlcr;
380 u8 efr;
381
382 oldlcr = inb(baseio + UART_LCR);
383 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
384
385 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
386 efr &= ~MOXA_MUST_EFR_BANK_MASK;
387 efr |= MOXA_MUST_EFR_BANK2;
388
389 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
390 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
391 outb(oldlcr, baseio + UART_LCR);
392}
393
394#ifdef CONFIG_PCI
395static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
396{
397 u8 oldlcr;
398 u8 efr;
399
400 oldlcr = inb(baseio + UART_LCR);
401 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
402
403 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
404 efr &= ~MOXA_MUST_EFR_BANK_MASK;
405 efr |= MOXA_MUST_EFR_BANK2;
406
407 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
408 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
409 outb(oldlcr, baseio + UART_LCR);
410}
411#endif
412
413static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
414{
415 u8 oldlcr;
416 u8 efr;
417
418 oldlcr = inb(baseio + UART_LCR);
419 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
420
421 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
422 efr &= ~MOXA_MUST_EFR_SF_MASK;
423
424 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
425 outb(oldlcr, baseio + UART_LCR);
426}
427
428static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
429{
430 u8 oldlcr;
431 u8 efr;
432
433 oldlcr = inb(baseio + UART_LCR);
434 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
435
436 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
437 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
438 efr |= MOXA_MUST_EFR_SF_TX1;
439
440 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
441 outb(oldlcr, baseio + UART_LCR);
442}
443
444static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
445{
446 u8 oldlcr;
447 u8 efr;
448
449 oldlcr = inb(baseio + UART_LCR);
450 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
451
452 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
453 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
454
455 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
456 outb(oldlcr, baseio + UART_LCR);
457}
458
459static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
460{
461 u8 oldlcr;
462 u8 efr;
463
464 oldlcr = inb(baseio + UART_LCR);
465 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
466
467 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
468 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
469 efr |= MOXA_MUST_EFR_SF_RX1;
470
471 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
472 outb(oldlcr, baseio + UART_LCR);
473}
474
475static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
476{
477 u8 oldlcr;
478 u8 efr;
479
480 oldlcr = inb(baseio + UART_LCR);
481 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
482
483 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
484 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
485
486 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
487 outb(oldlcr, baseio + UART_LCR);
488}
489
490#ifdef CONFIG_PCI
491static int __devinit CheckIsMoxaMust(unsigned long io)
492{
493 u8 oldmcr, hwid;
494 int i;
495
496 outb(0, io + UART_LCR);
497 mxser_disable_must_enchance_mode(io);
498 oldmcr = inb(io + UART_MCR);
499 outb(0, io + UART_MCR);
500 mxser_set_must_xon1_value(io, 0x11);
501 if ((hwid = inb(io + UART_MCR)) != 0) {
502 outb(oldmcr, io + UART_MCR);
503 return MOXA_OTHER_UART;
504 }
505
506 mxser_get_must_hardware_id(io, &hwid);
507 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
508 if (hwid == Gpci_uart_info[i].type)
509 return (int)hwid;
510 }
511 return MOXA_OTHER_UART;
512}
513#endif
514
515static void process_txrx_fifo(struct mxser_port *info)
516{
517 int i;
518
519 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
520 info->rx_trigger = 1;
521 info->rx_high_water = 1;
522 info->rx_low_water = 1;
523 info->xmit_fifo_size = 1;
524 } else
525 for (i = 0; i < UART_INFO_NUM; i++)
526 if (info->board->chip_flag == Gpci_uart_info[i].type) {
527 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
528 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
529 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
530 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
531 break;
532 }
533}
534
535static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
536{
537 static unsigned char mxser_msr[MXSER_PORTS + 1];
538 unsigned char status = 0;
539
540 status = inb(baseaddr + UART_MSR);
541
542 mxser_msr[port] &= 0x0F;
543 mxser_msr[port] |= status;
544 status = mxser_msr[port];
545 if (mode)
546 mxser_msr[port] = 0;
547
548 return status;
549}
550
551static int mxser_carrier_raised(struct tty_port *port)
552{
553 struct mxser_port *mp = container_of(port, struct mxser_port, port);
554 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
555}
556
557static void mxser_dtr_rts(struct tty_port *port, int on)
558{
559 struct mxser_port *mp = container_of(port, struct mxser_port, port);
560 unsigned long flags;
561
562 spin_lock_irqsave(&mp->slock, flags);
563 if (on)
564 outb(inb(mp->ioaddr + UART_MCR) |
565 UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
566 else
567 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
568 mp->ioaddr + UART_MCR);
569 spin_unlock_irqrestore(&mp->slock, flags);
570}
571
572static int mxser_set_baud(struct tty_struct *tty, long newspd)
573{
574 struct mxser_port *info = tty->driver_data;
575 int quot = 0, baud;
576 unsigned char cval;
577
578 if (!info->ioaddr)
579 return -1;
580
581 if (newspd > info->max_baud)
582 return -1;
583
584 if (newspd == 134) {
585 quot = 2 * info->baud_base / 269;
586 tty_encode_baud_rate(tty, 134, 134);
587 } else if (newspd) {
588 quot = info->baud_base / newspd;
589 if (quot == 0)
590 quot = 1;
591 baud = info->baud_base/quot;
592 tty_encode_baud_rate(tty, baud, baud);
593 } else {
594 quot = 0;
595 }
596
597 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
598 info->timeout += HZ / 50; /* Add .02 seconds of slop */
599
600 if (quot) {
601 info->MCR |= UART_MCR_DTR;
602 outb(info->MCR, info->ioaddr + UART_MCR);
603 } else {
604 info->MCR &= ~UART_MCR_DTR;
605 outb(info->MCR, info->ioaddr + UART_MCR);
606 return 0;
607 }
608
609 cval = inb(info->ioaddr + UART_LCR);
610
611 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
612
613 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
614 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
615 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
616
617#ifdef BOTHER
618 if (C_BAUD(tty) == BOTHER) {
619 quot = info->baud_base % newspd;
620 quot *= 8;
621 if (quot % newspd > newspd / 2) {
622 quot /= newspd;
623 quot++;
624 } else
625 quot /= newspd;
626
627 mxser_set_must_enum_value(info->ioaddr, quot);
628 } else
629#endif
630 mxser_set_must_enum_value(info->ioaddr, 0);
631
632 return 0;
633}
634
635/*
636 * This routine is called to set the UART divisor registers to match
637 * the specified baud rate for a serial port.
638 */
639static int mxser_change_speed(struct tty_struct *tty,
640 struct ktermios *old_termios)
641{
642 struct mxser_port *info = tty->driver_data;
643 unsigned cflag, cval, fcr;
644 int ret = 0;
645 unsigned char status;
646
647 cflag = tty->termios->c_cflag;
648 if (!info->ioaddr)
649 return ret;
650
651 if (mxser_set_baud_method[tty->index] == 0)
652 mxser_set_baud(tty, tty_get_baud_rate(tty));
653
654 /* byte size and parity */
655 switch (cflag & CSIZE) {
656 case CS5:
657 cval = 0x00;
658 break;
659 case CS6:
660 cval = 0x01;
661 break;
662 case CS7:
663 cval = 0x02;
664 break;
665 case CS8:
666 cval = 0x03;
667 break;
668 default:
669 cval = 0x00;
670 break; /* too keep GCC shut... */
671 }
672 if (cflag & CSTOPB)
673 cval |= 0x04;
674 if (cflag & PARENB)
675 cval |= UART_LCR_PARITY;
676 if (!(cflag & PARODD))
677 cval |= UART_LCR_EPAR;
678 if (cflag & CMSPAR)
679 cval |= UART_LCR_SPAR;
680
681 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
682 if (info->board->chip_flag) {
683 fcr = UART_FCR_ENABLE_FIFO;
684 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
685 mxser_set_must_fifo_value(info);
686 } else
687 fcr = 0;
688 } else {
689 fcr = UART_FCR_ENABLE_FIFO;
690 if (info->board->chip_flag) {
691 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
692 mxser_set_must_fifo_value(info);
693 } else {
694 switch (info->rx_trigger) {
695 case 1:
696 fcr |= UART_FCR_TRIGGER_1;
697 break;
698 case 4:
699 fcr |= UART_FCR_TRIGGER_4;
700 break;
701 case 8:
702 fcr |= UART_FCR_TRIGGER_8;
703 break;
704 default:
705 fcr |= UART_FCR_TRIGGER_14;
706 break;
707 }
708 }
709 }
710
711 /* CTS flow control flag and modem status interrupts */
712 info->IER &= ~UART_IER_MSI;
713 info->MCR &= ~UART_MCR_AFE;
714 if (cflag & CRTSCTS) {
715 info->port.flags |= ASYNC_CTS_FLOW;
716 info->IER |= UART_IER_MSI;
717 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
718 info->MCR |= UART_MCR_AFE;
719 } else {
720 status = inb(info->ioaddr + UART_MSR);
721 if (tty->hw_stopped) {
722 if (status & UART_MSR_CTS) {
723 tty->hw_stopped = 0;
724 if (info->type != PORT_16550A &&
725 !info->board->chip_flag) {
726 outb(info->IER & ~UART_IER_THRI,
727 info->ioaddr +
728 UART_IER);
729 info->IER |= UART_IER_THRI;
730 outb(info->IER, info->ioaddr +
731 UART_IER);
732 }
733 tty_wakeup(tty);
734 }
735 } else {
736 if (!(status & UART_MSR_CTS)) {
737 tty->hw_stopped = 1;
738 if ((info->type != PORT_16550A) &&
739 (!info->board->chip_flag)) {
740 info->IER &= ~UART_IER_THRI;
741 outb(info->IER, info->ioaddr +
742 UART_IER);
743 }
744 }
745 }
746 }
747 } else {
748 info->port.flags &= ~ASYNC_CTS_FLOW;
749 }
750 outb(info->MCR, info->ioaddr + UART_MCR);
751 if (cflag & CLOCAL) {
752 info->port.flags &= ~ASYNC_CHECK_CD;
753 } else {
754 info->port.flags |= ASYNC_CHECK_CD;
755 info->IER |= UART_IER_MSI;
756 }
757 outb(info->IER, info->ioaddr + UART_IER);
758
759 /*
760 * Set up parity check flag
761 */
762 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
763 if (I_INPCK(tty))
764 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
765 if (I_BRKINT(tty) || I_PARMRK(tty))
766 info->read_status_mask |= UART_LSR_BI;
767
768 info->ignore_status_mask = 0;
769
770 if (I_IGNBRK(tty)) {
771 info->ignore_status_mask |= UART_LSR_BI;
772 info->read_status_mask |= UART_LSR_BI;
773 /*
774 * If we're ignore parity and break indicators, ignore
775 * overruns too. (For real raw support).
776 */
777 if (I_IGNPAR(tty)) {
778 info->ignore_status_mask |=
779 UART_LSR_OE |
780 UART_LSR_PE |
781 UART_LSR_FE;
782 info->read_status_mask |=
783 UART_LSR_OE |
784 UART_LSR_PE |
785 UART_LSR_FE;
786 }
787 }
788 if (info->board->chip_flag) {
789 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
790 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
791 if (I_IXON(tty)) {
792 mxser_enable_must_rx_software_flow_control(
793 info->ioaddr);
794 } else {
795 mxser_disable_must_rx_software_flow_control(
796 info->ioaddr);
797 }
798 if (I_IXOFF(tty)) {
799 mxser_enable_must_tx_software_flow_control(
800 info->ioaddr);
801 } else {
802 mxser_disable_must_tx_software_flow_control(
803 info->ioaddr);
804 }
805 }
806
807
808 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
809 outb(cval, info->ioaddr + UART_LCR);
810
811 return ret;
812}
813
814static void mxser_check_modem_status(struct tty_struct *tty,
815 struct mxser_port *port, int status)
816{
817 /* update input line counters */
818 if (status & UART_MSR_TERI)
819 port->icount.rng++;
820 if (status & UART_MSR_DDSR)
821 port->icount.dsr++;
822 if (status & UART_MSR_DDCD)
823 port->icount.dcd++;
824 if (status & UART_MSR_DCTS)
825 port->icount.cts++;
826 port->mon_data.modem_status = status;
827 wake_up_interruptible(&port->port.delta_msr_wait);
828
829 if ((port->port.flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
830 if (status & UART_MSR_DCD)
831 wake_up_interruptible(&port->port.open_wait);
832 }
833
834 if (port->port.flags & ASYNC_CTS_FLOW) {
835 if (tty->hw_stopped) {
836 if (status & UART_MSR_CTS) {
837 tty->hw_stopped = 0;
838
839 if ((port->type != PORT_16550A) &&
840 (!port->board->chip_flag)) {
841 outb(port->IER & ~UART_IER_THRI,
842 port->ioaddr + UART_IER);
843 port->IER |= UART_IER_THRI;
844 outb(port->IER, port->ioaddr +
845 UART_IER);
846 }
847 tty_wakeup(tty);
848 }
849 } else {
850 if (!(status & UART_MSR_CTS)) {
851 tty->hw_stopped = 1;
852 if (port->type != PORT_16550A &&
853 !port->board->chip_flag) {
854 port->IER &= ~UART_IER_THRI;
855 outb(port->IER, port->ioaddr +
856 UART_IER);
857 }
858 }
859 }
860 }
861}
862
863static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
864{
865 struct mxser_port *info = container_of(port, struct mxser_port, port);
866 unsigned long page;
867 unsigned long flags;
868
869 page = __get_free_page(GFP_KERNEL);
870 if (!page)
871 return -ENOMEM;
872
873 spin_lock_irqsave(&info->slock, flags);
874
875 if (!info->ioaddr || !info->type) {
876 set_bit(TTY_IO_ERROR, &tty->flags);
877 free_page(page);
878 spin_unlock_irqrestore(&info->slock, flags);
879 return 0;
880 }
881 info->port.xmit_buf = (unsigned char *) page;
882
883 /*
884 * Clear the FIFO buffers and disable them
885 * (they will be reenabled in mxser_change_speed())
886 */
887 if (info->board->chip_flag)
888 outb((UART_FCR_CLEAR_RCVR |
889 UART_FCR_CLEAR_XMIT |
890 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
891 else
892 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
893 info->ioaddr + UART_FCR);
894
895 /*
896 * At this point there's no way the LSR could still be 0xFF;
897 * if it is, then bail out, because there's likely no UART
898 * here.
899 */
900 if (inb(info->ioaddr + UART_LSR) == 0xff) {
901 spin_unlock_irqrestore(&info->slock, flags);
902 if (capable(CAP_SYS_ADMIN)) {
903 set_bit(TTY_IO_ERROR, &tty->flags);
904 return 0;
905 } else
906 return -ENODEV;
907 }
908
909 /*
910 * Clear the interrupt registers.
911 */
912 (void) inb(info->ioaddr + UART_LSR);
913 (void) inb(info->ioaddr + UART_RX);
914 (void) inb(info->ioaddr + UART_IIR);
915 (void) inb(info->ioaddr + UART_MSR);
916
917 /*
918 * Now, initialize the UART
919 */
920 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
921 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
922 outb(info->MCR, info->ioaddr + UART_MCR);
923
924 /*
925 * Finally, enable interrupts
926 */
927 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
928
929 if (info->board->chip_flag)
930 info->IER |= MOXA_MUST_IER_EGDAI;
931 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
932
933 /*
934 * And clear the interrupt registers again for luck.
935 */
936 (void) inb(info->ioaddr + UART_LSR);
937 (void) inb(info->ioaddr + UART_RX);
938 (void) inb(info->ioaddr + UART_IIR);
939 (void) inb(info->ioaddr + UART_MSR);
940
941 clear_bit(TTY_IO_ERROR, &tty->flags);
942 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
943
944 /*
945 * and set the speed of the serial port
946 */
947 mxser_change_speed(tty, NULL);
948 spin_unlock_irqrestore(&info->slock, flags);
949
950 return 0;
951}
952
953/*
954 * This routine will shutdown a serial port
955 */
956static void mxser_shutdown_port(struct tty_port *port)
957{
958 struct mxser_port *info = container_of(port, struct mxser_port, port);
959 unsigned long flags;
960
961 spin_lock_irqsave(&info->slock, flags);
962
963 /*
964 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
965 * here so the queue might never be waken up
966 */
967 wake_up_interruptible(&info->port.delta_msr_wait);
968
969 /*
970 * Free the xmit buffer, if necessary
971 */
972 if (info->port.xmit_buf) {
973 free_page((unsigned long) info->port.xmit_buf);
974 info->port.xmit_buf = NULL;
975 }
976
977 info->IER = 0;
978 outb(0x00, info->ioaddr + UART_IER);
979
980 /* clear Rx/Tx FIFO's */
981 if (info->board->chip_flag)
982 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
983 MOXA_MUST_FCR_GDA_MODE_ENABLE,
984 info->ioaddr + UART_FCR);
985 else
986 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
987 info->ioaddr + UART_FCR);
988
989 /* read data port to reset things */
990 (void) inb(info->ioaddr + UART_RX);
991
992
993 if (info->board->chip_flag)
994 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
995
996 spin_unlock_irqrestore(&info->slock, flags);
997}
998
999/*
1000 * This routine is called whenever a serial port is opened. It
1001 * enables interrupts for a serial port, linking in its async structure into
1002 * the IRQ chain. It also performs the serial-specific
1003 * initialization for the tty structure.
1004 */
1005static int mxser_open(struct tty_struct *tty, struct file *filp)
1006{
1007 struct mxser_port *info;
1008 int line;
1009
1010 line = tty->index;
1011 if (line == MXSER_PORTS)
1012 return 0;
1013 if (line < 0 || line > MXSER_PORTS)
1014 return -ENODEV;
1015 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1016 if (!info->ioaddr)
1017 return -ENODEV;
1018
1019 tty->driver_data = info;
1020 return tty_port_open(&info->port, tty, filp);
1021}
1022
1023static void mxser_flush_buffer(struct tty_struct *tty)
1024{
1025 struct mxser_port *info = tty->driver_data;
1026 char fcr;
1027 unsigned long flags;
1028
1029
1030 spin_lock_irqsave(&info->slock, flags);
1031 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1032
1033 fcr = inb(info->ioaddr + UART_FCR);
1034 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1035 info->ioaddr + UART_FCR);
1036 outb(fcr, info->ioaddr + UART_FCR);
1037
1038 spin_unlock_irqrestore(&info->slock, flags);
1039
1040 tty_wakeup(tty);
1041}
1042
1043
1044static void mxser_close_port(struct tty_port *port)
1045{
1046 struct mxser_port *info = container_of(port, struct mxser_port, port);
1047 unsigned long timeout;
1048 /*
1049 * At this point we stop accepting input. To do this, we
1050 * disable the receive line status interrupts, and tell the
1051 * interrupt driver to stop checking the data ready bit in the
1052 * line status register.
1053 */
1054 info->IER &= ~UART_IER_RLSI;
1055 if (info->board->chip_flag)
1056 info->IER &= ~MOXA_MUST_RECV_ISR;
1057
1058 outb(info->IER, info->ioaddr + UART_IER);
1059 /*
1060 * Before we drop DTR, make sure the UART transmitter
1061 * has completely drained; this is especially
1062 * important if there is a transmit FIFO!
1063 */
1064 timeout = jiffies + HZ;
1065 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1066 schedule_timeout_interruptible(5);
1067 if (time_after(jiffies, timeout))
1068 break;
1069 }
1070}
1071
1072/*
1073 * This routine is called when the serial port gets closed. First, we
1074 * wait for the last remaining data to be sent. Then, we unlink its
1075 * async structure from the interrupt chain if necessary, and we free
1076 * that IRQ if nothing is left in the chain.
1077 */
1078static void mxser_close(struct tty_struct *tty, struct file *filp)
1079{
1080 struct mxser_port *info = tty->driver_data;
1081 struct tty_port *port = &info->port;
1082
1083 if (tty->index == MXSER_PORTS || info == NULL)
1084 return;
1085 if (tty_port_close_start(port, tty, filp) == 0)
1086 return;
1087 mutex_lock(&port->mutex);
1088 mxser_close_port(port);
1089 mxser_flush_buffer(tty);
1090 mxser_shutdown_port(port);
1091 clear_bit(ASYNCB_INITIALIZED, &port->flags);
1092 mutex_unlock(&port->mutex);
1093 /* Right now the tty_port set is done outside of the close_end helper
1094 as we don't yet have everyone using refcounts */
1095 tty_port_close_end(port, tty);
1096 tty_port_tty_set(port, NULL);
1097}
1098
1099static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1100{
1101 int c, total = 0;
1102 struct mxser_port *info = tty->driver_data;
1103 unsigned long flags;
1104
1105 if (!info->port.xmit_buf)
1106 return 0;
1107
1108 while (1) {
1109 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1110 SERIAL_XMIT_SIZE - info->xmit_head));
1111 if (c <= 0)
1112 break;
1113
1114 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1115 spin_lock_irqsave(&info->slock, flags);
1116 info->xmit_head = (info->xmit_head + c) &
1117 (SERIAL_XMIT_SIZE - 1);
1118 info->xmit_cnt += c;
1119 spin_unlock_irqrestore(&info->slock, flags);
1120
1121 buf += c;
1122 count -= c;
1123 total += c;
1124 }
1125
1126 if (info->xmit_cnt && !tty->stopped) {
1127 if (!tty->hw_stopped ||
1128 (info->type == PORT_16550A) ||
1129 (info->board->chip_flag)) {
1130 spin_lock_irqsave(&info->slock, flags);
1131 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1132 UART_IER);
1133 info->IER |= UART_IER_THRI;
1134 outb(info->IER, info->ioaddr + UART_IER);
1135 spin_unlock_irqrestore(&info->slock, flags);
1136 }
1137 }
1138 return total;
1139}
1140
1141static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1142{
1143 struct mxser_port *info = tty->driver_data;
1144 unsigned long flags;
1145
1146 if (!info->port.xmit_buf)
1147 return 0;
1148
1149 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1150 return 0;
1151
1152 spin_lock_irqsave(&info->slock, flags);
1153 info->port.xmit_buf[info->xmit_head++] = ch;
1154 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1155 info->xmit_cnt++;
1156 spin_unlock_irqrestore(&info->slock, flags);
1157 if (!tty->stopped) {
1158 if (!tty->hw_stopped ||
1159 (info->type == PORT_16550A) ||
1160 info->board->chip_flag) {
1161 spin_lock_irqsave(&info->slock, flags);
1162 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1163 info->IER |= UART_IER_THRI;
1164 outb(info->IER, info->ioaddr + UART_IER);
1165 spin_unlock_irqrestore(&info->slock, flags);
1166 }
1167 }
1168 return 1;
1169}
1170
1171
1172static void mxser_flush_chars(struct tty_struct *tty)
1173{
1174 struct mxser_port *info = tty->driver_data;
1175 unsigned long flags;
1176
1177 if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
1178 (tty->hw_stopped && info->type != PORT_16550A &&
1179 !info->board->chip_flag))
1180 return;
1181
1182 spin_lock_irqsave(&info->slock, flags);
1183
1184 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1185 info->IER |= UART_IER_THRI;
1186 outb(info->IER, info->ioaddr + UART_IER);
1187
1188 spin_unlock_irqrestore(&info->slock, flags);
1189}
1190
1191static int mxser_write_room(struct tty_struct *tty)
1192{
1193 struct mxser_port *info = tty->driver_data;
1194 int ret;
1195
1196 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1197 return ret < 0 ? 0 : ret;
1198}
1199
1200static int mxser_chars_in_buffer(struct tty_struct *tty)
1201{
1202 struct mxser_port *info = tty->driver_data;
1203 return info->xmit_cnt;
1204}
1205
1206/*
1207 * ------------------------------------------------------------
1208 * friends of mxser_ioctl()
1209 * ------------------------------------------------------------
1210 */
1211static int mxser_get_serial_info(struct tty_struct *tty,
1212 struct serial_struct __user *retinfo)
1213{
1214 struct mxser_port *info = tty->driver_data;
1215 struct serial_struct tmp = {
1216 .type = info->type,
1217 .line = tty->index,
1218 .port = info->ioaddr,
1219 .irq = info->board->irq,
1220 .flags = info->port.flags,
1221 .baud_base = info->baud_base,
1222 .close_delay = info->port.close_delay,
1223 .closing_wait = info->port.closing_wait,
1224 .custom_divisor = info->custom_divisor,
1225 .hub6 = 0
1226 };
1227 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1228 return -EFAULT;
1229 return 0;
1230}
1231
1232static int mxser_set_serial_info(struct tty_struct *tty,
1233 struct serial_struct __user *new_info)
1234{
1235 struct mxser_port *info = tty->driver_data;
1236 struct tty_port *port = &info->port;
1237 struct serial_struct new_serial;
1238 speed_t baud;
1239 unsigned long sl_flags;
1240 unsigned int flags;
1241 int retval = 0;
1242
1243 if (!new_info || !info->ioaddr)
1244 return -ENODEV;
1245 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1246 return -EFAULT;
1247
1248 if (new_serial.irq != info->board->irq ||
1249 new_serial.port != info->ioaddr)
1250 return -EINVAL;
1251
1252 flags = port->flags & ASYNC_SPD_MASK;
1253
1254 if (!capable(CAP_SYS_ADMIN)) {
1255 if ((new_serial.baud_base != info->baud_base) ||
1256 (new_serial.close_delay != info->port.close_delay) ||
1257 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK)))
1258 return -EPERM;
1259 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1260 (new_serial.flags & ASYNC_USR_MASK));
1261 } else {
1262 /*
1263 * OK, past this point, all the error checking has been done.
1264 * At this point, we start making changes.....
1265 */
1266 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1267 (new_serial.flags & ASYNC_FLAGS));
1268 port->close_delay = new_serial.close_delay * HZ / 100;
1269 port->closing_wait = new_serial.closing_wait * HZ / 100;
1270 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1271 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1272 (new_serial.baud_base != info->baud_base ||
1273 new_serial.custom_divisor !=
1274 info->custom_divisor)) {
1275 if (new_serial.custom_divisor == 0)
1276 return -EINVAL;
1277 baud = new_serial.baud_base / new_serial.custom_divisor;
1278 tty_encode_baud_rate(tty, baud, baud);
1279 }
1280 }
1281
1282 info->type = new_serial.type;
1283
1284 process_txrx_fifo(info);
1285
1286 if (test_bit(ASYNCB_INITIALIZED, &port->flags)) {
1287 if (flags != (port->flags & ASYNC_SPD_MASK)) {
1288 spin_lock_irqsave(&info->slock, sl_flags);
1289 mxser_change_speed(tty, NULL);
1290 spin_unlock_irqrestore(&info->slock, sl_flags);
1291 }
1292 } else {
1293 retval = mxser_activate(port, tty);
1294 if (retval == 0)
1295 set_bit(ASYNCB_INITIALIZED, &port->flags);
1296 }
1297 return retval;
1298}
1299
1300/*
1301 * mxser_get_lsr_info - get line status register info
1302 *
1303 * Purpose: Let user call ioctl() to get info when the UART physically
1304 * is emptied. On bus types like RS485, the transmitter must
1305 * release the bus after transmitting. This must be done when
1306 * the transmit shift register is empty, not be done when the
1307 * transmit holding register is empty. This functionality
1308 * allows an RS485 driver to be written in user space.
1309 */
1310static int mxser_get_lsr_info(struct mxser_port *info,
1311 unsigned int __user *value)
1312{
1313 unsigned char status;
1314 unsigned int result;
1315 unsigned long flags;
1316
1317 spin_lock_irqsave(&info->slock, flags);
1318 status = inb(info->ioaddr + UART_LSR);
1319 spin_unlock_irqrestore(&info->slock, flags);
1320 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1321 return put_user(result, value);
1322}
1323
1324static int mxser_tiocmget(struct tty_struct *tty)
1325{
1326 struct mxser_port *info = tty->driver_data;
1327 unsigned char control, status;
1328 unsigned long flags;
1329
1330
1331 if (tty->index == MXSER_PORTS)
1332 return -ENOIOCTLCMD;
1333 if (test_bit(TTY_IO_ERROR, &tty->flags))
1334 return -EIO;
1335
1336 control = info->MCR;
1337
1338 spin_lock_irqsave(&info->slock, flags);
1339 status = inb(info->ioaddr + UART_MSR);
1340 if (status & UART_MSR_ANY_DELTA)
1341 mxser_check_modem_status(tty, info, status);
1342 spin_unlock_irqrestore(&info->slock, flags);
1343 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1344 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1345 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1346 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1347 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1348 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1349}
1350
1351static int mxser_tiocmset(struct tty_struct *tty,
1352 unsigned int set, unsigned int clear)
1353{
1354 struct mxser_port *info = tty->driver_data;
1355 unsigned long flags;
1356
1357
1358 if (tty->index == MXSER_PORTS)
1359 return -ENOIOCTLCMD;
1360 if (test_bit(TTY_IO_ERROR, &tty->flags))
1361 return -EIO;
1362
1363 spin_lock_irqsave(&info->slock, flags);
1364
1365 if (set & TIOCM_RTS)
1366 info->MCR |= UART_MCR_RTS;
1367 if (set & TIOCM_DTR)
1368 info->MCR |= UART_MCR_DTR;
1369
1370 if (clear & TIOCM_RTS)
1371 info->MCR &= ~UART_MCR_RTS;
1372 if (clear & TIOCM_DTR)
1373 info->MCR &= ~UART_MCR_DTR;
1374
1375 outb(info->MCR, info->ioaddr + UART_MCR);
1376 spin_unlock_irqrestore(&info->slock, flags);
1377 return 0;
1378}
1379
1380static int __init mxser_program_mode(int port)
1381{
1382 int id, i, j, n;
1383
1384 outb(0, port);
1385 outb(0, port);
1386 outb(0, port);
1387 (void)inb(port);
1388 (void)inb(port);
1389 outb(0, port);
1390 (void)inb(port);
1391
1392 id = inb(port + 1) & 0x1F;
1393 if ((id != C168_ASIC_ID) &&
1394 (id != C104_ASIC_ID) &&
1395 (id != C102_ASIC_ID) &&
1396 (id != CI132_ASIC_ID) &&
1397 (id != CI134_ASIC_ID) &&
1398 (id != CI104J_ASIC_ID))
1399 return -1;
1400 for (i = 0, j = 0; i < 4; i++) {
1401 n = inb(port + 2);
1402 if (n == 'M') {
1403 j = 1;
1404 } else if ((j == 1) && (n == 1)) {
1405 j = 2;
1406 break;
1407 } else
1408 j = 0;
1409 }
1410 if (j != 2)
1411 id = -2;
1412 return id;
1413}
1414
1415static void __init mxser_normal_mode(int port)
1416{
1417 int i, n;
1418
1419 outb(0xA5, port + 1);
1420 outb(0x80, port + 3);
1421 outb(12, port + 0); /* 9600 bps */
1422 outb(0, port + 1);
1423 outb(0x03, port + 3); /* 8 data bits */
1424 outb(0x13, port + 4); /* loop back mode */
1425 for (i = 0; i < 16; i++) {
1426 n = inb(port + 5);
1427 if ((n & 0x61) == 0x60)
1428 break;
1429 if ((n & 1) == 1)
1430 (void)inb(port);
1431 }
1432 outb(0x00, port + 4);
1433}
1434
1435#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1436#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1437#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1438#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1439#define EN_CCMD 0x000 /* Chip's command register */
1440#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1441#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1442#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1443#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1444#define EN0_DCFG 0x00E /* Data configuration reg WR */
1445#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1446#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1447#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1448static int __init mxser_read_register(int port, unsigned short *regs)
1449{
1450 int i, k, value, id;
1451 unsigned int j;
1452
1453 id = mxser_program_mode(port);
1454 if (id < 0)
1455 return id;
1456 for (i = 0; i < 14; i++) {
1457 k = (i & 0x3F) | 0x180;
1458 for (j = 0x100; j > 0; j >>= 1) {
1459 outb(CHIP_CS, port);
1460 if (k & j) {
1461 outb(CHIP_CS | CHIP_DO, port);
1462 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1463 } else {
1464 outb(CHIP_CS, port);
1465 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1466 }
1467 }
1468 (void)inb(port);
1469 value = 0;
1470 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1471 outb(CHIP_CS, port);
1472 outb(CHIP_CS | CHIP_SK, port);
1473 if (inb(port) & CHIP_DI)
1474 value |= j;
1475 }
1476 regs[i] = value;
1477 outb(0, port);
1478 }
1479 mxser_normal_mode(port);
1480 return id;
1481}
1482
1483static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1484{
1485 struct mxser_port *ip;
1486 struct tty_port *port;
1487 struct tty_struct *tty;
1488 int result, status;
1489 unsigned int i, j;
1490 int ret = 0;
1491
1492 switch (cmd) {
1493 case MOXA_GET_MAJOR:
1494 printk_ratelimited(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
1495 "%x (GET_MAJOR), fix your userspace\n",
1496 current->comm, cmd);
1497 return put_user(ttymajor, (int __user *)argp);
1498
1499 case MOXA_CHKPORTENABLE:
1500 result = 0;
1501 for (i = 0; i < MXSER_BOARDS; i++)
1502 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1503 if (mxser_boards[i].ports[j].ioaddr)
1504 result |= (1 << i);
1505 return put_user(result, (unsigned long __user *)argp);
1506 case MOXA_GETDATACOUNT:
1507 /* The receive side is locked by port->slock but it isn't
1508 clear that an exact snapshot is worth copying here */
1509 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1510 ret = -EFAULT;
1511 return ret;
1512 case MOXA_GETMSTATUS: {
1513 struct mxser_mstatus ms, __user *msu = argp;
1514 for (i = 0; i < MXSER_BOARDS; i++)
1515 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1516 ip = &mxser_boards[i].ports[j];
1517 port = &ip->port;
1518 memset(&ms, 0, sizeof(ms));
1519
1520 mutex_lock(&port->mutex);
1521 if (!ip->ioaddr)
1522 goto copy;
1523
1524 tty = tty_port_tty_get(port);
1525
1526 if (!tty || !tty->termios)
1527 ms.cflag = ip->normal_termios.c_cflag;
1528 else
1529 ms.cflag = tty->termios->c_cflag;
1530 tty_kref_put(tty);
1531 spin_lock_irq(&ip->slock);
1532 status = inb(ip->ioaddr + UART_MSR);
1533 spin_unlock_irq(&ip->slock);
1534 if (status & UART_MSR_DCD)
1535 ms.dcd = 1;
1536 if (status & UART_MSR_DSR)
1537 ms.dsr = 1;
1538 if (status & UART_MSR_CTS)
1539 ms.cts = 1;
1540 copy:
1541 mutex_unlock(&port->mutex);
1542 if (copy_to_user(msu, &ms, sizeof(ms)))
1543 return -EFAULT;
1544 msu++;
1545 }
1546 return 0;
1547 }
1548 case MOXA_ASPP_MON_EXT: {
1549 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1550 unsigned int cflag, iflag, p;
1551 u8 opmode;
1552
1553 me = kzalloc(sizeof(*me), GFP_KERNEL);
1554 if (!me)
1555 return -ENOMEM;
1556
1557 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1558 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1559 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1560 i = MXSER_BOARDS;
1561 break;
1562 }
1563 ip = &mxser_boards[i].ports[j];
1564 port = &ip->port;
1565
1566 mutex_lock(&port->mutex);
1567 if (!ip->ioaddr) {
1568 mutex_unlock(&port->mutex);
1569 continue;
1570 }
1571
1572 spin_lock_irq(&ip->slock);
1573 status = mxser_get_msr(ip->ioaddr, 0, p);
1574
1575 if (status & UART_MSR_TERI)
1576 ip->icount.rng++;
1577 if (status & UART_MSR_DDSR)
1578 ip->icount.dsr++;
1579 if (status & UART_MSR_DDCD)
1580 ip->icount.dcd++;
1581 if (status & UART_MSR_DCTS)
1582 ip->icount.cts++;
1583
1584 ip->mon_data.modem_status = status;
1585 me->rx_cnt[p] = ip->mon_data.rxcnt;
1586 me->tx_cnt[p] = ip->mon_data.txcnt;
1587 me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
1588 me->up_txcnt[p] = ip->mon_data.up_txcnt;
1589 me->modem_status[p] =
1590 ip->mon_data.modem_status;
1591 spin_unlock_irq(&ip->slock);
1592
1593 tty = tty_port_tty_get(&ip->port);
1594
1595 if (!tty || !tty->termios) {
1596 cflag = ip->normal_termios.c_cflag;
1597 iflag = ip->normal_termios.c_iflag;
1598 me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
1599 } else {
1600 cflag = tty->termios->c_cflag;
1601 iflag = tty->termios->c_iflag;
1602 me->baudrate[p] = tty_get_baud_rate(tty);
1603 }
1604 tty_kref_put(tty);
1605
1606 me->databits[p] = cflag & CSIZE;
1607 me->stopbits[p] = cflag & CSTOPB;
1608 me->parity[p] = cflag & (PARENB | PARODD |
1609 CMSPAR);
1610
1611 if (cflag & CRTSCTS)
1612 me->flowctrl[p] |= 0x03;
1613
1614 if (iflag & (IXON | IXOFF))
1615 me->flowctrl[p] |= 0x0C;
1616
1617 if (ip->type == PORT_16550A)
1618 me->fifo[p] = 1;
1619
1620 opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
1621 opmode &= OP_MODE_MASK;
1622 me->iftype[p] = opmode;
1623 mutex_unlock(&port->mutex);
1624 }
1625 }
1626 if (copy_to_user(argp, me, sizeof(*me)))
1627 ret = -EFAULT;
1628 kfree(me);
1629 return ret;
1630 }
1631 default:
1632 return -ENOIOCTLCMD;
1633 }
1634 return 0;
1635}
1636
1637static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1638 struct async_icount *cprev)
1639{
1640 struct async_icount cnow;
1641 unsigned long flags;
1642 int ret;
1643
1644 spin_lock_irqsave(&info->slock, flags);
1645 cnow = info->icount; /* atomic copy */
1646 spin_unlock_irqrestore(&info->slock, flags);
1647
1648 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1649 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1650 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1651 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1652
1653 *cprev = cnow;
1654
1655 return ret;
1656}
1657
1658static int mxser_ioctl(struct tty_struct *tty,
1659 unsigned int cmd, unsigned long arg)
1660{
1661 struct mxser_port *info = tty->driver_data;
1662 struct tty_port *port = &info->port;
1663 struct async_icount cnow;
1664 unsigned long flags;
1665 void __user *argp = (void __user *)arg;
1666 int retval;
1667
1668 if (tty->index == MXSER_PORTS)
1669 return mxser_ioctl_special(cmd, argp);
1670
1671 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1672 int p;
1673 unsigned long opmode;
1674 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1675 int shiftbit;
1676 unsigned char val, mask;
1677
1678 p = tty->index % 4;
1679 if (cmd == MOXA_SET_OP_MODE) {
1680 if (get_user(opmode, (int __user *) argp))
1681 return -EFAULT;
1682 if (opmode != RS232_MODE &&
1683 opmode != RS485_2WIRE_MODE &&
1684 opmode != RS422_MODE &&
1685 opmode != RS485_4WIRE_MODE)
1686 return -EFAULT;
1687 mask = ModeMask[p];
1688 shiftbit = p * 2;
1689 spin_lock_irq(&info->slock);
1690 val = inb(info->opmode_ioaddr);
1691 val &= mask;
1692 val |= (opmode << shiftbit);
1693 outb(val, info->opmode_ioaddr);
1694 spin_unlock_irq(&info->slock);
1695 } else {
1696 shiftbit = p * 2;
1697 spin_lock_irq(&info->slock);
1698 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1699 spin_unlock_irq(&info->slock);
1700 opmode &= OP_MODE_MASK;
1701 if (put_user(opmode, (int __user *)argp))
1702 return -EFAULT;
1703 }
1704 return 0;
1705 }
1706
1707 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT &&
1708 test_bit(TTY_IO_ERROR, &tty->flags))
1709 return -EIO;
1710
1711 switch (cmd) {
1712 case TIOCGSERIAL:
1713 mutex_lock(&port->mutex);
1714 retval = mxser_get_serial_info(tty, argp);
1715 mutex_unlock(&port->mutex);
1716 return retval;
1717 case TIOCSSERIAL:
1718 mutex_lock(&port->mutex);
1719 retval = mxser_set_serial_info(tty, argp);
1720 mutex_unlock(&port->mutex);
1721 return retval;
1722 case TIOCSERGETLSR: /* Get line status register */
1723 return mxser_get_lsr_info(info, argp);
1724 /*
1725 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1726 * - mask passed in arg for lines of interest
1727 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1728 * Caller should use TIOCGICOUNT to see which one it was
1729 */
1730 case TIOCMIWAIT:
1731 spin_lock_irqsave(&info->slock, flags);
1732 cnow = info->icount; /* note the counters on entry */
1733 spin_unlock_irqrestore(&info->slock, flags);
1734
1735 return wait_event_interruptible(info->port.delta_msr_wait,
1736 mxser_cflags_changed(info, arg, &cnow));
1737 case MOXA_HighSpeedOn:
1738 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1739 case MOXA_SDS_RSTICOUNTER:
1740 spin_lock_irq(&info->slock);
1741 info->mon_data.rxcnt = 0;
1742 info->mon_data.txcnt = 0;
1743 spin_unlock_irq(&info->slock);
1744 return 0;
1745
1746 case MOXA_ASPP_OQUEUE:{
1747 int len, lsr;
1748
1749 len = mxser_chars_in_buffer(tty);
1750 spin_lock_irq(&info->slock);
1751 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
1752 spin_unlock_irq(&info->slock);
1753 len += (lsr ? 0 : 1);
1754
1755 return put_user(len, (int __user *)argp);
1756 }
1757 case MOXA_ASPP_MON: {
1758 int mcr, status;
1759
1760 spin_lock_irq(&info->slock);
1761 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1762 mxser_check_modem_status(tty, info, status);
1763
1764 mcr = inb(info->ioaddr + UART_MCR);
1765 spin_unlock_irq(&info->slock);
1766
1767 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1768 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1769 else
1770 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1771
1772 if (mcr & MOXA_MUST_MCR_TX_XON)
1773 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1774 else
1775 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1776
1777 if (tty->hw_stopped)
1778 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1779 else
1780 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1781
1782 if (copy_to_user(argp, &info->mon_data,
1783 sizeof(struct mxser_mon)))
1784 return -EFAULT;
1785
1786 return 0;
1787 }
1788 case MOXA_ASPP_LSTATUS: {
1789 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1790 return -EFAULT;
1791
1792 info->err_shadow = 0;
1793 return 0;
1794 }
1795 case MOXA_SET_BAUD_METHOD: {
1796 int method;
1797
1798 if (get_user(method, (int __user *)argp))
1799 return -EFAULT;
1800 mxser_set_baud_method[tty->index] = method;
1801 return put_user(method, (int __user *)argp);
1802 }
1803 default:
1804 return -ENOIOCTLCMD;
1805 }
1806 return 0;
1807}
1808
1809 /*
1810 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1811 * Return: write counters to the user passed counter struct
1812 * NB: both 1->0 and 0->1 transitions are counted except for
1813 * RI where only 0->1 is counted.
1814 */
1815
1816static int mxser_get_icount(struct tty_struct *tty,
1817 struct serial_icounter_struct *icount)
1818
1819{
1820 struct mxser_port *info = tty->driver_data;
1821 struct async_icount cnow;
1822 unsigned long flags;
1823
1824 spin_lock_irqsave(&info->slock, flags);
1825 cnow = info->icount;
1826 spin_unlock_irqrestore(&info->slock, flags);
1827
1828 icount->frame = cnow.frame;
1829 icount->brk = cnow.brk;
1830 icount->overrun = cnow.overrun;
1831 icount->buf_overrun = cnow.buf_overrun;
1832 icount->parity = cnow.parity;
1833 icount->rx = cnow.rx;
1834 icount->tx = cnow.tx;
1835 icount->cts = cnow.cts;
1836 icount->dsr = cnow.dsr;
1837 icount->rng = cnow.rng;
1838 icount->dcd = cnow.dcd;
1839 return 0;
1840}
1841
1842static void mxser_stoprx(struct tty_struct *tty)
1843{
1844 struct mxser_port *info = tty->driver_data;
1845
1846 info->ldisc_stop_rx = 1;
1847 if (I_IXOFF(tty)) {
1848 if (info->board->chip_flag) {
1849 info->IER &= ~MOXA_MUST_RECV_ISR;
1850 outb(info->IER, info->ioaddr + UART_IER);
1851 } else {
1852 info->x_char = STOP_CHAR(tty);
1853 outb(0, info->ioaddr + UART_IER);
1854 info->IER |= UART_IER_THRI;
1855 outb(info->IER, info->ioaddr + UART_IER);
1856 }
1857 }
1858
1859 if (tty->termios->c_cflag & CRTSCTS) {
1860 info->MCR &= ~UART_MCR_RTS;
1861 outb(info->MCR, info->ioaddr + UART_MCR);
1862 }
1863}
1864
1865/*
1866 * This routine is called by the upper-layer tty layer to signal that
1867 * incoming characters should be throttled.
1868 */
1869static void mxser_throttle(struct tty_struct *tty)
1870{
1871 mxser_stoprx(tty);
1872}
1873
1874static void mxser_unthrottle(struct tty_struct *tty)
1875{
1876 struct mxser_port *info = tty->driver_data;
1877
1878 /* startrx */
1879 info->ldisc_stop_rx = 0;
1880 if (I_IXOFF(tty)) {
1881 if (info->x_char)
1882 info->x_char = 0;
1883 else {
1884 if (info->board->chip_flag) {
1885 info->IER |= MOXA_MUST_RECV_ISR;
1886 outb(info->IER, info->ioaddr + UART_IER);
1887 } else {
1888 info->x_char = START_CHAR(tty);
1889 outb(0, info->ioaddr + UART_IER);
1890 info->IER |= UART_IER_THRI;
1891 outb(info->IER, info->ioaddr + UART_IER);
1892 }
1893 }
1894 }
1895
1896 if (tty->termios->c_cflag & CRTSCTS) {
1897 info->MCR |= UART_MCR_RTS;
1898 outb(info->MCR, info->ioaddr + UART_MCR);
1899 }
1900}
1901
1902/*
1903 * mxser_stop() and mxser_start()
1904 *
1905 * This routines are called before setting or resetting tty->stopped.
1906 * They enable or disable transmitter interrupts, as necessary.
1907 */
1908static void mxser_stop(struct tty_struct *tty)
1909{
1910 struct mxser_port *info = tty->driver_data;
1911 unsigned long flags;
1912
1913 spin_lock_irqsave(&info->slock, flags);
1914 if (info->IER & UART_IER_THRI) {
1915 info->IER &= ~UART_IER_THRI;
1916 outb(info->IER, info->ioaddr + UART_IER);
1917 }
1918 spin_unlock_irqrestore(&info->slock, flags);
1919}
1920
1921static void mxser_start(struct tty_struct *tty)
1922{
1923 struct mxser_port *info = tty->driver_data;
1924 unsigned long flags;
1925
1926 spin_lock_irqsave(&info->slock, flags);
1927 if (info->xmit_cnt && info->port.xmit_buf) {
1928 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1929 info->IER |= UART_IER_THRI;
1930 outb(info->IER, info->ioaddr + UART_IER);
1931 }
1932 spin_unlock_irqrestore(&info->slock, flags);
1933}
1934
1935static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1936{
1937 struct mxser_port *info = tty->driver_data;
1938 unsigned long flags;
1939
1940 spin_lock_irqsave(&info->slock, flags);
1941 mxser_change_speed(tty, old_termios);
1942 spin_unlock_irqrestore(&info->slock, flags);
1943
1944 if ((old_termios->c_cflag & CRTSCTS) &&
1945 !(tty->termios->c_cflag & CRTSCTS)) {
1946 tty->hw_stopped = 0;
1947 mxser_start(tty);
1948 }
1949
1950 /* Handle sw stopped */
1951 if ((old_termios->c_iflag & IXON) &&
1952 !(tty->termios->c_iflag & IXON)) {
1953 tty->stopped = 0;
1954
1955 if (info->board->chip_flag) {
1956 spin_lock_irqsave(&info->slock, flags);
1957 mxser_disable_must_rx_software_flow_control(
1958 info->ioaddr);
1959 spin_unlock_irqrestore(&info->slock, flags);
1960 }
1961
1962 mxser_start(tty);
1963 }
1964}
1965
1966/*
1967 * mxser_wait_until_sent() --- wait until the transmitter is empty
1968 */
1969static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1970{
1971 struct mxser_port *info = tty->driver_data;
1972 unsigned long orig_jiffies, char_time;
1973 unsigned long flags;
1974 int lsr;
1975
1976 if (info->type == PORT_UNKNOWN)
1977 return;
1978
1979 if (info->xmit_fifo_size == 0)
1980 return; /* Just in case.... */
1981
1982 orig_jiffies = jiffies;
1983 /*
1984 * Set the check interval to be 1/5 of the estimated time to
1985 * send a single character, and make it at least 1. The check
1986 * interval should also be less than the timeout.
1987 *
1988 * Note: we have to use pretty tight timings here to satisfy
1989 * the NIST-PCTS.
1990 */
1991 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1992 char_time = char_time / 5;
1993 if (char_time == 0)
1994 char_time = 1;
1995 if (timeout && timeout < char_time)
1996 char_time = timeout;
1997 /*
1998 * If the transmitter hasn't cleared in twice the approximate
1999 * amount of time to send the entire FIFO, it probably won't
2000 * ever clear. This assumes the UART isn't doing flow
2001 * control, which is currently the case. Hence, if it ever
2002 * takes longer than info->timeout, this is probably due to a
2003 * UART bug of some kind. So, we clamp the timeout parameter at
2004 * 2*info->timeout.
2005 */
2006 if (!timeout || timeout > 2 * info->timeout)
2007 timeout = 2 * info->timeout;
2008#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2009 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2010 timeout, char_time);
2011 printk("jiff=%lu...", jiffies);
2012#endif
2013 spin_lock_irqsave(&info->slock, flags);
2014 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
2015#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2016 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2017#endif
2018 spin_unlock_irqrestore(&info->slock, flags);
2019 schedule_timeout_interruptible(char_time);
2020 spin_lock_irqsave(&info->slock, flags);
2021 if (signal_pending(current))
2022 break;
2023 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2024 break;
2025 }
2026 spin_unlock_irqrestore(&info->slock, flags);
2027 set_current_state(TASK_RUNNING);
2028
2029#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2030 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
2031#endif
2032}
2033
2034/*
2035 * This routine is called by tty_hangup() when a hangup is signaled.
2036 */
2037static void mxser_hangup(struct tty_struct *tty)
2038{
2039 struct mxser_port *info = tty->driver_data;
2040
2041 mxser_flush_buffer(tty);
2042 tty_port_hangup(&info->port);
2043}
2044
2045/*
2046 * mxser_rs_break() --- routine which turns the break handling on or off
2047 */
2048static int mxser_rs_break(struct tty_struct *tty, int break_state)
2049{
2050 struct mxser_port *info = tty->driver_data;
2051 unsigned long flags;
2052
2053 spin_lock_irqsave(&info->slock, flags);
2054 if (break_state == -1)
2055 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2056 info->ioaddr + UART_LCR);
2057 else
2058 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2059 info->ioaddr + UART_LCR);
2060 spin_unlock_irqrestore(&info->slock, flags);
2061 return 0;
2062}
2063
2064static void mxser_receive_chars(struct tty_struct *tty,
2065 struct mxser_port *port, int *status)
2066{
2067 unsigned char ch, gdl;
2068 int ignored = 0;
2069 int cnt = 0;
2070 int recv_room;
2071 int max = 256;
2072
2073 recv_room = tty->receive_room;
2074 if (recv_room == 0 && !port->ldisc_stop_rx)
2075 mxser_stoprx(tty);
2076 if (port->board->chip_flag != MOXA_OTHER_UART) {
2077
2078 if (*status & UART_LSR_SPECIAL)
2079 goto intr_old;
2080 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2081 (*status & MOXA_MUST_LSR_RERR))
2082 goto intr_old;
2083 if (*status & MOXA_MUST_LSR_RERR)
2084 goto intr_old;
2085
2086 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2087
2088 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2089 gdl &= MOXA_MUST_GDL_MASK;
2090 if (gdl >= recv_room) {
2091 if (!port->ldisc_stop_rx)
2092 mxser_stoprx(tty);
2093 }
2094 while (gdl--) {
2095 ch = inb(port->ioaddr + UART_RX);
2096 tty_insert_flip_char(tty, ch, 0);
2097 cnt++;
2098 }
2099 goto end_intr;
2100 }
2101intr_old:
2102
2103 do {
2104 if (max-- < 0)
2105 break;
2106
2107 ch = inb(port->ioaddr + UART_RX);
2108 if (port->board->chip_flag && (*status & UART_LSR_OE))
2109 outb(0x23, port->ioaddr + UART_FCR);
2110 *status &= port->read_status_mask;
2111 if (*status & port->ignore_status_mask) {
2112 if (++ignored > 100)
2113 break;
2114 } else {
2115 char flag = 0;
2116 if (*status & UART_LSR_SPECIAL) {
2117 if (*status & UART_LSR_BI) {
2118 flag = TTY_BREAK;
2119 port->icount.brk++;
2120
2121 if (port->port.flags & ASYNC_SAK)
2122 do_SAK(tty);
2123 } else if (*status & UART_LSR_PE) {
2124 flag = TTY_PARITY;
2125 port->icount.parity++;
2126 } else if (*status & UART_LSR_FE) {
2127 flag = TTY_FRAME;
2128 port->icount.frame++;
2129 } else if (*status & UART_LSR_OE) {
2130 flag = TTY_OVERRUN;
2131 port->icount.overrun++;
2132 } else
2133 flag = TTY_BREAK;
2134 }
2135 tty_insert_flip_char(tty, ch, flag);
2136 cnt++;
2137 if (cnt >= recv_room) {
2138 if (!port->ldisc_stop_rx)
2139 mxser_stoprx(tty);
2140 break;
2141 }
2142
2143 }
2144
2145 if (port->board->chip_flag)
2146 break;
2147
2148 *status = inb(port->ioaddr + UART_LSR);
2149 } while (*status & UART_LSR_DR);
2150
2151end_intr:
2152 mxvar_log.rxcnt[tty->index] += cnt;
2153 port->mon_data.rxcnt += cnt;
2154 port->mon_data.up_rxcnt += cnt;
2155
2156 /*
2157 * We are called from an interrupt context with &port->slock
2158 * being held. Drop it temporarily in order to prevent
2159 * recursive locking.
2160 */
2161 spin_unlock(&port->slock);
2162 tty_flip_buffer_push(tty);
2163 spin_lock(&port->slock);
2164}
2165
2166static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
2167{
2168 int count, cnt;
2169
2170 if (port->x_char) {
2171 outb(port->x_char, port->ioaddr + UART_TX);
2172 port->x_char = 0;
2173 mxvar_log.txcnt[tty->index]++;
2174 port->mon_data.txcnt++;
2175 port->mon_data.up_txcnt++;
2176 port->icount.tx++;
2177 return;
2178 }
2179
2180 if (port->port.xmit_buf == NULL)
2181 return;
2182
2183 if (port->xmit_cnt <= 0 || tty->stopped ||
2184 (tty->hw_stopped &&
2185 (port->type != PORT_16550A) &&
2186 (!port->board->chip_flag))) {
2187 port->IER &= ~UART_IER_THRI;
2188 outb(port->IER, port->ioaddr + UART_IER);
2189 return;
2190 }
2191
2192 cnt = port->xmit_cnt;
2193 count = port->xmit_fifo_size;
2194 do {
2195 outb(port->port.xmit_buf[port->xmit_tail++],
2196 port->ioaddr + UART_TX);
2197 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2198 if (--port->xmit_cnt <= 0)
2199 break;
2200 } while (--count > 0);
2201 mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
2202
2203 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2204 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2205 port->icount.tx += (cnt - port->xmit_cnt);
2206
2207 if (port->xmit_cnt < WAKEUP_CHARS)
2208 tty_wakeup(tty);
2209
2210 if (port->xmit_cnt <= 0) {
2211 port->IER &= ~UART_IER_THRI;
2212 outb(port->IER, port->ioaddr + UART_IER);
2213 }
2214}
2215
2216/*
2217 * This is the serial driver's generic interrupt routine
2218 */
2219static irqreturn_t mxser_interrupt(int irq, void *dev_id)
2220{
2221 int status, iir, i;
2222 struct mxser_board *brd = NULL;
2223 struct mxser_port *port;
2224 int max, irqbits, bits, msr;
2225 unsigned int int_cnt, pass_counter = 0;
2226 int handled = IRQ_NONE;
2227 struct tty_struct *tty;
2228
2229 for (i = 0; i < MXSER_BOARDS; i++)
2230 if (dev_id == &mxser_boards[i]) {
2231 brd = dev_id;
2232 break;
2233 }
2234
2235 if (i == MXSER_BOARDS)
2236 goto irq_stop;
2237 if (brd == NULL)
2238 goto irq_stop;
2239 max = brd->info->nports;
2240 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2241 irqbits = inb(brd->vector) & brd->vector_mask;
2242 if (irqbits == brd->vector_mask)
2243 break;
2244
2245 handled = IRQ_HANDLED;
2246 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2247 if (irqbits == brd->vector_mask)
2248 break;
2249 if (bits & irqbits)
2250 continue;
2251 port = &brd->ports[i];
2252
2253 int_cnt = 0;
2254 spin_lock(&port->slock);
2255 do {
2256 iir = inb(port->ioaddr + UART_IIR);
2257 if (iir & UART_IIR_NO_INT)
2258 break;
2259 iir &= MOXA_MUST_IIR_MASK;
2260 tty = tty_port_tty_get(&port->port);
2261 if (!tty ||
2262 (port->port.flags & ASYNC_CLOSING) ||
2263 !(port->port.flags &
2264 ASYNC_INITIALIZED)) {
2265 status = inb(port->ioaddr + UART_LSR);
2266 outb(0x27, port->ioaddr + UART_FCR);
2267 inb(port->ioaddr + UART_MSR);
2268 tty_kref_put(tty);
2269 break;
2270 }
2271
2272 status = inb(port->ioaddr + UART_LSR);
2273
2274 if (status & UART_LSR_PE)
2275 port->err_shadow |= NPPI_NOTIFY_PARITY;
2276 if (status & UART_LSR_FE)
2277 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2278 if (status & UART_LSR_OE)
2279 port->err_shadow |=
2280 NPPI_NOTIFY_HW_OVERRUN;
2281 if (status & UART_LSR_BI)
2282 port->err_shadow |= NPPI_NOTIFY_BREAK;
2283
2284 if (port->board->chip_flag) {
2285 if (iir == MOXA_MUST_IIR_GDA ||
2286 iir == MOXA_MUST_IIR_RDA ||
2287 iir == MOXA_MUST_IIR_RTO ||
2288 iir == MOXA_MUST_IIR_LSR)
2289 mxser_receive_chars(tty, port,
2290 &status);
2291
2292 } else {
2293 status &= port->read_status_mask;
2294 if (status & UART_LSR_DR)
2295 mxser_receive_chars(tty, port,
2296 &status);
2297 }
2298 msr = inb(port->ioaddr + UART_MSR);
2299 if (msr & UART_MSR_ANY_DELTA)
2300 mxser_check_modem_status(tty, port, msr);
2301
2302 if (port->board->chip_flag) {
2303 if (iir == 0x02 && (status &
2304 UART_LSR_THRE))
2305 mxser_transmit_chars(tty, port);
2306 } else {
2307 if (status & UART_LSR_THRE)
2308 mxser_transmit_chars(tty, port);
2309 }
2310 tty_kref_put(tty);
2311 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2312 spin_unlock(&port->slock);
2313 }
2314 }
2315
2316irq_stop:
2317 return handled;
2318}
2319
2320static const struct tty_operations mxser_ops = {
2321 .open = mxser_open,
2322 .close = mxser_close,
2323 .write = mxser_write,
2324 .put_char = mxser_put_char,
2325 .flush_chars = mxser_flush_chars,
2326 .write_room = mxser_write_room,
2327 .chars_in_buffer = mxser_chars_in_buffer,
2328 .flush_buffer = mxser_flush_buffer,
2329 .ioctl = mxser_ioctl,
2330 .throttle = mxser_throttle,
2331 .unthrottle = mxser_unthrottle,
2332 .set_termios = mxser_set_termios,
2333 .stop = mxser_stop,
2334 .start = mxser_start,
2335 .hangup = mxser_hangup,
2336 .break_ctl = mxser_rs_break,
2337 .wait_until_sent = mxser_wait_until_sent,
2338 .tiocmget = mxser_tiocmget,
2339 .tiocmset = mxser_tiocmset,
2340 .get_icount = mxser_get_icount,
2341};
2342
2343struct tty_port_operations mxser_port_ops = {
2344 .carrier_raised = mxser_carrier_raised,
2345 .dtr_rts = mxser_dtr_rts,
2346 .activate = mxser_activate,
2347 .shutdown = mxser_shutdown_port,
2348};
2349
2350/*
2351 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2352 */
2353
2354static void mxser_release_ISA_res(struct mxser_board *brd)
2355{
2356 free_irq(brd->irq, brd);
2357 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2358 release_region(brd->vector, 1);
2359}
2360
2361static int __devinit mxser_initbrd(struct mxser_board *brd,
2362 struct pci_dev *pdev)
2363{
2364 struct mxser_port *info;
2365 unsigned int i;
2366 int retval;
2367
2368 printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
2369 brd->ports[0].max_baud);
2370
2371 for (i = 0; i < brd->info->nports; i++) {
2372 info = &brd->ports[i];
2373 tty_port_init(&info->port);
2374 info->port.ops = &mxser_port_ops;
2375 info->board = brd;
2376 info->stop_rx = 0;
2377 info->ldisc_stop_rx = 0;
2378
2379 /* Enhance mode enabled here */
2380 if (brd->chip_flag != MOXA_OTHER_UART)
2381 mxser_enable_must_enchance_mode(info->ioaddr);
2382
2383 info->port.flags = ASYNC_SHARE_IRQ;
2384 info->type = brd->uart_type;
2385
2386 process_txrx_fifo(info);
2387
2388 info->custom_divisor = info->baud_base * 16;
2389 info->port.close_delay = 5 * HZ / 10;
2390 info->port.closing_wait = 30 * HZ;
2391 info->normal_termios = mxvar_sdriver->init_termios;
2392 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2393 info->err_shadow = 0;
2394 spin_lock_init(&info->slock);
2395
2396 /* before set INT ISR, disable all int */
2397 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2398 info->ioaddr + UART_IER);
2399 }
2400
2401 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2402 brd);
2403 if (retval)
2404 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2405 "conflict with another device.\n",
2406 brd->info->name, brd->irq);
2407
2408 return retval;
2409}
2410
2411static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
2412{
2413 int id, i, bits;
2414 unsigned short regs[16], irq;
2415 unsigned char scratch, scratch2;
2416
2417 brd->chip_flag = MOXA_OTHER_UART;
2418
2419 id = mxser_read_register(cap, regs);
2420 switch (id) {
2421 case C168_ASIC_ID:
2422 brd->info = &mxser_cards[0];
2423 break;
2424 case C104_ASIC_ID:
2425 brd->info = &mxser_cards[1];
2426 break;
2427 case CI104J_ASIC_ID:
2428 brd->info = &mxser_cards[2];
2429 break;
2430 case C102_ASIC_ID:
2431 brd->info = &mxser_cards[5];
2432 break;
2433 case CI132_ASIC_ID:
2434 brd->info = &mxser_cards[6];
2435 break;
2436 case CI134_ASIC_ID:
2437 brd->info = &mxser_cards[7];
2438 break;
2439 default:
2440 return 0;
2441 }
2442
2443 irq = 0;
2444 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2445 Flag-hack checks if configuration should be read as 2-port here. */
2446 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
2447 irq = regs[9] & 0xF000;
2448 irq = irq | (irq >> 4);
2449 if (irq != (regs[9] & 0xFF00))
2450 goto err_irqconflict;
2451 } else if (brd->info->nports == 4) {
2452 irq = regs[9] & 0xF000;
2453 irq = irq | (irq >> 4);
2454 irq = irq | (irq >> 8);
2455 if (irq != regs[9])
2456 goto err_irqconflict;
2457 } else if (brd->info->nports == 8) {
2458 irq = regs[9] & 0xF000;
2459 irq = irq | (irq >> 4);
2460 irq = irq | (irq >> 8);
2461 if ((irq != regs[9]) || (irq != regs[10]))
2462 goto err_irqconflict;
2463 }
2464
2465 if (!irq) {
2466 printk(KERN_ERR "mxser: interrupt number unset\n");
2467 return -EIO;
2468 }
2469 brd->irq = ((int)(irq & 0xF000) >> 12);
2470 for (i = 0; i < 8; i++)
2471 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2472 if ((regs[12] & 0x80) == 0) {
2473 printk(KERN_ERR "mxser: invalid interrupt vector\n");
2474 return -EIO;
2475 }
2476 brd->vector = (int)regs[11]; /* interrupt vector */
2477 if (id == 1)
2478 brd->vector_mask = 0x00FF;
2479 else
2480 brd->vector_mask = 0x000F;
2481 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2482 if (regs[12] & bits) {
2483 brd->ports[i].baud_base = 921600;
2484 brd->ports[i].max_baud = 921600;
2485 } else {
2486 brd->ports[i].baud_base = 115200;
2487 brd->ports[i].max_baud = 115200;
2488 }
2489 }
2490 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2491 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2492 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2493 outb(scratch2, cap + UART_LCR);
2494 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2495 scratch = inb(cap + UART_IIR);
2496
2497 if (scratch & 0xC0)
2498 brd->uart_type = PORT_16550A;
2499 else
2500 brd->uart_type = PORT_16450;
2501 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2502 "mxser(IO)")) {
2503 printk(KERN_ERR "mxser: can't request ports I/O region: "
2504 "0x%.8lx-0x%.8lx\n",
2505 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2506 8 * brd->info->nports - 1);
2507 return -EIO;
2508 }
2509 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2510 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2511 printk(KERN_ERR "mxser: can't request interrupt vector region: "
2512 "0x%.8lx-0x%.8lx\n",
2513 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2514 8 * brd->info->nports - 1);
2515 return -EIO;
2516 }
2517 return brd->info->nports;
2518
2519err_irqconflict:
2520 printk(KERN_ERR "mxser: invalid interrupt number\n");
2521 return -EIO;
2522}
2523
2524static int __devinit mxser_probe(struct pci_dev *pdev,
2525 const struct pci_device_id *ent)
2526{
2527#ifdef CONFIG_PCI
2528 struct mxser_board *brd;
2529 unsigned int i, j;
2530 unsigned long ioaddress;
2531 int retval = -EINVAL;
2532
2533 for (i = 0; i < MXSER_BOARDS; i++)
2534 if (mxser_boards[i].info == NULL)
2535 break;
2536
2537 if (i >= MXSER_BOARDS) {
2538 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2539 "not configured\n", MXSER_BOARDS);
2540 goto err;
2541 }
2542
2543 brd = &mxser_boards[i];
2544 brd->idx = i * MXSER_PORTS_PER_BOARD;
2545 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2546 mxser_cards[ent->driver_data].name,
2547 pdev->bus->number, PCI_SLOT(pdev->devfn));
2548
2549 retval = pci_enable_device(pdev);
2550 if (retval) {
2551 dev_err(&pdev->dev, "PCI enable failed\n");
2552 goto err;
2553 }
2554
2555 /* io address */
2556 ioaddress = pci_resource_start(pdev, 2);
2557 retval = pci_request_region(pdev, 2, "mxser(IO)");
2558 if (retval)
2559 goto err_dis;
2560
2561 brd->info = &mxser_cards[ent->driver_data];
2562 for (i = 0; i < brd->info->nports; i++)
2563 brd->ports[i].ioaddr = ioaddress + 8 * i;
2564
2565 /* vector */
2566 ioaddress = pci_resource_start(pdev, 3);
2567 retval = pci_request_region(pdev, 3, "mxser(vector)");
2568 if (retval)
2569 goto err_zero;
2570 brd->vector = ioaddress;
2571
2572 /* irq */
2573 brd->irq = pdev->irq;
2574
2575 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2576 brd->uart_type = PORT_16550A;
2577 brd->vector_mask = 0;
2578
2579 for (i = 0; i < brd->info->nports; i++) {
2580 for (j = 0; j < UART_INFO_NUM; j++) {
2581 if (Gpci_uart_info[j].type == brd->chip_flag) {
2582 brd->ports[i].max_baud =
2583 Gpci_uart_info[j].max_baud;
2584
2585 /* exception....CP-102 */
2586 if (brd->info->flags & MXSER_HIGHBAUD)
2587 brd->ports[i].max_baud = 921600;
2588 break;
2589 }
2590 }
2591 }
2592
2593 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2594 for (i = 0; i < brd->info->nports; i++) {
2595 if (i < 4)
2596 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2597 else
2598 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2599 }
2600 outb(0, ioaddress + 4); /* default set to RS232 mode */
2601 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
2602 }
2603
2604 for (i = 0; i < brd->info->nports; i++) {
2605 brd->vector_mask |= (1 << i);
2606 brd->ports[i].baud_base = 921600;
2607 }
2608
2609 /* mxser_initbrd will hook ISR. */
2610 retval = mxser_initbrd(brd, pdev);
2611 if (retval)
2612 goto err_rel3;
2613
2614 for (i = 0; i < brd->info->nports; i++)
2615 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2616
2617 pci_set_drvdata(pdev, brd);
2618
2619 return 0;
2620err_rel3:
2621 pci_release_region(pdev, 3);
2622err_zero:
2623 brd->info = NULL;
2624 pci_release_region(pdev, 2);
2625err_dis:
2626 pci_disable_device(pdev);
2627err:
2628 return retval;
2629#else
2630 return -ENODEV;
2631#endif
2632}
2633
2634static void __devexit mxser_remove(struct pci_dev *pdev)
2635{
2636#ifdef CONFIG_PCI
2637 struct mxser_board *brd = pci_get_drvdata(pdev);
2638 unsigned int i;
2639
2640 for (i = 0; i < brd->info->nports; i++)
2641 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2642
2643 free_irq(pdev->irq, brd);
2644 pci_release_region(pdev, 2);
2645 pci_release_region(pdev, 3);
2646 pci_disable_device(pdev);
2647 brd->info = NULL;
2648#endif
2649}
2650
2651static struct pci_driver mxser_driver = {
2652 .name = "mxser",
2653 .id_table = mxser_pcibrds,
2654 .probe = mxser_probe,
2655 .remove = __devexit_p(mxser_remove)
2656};
2657
2658static int __init mxser_module_init(void)
2659{
2660 struct mxser_board *brd;
2661 unsigned int b, i, m;
2662 int retval;
2663
2664 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2665 if (!mxvar_sdriver)
2666 return -ENOMEM;
2667
2668 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2669 MXSER_VERSION);
2670
2671 /* Initialize the tty_driver structure */
2672 mxvar_sdriver->owner = THIS_MODULE;
2673 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2674 mxvar_sdriver->name = "ttyMI";
2675 mxvar_sdriver->major = ttymajor;
2676 mxvar_sdriver->minor_start = 0;
2677 mxvar_sdriver->num = MXSER_PORTS + 1;
2678 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2679 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2680 mxvar_sdriver->init_termios = tty_std_termios;
2681 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2682 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2683 tty_set_operations(mxvar_sdriver, &mxser_ops);
2684
2685 retval = tty_register_driver(mxvar_sdriver);
2686 if (retval) {
2687 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2688 "tty driver !\n");
2689 goto err_put;
2690 }
2691
2692 /* Start finding ISA boards here */
2693 for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
2694 if (!ioaddr[b])
2695 continue;
2696
2697 brd = &mxser_boards[m];
2698 retval = mxser_get_ISA_conf(ioaddr[b], brd);
2699 if (retval <= 0) {
2700 brd->info = NULL;
2701 continue;
2702 }
2703
2704 printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
2705 brd->info->name, ioaddr[b]);
2706
2707 /* mxser_initbrd will hook ISR. */
2708 if (mxser_initbrd(brd, NULL) < 0) {
2709 brd->info = NULL;
2710 continue;
2711 }
2712
2713 brd->idx = m * MXSER_PORTS_PER_BOARD;
2714 for (i = 0; i < brd->info->nports; i++)
2715 tty_register_device(mxvar_sdriver, brd->idx + i, NULL);
2716
2717 m++;
2718 }
2719
2720 retval = pci_register_driver(&mxser_driver);
2721 if (retval) {
2722 printk(KERN_ERR "mxser: can't register pci driver\n");
2723 if (!m) {
2724 retval = -ENODEV;
2725 goto err_unr;
2726 } /* else: we have some ISA cards under control */
2727 }
2728
2729 return 0;
2730err_unr:
2731 tty_unregister_driver(mxvar_sdriver);
2732err_put:
2733 put_tty_driver(mxvar_sdriver);
2734 return retval;
2735}
2736
2737static void __exit mxser_module_exit(void)
2738{
2739 unsigned int i, j;
2740
2741 pci_unregister_driver(&mxser_driver);
2742
2743 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2744 if (mxser_boards[i].info != NULL)
2745 for (j = 0; j < mxser_boards[i].info->nports; j++)
2746 tty_unregister_device(mxvar_sdriver,
2747 mxser_boards[i].idx + j);
2748 tty_unregister_driver(mxvar_sdriver);
2749 put_tty_driver(mxvar_sdriver);
2750
2751 for (i = 0; i < MXSER_BOARDS; i++)
2752 if (mxser_boards[i].info != NULL)
2753 mxser_release_ISA_res(&mxser_boards[i]);
2754}
2755
2756module_init(mxser_module_init);
2757module_exit(mxser_module_exit);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
11 *
12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
15 * - Fixed x86_64 cleanness
16 */
17
18#include <linux/module.h>
19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/major.h>
29#include <linux/string.h>
30#include <linux/fcntl.h>
31#include <linux/ptrace.h>
32#include <linux/ioport.h>
33#include <linux/mm.h>
34#include <linux/delay.h>
35#include <linux/pci.h>
36#include <linux/bitops.h>
37#include <linux/slab.h>
38#include <linux/ratelimit.h>
39
40#include <asm/io.h>
41#include <asm/irq.h>
42#include <linux/uaccess.h>
43
44/*
45 * Semi-public control interfaces
46 */
47
48/*
49 * MOXA ioctls
50 */
51
52#define MOXA 0x400
53#define MOXA_SET_OP_MODE (MOXA + 66)
54#define MOXA_GET_OP_MODE (MOXA + 67)
55
56#define RS232_MODE 0
57#define RS485_2WIRE_MODE 1
58#define RS422_MODE 2
59#define RS485_4WIRE_MODE 3
60#define OP_MODE_MASK 3
61
62/* --------------------------------------------------- */
63
64/*
65 * Follow just what Moxa Must chip defines.
66 *
67 * When LCR register (offset 0x03) is written the following value, the Must chip
68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
69 * change bank.
70 */
71#define MOXA_MUST_ENTER_ENHANCED 0xBF
72
73/* when enhanced mode is enabled, access to general bank register */
74#define MOXA_MUST_GDL_REGISTER 0x07
75#define MOXA_MUST_GDL_MASK 0x7F
76#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
77
78#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79/* enhanced register bank select and enhanced mode setting register */
80/* This works only when LCR register equals to 0xBF */
81#define MOXA_MUST_EFR_REGISTER 0x02
82#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
83/* enhanced register bank set 0, 1, 2 */
84#define MOXA_MUST_EFR_BANK0 0x00
85#define MOXA_MUST_EFR_BANK1 0x40
86#define MOXA_MUST_EFR_BANK2 0x80
87#define MOXA_MUST_EFR_BANK3 0xC0
88#define MOXA_MUST_EFR_BANK_MASK 0xC0
89
90/* set XON1 value register, when LCR=0xBF and change to bank0 */
91#define MOXA_MUST_XON1_REGISTER 0x04
92
93/* set XON2 value register, when LCR=0xBF and change to bank0 */
94#define MOXA_MUST_XON2_REGISTER 0x05
95
96/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97#define MOXA_MUST_XOFF1_REGISTER 0x06
98
99/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100#define MOXA_MUST_XOFF2_REGISTER 0x07
101
102#define MOXA_MUST_RBRTL_REGISTER 0x04
103#define MOXA_MUST_RBRTH_REGISTER 0x05
104#define MOXA_MUST_RBRTI_REGISTER 0x06
105#define MOXA_MUST_THRTL_REGISTER 0x07
106#define MOXA_MUST_ENUM_REGISTER 0x04
107#define MOXA_MUST_HWID_REGISTER 0x05
108#define MOXA_MUST_ECR_REGISTER 0x06
109#define MOXA_MUST_CSR_REGISTER 0x07
110
111#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
113
114#define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115#define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116#define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117#define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
118
119#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
120
121/* GDA interrupt pending */
122#define MOXA_MUST_IIR_GDA 0x1C
123#define MOXA_MUST_IIR_RDA 0x04
124#define MOXA_MUST_IIR_RTO 0x0C
125#define MOXA_MUST_IIR_LSR 0x06
126
127/* received Xon/Xoff or specical interrupt pending */
128#define MOXA_MUST_IIR_XSC 0x10
129
130/* RTS/CTS change state interrupt pending */
131#define MOXA_MUST_IIR_RTSCTS 0x20
132#define MOXA_MUST_IIR_MASK 0x3E
133
134#define MOXA_MUST_MCR_XON_FLAG 0x40
135#define MOXA_MUST_MCR_XON_ANY 0x80
136#define MOXA_MUST_MCR_TX_XON 0x08
137
138#define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139#define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140#define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141#define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142#define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143#define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144#define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145#define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146#define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147#define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
149
150#define MXSERMAJOR 174
151
152#define MXSER_BOARDS 4 /* Max. boards */
153#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
154#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155#define MXSER_ISR_PASS_LIMIT 100
156
157#define WAKEUP_CHARS 256
158
159#define MXSER_BAUD_BASE 921600
160#define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
161
162#define PCI_DEVICE_ID_MOXA_RC7000 0x0001
163#define PCI_DEVICE_ID_MOXA_CP102 0x1020
164#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
165#define PCI_DEVICE_ID_MOXA_CP102U 0x1022
166#define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
167#define PCI_DEVICE_ID_MOXA_C104 0x1040
168#define PCI_DEVICE_ID_MOXA_CP104U 0x1041
169#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
170#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
171#define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
172#define PCI_DEVICE_ID_MOXA_CB108 0x1080
173#define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
174#define PCI_DEVICE_ID_MOXA_CT114 0x1140
175#define PCI_DEVICE_ID_MOXA_CP114 0x1141
176#define PCI_DEVICE_ID_MOXA_CB114 0x1142
177#define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
178#define PCI_DEVICE_ID_MOXA_CP118U 0x1180
179#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
180#define PCI_DEVICE_ID_MOXA_CP132 0x1320
181#define PCI_DEVICE_ID_MOXA_CP132U 0x1321
182#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
183#define PCI_DEVICE_ID_MOXA_CB134I 0x1341
184#define PCI_DEVICE_ID_MOXA_CP138U 0x1380
185#define PCI_DEVICE_ID_MOXA_C168 0x1680
186#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
187#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
188
189#define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
190#define MXSER_HIGHBAUD 0x0100
191
192enum mxser_must_hwid {
193 MOXA_OTHER_UART = 0x00,
194 MOXA_MUST_MU150_HWID = 0x01,
195 MOXA_MUST_MU860_HWID = 0x02,
196};
197
198static const struct {
199 u8 type;
200 u8 fifo_size;
201 u8 rx_high_water;
202 u8 rx_low_water;
203 speed_t max_baud;
204} Gpci_uart_info[] = {
205 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
208};
209#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
210
211static const struct pci_device_id mxser_pcibrds[] = {
212 { PCI_DEVICE_DATA(MOXA, C168, 8) },
213 { PCI_DEVICE_DATA(MOXA, C104, 4) },
214 { PCI_DEVICE_DATA(MOXA, CP132, 2) },
215 { PCI_DEVICE_DATA(MOXA, CP114, 4) },
216 { PCI_DEVICE_DATA(MOXA, CT114, 4) },
217 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) },
218 { PCI_DEVICE_DATA(MOXA, CP104U, 4) },
219 { PCI_DEVICE_DATA(MOXA, CP168U, 8) },
220 { PCI_DEVICE_DATA(MOXA, CP132U, 2) },
221 { PCI_DEVICE_DATA(MOXA, CP134U, 4) },
222 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) },
223 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */
224 { PCI_DEVICE_DATA(MOXA, CP118U, 8) },
225 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) },
226 { PCI_DEVICE_DATA(MOXA, CP102U, 2) },
227 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) },
228 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) },
229 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) },
230 { PCI_DEVICE_DATA(MOXA, CB108, 8) },
231 { PCI_DEVICE_DATA(MOXA, CB114, 4) },
232 { PCI_DEVICE_DATA(MOXA, CB134I, 4) },
233 { PCI_DEVICE_DATA(MOXA, CP138U, 8) },
234 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) },
235 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) },
236 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) },
237 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) },
238 { }
239};
240MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
241
242static int ttymajor = MXSERMAJOR;
243
244/* Variables for insmod */
245
246MODULE_AUTHOR("Casper Yang");
247MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
248module_param(ttymajor, int, 0);
249MODULE_LICENSE("GPL");
250
251struct mxser_board;
252
253struct mxser_port {
254 struct tty_port port;
255 struct mxser_board *board;
256
257 unsigned long ioaddr;
258 unsigned long opmode_ioaddr;
259
260 u8 rx_high_water;
261 u8 rx_low_water;
262 int type; /* UART type */
263
264 u8 x_char; /* xon/xoff character */
265 u8 IER; /* Interrupt Enable Register */
266 u8 MCR; /* Modem control register */
267 u8 FCR; /* FIFO control register */
268
269 struct async_icount icount; /* kernel counters for 4 input interrupts */
270 unsigned int timeout;
271
272 u8 read_status_mask;
273 u8 ignore_status_mask;
274 u8 xmit_fifo_size;
275
276 spinlock_t slock;
277};
278
279struct mxser_board {
280 unsigned int idx;
281 unsigned short nports;
282 int irq;
283 unsigned long vector;
284
285 enum mxser_must_hwid must_hwid;
286 speed_t max_baud;
287
288 struct mxser_port ports[] /* __counted_by(nports) */;
289};
290
291static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
292static struct tty_driver *mxvar_sdriver;
293
294static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
295 bool restore_LCR)
296{
297 u8 oldlcr, efr;
298
299 oldlcr = inb(baseio + UART_LCR);
300 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
301
302 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
303 efr &= ~clear;
304 efr |= set;
305
306 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
307
308 if (restore_LCR)
309 outb(oldlcr, baseio + UART_LCR);
310
311 return oldlcr;
312}
313
314static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
315{
316 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
317 false);
318}
319
320static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
321{
322 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
323 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
324 outb(oldlcr, baseio + UART_LCR);
325}
326
327static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
328{
329 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
330 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
331 outb(oldlcr, baseio + UART_LCR);
332}
333
334static void mxser_set_must_fifo_value(struct mxser_port *info)
335{
336 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
337 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
338 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
339 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
340 outb(oldlcr, info->ioaddr + UART_LCR);
341}
342
343static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
344{
345 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
346 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
347 outb(oldlcr, baseio + UART_LCR);
348}
349
350static u8 mxser_get_must_hardware_id(unsigned long baseio)
351{
352 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
353 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
354 outb(oldlcr, baseio + UART_LCR);
355
356 return id;
357}
358
359static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
360{
361 __mxser_must_set_EFR(baseio, clear, set, true);
362}
363
364static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
365{
366 mxser_must_set_EFR(baseio,
367 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
368 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
369}
370
371static void mxser_must_no_sw_flow_control(unsigned long baseio)
372{
373 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
374}
375
376static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
377{
378 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
379 enable ? MOXA_MUST_EFR_SF_TX1 : 0);
380}
381
382static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
383{
384 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
385 enable ? MOXA_MUST_EFR_SF_RX1 : 0);
386}
387
388static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
389{
390 u8 oldmcr, hwid;
391 int i;
392
393 outb(0, io + UART_LCR);
394 mxser_must_set_enhance_mode(io, false);
395 oldmcr = inb(io + UART_MCR);
396 outb(0, io + UART_MCR);
397 mxser_set_must_xon1_value(io, 0x11);
398 if (inb(io + UART_MCR) != 0) {
399 outb(oldmcr, io + UART_MCR);
400 return MOXA_OTHER_UART;
401 }
402
403 hwid = mxser_get_must_hardware_id(io);
404 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
405 if (hwid == Gpci_uart_info[i].type)
406 return hwid;
407
408 return MOXA_OTHER_UART;
409}
410
411static bool mxser_16550A_or_MUST(struct mxser_port *info)
412{
413 return info->type == PORT_16550A || info->board->must_hwid;
414}
415
416static void mxser_process_txrx_fifo(struct mxser_port *info)
417{
418 unsigned int i;
419
420 if (info->type == PORT_16450 || info->type == PORT_8250) {
421 info->rx_high_water = 1;
422 info->rx_low_water = 1;
423 info->xmit_fifo_size = 1;
424 return;
425 }
426
427 for (i = 0; i < UART_INFO_NUM; i++)
428 if (info->board->must_hwid == Gpci_uart_info[i].type) {
429 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
430 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
431 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
432 break;
433 }
434}
435
436static void __mxser_start_tx(struct mxser_port *info)
437{
438 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
439 info->IER |= UART_IER_THRI;
440 outb(info->IER, info->ioaddr + UART_IER);
441}
442
443static void mxser_start_tx(struct mxser_port *info)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&info->slock, flags);
448 __mxser_start_tx(info);
449 spin_unlock_irqrestore(&info->slock, flags);
450}
451
452static void __mxser_stop_tx(struct mxser_port *info)
453{
454 info->IER &= ~UART_IER_THRI;
455 outb(info->IER, info->ioaddr + UART_IER);
456}
457
458static bool mxser_carrier_raised(struct tty_port *port)
459{
460 struct mxser_port *mp = container_of(port, struct mxser_port, port);
461
462 return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD;
463}
464
465static void mxser_dtr_rts(struct tty_port *port, bool active)
466{
467 struct mxser_port *mp = container_of(port, struct mxser_port, port);
468 unsigned long flags;
469 u8 mcr;
470
471 spin_lock_irqsave(&mp->slock, flags);
472 mcr = inb(mp->ioaddr + UART_MCR);
473 if (active)
474 mcr |= UART_MCR_DTR | UART_MCR_RTS;
475 else
476 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
477 outb(mcr, mp->ioaddr + UART_MCR);
478 spin_unlock_irqrestore(&mp->slock, flags);
479}
480
481static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
482{
483 struct mxser_port *info = tty->driver_data;
484 unsigned int quot = 0, baud;
485 unsigned char cval;
486 u64 timeout;
487
488 if (newspd > info->board->max_baud)
489 return -1;
490
491 if (newspd == 134) {
492 quot = 2 * MXSER_BAUD_BASE / 269;
493 tty_encode_baud_rate(tty, 134, 134);
494 } else if (newspd) {
495 quot = MXSER_BAUD_BASE / newspd;
496 if (quot == 0)
497 quot = 1;
498 baud = MXSER_BAUD_BASE / quot;
499 tty_encode_baud_rate(tty, baud, baud);
500 } else {
501 quot = 0;
502 }
503
504 /*
505 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
506 * u64 domain
507 */
508 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
509 do_div(timeout, MXSER_BAUD_BASE);
510 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
511
512 if (quot) {
513 info->MCR |= UART_MCR_DTR;
514 outb(info->MCR, info->ioaddr + UART_MCR);
515 } else {
516 info->MCR &= ~UART_MCR_DTR;
517 outb(info->MCR, info->ioaddr + UART_MCR);
518 return 0;
519 }
520
521 cval = inb(info->ioaddr + UART_LCR);
522
523 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
524
525 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
526 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
527 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
528
529 if (C_BAUD(tty) == BOTHER) {
530 quot = MXSER_BAUD_BASE % newspd;
531 quot *= 8;
532 if (quot % newspd > newspd / 2) {
533 quot /= newspd;
534 quot++;
535 } else
536 quot /= newspd;
537
538 mxser_set_must_enum_value(info->ioaddr, quot);
539 } else {
540 mxser_set_must_enum_value(info->ioaddr, 0);
541 }
542
543 return 0;
544}
545
546static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
547 u8 msr)
548{
549 bool cts = msr & UART_MSR_CTS;
550
551 if (tty->hw_stopped) {
552 if (cts) {
553 tty->hw_stopped = false;
554
555 if (!mxser_16550A_or_MUST(info))
556 __mxser_start_tx(info);
557 tty_wakeup(tty);
558 }
559 return;
560 } else if (cts)
561 return;
562
563 tty->hw_stopped = true;
564 if (!mxser_16550A_or_MUST(info))
565 __mxser_stop_tx(info);
566}
567
568/*
569 * This routine is called to set the UART divisor registers to match
570 * the specified baud rate for a serial port.
571 */
572static void mxser_change_speed(struct tty_struct *tty,
573 const struct ktermios *old_termios)
574{
575 struct mxser_port *info = tty->driver_data;
576 unsigned cflag, cval;
577
578 cflag = tty->termios.c_cflag;
579
580 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
581 /* Use previous rate on a failure */
582 if (old_termios) {
583 speed_t baud = tty_termios_baud_rate(old_termios);
584 tty_encode_baud_rate(tty, baud, baud);
585 }
586 }
587
588 /* byte size and parity */
589 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
590
591 if (cflag & CSTOPB)
592 cval |= UART_LCR_STOP;
593 if (cflag & PARENB)
594 cval |= UART_LCR_PARITY;
595 if (!(cflag & PARODD))
596 cval |= UART_LCR_EPAR;
597 if (cflag & CMSPAR)
598 cval |= UART_LCR_SPAR;
599
600 info->FCR = 0;
601 if (info->board->must_hwid) {
602 info->FCR |= UART_FCR_ENABLE_FIFO |
603 MOXA_MUST_FCR_GDA_MODE_ENABLE;
604 mxser_set_must_fifo_value(info);
605 } else if (info->type != PORT_8250 && info->type != PORT_16450) {
606 info->FCR |= UART_FCR_ENABLE_FIFO;
607 switch (info->rx_high_water) {
608 case 1:
609 info->FCR |= UART_FCR_TRIGGER_1;
610 break;
611 case 4:
612 info->FCR |= UART_FCR_TRIGGER_4;
613 break;
614 case 8:
615 info->FCR |= UART_FCR_TRIGGER_8;
616 break;
617 default:
618 info->FCR |= UART_FCR_TRIGGER_14;
619 break;
620 }
621 }
622
623 /* CTS flow control flag and modem status interrupts */
624 info->IER &= ~UART_IER_MSI;
625 info->MCR &= ~UART_MCR_AFE;
626 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
627 if (cflag & CRTSCTS) {
628 info->IER |= UART_IER_MSI;
629 if (mxser_16550A_or_MUST(info)) {
630 info->MCR |= UART_MCR_AFE;
631 } else {
632 mxser_handle_cts(tty, info,
633 inb(info->ioaddr + UART_MSR));
634 }
635 }
636 outb(info->MCR, info->ioaddr + UART_MCR);
637 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
638 if (~cflag & CLOCAL)
639 info->IER |= UART_IER_MSI;
640 outb(info->IER, info->ioaddr + UART_IER);
641
642 /*
643 * Set up parity check flag
644 */
645 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
646 if (I_INPCK(tty))
647 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
648 if (I_BRKINT(tty) || I_PARMRK(tty))
649 info->read_status_mask |= UART_LSR_BI;
650
651 info->ignore_status_mask = 0;
652
653 if (I_IGNBRK(tty)) {
654 info->ignore_status_mask |= UART_LSR_BI;
655 info->read_status_mask |= UART_LSR_BI;
656 /*
657 * If we're ignore parity and break indicators, ignore
658 * overruns too. (For real raw support).
659 */
660 if (I_IGNPAR(tty)) {
661 info->ignore_status_mask |=
662 UART_LSR_OE |
663 UART_LSR_PE |
664 UART_LSR_FE;
665 info->read_status_mask |=
666 UART_LSR_OE |
667 UART_LSR_PE |
668 UART_LSR_FE;
669 }
670 }
671 if (info->board->must_hwid) {
672 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
673 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
674 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
675 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
676 }
677
678
679 outb(info->FCR, info->ioaddr + UART_FCR);
680 outb(cval, info->ioaddr + UART_LCR);
681}
682
683static u8 mxser_check_modem_status(struct tty_struct *tty,
684 struct mxser_port *port)
685{
686 u8 msr = inb(port->ioaddr + UART_MSR);
687
688 if (!(msr & UART_MSR_ANY_DELTA))
689 return msr;
690
691 /* update input line counters */
692 if (msr & UART_MSR_TERI)
693 port->icount.rng++;
694 if (msr & UART_MSR_DDSR)
695 port->icount.dsr++;
696 if (msr & UART_MSR_DDCD)
697 port->icount.dcd++;
698 if (msr & UART_MSR_DCTS)
699 port->icount.cts++;
700 wake_up_interruptible(&port->port.delta_msr_wait);
701
702 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
703 if (msr & UART_MSR_DCD)
704 wake_up_interruptible(&port->port.open_wait);
705 }
706
707 if (tty_port_cts_enabled(&port->port))
708 mxser_handle_cts(tty, port, msr);
709
710 return msr;
711}
712
713static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
714{
715 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
716
717 if (info->board->must_hwid)
718 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
719
720 outb(fcr, info->ioaddr + UART_FCR);
721}
722
723static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
724{
725 struct mxser_port *info = container_of(port, struct mxser_port, port);
726 unsigned long flags;
727 int ret;
728
729 ret = tty_port_alloc_xmit_buf(port);
730 if (ret < 0)
731 return ret;
732
733 spin_lock_irqsave(&info->slock, flags);
734
735 if (!info->type) {
736 set_bit(TTY_IO_ERROR, &tty->flags);
737 spin_unlock_irqrestore(&info->slock, flags);
738 ret = 0;
739 goto err_free_xmit;
740 }
741
742 /*
743 * Clear the FIFO buffers and disable them
744 * (they will be reenabled in mxser_change_speed())
745 */
746 mxser_disable_and_clear_FIFO(info);
747
748 /*
749 * At this point there's no way the LSR could still be 0xFF;
750 * if it is, then bail out, because there's likely no UART
751 * here.
752 */
753 if (inb(info->ioaddr + UART_LSR) == 0xff) {
754 spin_unlock_irqrestore(&info->slock, flags);
755 if (capable(CAP_SYS_ADMIN)) {
756 set_bit(TTY_IO_ERROR, &tty->flags);
757 return 0;
758 }
759
760 ret = -ENODEV;
761 goto err_free_xmit;
762 }
763
764 /*
765 * Clear the interrupt registers.
766 */
767 (void) inb(info->ioaddr + UART_LSR);
768 (void) inb(info->ioaddr + UART_RX);
769 (void) inb(info->ioaddr + UART_IIR);
770 (void) inb(info->ioaddr + UART_MSR);
771
772 /*
773 * Now, initialize the UART
774 */
775 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
776 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
777 outb(info->MCR, info->ioaddr + UART_MCR);
778
779 /*
780 * Finally, enable interrupts
781 */
782 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
783
784 if (info->board->must_hwid)
785 info->IER |= MOXA_MUST_IER_EGDAI;
786 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
787
788 /*
789 * And clear the interrupt registers again for luck.
790 */
791 (void) inb(info->ioaddr + UART_LSR);
792 (void) inb(info->ioaddr + UART_RX);
793 (void) inb(info->ioaddr + UART_IIR);
794 (void) inb(info->ioaddr + UART_MSR);
795
796 clear_bit(TTY_IO_ERROR, &tty->flags);
797 kfifo_reset(&port->xmit_fifo);
798
799 /*
800 * and set the speed of the serial port
801 */
802 mxser_change_speed(tty, NULL);
803 spin_unlock_irqrestore(&info->slock, flags);
804
805 return 0;
806err_free_xmit:
807 tty_port_free_xmit_buf(port);
808 return ret;
809}
810
811/*
812 * To stop accepting input, we disable the receive line status interrupts, and
813 * tell the interrupt driver to stop checking the data ready bit in the line
814 * status register.
815 */
816static void mxser_stop_rx(struct mxser_port *info)
817{
818 info->IER &= ~UART_IER_RLSI;
819 if (info->board->must_hwid)
820 info->IER &= ~MOXA_MUST_RECV_ISR;
821
822 outb(info->IER, info->ioaddr + UART_IER);
823}
824
825/*
826 * This routine will shutdown a serial port
827 */
828static void mxser_shutdown_port(struct tty_port *port)
829{
830 struct mxser_port *info = container_of(port, struct mxser_port, port);
831 unsigned long flags;
832
833 spin_lock_irqsave(&info->slock, flags);
834
835 mxser_stop_rx(info);
836
837 /*
838 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
839 * here so the queue might never be waken up
840 */
841 wake_up_interruptible(&info->port.delta_msr_wait);
842
843 info->IER = 0;
844 outb(0x00, info->ioaddr + UART_IER);
845
846 /* clear Rx/Tx FIFO's */
847 mxser_disable_and_clear_FIFO(info);
848
849 /* read data port to reset things */
850 (void) inb(info->ioaddr + UART_RX);
851
852
853 if (info->board->must_hwid)
854 mxser_must_no_sw_flow_control(info->ioaddr);
855
856 spin_unlock_irqrestore(&info->slock, flags);
857
858 /* make sure ISR is not running while we free the buffer */
859 synchronize_irq(info->board->irq);
860
861 tty_port_free_xmit_buf(port);
862}
863
864/*
865 * This routine is called whenever a serial port is opened. It
866 * enables interrupts for a serial port, linking in its async structure into
867 * the IRQ chain. It also performs the serial-specific
868 * initialization for the tty structure.
869 */
870static int mxser_open(struct tty_struct *tty, struct file *filp)
871{
872 struct tty_port *tport = tty->port;
873 struct mxser_port *port = container_of(tport, struct mxser_port, port);
874
875 tty->driver_data = port;
876
877 return tty_port_open(tport, tty, filp);
878}
879
880static void mxser_flush_buffer(struct tty_struct *tty)
881{
882 struct mxser_port *info = tty->driver_data;
883 unsigned long flags;
884
885 spin_lock_irqsave(&info->slock, flags);
886 kfifo_reset(&info->port.xmit_fifo);
887
888 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
889 info->ioaddr + UART_FCR);
890
891 spin_unlock_irqrestore(&info->slock, flags);
892
893 tty_wakeup(tty);
894}
895
896static void mxser_close(struct tty_struct *tty, struct file *filp)
897{
898 tty_port_close(tty->port, tty, filp);
899}
900
901static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count)
902{
903 struct mxser_port *info = tty->driver_data;
904 unsigned long flags;
905 size_t written;
906 bool is_empty;
907
908 spin_lock_irqsave(&info->slock, flags);
909 written = kfifo_in(&info->port.xmit_fifo, buf, count);
910 is_empty = kfifo_is_empty(&info->port.xmit_fifo);
911 spin_unlock_irqrestore(&info->slock, flags);
912
913 if (!is_empty && !tty->flow.stopped)
914 if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
915 mxser_start_tx(info);
916
917 return written;
918}
919
920static int mxser_put_char(struct tty_struct *tty, u8 ch)
921{
922 struct mxser_port *info = tty->driver_data;
923 unsigned long flags;
924 int ret;
925
926 spin_lock_irqsave(&info->slock, flags);
927 ret = kfifo_put(&info->port.xmit_fifo, ch);
928 spin_unlock_irqrestore(&info->slock, flags);
929
930 return ret;
931}
932
933
934static void mxser_flush_chars(struct tty_struct *tty)
935{
936 struct mxser_port *info = tty->driver_data;
937
938 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
939 (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
940 return;
941
942 mxser_start_tx(info);
943}
944
945static unsigned int mxser_write_room(struct tty_struct *tty)
946{
947 struct mxser_port *info = tty->driver_data;
948
949 return kfifo_avail(&info->port.xmit_fifo);
950}
951
952static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
953{
954 struct mxser_port *info = tty->driver_data;
955
956 return kfifo_len(&info->port.xmit_fifo);
957}
958
959/*
960 * ------------------------------------------------------------
961 * friends of mxser_ioctl()
962 * ------------------------------------------------------------
963 */
964static int mxser_get_serial_info(struct tty_struct *tty,
965 struct serial_struct *ss)
966{
967 struct mxser_port *info = tty->driver_data;
968 struct tty_port *port = &info->port;
969 unsigned int closing_wait, close_delay;
970
971 mutex_lock(&port->mutex);
972
973 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
974 closing_wait = info->port.closing_wait;
975 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
976 closing_wait = jiffies_to_msecs(closing_wait) / 10;
977
978 ss->type = info->type;
979 ss->line = tty->index;
980 ss->port = info->ioaddr;
981 ss->irq = info->board->irq;
982 ss->flags = info->port.flags;
983 ss->baud_base = MXSER_BAUD_BASE;
984 ss->close_delay = close_delay;
985 ss->closing_wait = closing_wait;
986 ss->custom_divisor = MXSER_CUSTOM_DIVISOR;
987 mutex_unlock(&port->mutex);
988 return 0;
989}
990
991static int mxser_set_serial_info(struct tty_struct *tty,
992 struct serial_struct *ss)
993{
994 struct mxser_port *info = tty->driver_data;
995 struct tty_port *port = &info->port;
996 speed_t baud;
997 unsigned long sl_flags;
998 unsigned int old_speed, close_delay, closing_wait;
999 int retval = 0;
1000
1001 if (tty_io_error(tty))
1002 return -EIO;
1003
1004 mutex_lock(&port->mutex);
1005
1006 if (ss->irq != info->board->irq ||
1007 ss->port != info->ioaddr) {
1008 mutex_unlock(&port->mutex);
1009 return -EINVAL;
1010 }
1011
1012 old_speed = port->flags & ASYNC_SPD_MASK;
1013
1014 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1015 closing_wait = ss->closing_wait;
1016 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1017 closing_wait = msecs_to_jiffies(closing_wait * 10);
1018
1019 if (!capable(CAP_SYS_ADMIN)) {
1020 if ((ss->baud_base != MXSER_BAUD_BASE) ||
1021 (close_delay != port->close_delay) ||
1022 (closing_wait != port->closing_wait) ||
1023 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
1024 mutex_unlock(&port->mutex);
1025 return -EPERM;
1026 }
1027 port->flags = (port->flags & ~ASYNC_USR_MASK) |
1028 (ss->flags & ASYNC_USR_MASK);
1029 } else {
1030 /*
1031 * OK, past this point, all the error checking has been done.
1032 * At this point, we start making changes.....
1033 */
1034 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1035 (ss->flags & ASYNC_FLAGS));
1036 port->close_delay = close_delay;
1037 port->closing_wait = closing_wait;
1038 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1039 (ss->baud_base != MXSER_BAUD_BASE ||
1040 ss->custom_divisor !=
1041 MXSER_CUSTOM_DIVISOR)) {
1042 if (ss->custom_divisor == 0) {
1043 mutex_unlock(&port->mutex);
1044 return -EINVAL;
1045 }
1046 baud = ss->baud_base / ss->custom_divisor;
1047 tty_encode_baud_rate(tty, baud, baud);
1048 }
1049
1050 info->type = ss->type;
1051
1052 mxser_process_txrx_fifo(info);
1053 }
1054
1055 if (tty_port_initialized(port)) {
1056 if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1057 spin_lock_irqsave(&info->slock, sl_flags);
1058 mxser_change_speed(tty, NULL);
1059 spin_unlock_irqrestore(&info->slock, sl_flags);
1060 }
1061 } else {
1062 retval = mxser_activate(port, tty);
1063 if (retval == 0)
1064 tty_port_set_initialized(port, true);
1065 }
1066 mutex_unlock(&port->mutex);
1067 return retval;
1068}
1069
1070/*
1071 * mxser_get_lsr_info - get line status register info
1072 *
1073 * Purpose: Let user call ioctl() to get info when the UART physically
1074 * is emptied. On bus types like RS485, the transmitter must
1075 * release the bus after transmitting. This must be done when
1076 * the transmit shift register is empty, not be done when the
1077 * transmit holding register is empty. This functionality
1078 * allows an RS485 driver to be written in user space.
1079 */
1080static int mxser_get_lsr_info(struct mxser_port *info,
1081 unsigned int __user *value)
1082{
1083 unsigned char status;
1084 unsigned int result;
1085 unsigned long flags;
1086
1087 spin_lock_irqsave(&info->slock, flags);
1088 status = inb(info->ioaddr + UART_LSR);
1089 spin_unlock_irqrestore(&info->slock, flags);
1090 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1091 return put_user(result, value);
1092}
1093
1094static int mxser_tiocmget(struct tty_struct *tty)
1095{
1096 struct mxser_port *info = tty->driver_data;
1097 unsigned char control;
1098 unsigned long flags;
1099 u8 msr;
1100
1101 if (tty_io_error(tty))
1102 return -EIO;
1103
1104 spin_lock_irqsave(&info->slock, flags);
1105 control = info->MCR;
1106 msr = mxser_check_modem_status(tty, info);
1107 spin_unlock_irqrestore(&info->slock, flags);
1108
1109 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1110 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1111 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1112 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
1113 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1114 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
1115}
1116
1117static int mxser_tiocmset(struct tty_struct *tty,
1118 unsigned int set, unsigned int clear)
1119{
1120 struct mxser_port *info = tty->driver_data;
1121 unsigned long flags;
1122
1123 if (tty_io_error(tty))
1124 return -EIO;
1125
1126 spin_lock_irqsave(&info->slock, flags);
1127
1128 if (set & TIOCM_RTS)
1129 info->MCR |= UART_MCR_RTS;
1130 if (set & TIOCM_DTR)
1131 info->MCR |= UART_MCR_DTR;
1132
1133 if (clear & TIOCM_RTS)
1134 info->MCR &= ~UART_MCR_RTS;
1135 if (clear & TIOCM_DTR)
1136 info->MCR &= ~UART_MCR_DTR;
1137
1138 outb(info->MCR, info->ioaddr + UART_MCR);
1139 spin_unlock_irqrestore(&info->slock, flags);
1140 return 0;
1141}
1142
1143static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1144 struct async_icount *cprev)
1145{
1146 struct async_icount cnow;
1147 unsigned long flags;
1148 int ret;
1149
1150 spin_lock_irqsave(&info->slock, flags);
1151 cnow = info->icount; /* atomic copy */
1152 spin_unlock_irqrestore(&info->slock, flags);
1153
1154 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1155 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1156 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1157 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1158
1159 *cprev = cnow;
1160
1161 return ret;
1162}
1163
1164/* We should likely switch to TIOCGRS485/TIOCSRS485. */
1165static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1166 int __user *u_opmode)
1167{
1168 int opmode, p = index % 4;
1169 int shiftbit = p * 2;
1170 u8 val;
1171
1172 if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1173 return -EFAULT;
1174
1175 if (set) {
1176 if (get_user(opmode, u_opmode))
1177 return -EFAULT;
1178
1179 if (opmode & ~OP_MODE_MASK)
1180 return -EINVAL;
1181
1182 spin_lock_irq(&port->slock);
1183 val = inb(port->opmode_ioaddr);
1184 val &= ~(OP_MODE_MASK << shiftbit);
1185 val |= (opmode << shiftbit);
1186 outb(val, port->opmode_ioaddr);
1187 spin_unlock_irq(&port->slock);
1188
1189 return 0;
1190 }
1191
1192 spin_lock_irq(&port->slock);
1193 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1194 spin_unlock_irq(&port->slock);
1195
1196 return put_user(opmode & OP_MODE_MASK, u_opmode);
1197}
1198
1199static int mxser_ioctl(struct tty_struct *tty,
1200 unsigned int cmd, unsigned long arg)
1201{
1202 struct mxser_port *info = tty->driver_data;
1203 struct async_icount cnow;
1204 unsigned long flags;
1205 void __user *argp = (void __user *)arg;
1206
1207 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1208 return mxser_ioctl_op_mode(info, tty->index,
1209 cmd == MOXA_SET_OP_MODE, argp);
1210
1211 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1212 return -EIO;
1213
1214 switch (cmd) {
1215 case TIOCSERGETLSR: /* Get line status register */
1216 return mxser_get_lsr_info(info, argp);
1217 /*
1218 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1219 * - mask passed in arg for lines of interest
1220 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1221 * Caller should use TIOCGICOUNT to see which one it was
1222 */
1223 case TIOCMIWAIT:
1224 spin_lock_irqsave(&info->slock, flags);
1225 cnow = info->icount; /* note the counters on entry */
1226 spin_unlock_irqrestore(&info->slock, flags);
1227
1228 return wait_event_interruptible(info->port.delta_msr_wait,
1229 mxser_cflags_changed(info, arg, &cnow));
1230 default:
1231 return -ENOIOCTLCMD;
1232 }
1233 return 0;
1234}
1235
1236 /*
1237 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1238 * Return: write counters to the user passed counter struct
1239 * NB: both 1->0 and 0->1 transitions are counted except for
1240 * RI where only 0->1 is counted.
1241 */
1242
1243static int mxser_get_icount(struct tty_struct *tty,
1244 struct serial_icounter_struct *icount)
1245
1246{
1247 struct mxser_port *info = tty->driver_data;
1248 struct async_icount cnow;
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&info->slock, flags);
1252 cnow = info->icount;
1253 spin_unlock_irqrestore(&info->slock, flags);
1254
1255 icount->frame = cnow.frame;
1256 icount->brk = cnow.brk;
1257 icount->overrun = cnow.overrun;
1258 icount->buf_overrun = cnow.buf_overrun;
1259 icount->parity = cnow.parity;
1260 icount->rx = cnow.rx;
1261 icount->tx = cnow.tx;
1262 icount->cts = cnow.cts;
1263 icount->dsr = cnow.dsr;
1264 icount->rng = cnow.rng;
1265 icount->dcd = cnow.dcd;
1266 return 0;
1267}
1268
1269/*
1270 * This routine is called by the upper-layer tty layer to signal that
1271 * incoming characters should be throttled.
1272 */
1273static void mxser_throttle(struct tty_struct *tty)
1274{
1275 struct mxser_port *info = tty->driver_data;
1276
1277 if (I_IXOFF(tty)) {
1278 if (info->board->must_hwid) {
1279 info->IER &= ~MOXA_MUST_RECV_ISR;
1280 outb(info->IER, info->ioaddr + UART_IER);
1281 } else {
1282 info->x_char = STOP_CHAR(tty);
1283 outb(0, info->ioaddr + UART_IER);
1284 info->IER |= UART_IER_THRI;
1285 outb(info->IER, info->ioaddr + UART_IER);
1286 }
1287 }
1288
1289 if (C_CRTSCTS(tty)) {
1290 info->MCR &= ~UART_MCR_RTS;
1291 outb(info->MCR, info->ioaddr + UART_MCR);
1292 }
1293}
1294
1295static void mxser_unthrottle(struct tty_struct *tty)
1296{
1297 struct mxser_port *info = tty->driver_data;
1298
1299 /* startrx */
1300 if (I_IXOFF(tty)) {
1301 if (info->x_char)
1302 info->x_char = 0;
1303 else {
1304 if (info->board->must_hwid) {
1305 info->IER |= MOXA_MUST_RECV_ISR;
1306 outb(info->IER, info->ioaddr + UART_IER);
1307 } else {
1308 info->x_char = START_CHAR(tty);
1309 outb(0, info->ioaddr + UART_IER);
1310 info->IER |= UART_IER_THRI;
1311 outb(info->IER, info->ioaddr + UART_IER);
1312 }
1313 }
1314 }
1315
1316 if (C_CRTSCTS(tty)) {
1317 info->MCR |= UART_MCR_RTS;
1318 outb(info->MCR, info->ioaddr + UART_MCR);
1319 }
1320}
1321
1322/*
1323 * mxser_stop() and mxser_start()
1324 *
1325 * This routines are called before setting or resetting tty->flow.stopped.
1326 * They enable or disable transmitter interrupts, as necessary.
1327 */
1328static void mxser_stop(struct tty_struct *tty)
1329{
1330 struct mxser_port *info = tty->driver_data;
1331 unsigned long flags;
1332
1333 spin_lock_irqsave(&info->slock, flags);
1334 if (info->IER & UART_IER_THRI)
1335 __mxser_stop_tx(info);
1336 spin_unlock_irqrestore(&info->slock, flags);
1337}
1338
1339static void mxser_start(struct tty_struct *tty)
1340{
1341 struct mxser_port *info = tty->driver_data;
1342 unsigned long flags;
1343
1344 spin_lock_irqsave(&info->slock, flags);
1345 if (!kfifo_is_empty(&info->port.xmit_fifo))
1346 __mxser_start_tx(info);
1347 spin_unlock_irqrestore(&info->slock, flags);
1348}
1349
1350static void mxser_set_termios(struct tty_struct *tty,
1351 const struct ktermios *old_termios)
1352{
1353 struct mxser_port *info = tty->driver_data;
1354 unsigned long flags;
1355
1356 spin_lock_irqsave(&info->slock, flags);
1357 mxser_change_speed(tty, old_termios);
1358 spin_unlock_irqrestore(&info->slock, flags);
1359
1360 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1361 tty->hw_stopped = false;
1362 mxser_start(tty);
1363 }
1364
1365 /* Handle sw stopped */
1366 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1367 tty->flow.stopped = 0;
1368
1369 if (info->board->must_hwid) {
1370 spin_lock_irqsave(&info->slock, flags);
1371 mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1372 spin_unlock_irqrestore(&info->slock, flags);
1373 }
1374
1375 mxser_start(tty);
1376 }
1377}
1378
1379static bool mxser_tx_empty(struct mxser_port *info)
1380{
1381 unsigned long flags;
1382 u8 lsr;
1383
1384 spin_lock_irqsave(&info->slock, flags);
1385 lsr = inb(info->ioaddr + UART_LSR);
1386 spin_unlock_irqrestore(&info->slock, flags);
1387
1388 return !(lsr & UART_LSR_TEMT);
1389}
1390
1391/*
1392 * mxser_wait_until_sent() --- wait until the transmitter is empty
1393 */
1394static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1395{
1396 struct mxser_port *info = tty->driver_data;
1397 unsigned long expire, char_time;
1398
1399 if (info->type == PORT_UNKNOWN)
1400 return;
1401
1402 if (info->xmit_fifo_size == 0)
1403 return; /* Just in case.... */
1404
1405 /*
1406 * Set the check interval to be 1/5 of the estimated time to
1407 * send a single character, and make it at least 1. The check
1408 * interval should also be less than the timeout.
1409 *
1410 * Note: we have to use pretty tight timings here to satisfy
1411 * the NIST-PCTS.
1412 */
1413 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1414 char_time = char_time / 5;
1415 if (char_time == 0)
1416 char_time = 1;
1417 if (timeout && timeout < char_time)
1418 char_time = timeout;
1419
1420 char_time = jiffies_to_msecs(char_time);
1421
1422 /*
1423 * If the transmitter hasn't cleared in twice the approximate
1424 * amount of time to send the entire FIFO, it probably won't
1425 * ever clear. This assumes the UART isn't doing flow
1426 * control, which is currently the case. Hence, if it ever
1427 * takes longer than info->timeout, this is probably due to a
1428 * UART bug of some kind. So, we clamp the timeout parameter at
1429 * 2*info->timeout.
1430 */
1431 if (!timeout || timeout > 2 * info->timeout)
1432 timeout = 2 * info->timeout;
1433
1434 expire = jiffies + timeout;
1435
1436 while (mxser_tx_empty(info)) {
1437 msleep_interruptible(char_time);
1438 if (signal_pending(current))
1439 break;
1440 if (time_after(jiffies, expire))
1441 break;
1442 }
1443}
1444
1445/*
1446 * This routine is called by tty_hangup() when a hangup is signaled.
1447 */
1448static void mxser_hangup(struct tty_struct *tty)
1449{
1450 struct mxser_port *info = tty->driver_data;
1451
1452 mxser_flush_buffer(tty);
1453 tty_port_hangup(&info->port);
1454}
1455
1456/*
1457 * mxser_rs_break() --- routine which turns the break handling on or off
1458 */
1459static int mxser_rs_break(struct tty_struct *tty, int break_state)
1460{
1461 struct mxser_port *info = tty->driver_data;
1462 unsigned long flags;
1463 u8 lcr;
1464
1465 spin_lock_irqsave(&info->slock, flags);
1466 lcr = inb(info->ioaddr + UART_LCR);
1467 if (break_state == -1)
1468 lcr |= UART_LCR_SBC;
1469 else
1470 lcr &= ~UART_LCR_SBC;
1471 outb(lcr, info->ioaddr + UART_LCR);
1472 spin_unlock_irqrestore(&info->slock, flags);
1473
1474 return 0;
1475}
1476
1477static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
1478{
1479 enum mxser_must_hwid hwid = port->board->must_hwid;
1480 u8 gdl;
1481
1482 if (hwid == MOXA_OTHER_UART)
1483 return false;
1484 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
1485 return false;
1486
1487 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1488 if (hwid == MOXA_MUST_MU150_HWID)
1489 gdl &= MOXA_MUST_GDL_MASK;
1490
1491 while (gdl--) {
1492 u8 ch = inb(port->ioaddr + UART_RX);
1493 if (!tty_insert_flip_char(&port->port, ch, 0))
1494 port->icount.buf_overrun++;
1495 }
1496
1497 return true;
1498}
1499
1500static u8 mxser_receive_chars_old(struct tty_struct *tty,
1501 struct mxser_port *port, u8 status)
1502{
1503 enum mxser_must_hwid hwid = port->board->must_hwid;
1504 int ignored = 0;
1505 int max = 256;
1506 u8 ch;
1507
1508 do {
1509 if (max-- < 0)
1510 break;
1511
1512 ch = inb(port->ioaddr + UART_RX);
1513 if (hwid && (status & UART_LSR_OE))
1514 outb(port->FCR | UART_FCR_CLEAR_RCVR,
1515 port->ioaddr + UART_FCR);
1516 status &= port->read_status_mask;
1517 if (status & port->ignore_status_mask) {
1518 if (++ignored > 100)
1519 break;
1520 } else {
1521 u8 flag = 0;
1522 if (status & UART_LSR_BRK_ERROR_BITS) {
1523 if (status & UART_LSR_BI) {
1524 flag = TTY_BREAK;
1525 port->icount.brk++;
1526
1527 if (port->port.flags & ASYNC_SAK)
1528 do_SAK(tty);
1529 } else if (status & UART_LSR_PE) {
1530 flag = TTY_PARITY;
1531 port->icount.parity++;
1532 } else if (status & UART_LSR_FE) {
1533 flag = TTY_FRAME;
1534 port->icount.frame++;
1535 } else if (status & UART_LSR_OE) {
1536 flag = TTY_OVERRUN;
1537 port->icount.overrun++;
1538 }
1539 }
1540 if (!tty_insert_flip_char(&port->port, ch, flag)) {
1541 port->icount.buf_overrun++;
1542 break;
1543 }
1544 }
1545
1546 if (hwid)
1547 break;
1548
1549 status = inb(port->ioaddr + UART_LSR);
1550 } while (status & UART_LSR_DR);
1551
1552 return status;
1553}
1554
1555static u8 mxser_receive_chars(struct tty_struct *tty,
1556 struct mxser_port *port, u8 status)
1557{
1558 if (!mxser_receive_chars_new(port, status))
1559 status = mxser_receive_chars_old(tty, port, status);
1560
1561 tty_flip_buffer_push(&port->port);
1562
1563 return status;
1564}
1565
1566static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1567{
1568 int count;
1569
1570 if (port->x_char) {
1571 outb(port->x_char, port->ioaddr + UART_TX);
1572 port->x_char = 0;
1573 port->icount.tx++;
1574 return;
1575 }
1576
1577 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
1578 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1579 __mxser_stop_tx(port);
1580 return;
1581 }
1582
1583 count = port->xmit_fifo_size;
1584 do {
1585 u8 c;
1586
1587 if (!kfifo_get(&port->port.xmit_fifo, &c))
1588 break;
1589
1590 outb(c, port->ioaddr + UART_TX);
1591 port->icount.tx++;
1592 } while (--count > 0);
1593
1594 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
1595 tty_wakeup(tty);
1596
1597 if (kfifo_is_empty(&port->port.xmit_fifo))
1598 __mxser_stop_tx(port);
1599}
1600
1601static bool mxser_port_isr(struct mxser_port *port)
1602{
1603 struct tty_struct *tty;
1604 u8 iir, status;
1605 bool error = false;
1606
1607 iir = inb(port->ioaddr + UART_IIR);
1608 if (iir & UART_IIR_NO_INT)
1609 return true;
1610
1611 iir &= MOXA_MUST_IIR_MASK;
1612 tty = tty_port_tty_get(&port->port);
1613 if (!tty) {
1614 status = inb(port->ioaddr + UART_LSR);
1615 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1616 port->ioaddr + UART_FCR);
1617 inb(port->ioaddr + UART_MSR);
1618
1619 error = true;
1620 goto put_tty;
1621 }
1622
1623 status = inb(port->ioaddr + UART_LSR);
1624
1625 if (port->board->must_hwid) {
1626 if (iir == MOXA_MUST_IIR_GDA ||
1627 iir == MOXA_MUST_IIR_RDA ||
1628 iir == MOXA_MUST_IIR_RTO ||
1629 iir == MOXA_MUST_IIR_LSR)
1630 status = mxser_receive_chars(tty, port, status);
1631 } else {
1632 status &= port->read_status_mask;
1633 if (status & UART_LSR_DR)
1634 status = mxser_receive_chars(tty, port, status);
1635 }
1636
1637 mxser_check_modem_status(tty, port);
1638
1639 if (port->board->must_hwid) {
1640 if (iir == 0x02 && (status & UART_LSR_THRE))
1641 mxser_transmit_chars(tty, port);
1642 } else {
1643 if (status & UART_LSR_THRE)
1644 mxser_transmit_chars(tty, port);
1645 }
1646
1647put_tty:
1648 tty_kref_put(tty);
1649
1650 return error;
1651}
1652
1653/*
1654 * This is the serial driver's generic interrupt routine
1655 */
1656static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1657{
1658 struct mxser_board *brd = dev_id;
1659 struct mxser_port *port;
1660 unsigned int int_cnt, pass_counter = 0;
1661 unsigned int i, max = brd->nports;
1662 int handled = IRQ_NONE;
1663 u8 irqbits, bits, mask = BIT(max) - 1;
1664
1665 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1666 irqbits = inb(brd->vector) & mask;
1667 if (irqbits == mask)
1668 break;
1669
1670 handled = IRQ_HANDLED;
1671 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1672 if (irqbits == mask)
1673 break;
1674 if (bits & irqbits)
1675 continue;
1676 port = &brd->ports[i];
1677
1678 int_cnt = 0;
1679 spin_lock(&port->slock);
1680 do {
1681 if (mxser_port_isr(port))
1682 break;
1683 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1684 spin_unlock(&port->slock);
1685 }
1686 }
1687
1688 return handled;
1689}
1690
1691static const struct tty_operations mxser_ops = {
1692 .open = mxser_open,
1693 .close = mxser_close,
1694 .write = mxser_write,
1695 .put_char = mxser_put_char,
1696 .flush_chars = mxser_flush_chars,
1697 .write_room = mxser_write_room,
1698 .chars_in_buffer = mxser_chars_in_buffer,
1699 .flush_buffer = mxser_flush_buffer,
1700 .ioctl = mxser_ioctl,
1701 .throttle = mxser_throttle,
1702 .unthrottle = mxser_unthrottle,
1703 .set_termios = mxser_set_termios,
1704 .stop = mxser_stop,
1705 .start = mxser_start,
1706 .hangup = mxser_hangup,
1707 .break_ctl = mxser_rs_break,
1708 .wait_until_sent = mxser_wait_until_sent,
1709 .tiocmget = mxser_tiocmget,
1710 .tiocmset = mxser_tiocmset,
1711 .set_serial = mxser_set_serial_info,
1712 .get_serial = mxser_get_serial_info,
1713 .get_icount = mxser_get_icount,
1714};
1715
1716static const struct tty_port_operations mxser_port_ops = {
1717 .carrier_raised = mxser_carrier_raised,
1718 .dtr_rts = mxser_dtr_rts,
1719 .activate = mxser_activate,
1720 .shutdown = mxser_shutdown_port,
1721};
1722
1723/*
1724 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1725 */
1726
1727static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1728{
1729 struct mxser_port *info;
1730 unsigned int i;
1731 bool is_mu860;
1732
1733 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1734 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1735
1736 for (i = 0; i < UART_INFO_NUM; i++) {
1737 if (Gpci_uart_info[i].type == brd->must_hwid) {
1738 brd->max_baud = Gpci_uart_info[i].max_baud;
1739
1740 /* exception....CP-102 */
1741 if (high_baud)
1742 brd->max_baud = 921600;
1743 break;
1744 }
1745 }
1746
1747 if (is_mu860) {
1748 /* set to RS232 mode by default */
1749 outb(0, brd->vector + 4);
1750 outb(0, brd->vector + 0x0c);
1751 }
1752
1753 for (i = 0; i < brd->nports; i++) {
1754 info = &brd->ports[i];
1755 if (is_mu860) {
1756 if (i < 4)
1757 info->opmode_ioaddr = brd->vector + 4;
1758 else
1759 info->opmode_ioaddr = brd->vector + 0x0c;
1760 }
1761 tty_port_init(&info->port);
1762 info->port.ops = &mxser_port_ops;
1763 info->board = brd;
1764
1765 /* Enhance mode enabled here */
1766 if (brd->must_hwid != MOXA_OTHER_UART)
1767 mxser_must_set_enhance_mode(info->ioaddr, true);
1768
1769 info->type = PORT_16550A;
1770
1771 mxser_process_txrx_fifo(info);
1772
1773 spin_lock_init(&info->slock);
1774
1775 /* before set INT ISR, disable all int */
1776 outb(inb(info->ioaddr + UART_IER) & 0xf0,
1777 info->ioaddr + UART_IER);
1778 }
1779}
1780
1781static int mxser_probe(struct pci_dev *pdev,
1782 const struct pci_device_id *ent)
1783{
1784 struct mxser_board *brd;
1785 unsigned int i, base;
1786 unsigned long ioaddress;
1787 unsigned short nports = MXSER_NPORTS(ent->driver_data);
1788 struct device *tty_dev;
1789 int retval = -EINVAL;
1790
1791 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1792 if (i >= MXSER_BOARDS) {
1793 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1794 "not configured\n", MXSER_BOARDS);
1795 goto err;
1796 }
1797
1798 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1799 GFP_KERNEL);
1800 if (!brd)
1801 goto err;
1802
1803 brd->idx = i;
1804 __set_bit(brd->idx, mxser_boards);
1805 base = i * MXSER_PORTS_PER_BOARD;
1806
1807 retval = pcim_enable_device(pdev);
1808 if (retval) {
1809 dev_err(&pdev->dev, "PCI enable failed\n");
1810 goto err_zero;
1811 }
1812
1813 /* io address */
1814 ioaddress = pci_resource_start(pdev, 2);
1815 retval = pci_request_region(pdev, 2, "mxser(IO)");
1816 if (retval)
1817 goto err_zero;
1818
1819 brd->nports = nports;
1820 for (i = 0; i < nports; i++)
1821 brd->ports[i].ioaddr = ioaddress + 8 * i;
1822
1823 /* vector */
1824 ioaddress = pci_resource_start(pdev, 3);
1825 retval = pci_request_region(pdev, 3, "mxser(vector)");
1826 if (retval)
1827 goto err_zero;
1828 brd->vector = ioaddress;
1829
1830 /* irq */
1831 brd->irq = pdev->irq;
1832
1833 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1834
1835 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1836 IRQF_SHARED, "mxser", brd);
1837 if (retval) {
1838 dev_err(&pdev->dev, "request irq failed");
1839 goto err_relbrd;
1840 }
1841
1842 for (i = 0; i < nports; i++) {
1843 tty_dev = tty_port_register_device(&brd->ports[i].port,
1844 mxvar_sdriver, base + i, &pdev->dev);
1845 if (IS_ERR(tty_dev)) {
1846 retval = PTR_ERR(tty_dev);
1847 for (; i > 0; i--)
1848 tty_unregister_device(mxvar_sdriver,
1849 base + i - 1);
1850 goto err_relbrd;
1851 }
1852 }
1853
1854 pci_set_drvdata(pdev, brd);
1855
1856 return 0;
1857err_relbrd:
1858 for (i = 0; i < nports; i++)
1859 tty_port_destroy(&brd->ports[i].port);
1860err_zero:
1861 __clear_bit(brd->idx, mxser_boards);
1862err:
1863 return retval;
1864}
1865
1866static void mxser_remove(struct pci_dev *pdev)
1867{
1868 struct mxser_board *brd = pci_get_drvdata(pdev);
1869 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1870
1871 for (i = 0; i < brd->nports; i++) {
1872 tty_unregister_device(mxvar_sdriver, base + i);
1873 tty_port_destroy(&brd->ports[i].port);
1874 }
1875
1876 __clear_bit(brd->idx, mxser_boards);
1877}
1878
1879static struct pci_driver mxser_driver = {
1880 .name = "mxser",
1881 .id_table = mxser_pcibrds,
1882 .probe = mxser_probe,
1883 .remove = mxser_remove
1884};
1885
1886static int __init mxser_module_init(void)
1887{
1888 int retval;
1889
1890 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1891 TTY_DRIVER_DYNAMIC_DEV);
1892 if (IS_ERR(mxvar_sdriver))
1893 return PTR_ERR(mxvar_sdriver);
1894
1895 /* Initialize the tty_driver structure */
1896 mxvar_sdriver->name = "ttyMI";
1897 mxvar_sdriver->major = ttymajor;
1898 mxvar_sdriver->minor_start = 0;
1899 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1900 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1901 mxvar_sdriver->init_termios = tty_std_termios;
1902 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1903 tty_set_operations(mxvar_sdriver, &mxser_ops);
1904
1905 retval = tty_register_driver(mxvar_sdriver);
1906 if (retval) {
1907 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
1908 "tty driver !\n");
1909 goto err_put;
1910 }
1911
1912 retval = pci_register_driver(&mxser_driver);
1913 if (retval) {
1914 printk(KERN_ERR "mxser: can't register pci driver\n");
1915 goto err_unr;
1916 }
1917
1918 return 0;
1919err_unr:
1920 tty_unregister_driver(mxvar_sdriver);
1921err_put:
1922 tty_driver_kref_put(mxvar_sdriver);
1923 return retval;
1924}
1925
1926static void __exit mxser_module_exit(void)
1927{
1928 pci_unregister_driver(&mxser_driver);
1929 tty_unregister_driver(mxvar_sdriver);
1930 tty_driver_kref_put(mxvar_sdriver);
1931}
1932
1933module_init(mxser_module_init);
1934module_exit(mxser_module_exit);