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1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005-2009 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21#include <linux/time.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/byteorder.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_host.h>
35#include <scsi/scsi_tcq.h>
36#include <scsi/scsi_dbg.h>
37#include <scsi/scsi_eh.h>
38
39#define DRV_NAME "stex"
40#define ST_DRIVER_VERSION "4.6.0000.4"
41#define ST_VER_MAJOR 4
42#define ST_VER_MINOR 6
43#define ST_OEM 0
44#define ST_BUILD_VER 4
45
46enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 YIOA_STATUS = 0x00,
60 YH2I_INT = 0x20,
61 YINT_EN = 0x34,
62 YI2H_INT = 0x9c,
63 YI2H_INT_C = 0xa0,
64 YH2I_REQ = 0xc0,
65 YH2I_REQ_HI = 0xc4,
66
67 /* MU register value */
68 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
69 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
70 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
71 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
72 MU_INBOUND_DOORBELL_RESET = (1 << 4),
73
74 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
75 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
76 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
77 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
78 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
79 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
80
81 /* MU status code */
82 MU_STATE_STARTING = 1,
83 MU_STATE_STARTED = 2,
84 MU_STATE_RESETTING = 3,
85 MU_STATE_FAILED = 4,
86
87 MU_MAX_DELAY = 120,
88 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
89 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
90 MU_HARD_RESET_WAIT = 30000,
91 HMU_PARTNER_TYPE = 2,
92
93 /* firmware returned values */
94 SRB_STATUS_SUCCESS = 0x01,
95 SRB_STATUS_ERROR = 0x04,
96 SRB_STATUS_BUSY = 0x05,
97 SRB_STATUS_INVALID_REQUEST = 0x06,
98 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
99 SRB_SEE_SENSE = 0x80,
100
101 /* task attribute */
102 TASK_ATTRIBUTE_SIMPLE = 0x0,
103 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
104 TASK_ATTRIBUTE_ORDERED = 0x2,
105 TASK_ATTRIBUTE_ACA = 0x4,
106
107 SS_STS_NORMAL = 0x80000000,
108 SS_STS_DONE = 0x40000000,
109 SS_STS_HANDSHAKE = 0x20000000,
110
111 SS_HEAD_HANDSHAKE = 0x80,
112
113 SS_H2I_INT_RESET = 0x100,
114
115 SS_I2H_REQUEST_RESET = 0x2000,
116
117 SS_MU_OPERATIONAL = 0x80000000,
118
119 STEX_CDB_LENGTH = 16,
120 STATUS_VAR_LEN = 128,
121
122 /* sg flags */
123 SG_CF_EOT = 0x80, /* end of table */
124 SG_CF_64B = 0x40, /* 64 bit item */
125 SG_CF_HOST = 0x20, /* sg in host memory */
126 MSG_DATA_DIR_ND = 0,
127 MSG_DATA_DIR_IN = 1,
128 MSG_DATA_DIR_OUT = 2,
129
130 st_shasta = 0,
131 st_vsc = 1,
132 st_yosemite = 2,
133 st_seq = 3,
134 st_yel = 4,
135
136 PASSTHRU_REQ_TYPE = 0x00000001,
137 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
138 ST_INTERNAL_TIMEOUT = 180,
139
140 ST_TO_CMD = 0,
141 ST_FROM_CMD = 1,
142
143 /* vendor specific commands of Promise */
144 MGT_CMD = 0xd8,
145 SINBAND_MGT_CMD = 0xd9,
146 ARRAY_CMD = 0xe0,
147 CONTROLLER_CMD = 0xe1,
148 DEBUGGING_CMD = 0xe2,
149 PASSTHRU_CMD = 0xe3,
150
151 PASSTHRU_GET_ADAPTER = 0x05,
152 PASSTHRU_GET_DRVVER = 0x10,
153
154 CTLR_CONFIG_CMD = 0x03,
155 CTLR_SHUTDOWN = 0x0d,
156
157 CTLR_POWER_STATE_CHANGE = 0x0e,
158 CTLR_POWER_SAVING = 0x01,
159
160 PASSTHRU_SIGNATURE = 0x4e415041,
161 MGT_CMD_SIGNATURE = 0xba,
162
163 INQUIRY_EVPD = 0x01,
164
165 ST_ADDITIONAL_MEM = 0x200000,
166 ST_ADDITIONAL_MEM_MIN = 0x80000,
167};
168
169struct st_sgitem {
170 u8 ctrl; /* SG_CF_xxx */
171 u8 reserved[3];
172 __le32 count;
173 __le64 addr;
174};
175
176struct st_ss_sgitem {
177 __le32 addr;
178 __le32 addr_hi;
179 __le32 count;
180};
181
182struct st_sgtable {
183 __le16 sg_count;
184 __le16 max_sg_count;
185 __le32 sz_in_byte;
186};
187
188struct st_msg_header {
189 __le64 handle;
190 u8 flag;
191 u8 channel;
192 __le16 timeout;
193 u32 reserved;
194};
195
196struct handshake_frame {
197 __le64 rb_phy; /* request payload queue physical address */
198 __le16 req_sz; /* size of each request payload */
199 __le16 req_cnt; /* count of reqs the buffer can hold */
200 __le16 status_sz; /* size of each status payload */
201 __le16 status_cnt; /* count of status the buffer can hold */
202 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
203 u8 partner_type; /* who sends this frame */
204 u8 reserved0[7];
205 __le32 partner_ver_major;
206 __le32 partner_ver_minor;
207 __le32 partner_ver_oem;
208 __le32 partner_ver_build;
209 __le32 extra_offset; /* NEW */
210 __le32 extra_size; /* NEW */
211 __le32 scratch_size;
212 u32 reserved1;
213};
214
215struct req_msg {
216 __le16 tag;
217 u8 lun;
218 u8 target;
219 u8 task_attr;
220 u8 task_manage;
221 u8 data_dir;
222 u8 payload_sz; /* payload size in 4-byte, not used */
223 u8 cdb[STEX_CDB_LENGTH];
224 u32 variable[0];
225};
226
227struct status_msg {
228 __le16 tag;
229 u8 lun;
230 u8 target;
231 u8 srb_status;
232 u8 scsi_status;
233 u8 reserved;
234 u8 payload_sz; /* payload size in 4-byte */
235 u8 variable[STATUS_VAR_LEN];
236};
237
238struct ver_info {
239 u32 major;
240 u32 minor;
241 u32 oem;
242 u32 build;
243 u32 reserved[2];
244};
245
246struct st_frame {
247 u32 base[6];
248 u32 rom_addr;
249
250 struct ver_info drv_ver;
251 struct ver_info bios_ver;
252
253 u32 bus;
254 u32 slot;
255 u32 irq_level;
256 u32 irq_vec;
257 u32 id;
258 u32 subid;
259
260 u32 dimm_size;
261 u8 dimm_type;
262 u8 reserved[3];
263
264 u32 channel;
265 u32 reserved1;
266};
267
268struct st_drvver {
269 u32 major;
270 u32 minor;
271 u32 oem;
272 u32 build;
273 u32 signature[2];
274 u8 console_id;
275 u8 host_no;
276 u8 reserved0[2];
277 u32 reserved[3];
278};
279
280struct st_ccb {
281 struct req_msg *req;
282 struct scsi_cmnd *cmd;
283
284 void *sense_buffer;
285 unsigned int sense_bufflen;
286 int sg_count;
287
288 u32 req_type;
289 u8 srb_status;
290 u8 scsi_status;
291 u8 reserved[2];
292};
293
294struct st_hba {
295 void __iomem *mmio_base; /* iomapped PCI memory space */
296 void *dma_mem;
297 dma_addr_t dma_handle;
298 size_t dma_size;
299
300 struct Scsi_Host *host;
301 struct pci_dev *pdev;
302
303 struct req_msg * (*alloc_rq) (struct st_hba *);
304 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
305 void (*send) (struct st_hba *, struct req_msg *, u16);
306
307 u32 req_head;
308 u32 req_tail;
309 u32 status_head;
310 u32 status_tail;
311
312 struct status_msg *status_buffer;
313 void *copy_buffer; /* temp buffer for driver-handled commands */
314 struct st_ccb *ccb;
315 struct st_ccb *wait_ccb;
316 __le32 *scratch;
317
318 char work_q_name[20];
319 struct workqueue_struct *work_q;
320 struct work_struct reset_work;
321 wait_queue_head_t reset_waitq;
322 unsigned int mu_status;
323 unsigned int cardtype;
324 int msi_enabled;
325 int out_req_cnt;
326 u32 extra_offset;
327 u16 rq_count;
328 u16 rq_size;
329 u16 sts_count;
330};
331
332struct st_card_info {
333 struct req_msg * (*alloc_rq) (struct st_hba *);
334 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
335 void (*send) (struct st_hba *, struct req_msg *, u16);
336 unsigned int max_id;
337 unsigned int max_lun;
338 unsigned int max_channel;
339 u16 rq_count;
340 u16 rq_size;
341 u16 sts_count;
342};
343
344static int msi;
345module_param(msi, int, 0);
346MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
347
348static const char console_inq_page[] =
349{
350 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
351 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
352 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
353 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
354 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
355 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
356 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
357 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
358};
359
360MODULE_AUTHOR("Ed Lin");
361MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
362MODULE_LICENSE("GPL");
363MODULE_VERSION(ST_DRIVER_VERSION);
364
365static void stex_gettime(__le64 *time)
366{
367 struct timeval tv;
368
369 do_gettimeofday(&tv);
370 *time = cpu_to_le64(tv.tv_sec);
371}
372
373static struct status_msg *stex_get_status(struct st_hba *hba)
374{
375 struct status_msg *status = hba->status_buffer + hba->status_tail;
376
377 ++hba->status_tail;
378 hba->status_tail %= hba->sts_count+1;
379
380 return status;
381}
382
383static void stex_invalid_field(struct scsi_cmnd *cmd,
384 void (*done)(struct scsi_cmnd *))
385{
386 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
387
388 /* "Invalid field in cdb" */
389 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
390 0x0);
391 done(cmd);
392}
393
394static struct req_msg *stex_alloc_req(struct st_hba *hba)
395{
396 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
397
398 ++hba->req_head;
399 hba->req_head %= hba->rq_count+1;
400
401 return req;
402}
403
404static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
405{
406 return (struct req_msg *)(hba->dma_mem +
407 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
408}
409
410static int stex_map_sg(struct st_hba *hba,
411 struct req_msg *req, struct st_ccb *ccb)
412{
413 struct scsi_cmnd *cmd;
414 struct scatterlist *sg;
415 struct st_sgtable *dst;
416 struct st_sgitem *table;
417 int i, nseg;
418
419 cmd = ccb->cmd;
420 nseg = scsi_dma_map(cmd);
421 BUG_ON(nseg < 0);
422 if (nseg) {
423 dst = (struct st_sgtable *)req->variable;
424
425 ccb->sg_count = nseg;
426 dst->sg_count = cpu_to_le16((u16)nseg);
427 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
428 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
429
430 table = (struct st_sgitem *)(dst + 1);
431 scsi_for_each_sg(cmd, sg, nseg, i) {
432 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
433 table[i].addr = cpu_to_le64(sg_dma_address(sg));
434 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
435 }
436 table[--i].ctrl |= SG_CF_EOT;
437 }
438
439 return nseg;
440}
441
442static int stex_ss_map_sg(struct st_hba *hba,
443 struct req_msg *req, struct st_ccb *ccb)
444{
445 struct scsi_cmnd *cmd;
446 struct scatterlist *sg;
447 struct st_sgtable *dst;
448 struct st_ss_sgitem *table;
449 int i, nseg;
450
451 cmd = ccb->cmd;
452 nseg = scsi_dma_map(cmd);
453 BUG_ON(nseg < 0);
454 if (nseg) {
455 dst = (struct st_sgtable *)req->variable;
456
457 ccb->sg_count = nseg;
458 dst->sg_count = cpu_to_le16((u16)nseg);
459 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
460 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
461
462 table = (struct st_ss_sgitem *)(dst + 1);
463 scsi_for_each_sg(cmd, sg, nseg, i) {
464 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
465 table[i].addr =
466 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
467 table[i].addr_hi =
468 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
469 }
470 }
471
472 return nseg;
473}
474
475static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
476{
477 struct st_frame *p;
478 size_t count = sizeof(struct st_frame);
479
480 p = hba->copy_buffer;
481 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
482 memset(p->base, 0, sizeof(u32)*6);
483 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
484 p->rom_addr = 0;
485
486 p->drv_ver.major = ST_VER_MAJOR;
487 p->drv_ver.minor = ST_VER_MINOR;
488 p->drv_ver.oem = ST_OEM;
489 p->drv_ver.build = ST_BUILD_VER;
490
491 p->bus = hba->pdev->bus->number;
492 p->slot = hba->pdev->devfn;
493 p->irq_level = 0;
494 p->irq_vec = hba->pdev->irq;
495 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
496 p->subid =
497 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
498
499 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
500}
501
502static void
503stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
504{
505 req->tag = cpu_to_le16(tag);
506
507 hba->ccb[tag].req = req;
508 hba->out_req_cnt++;
509
510 writel(hba->req_head, hba->mmio_base + IMR0);
511 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
512 readl(hba->mmio_base + IDBL); /* flush */
513}
514
515static void
516stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
517{
518 struct scsi_cmnd *cmd;
519 struct st_msg_header *msg_h;
520 dma_addr_t addr;
521
522 req->tag = cpu_to_le16(tag);
523
524 hba->ccb[tag].req = req;
525 hba->out_req_cnt++;
526
527 cmd = hba->ccb[tag].cmd;
528 msg_h = (struct st_msg_header *)req - 1;
529 if (likely(cmd)) {
530 msg_h->channel = (u8)cmd->device->channel;
531 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
532 }
533 addr = hba->dma_handle + hba->req_head * hba->rq_size;
534 addr += (hba->ccb[tag].sg_count+4)/11;
535 msg_h->handle = cpu_to_le64(addr);
536
537 ++hba->req_head;
538 hba->req_head %= hba->rq_count+1;
539
540 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
541 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
542 writel(addr, hba->mmio_base + YH2I_REQ);
543 readl(hba->mmio_base + YH2I_REQ); /* flush */
544}
545
546static int
547stex_slave_alloc(struct scsi_device *sdev)
548{
549 /* Cheat: usually extracted from Inquiry data */
550 sdev->tagged_supported = 1;
551
552 scsi_activate_tcq(sdev, sdev->host->can_queue);
553
554 return 0;
555}
556
557static int
558stex_slave_config(struct scsi_device *sdev)
559{
560 sdev->use_10_for_rw = 1;
561 sdev->use_10_for_ms = 1;
562 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
563 sdev->tagged_supported = 1;
564
565 return 0;
566}
567
568static void
569stex_slave_destroy(struct scsi_device *sdev)
570{
571 scsi_deactivate_tcq(sdev, 1);
572}
573
574static int
575stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
576{
577 struct st_hba *hba;
578 struct Scsi_Host *host;
579 unsigned int id, lun;
580 struct req_msg *req;
581 u16 tag;
582
583 host = cmd->device->host;
584 id = cmd->device->id;
585 lun = cmd->device->lun;
586 hba = (struct st_hba *) &host->hostdata[0];
587
588 if (unlikely(hba->mu_status == MU_STATE_RESETTING))
589 return SCSI_MLQUEUE_HOST_BUSY;
590
591 switch (cmd->cmnd[0]) {
592 case MODE_SENSE_10:
593 {
594 static char ms10_caching_page[12] =
595 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
596 unsigned char page;
597
598 page = cmd->cmnd[2] & 0x3f;
599 if (page == 0x8 || page == 0x3f) {
600 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
601 sizeof(ms10_caching_page));
602 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
603 done(cmd);
604 } else
605 stex_invalid_field(cmd, done);
606 return 0;
607 }
608 case REPORT_LUNS:
609 /*
610 * The shasta firmware does not report actual luns in the
611 * target, so fail the command to force sequential lun scan.
612 * Also, the console device does not support this command.
613 */
614 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
615 stex_invalid_field(cmd, done);
616 return 0;
617 }
618 break;
619 case TEST_UNIT_READY:
620 if (id == host->max_id - 1) {
621 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
622 done(cmd);
623 return 0;
624 }
625 break;
626 case INQUIRY:
627 if (lun >= host->max_lun) {
628 cmd->result = DID_NO_CONNECT << 16;
629 done(cmd);
630 return 0;
631 }
632 if (id != host->max_id - 1)
633 break;
634 if (!lun && !cmd->device->channel &&
635 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
636 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
637 sizeof(console_inq_page));
638 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
639 done(cmd);
640 } else
641 stex_invalid_field(cmd, done);
642 return 0;
643 case PASSTHRU_CMD:
644 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
645 struct st_drvver ver;
646 size_t cp_len = sizeof(ver);
647
648 ver.major = ST_VER_MAJOR;
649 ver.minor = ST_VER_MINOR;
650 ver.oem = ST_OEM;
651 ver.build = ST_BUILD_VER;
652 ver.signature[0] = PASSTHRU_SIGNATURE;
653 ver.console_id = host->max_id - 1;
654 ver.host_no = hba->host->host_no;
655 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
656 cmd->result = sizeof(ver) == cp_len ?
657 DID_OK << 16 | COMMAND_COMPLETE << 8 :
658 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
659 done(cmd);
660 return 0;
661 }
662 default:
663 break;
664 }
665
666 cmd->scsi_done = done;
667
668 tag = cmd->request->tag;
669
670 if (unlikely(tag >= host->can_queue))
671 return SCSI_MLQUEUE_HOST_BUSY;
672
673 req = hba->alloc_rq(hba);
674
675 req->lun = lun;
676 req->target = id;
677
678 /* cdb */
679 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
680
681 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
682 req->data_dir = MSG_DATA_DIR_IN;
683 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
684 req->data_dir = MSG_DATA_DIR_OUT;
685 else
686 req->data_dir = MSG_DATA_DIR_ND;
687
688 hba->ccb[tag].cmd = cmd;
689 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
690 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
691
692 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
693 hba->ccb[tag].sg_count = 0;
694 memset(&req->variable[0], 0, 8);
695 }
696
697 hba->send(hba, req, tag);
698 return 0;
699}
700
701static DEF_SCSI_QCMD(stex_queuecommand)
702
703static void stex_scsi_done(struct st_ccb *ccb)
704{
705 struct scsi_cmnd *cmd = ccb->cmd;
706 int result;
707
708 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
709 result = ccb->scsi_status;
710 switch (ccb->scsi_status) {
711 case SAM_STAT_GOOD:
712 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
713 break;
714 case SAM_STAT_CHECK_CONDITION:
715 result |= DRIVER_SENSE << 24;
716 break;
717 case SAM_STAT_BUSY:
718 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
719 break;
720 default:
721 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
722 break;
723 }
724 }
725 else if (ccb->srb_status & SRB_SEE_SENSE)
726 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
727 else switch (ccb->srb_status) {
728 case SRB_STATUS_SELECTION_TIMEOUT:
729 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
730 break;
731 case SRB_STATUS_BUSY:
732 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
733 break;
734 case SRB_STATUS_INVALID_REQUEST:
735 case SRB_STATUS_ERROR:
736 default:
737 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
738 break;
739 }
740
741 cmd->result = result;
742 cmd->scsi_done(cmd);
743}
744
745static void stex_copy_data(struct st_ccb *ccb,
746 struct status_msg *resp, unsigned int variable)
747{
748 if (resp->scsi_status != SAM_STAT_GOOD) {
749 if (ccb->sense_buffer != NULL)
750 memcpy(ccb->sense_buffer, resp->variable,
751 min(variable, ccb->sense_bufflen));
752 return;
753 }
754
755 if (ccb->cmd == NULL)
756 return;
757 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
758}
759
760static void stex_check_cmd(struct st_hba *hba,
761 struct st_ccb *ccb, struct status_msg *resp)
762{
763 if (ccb->cmd->cmnd[0] == MGT_CMD &&
764 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
765 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
766 le32_to_cpu(*(__le32 *)&resp->variable[0]));
767}
768
769static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
770{
771 void __iomem *base = hba->mmio_base;
772 struct status_msg *resp;
773 struct st_ccb *ccb;
774 unsigned int size;
775 u16 tag;
776
777 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
778 return;
779
780 /* status payloads */
781 hba->status_head = readl(base + OMR1);
782 if (unlikely(hba->status_head > hba->sts_count)) {
783 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
784 pci_name(hba->pdev));
785 return;
786 }
787
788 /*
789 * it's not a valid status payload if:
790 * 1. there are no pending requests(e.g. during init stage)
791 * 2. there are some pending requests, but the controller is in
792 * reset status, and its type is not st_yosemite
793 * firmware of st_yosemite in reset status will return pending requests
794 * to driver, so we allow it to pass
795 */
796 if (unlikely(hba->out_req_cnt <= 0 ||
797 (hba->mu_status == MU_STATE_RESETTING &&
798 hba->cardtype != st_yosemite))) {
799 hba->status_tail = hba->status_head;
800 goto update_status;
801 }
802
803 while (hba->status_tail != hba->status_head) {
804 resp = stex_get_status(hba);
805 tag = le16_to_cpu(resp->tag);
806 if (unlikely(tag >= hba->host->can_queue)) {
807 printk(KERN_WARNING DRV_NAME
808 "(%s): invalid tag\n", pci_name(hba->pdev));
809 continue;
810 }
811
812 hba->out_req_cnt--;
813 ccb = &hba->ccb[tag];
814 if (unlikely(hba->wait_ccb == ccb))
815 hba->wait_ccb = NULL;
816 if (unlikely(ccb->req == NULL)) {
817 printk(KERN_WARNING DRV_NAME
818 "(%s): lagging req\n", pci_name(hba->pdev));
819 continue;
820 }
821
822 size = resp->payload_sz * sizeof(u32); /* payload size */
823 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
824 size > sizeof(*resp))) {
825 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
826 pci_name(hba->pdev));
827 } else {
828 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
829 if (size)
830 stex_copy_data(ccb, resp, size);
831 }
832
833 ccb->req = NULL;
834 ccb->srb_status = resp->srb_status;
835 ccb->scsi_status = resp->scsi_status;
836
837 if (likely(ccb->cmd != NULL)) {
838 if (hba->cardtype == st_yosemite)
839 stex_check_cmd(hba, ccb, resp);
840
841 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
842 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
843 stex_controller_info(hba, ccb);
844
845 scsi_dma_unmap(ccb->cmd);
846 stex_scsi_done(ccb);
847 } else
848 ccb->req_type = 0;
849 }
850
851update_status:
852 writel(hba->status_head, base + IMR1);
853 readl(base + IMR1); /* flush */
854}
855
856static irqreturn_t stex_intr(int irq, void *__hba)
857{
858 struct st_hba *hba = __hba;
859 void __iomem *base = hba->mmio_base;
860 u32 data;
861 unsigned long flags;
862
863 spin_lock_irqsave(hba->host->host_lock, flags);
864
865 data = readl(base + ODBL);
866
867 if (data && data != 0xffffffff) {
868 /* clear the interrupt */
869 writel(data, base + ODBL);
870 readl(base + ODBL); /* flush */
871 stex_mu_intr(hba, data);
872 spin_unlock_irqrestore(hba->host->host_lock, flags);
873 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
874 hba->cardtype == st_shasta))
875 queue_work(hba->work_q, &hba->reset_work);
876 return IRQ_HANDLED;
877 }
878
879 spin_unlock_irqrestore(hba->host->host_lock, flags);
880
881 return IRQ_NONE;
882}
883
884static void stex_ss_mu_intr(struct st_hba *hba)
885{
886 struct status_msg *resp;
887 struct st_ccb *ccb;
888 __le32 *scratch;
889 unsigned int size;
890 int count = 0;
891 u32 value;
892 u16 tag;
893
894 if (unlikely(hba->out_req_cnt <= 0 ||
895 hba->mu_status == MU_STATE_RESETTING))
896 return;
897
898 while (count < hba->sts_count) {
899 scratch = hba->scratch + hba->status_tail;
900 value = le32_to_cpu(*scratch);
901 if (unlikely(!(value & SS_STS_NORMAL)))
902 return;
903
904 resp = hba->status_buffer + hba->status_tail;
905 *scratch = 0;
906 ++count;
907 ++hba->status_tail;
908 hba->status_tail %= hba->sts_count+1;
909
910 tag = (u16)value;
911 if (unlikely(tag >= hba->host->can_queue)) {
912 printk(KERN_WARNING DRV_NAME
913 "(%s): invalid tag\n", pci_name(hba->pdev));
914 continue;
915 }
916
917 hba->out_req_cnt--;
918 ccb = &hba->ccb[tag];
919 if (unlikely(hba->wait_ccb == ccb))
920 hba->wait_ccb = NULL;
921 if (unlikely(ccb->req == NULL)) {
922 printk(KERN_WARNING DRV_NAME
923 "(%s): lagging req\n", pci_name(hba->pdev));
924 continue;
925 }
926
927 ccb->req = NULL;
928 if (likely(value & SS_STS_DONE)) { /* normal case */
929 ccb->srb_status = SRB_STATUS_SUCCESS;
930 ccb->scsi_status = SAM_STAT_GOOD;
931 } else {
932 ccb->srb_status = resp->srb_status;
933 ccb->scsi_status = resp->scsi_status;
934 size = resp->payload_sz * sizeof(u32);
935 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
936 size > sizeof(*resp))) {
937 printk(KERN_WARNING DRV_NAME
938 "(%s): bad status size\n",
939 pci_name(hba->pdev));
940 } else {
941 size -= sizeof(*resp) - STATUS_VAR_LEN;
942 if (size)
943 stex_copy_data(ccb, resp, size);
944 }
945 if (likely(ccb->cmd != NULL))
946 stex_check_cmd(hba, ccb, resp);
947 }
948
949 if (likely(ccb->cmd != NULL)) {
950 scsi_dma_unmap(ccb->cmd);
951 stex_scsi_done(ccb);
952 } else
953 ccb->req_type = 0;
954 }
955}
956
957static irqreturn_t stex_ss_intr(int irq, void *__hba)
958{
959 struct st_hba *hba = __hba;
960 void __iomem *base = hba->mmio_base;
961 u32 data;
962 unsigned long flags;
963
964 spin_lock_irqsave(hba->host->host_lock, flags);
965
966 data = readl(base + YI2H_INT);
967 if (data && data != 0xffffffff) {
968 /* clear the interrupt */
969 writel(data, base + YI2H_INT_C);
970 stex_ss_mu_intr(hba);
971 spin_unlock_irqrestore(hba->host->host_lock, flags);
972 if (unlikely(data & SS_I2H_REQUEST_RESET))
973 queue_work(hba->work_q, &hba->reset_work);
974 return IRQ_HANDLED;
975 }
976
977 spin_unlock_irqrestore(hba->host->host_lock, flags);
978
979 return IRQ_NONE;
980}
981
982static int stex_common_handshake(struct st_hba *hba)
983{
984 void __iomem *base = hba->mmio_base;
985 struct handshake_frame *h;
986 dma_addr_t status_phys;
987 u32 data;
988 unsigned long before;
989
990 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
991 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
992 readl(base + IDBL);
993 before = jiffies;
994 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
995 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
996 printk(KERN_ERR DRV_NAME
997 "(%s): no handshake signature\n",
998 pci_name(hba->pdev));
999 return -1;
1000 }
1001 rmb();
1002 msleep(1);
1003 }
1004 }
1005
1006 udelay(10);
1007
1008 data = readl(base + OMR1);
1009 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1010 data &= 0x0000ffff;
1011 if (hba->host->can_queue > data) {
1012 hba->host->can_queue = data;
1013 hba->host->cmd_per_lun = data;
1014 }
1015 }
1016
1017 h = (struct handshake_frame *)hba->status_buffer;
1018 h->rb_phy = cpu_to_le64(hba->dma_handle);
1019 h->req_sz = cpu_to_le16(hba->rq_size);
1020 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1021 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1022 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1023 stex_gettime(&h->hosttime);
1024 h->partner_type = HMU_PARTNER_TYPE;
1025 if (hba->extra_offset) {
1026 h->extra_offset = cpu_to_le32(hba->extra_offset);
1027 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1028 } else
1029 h->extra_offset = h->extra_size = 0;
1030
1031 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1032 writel(status_phys, base + IMR0);
1033 readl(base + IMR0);
1034 writel((status_phys >> 16) >> 16, base + IMR1);
1035 readl(base + IMR1);
1036
1037 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1038 readl(base + OMR0);
1039 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1040 readl(base + IDBL); /* flush */
1041
1042 udelay(10);
1043 before = jiffies;
1044 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1045 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1046 printk(KERN_ERR DRV_NAME
1047 "(%s): no signature after handshake frame\n",
1048 pci_name(hba->pdev));
1049 return -1;
1050 }
1051 rmb();
1052 msleep(1);
1053 }
1054
1055 writel(0, base + IMR0);
1056 readl(base + IMR0);
1057 writel(0, base + OMR0);
1058 readl(base + OMR0);
1059 writel(0, base + IMR1);
1060 readl(base + IMR1);
1061 writel(0, base + OMR1);
1062 readl(base + OMR1); /* flush */
1063 return 0;
1064}
1065
1066static int stex_ss_handshake(struct st_hba *hba)
1067{
1068 void __iomem *base = hba->mmio_base;
1069 struct st_msg_header *msg_h;
1070 struct handshake_frame *h;
1071 __le32 *scratch;
1072 u32 data, scratch_size;
1073 unsigned long before;
1074 int ret = 0;
1075
1076 before = jiffies;
1077 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1078 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1079 printk(KERN_ERR DRV_NAME
1080 "(%s): firmware not operational\n",
1081 pci_name(hba->pdev));
1082 return -1;
1083 }
1084 msleep(1);
1085 }
1086
1087 msg_h = (struct st_msg_header *)hba->dma_mem;
1088 msg_h->handle = cpu_to_le64(hba->dma_handle);
1089 msg_h->flag = SS_HEAD_HANDSHAKE;
1090
1091 h = (struct handshake_frame *)(msg_h + 1);
1092 h->rb_phy = cpu_to_le64(hba->dma_handle);
1093 h->req_sz = cpu_to_le16(hba->rq_size);
1094 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1095 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1096 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1097 stex_gettime(&h->hosttime);
1098 h->partner_type = HMU_PARTNER_TYPE;
1099 h->extra_offset = h->extra_size = 0;
1100 scratch_size = (hba->sts_count+1)*sizeof(u32);
1101 h->scratch_size = cpu_to_le32(scratch_size);
1102
1103 data = readl(base + YINT_EN);
1104 data &= ~4;
1105 writel(data, base + YINT_EN);
1106 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1107 readl(base + YH2I_REQ_HI);
1108 writel(hba->dma_handle, base + YH2I_REQ);
1109 readl(base + YH2I_REQ); /* flush */
1110
1111 scratch = hba->scratch;
1112 before = jiffies;
1113 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1114 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1115 printk(KERN_ERR DRV_NAME
1116 "(%s): no signature after handshake frame\n",
1117 pci_name(hba->pdev));
1118 ret = -1;
1119 break;
1120 }
1121 rmb();
1122 msleep(1);
1123 }
1124
1125 memset(scratch, 0, scratch_size);
1126 msg_h->flag = 0;
1127 return ret;
1128}
1129
1130static int stex_handshake(struct st_hba *hba)
1131{
1132 int err;
1133 unsigned long flags;
1134 unsigned int mu_status;
1135
1136 err = (hba->cardtype == st_yel) ?
1137 stex_ss_handshake(hba) : stex_common_handshake(hba);
1138 spin_lock_irqsave(hba->host->host_lock, flags);
1139 mu_status = hba->mu_status;
1140 if (err == 0) {
1141 hba->req_head = 0;
1142 hba->req_tail = 0;
1143 hba->status_head = 0;
1144 hba->status_tail = 0;
1145 hba->out_req_cnt = 0;
1146 hba->mu_status = MU_STATE_STARTED;
1147 } else
1148 hba->mu_status = MU_STATE_FAILED;
1149 if (mu_status == MU_STATE_RESETTING)
1150 wake_up_all(&hba->reset_waitq);
1151 spin_unlock_irqrestore(hba->host->host_lock, flags);
1152 return err;
1153}
1154
1155static int stex_abort(struct scsi_cmnd *cmd)
1156{
1157 struct Scsi_Host *host = cmd->device->host;
1158 struct st_hba *hba = (struct st_hba *)host->hostdata;
1159 u16 tag = cmd->request->tag;
1160 void __iomem *base;
1161 u32 data;
1162 int result = SUCCESS;
1163 unsigned long flags;
1164
1165 printk(KERN_INFO DRV_NAME
1166 "(%s): aborting command\n", pci_name(hba->pdev));
1167 scsi_print_command(cmd);
1168
1169 base = hba->mmio_base;
1170 spin_lock_irqsave(host->host_lock, flags);
1171 if (tag < host->can_queue &&
1172 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1173 hba->wait_ccb = &hba->ccb[tag];
1174 else
1175 goto out;
1176
1177 if (hba->cardtype == st_yel) {
1178 data = readl(base + YI2H_INT);
1179 if (data == 0 || data == 0xffffffff)
1180 goto fail_out;
1181
1182 writel(data, base + YI2H_INT_C);
1183 stex_ss_mu_intr(hba);
1184 } else {
1185 data = readl(base + ODBL);
1186 if (data == 0 || data == 0xffffffff)
1187 goto fail_out;
1188
1189 writel(data, base + ODBL);
1190 readl(base + ODBL); /* flush */
1191
1192 stex_mu_intr(hba, data);
1193 }
1194 if (hba->wait_ccb == NULL) {
1195 printk(KERN_WARNING DRV_NAME
1196 "(%s): lost interrupt\n", pci_name(hba->pdev));
1197 goto out;
1198 }
1199
1200fail_out:
1201 scsi_dma_unmap(cmd);
1202 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1203 hba->wait_ccb = NULL;
1204 result = FAILED;
1205out:
1206 spin_unlock_irqrestore(host->host_lock, flags);
1207 return result;
1208}
1209
1210static void stex_hard_reset(struct st_hba *hba)
1211{
1212 struct pci_bus *bus;
1213 int i;
1214 u16 pci_cmd;
1215 u8 pci_bctl;
1216
1217 for (i = 0; i < 16; i++)
1218 pci_read_config_dword(hba->pdev, i * 4,
1219 &hba->pdev->saved_config_space[i]);
1220
1221 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1222 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1223 bus = hba->pdev->bus;
1224 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1225 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1226 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1227
1228 /*
1229 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1230 * require more time to finish bus reset. Use 100 ms here for safety
1231 */
1232 msleep(100);
1233 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1234 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1235
1236 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1237 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1238 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1239 break;
1240 msleep(1);
1241 }
1242
1243 ssleep(5);
1244 for (i = 0; i < 16; i++)
1245 pci_write_config_dword(hba->pdev, i * 4,
1246 hba->pdev->saved_config_space[i]);
1247}
1248
1249static int stex_yos_reset(struct st_hba *hba)
1250{
1251 void __iomem *base;
1252 unsigned long flags, before;
1253 int ret = 0;
1254
1255 base = hba->mmio_base;
1256 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1257 readl(base + IDBL); /* flush */
1258 before = jiffies;
1259 while (hba->out_req_cnt > 0) {
1260 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1261 printk(KERN_WARNING DRV_NAME
1262 "(%s): reset timeout\n", pci_name(hba->pdev));
1263 ret = -1;
1264 break;
1265 }
1266 msleep(1);
1267 }
1268
1269 spin_lock_irqsave(hba->host->host_lock, flags);
1270 if (ret == -1)
1271 hba->mu_status = MU_STATE_FAILED;
1272 else
1273 hba->mu_status = MU_STATE_STARTED;
1274 wake_up_all(&hba->reset_waitq);
1275 spin_unlock_irqrestore(hba->host->host_lock, flags);
1276
1277 return ret;
1278}
1279
1280static void stex_ss_reset(struct st_hba *hba)
1281{
1282 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1283 readl(hba->mmio_base + YH2I_INT);
1284 ssleep(5);
1285}
1286
1287static int stex_do_reset(struct st_hba *hba)
1288{
1289 struct st_ccb *ccb;
1290 unsigned long flags;
1291 unsigned int mu_status = MU_STATE_RESETTING;
1292 u16 tag;
1293
1294 spin_lock_irqsave(hba->host->host_lock, flags);
1295 if (hba->mu_status == MU_STATE_STARTING) {
1296 spin_unlock_irqrestore(hba->host->host_lock, flags);
1297 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1298 pci_name(hba->pdev));
1299 return 0;
1300 }
1301 while (hba->mu_status == MU_STATE_RESETTING) {
1302 spin_unlock_irqrestore(hba->host->host_lock, flags);
1303 wait_event_timeout(hba->reset_waitq,
1304 hba->mu_status != MU_STATE_RESETTING,
1305 MU_MAX_DELAY * HZ);
1306 spin_lock_irqsave(hba->host->host_lock, flags);
1307 mu_status = hba->mu_status;
1308 }
1309
1310 if (mu_status != MU_STATE_RESETTING) {
1311 spin_unlock_irqrestore(hba->host->host_lock, flags);
1312 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1313 }
1314
1315 hba->mu_status = MU_STATE_RESETTING;
1316 spin_unlock_irqrestore(hba->host->host_lock, flags);
1317
1318 if (hba->cardtype == st_yosemite)
1319 return stex_yos_reset(hba);
1320
1321 if (hba->cardtype == st_shasta)
1322 stex_hard_reset(hba);
1323 else if (hba->cardtype == st_yel)
1324 stex_ss_reset(hba);
1325
1326 spin_lock_irqsave(hba->host->host_lock, flags);
1327 for (tag = 0; tag < hba->host->can_queue; tag++) {
1328 ccb = &hba->ccb[tag];
1329 if (ccb->req == NULL)
1330 continue;
1331 ccb->req = NULL;
1332 if (ccb->cmd) {
1333 scsi_dma_unmap(ccb->cmd);
1334 ccb->cmd->result = DID_RESET << 16;
1335 ccb->cmd->scsi_done(ccb->cmd);
1336 ccb->cmd = NULL;
1337 }
1338 }
1339 spin_unlock_irqrestore(hba->host->host_lock, flags);
1340
1341 if (stex_handshake(hba) == 0)
1342 return 0;
1343
1344 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1345 pci_name(hba->pdev));
1346 return -1;
1347}
1348
1349static int stex_reset(struct scsi_cmnd *cmd)
1350{
1351 struct st_hba *hba;
1352
1353 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1354
1355 printk(KERN_INFO DRV_NAME
1356 "(%s): resetting host\n", pci_name(hba->pdev));
1357 scsi_print_command(cmd);
1358
1359 return stex_do_reset(hba) ? FAILED : SUCCESS;
1360}
1361
1362static void stex_reset_work(struct work_struct *work)
1363{
1364 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1365
1366 stex_do_reset(hba);
1367}
1368
1369static int stex_biosparam(struct scsi_device *sdev,
1370 struct block_device *bdev, sector_t capacity, int geom[])
1371{
1372 int heads = 255, sectors = 63;
1373
1374 if (capacity < 0x200000) {
1375 heads = 64;
1376 sectors = 32;
1377 }
1378
1379 sector_div(capacity, heads * sectors);
1380
1381 geom[0] = heads;
1382 geom[1] = sectors;
1383 geom[2] = capacity;
1384
1385 return 0;
1386}
1387
1388static struct scsi_host_template driver_template = {
1389 .module = THIS_MODULE,
1390 .name = DRV_NAME,
1391 .proc_name = DRV_NAME,
1392 .bios_param = stex_biosparam,
1393 .queuecommand = stex_queuecommand,
1394 .slave_alloc = stex_slave_alloc,
1395 .slave_configure = stex_slave_config,
1396 .slave_destroy = stex_slave_destroy,
1397 .eh_abort_handler = stex_abort,
1398 .eh_host_reset_handler = stex_reset,
1399 .this_id = -1,
1400};
1401
1402static struct pci_device_id stex_pci_tbl[] = {
1403 /* st_shasta */
1404 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1405 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1406 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1407 st_shasta }, /* SuperTrak EX12350 */
1408 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1409 st_shasta }, /* SuperTrak EX4350 */
1410 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1411 st_shasta }, /* SuperTrak EX24350 */
1412
1413 /* st_vsc */
1414 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1415
1416 /* st_yosemite */
1417 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1418
1419 /* st_seq */
1420 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1421
1422 /* st_yel */
1423 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1424 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1425 { } /* terminate list */
1426};
1427
1428static struct st_card_info stex_card_info[] = {
1429 /* st_shasta */
1430 {
1431 .max_id = 17,
1432 .max_lun = 8,
1433 .max_channel = 0,
1434 .rq_count = 32,
1435 .rq_size = 1048,
1436 .sts_count = 32,
1437 .alloc_rq = stex_alloc_req,
1438 .map_sg = stex_map_sg,
1439 .send = stex_send_cmd,
1440 },
1441
1442 /* st_vsc */
1443 {
1444 .max_id = 129,
1445 .max_lun = 1,
1446 .max_channel = 0,
1447 .rq_count = 32,
1448 .rq_size = 1048,
1449 .sts_count = 32,
1450 .alloc_rq = stex_alloc_req,
1451 .map_sg = stex_map_sg,
1452 .send = stex_send_cmd,
1453 },
1454
1455 /* st_yosemite */
1456 {
1457 .max_id = 2,
1458 .max_lun = 256,
1459 .max_channel = 0,
1460 .rq_count = 256,
1461 .rq_size = 1048,
1462 .sts_count = 256,
1463 .alloc_rq = stex_alloc_req,
1464 .map_sg = stex_map_sg,
1465 .send = stex_send_cmd,
1466 },
1467
1468 /* st_seq */
1469 {
1470 .max_id = 129,
1471 .max_lun = 1,
1472 .max_channel = 0,
1473 .rq_count = 32,
1474 .rq_size = 1048,
1475 .sts_count = 32,
1476 .alloc_rq = stex_alloc_req,
1477 .map_sg = stex_map_sg,
1478 .send = stex_send_cmd,
1479 },
1480
1481 /* st_yel */
1482 {
1483 .max_id = 129,
1484 .max_lun = 256,
1485 .max_channel = 3,
1486 .rq_count = 801,
1487 .rq_size = 512,
1488 .sts_count = 801,
1489 .alloc_rq = stex_ss_alloc_req,
1490 .map_sg = stex_ss_map_sg,
1491 .send = stex_ss_send_cmd,
1492 },
1493};
1494
1495static int stex_set_dma_mask(struct pci_dev * pdev)
1496{
1497 int ret;
1498
1499 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1500 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1501 return 0;
1502 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1503 if (!ret)
1504 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1505 return ret;
1506}
1507
1508static int stex_request_irq(struct st_hba *hba)
1509{
1510 struct pci_dev *pdev = hba->pdev;
1511 int status;
1512
1513 if (msi) {
1514 status = pci_enable_msi(pdev);
1515 if (status != 0)
1516 printk(KERN_ERR DRV_NAME
1517 "(%s): error %d setting up MSI\n",
1518 pci_name(pdev), status);
1519 else
1520 hba->msi_enabled = 1;
1521 } else
1522 hba->msi_enabled = 0;
1523
1524 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1525 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1526
1527 if (status != 0) {
1528 if (hba->msi_enabled)
1529 pci_disable_msi(pdev);
1530 }
1531 return status;
1532}
1533
1534static void stex_free_irq(struct st_hba *hba)
1535{
1536 struct pci_dev *pdev = hba->pdev;
1537
1538 free_irq(pdev->irq, hba);
1539 if (hba->msi_enabled)
1540 pci_disable_msi(pdev);
1541}
1542
1543static int __devinit
1544stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1545{
1546 struct st_hba *hba;
1547 struct Scsi_Host *host;
1548 const struct st_card_info *ci = NULL;
1549 u32 sts_offset, cp_offset, scratch_offset;
1550 int err;
1551
1552 err = pci_enable_device(pdev);
1553 if (err)
1554 return err;
1555
1556 pci_set_master(pdev);
1557
1558 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1559
1560 if (!host) {
1561 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1562 pci_name(pdev));
1563 err = -ENOMEM;
1564 goto out_disable;
1565 }
1566
1567 hba = (struct st_hba *)host->hostdata;
1568 memset(hba, 0, sizeof(struct st_hba));
1569
1570 err = pci_request_regions(pdev, DRV_NAME);
1571 if (err < 0) {
1572 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1573 pci_name(pdev));
1574 goto out_scsi_host_put;
1575 }
1576
1577 hba->mmio_base = pci_ioremap_bar(pdev, 0);
1578 if ( !hba->mmio_base) {
1579 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1580 pci_name(pdev));
1581 err = -ENOMEM;
1582 goto out_release_regions;
1583 }
1584
1585 err = stex_set_dma_mask(pdev);
1586 if (err) {
1587 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1588 pci_name(pdev));
1589 goto out_iounmap;
1590 }
1591
1592 hba->cardtype = (unsigned int) id->driver_data;
1593 ci = &stex_card_info[hba->cardtype];
1594 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1595 if (hba->cardtype == st_yel)
1596 sts_offset += (ci->sts_count+1) * sizeof(u32);
1597 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1598 hba->dma_size = cp_offset + sizeof(struct st_frame);
1599 if (hba->cardtype == st_seq ||
1600 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1601 hba->extra_offset = hba->dma_size;
1602 hba->dma_size += ST_ADDITIONAL_MEM;
1603 }
1604 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1605 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1606 if (!hba->dma_mem) {
1607 /* Retry minimum coherent mapping for st_seq and st_vsc */
1608 if (hba->cardtype == st_seq ||
1609 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1610 printk(KERN_WARNING DRV_NAME
1611 "(%s): allocating min buffer for controller\n",
1612 pci_name(pdev));
1613 hba->dma_size = hba->extra_offset
1614 + ST_ADDITIONAL_MEM_MIN;
1615 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1616 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1617 }
1618
1619 if (!hba->dma_mem) {
1620 err = -ENOMEM;
1621 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1622 pci_name(pdev));
1623 goto out_iounmap;
1624 }
1625 }
1626
1627 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1628 if (!hba->ccb) {
1629 err = -ENOMEM;
1630 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1631 pci_name(pdev));
1632 goto out_pci_free;
1633 }
1634
1635 if (hba->cardtype == st_yel)
1636 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1637 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1638 hba->copy_buffer = hba->dma_mem + cp_offset;
1639 hba->rq_count = ci->rq_count;
1640 hba->rq_size = ci->rq_size;
1641 hba->sts_count = ci->sts_count;
1642 hba->alloc_rq = ci->alloc_rq;
1643 hba->map_sg = ci->map_sg;
1644 hba->send = ci->send;
1645 hba->mu_status = MU_STATE_STARTING;
1646
1647 if (hba->cardtype == st_yel)
1648 host->sg_tablesize = 38;
1649 else
1650 host->sg_tablesize = 32;
1651 host->can_queue = ci->rq_count;
1652 host->cmd_per_lun = ci->rq_count;
1653 host->max_id = ci->max_id;
1654 host->max_lun = ci->max_lun;
1655 host->max_channel = ci->max_channel;
1656 host->unique_id = host->host_no;
1657 host->max_cmd_len = STEX_CDB_LENGTH;
1658
1659 hba->host = host;
1660 hba->pdev = pdev;
1661 init_waitqueue_head(&hba->reset_waitq);
1662
1663 snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1664 "stex_wq_%d", host->host_no);
1665 hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1666 if (!hba->work_q) {
1667 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1668 pci_name(pdev));
1669 err = -ENOMEM;
1670 goto out_ccb_free;
1671 }
1672 INIT_WORK(&hba->reset_work, stex_reset_work);
1673
1674 err = stex_request_irq(hba);
1675 if (err) {
1676 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1677 pci_name(pdev));
1678 goto out_free_wq;
1679 }
1680
1681 err = stex_handshake(hba);
1682 if (err)
1683 goto out_free_irq;
1684
1685 err = scsi_init_shared_tag_map(host, host->can_queue);
1686 if (err) {
1687 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1688 pci_name(pdev));
1689 goto out_free_irq;
1690 }
1691
1692 pci_set_drvdata(pdev, hba);
1693
1694 err = scsi_add_host(host, &pdev->dev);
1695 if (err) {
1696 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1697 pci_name(pdev));
1698 goto out_free_irq;
1699 }
1700
1701 scsi_scan_host(host);
1702
1703 return 0;
1704
1705out_free_irq:
1706 stex_free_irq(hba);
1707out_free_wq:
1708 destroy_workqueue(hba->work_q);
1709out_ccb_free:
1710 kfree(hba->ccb);
1711out_pci_free:
1712 dma_free_coherent(&pdev->dev, hba->dma_size,
1713 hba->dma_mem, hba->dma_handle);
1714out_iounmap:
1715 iounmap(hba->mmio_base);
1716out_release_regions:
1717 pci_release_regions(pdev);
1718out_scsi_host_put:
1719 scsi_host_put(host);
1720out_disable:
1721 pci_disable_device(pdev);
1722
1723 return err;
1724}
1725
1726static void stex_hba_stop(struct st_hba *hba)
1727{
1728 struct req_msg *req;
1729 struct st_msg_header *msg_h;
1730 unsigned long flags;
1731 unsigned long before;
1732 u16 tag = 0;
1733
1734 spin_lock_irqsave(hba->host->host_lock, flags);
1735 req = hba->alloc_rq(hba);
1736 if (hba->cardtype == st_yel) {
1737 msg_h = (struct st_msg_header *)req - 1;
1738 memset(msg_h, 0, hba->rq_size);
1739 } else
1740 memset(req, 0, hba->rq_size);
1741
1742 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1743 req->cdb[0] = MGT_CMD;
1744 req->cdb[1] = MGT_CMD_SIGNATURE;
1745 req->cdb[2] = CTLR_CONFIG_CMD;
1746 req->cdb[3] = CTLR_SHUTDOWN;
1747 } else {
1748 req->cdb[0] = CONTROLLER_CMD;
1749 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1750 req->cdb[2] = CTLR_POWER_SAVING;
1751 }
1752
1753 hba->ccb[tag].cmd = NULL;
1754 hba->ccb[tag].sg_count = 0;
1755 hba->ccb[tag].sense_bufflen = 0;
1756 hba->ccb[tag].sense_buffer = NULL;
1757 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1758
1759 hba->send(hba, req, tag);
1760 spin_unlock_irqrestore(hba->host->host_lock, flags);
1761
1762 before = jiffies;
1763 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1764 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1765 hba->ccb[tag].req_type = 0;
1766 return;
1767 }
1768 msleep(1);
1769 }
1770}
1771
1772static void stex_hba_free(struct st_hba *hba)
1773{
1774 stex_free_irq(hba);
1775
1776 destroy_workqueue(hba->work_q);
1777
1778 iounmap(hba->mmio_base);
1779
1780 pci_release_regions(hba->pdev);
1781
1782 kfree(hba->ccb);
1783
1784 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1785 hba->dma_mem, hba->dma_handle);
1786}
1787
1788static void stex_remove(struct pci_dev *pdev)
1789{
1790 struct st_hba *hba = pci_get_drvdata(pdev);
1791
1792 scsi_remove_host(hba->host);
1793
1794 pci_set_drvdata(pdev, NULL);
1795
1796 stex_hba_stop(hba);
1797
1798 stex_hba_free(hba);
1799
1800 scsi_host_put(hba->host);
1801
1802 pci_disable_device(pdev);
1803}
1804
1805static void stex_shutdown(struct pci_dev *pdev)
1806{
1807 struct st_hba *hba = pci_get_drvdata(pdev);
1808
1809 stex_hba_stop(hba);
1810}
1811
1812MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1813
1814static struct pci_driver stex_pci_driver = {
1815 .name = DRV_NAME,
1816 .id_table = stex_pci_tbl,
1817 .probe = stex_probe,
1818 .remove = __devexit_p(stex_remove),
1819 .shutdown = stex_shutdown,
1820};
1821
1822static int __init stex_init(void)
1823{
1824 printk(KERN_INFO DRV_NAME
1825 ": Promise SuperTrak EX Driver version: %s\n",
1826 ST_DRIVER_VERSION);
1827
1828 return pci_register_driver(&stex_pci_driver);
1829}
1830
1831static void __exit stex_exit(void)
1832{
1833 pci_unregister_driver(&stex_pci_driver);
1834}
1835
1836module_init(stex_init);
1837module_exit(stex_exit);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SuperTrak EX Series Storage Controller driver for Linux
4 *
5 * Copyright (C) 2005-2015 Promise Technology Inc.
6 *
7 * Written By:
8 * Ed Lin <promise_linux@promise.com>
9 */
10
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/time.h>
17#include <linux/pci.h>
18#include <linux/blkdev.h>
19#include <linux/interrupt.h>
20#include <linux/types.h>
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/ktime.h>
24#include <linux/reboot.h>
25#include <asm/io.h>
26#include <asm/irq.h>
27#include <asm/byteorder.h>
28#include <scsi/scsi.h>
29#include <scsi/scsi_device.h>
30#include <scsi/scsi_cmnd.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_tcq.h>
33#include <scsi/scsi_dbg.h>
34#include <scsi/scsi_eh.h>
35
36#define DRV_NAME "stex"
37#define ST_DRIVER_VERSION "6.02.0000.01"
38#define ST_VER_MAJOR 6
39#define ST_VER_MINOR 02
40#define ST_OEM 0000
41#define ST_BUILD_VER 01
42
43enum {
44 /* MU register offset */
45 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
46 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
47 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
48 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
49 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
50 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
51 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
52 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
53 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
54 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
55
56 YIOA_STATUS = 0x00,
57 YH2I_INT = 0x20,
58 YINT_EN = 0x34,
59 YI2H_INT = 0x9c,
60 YI2H_INT_C = 0xa0,
61 YH2I_REQ = 0xc0,
62 YH2I_REQ_HI = 0xc4,
63 PSCRATCH0 = 0xb0,
64 PSCRATCH1 = 0xb4,
65 PSCRATCH2 = 0xb8,
66 PSCRATCH3 = 0xbc,
67 PSCRATCH4 = 0xc8,
68 MAILBOX_BASE = 0x1000,
69 MAILBOX_HNDSHK_STS = 0x0,
70
71 /* MU register value */
72 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
73 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
74 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
75 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
76 MU_INBOUND_DOORBELL_RESET = (1 << 4),
77
78 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
79 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
80 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
81 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
82 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
83 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
84
85 /* MU status code */
86 MU_STATE_STARTING = 1,
87 MU_STATE_STARTED = 2,
88 MU_STATE_RESETTING = 3,
89 MU_STATE_FAILED = 4,
90 MU_STATE_STOP = 5,
91 MU_STATE_NOCONNECT = 6,
92
93 MU_MAX_DELAY = 50,
94 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
95 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
96 MU_HARD_RESET_WAIT = 30000,
97 HMU_PARTNER_TYPE = 2,
98
99 /* firmware returned values */
100 SRB_STATUS_SUCCESS = 0x01,
101 SRB_STATUS_ERROR = 0x04,
102 SRB_STATUS_BUSY = 0x05,
103 SRB_STATUS_INVALID_REQUEST = 0x06,
104 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
105 SRB_SEE_SENSE = 0x80,
106
107 /* task attribute */
108 TASK_ATTRIBUTE_SIMPLE = 0x0,
109 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
110 TASK_ATTRIBUTE_ORDERED = 0x2,
111 TASK_ATTRIBUTE_ACA = 0x4,
112};
113
114enum {
115 SS_STS_NORMAL = 0x80000000,
116 SS_STS_DONE = 0x40000000,
117 SS_STS_HANDSHAKE = 0x20000000,
118
119 SS_HEAD_HANDSHAKE = 0x80,
120
121 SS_H2I_INT_RESET = 0x100,
122
123 SS_I2H_REQUEST_RESET = 0x2000,
124
125 SS_MU_OPERATIONAL = 0x80000000,
126};
127
128enum {
129 STEX_CDB_LENGTH = 16,
130 STATUS_VAR_LEN = 128,
131
132 /* sg flags */
133 SG_CF_EOT = 0x80, /* end of table */
134 SG_CF_64B = 0x40, /* 64 bit item */
135 SG_CF_HOST = 0x20, /* sg in host memory */
136 MSG_DATA_DIR_ND = 0,
137 MSG_DATA_DIR_IN = 1,
138 MSG_DATA_DIR_OUT = 2,
139
140 st_shasta = 0,
141 st_vsc = 1,
142 st_yosemite = 2,
143 st_seq = 3,
144 st_yel = 4,
145 st_P3 = 5,
146
147 PASSTHRU_REQ_TYPE = 0x00000001,
148 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
149 ST_INTERNAL_TIMEOUT = 180,
150
151 ST_TO_CMD = 0,
152 ST_FROM_CMD = 1,
153
154 /* vendor specific commands of Promise */
155 MGT_CMD = 0xd8,
156 SINBAND_MGT_CMD = 0xd9,
157 ARRAY_CMD = 0xe0,
158 CONTROLLER_CMD = 0xe1,
159 DEBUGGING_CMD = 0xe2,
160 PASSTHRU_CMD = 0xe3,
161
162 PASSTHRU_GET_ADAPTER = 0x05,
163 PASSTHRU_GET_DRVVER = 0x10,
164
165 CTLR_CONFIG_CMD = 0x03,
166 CTLR_SHUTDOWN = 0x0d,
167
168 CTLR_POWER_STATE_CHANGE = 0x0e,
169 CTLR_POWER_SAVING = 0x01,
170
171 PASSTHRU_SIGNATURE = 0x4e415041,
172 MGT_CMD_SIGNATURE = 0xba,
173
174 INQUIRY_EVPD = 0x01,
175
176 ST_ADDITIONAL_MEM = 0x200000,
177 ST_ADDITIONAL_MEM_MIN = 0x80000,
178 PMIC_SHUTDOWN = 0x0D,
179 PMIC_REUMSE = 0x10,
180 ST_IGNORED = -1,
181 ST_NOTHANDLED = 7,
182 ST_S3 = 3,
183 ST_S4 = 4,
184 ST_S5 = 5,
185 ST_S6 = 6,
186};
187
188struct st_sgitem {
189 u8 ctrl; /* SG_CF_xxx */
190 u8 reserved[3];
191 __le32 count;
192 __le64 addr;
193};
194
195struct st_ss_sgitem {
196 __le32 addr;
197 __le32 addr_hi;
198 __le32 count;
199};
200
201struct st_sgtable {
202 __le16 sg_count;
203 __le16 max_sg_count;
204 __le32 sz_in_byte;
205};
206
207struct st_msg_header {
208 __le64 handle;
209 u8 flag;
210 u8 channel;
211 __le16 timeout;
212 u32 reserved;
213};
214
215struct handshake_frame {
216 __le64 rb_phy; /* request payload queue physical address */
217 __le16 req_sz; /* size of each request payload */
218 __le16 req_cnt; /* count of reqs the buffer can hold */
219 __le16 status_sz; /* size of each status payload */
220 __le16 status_cnt; /* count of status the buffer can hold */
221 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
222 u8 partner_type; /* who sends this frame */
223 u8 reserved0[7];
224 __le32 partner_ver_major;
225 __le32 partner_ver_minor;
226 __le32 partner_ver_oem;
227 __le32 partner_ver_build;
228 __le32 extra_offset; /* NEW */
229 __le32 extra_size; /* NEW */
230 __le32 scratch_size;
231 u32 reserved1;
232};
233
234struct req_msg {
235 __le16 tag;
236 u8 lun;
237 u8 target;
238 u8 task_attr;
239 u8 task_manage;
240 u8 data_dir;
241 u8 payload_sz; /* payload size in 4-byte, not used */
242 u8 cdb[STEX_CDB_LENGTH];
243 u32 variable[];
244};
245
246struct status_msg {
247 __le16 tag;
248 u8 lun;
249 u8 target;
250 u8 srb_status;
251 u8 scsi_status;
252 u8 reserved;
253 u8 payload_sz; /* payload size in 4-byte */
254 u8 variable[STATUS_VAR_LEN];
255};
256
257struct ver_info {
258 u32 major;
259 u32 minor;
260 u32 oem;
261 u32 build;
262 u32 reserved[2];
263};
264
265struct st_frame {
266 u32 base[6];
267 u32 rom_addr;
268
269 struct ver_info drv_ver;
270 struct ver_info bios_ver;
271
272 u32 bus;
273 u32 slot;
274 u32 irq_level;
275 u32 irq_vec;
276 u32 id;
277 u32 subid;
278
279 u32 dimm_size;
280 u8 dimm_type;
281 u8 reserved[3];
282
283 u32 channel;
284 u32 reserved1;
285};
286
287struct st_drvver {
288 u32 major;
289 u32 minor;
290 u32 oem;
291 u32 build;
292 u32 signature[2];
293 u8 console_id;
294 u8 host_no;
295 u8 reserved0[2];
296 u32 reserved[3];
297};
298
299struct st_ccb {
300 struct req_msg *req;
301 struct scsi_cmnd *cmd;
302
303 void *sense_buffer;
304 unsigned int sense_bufflen;
305 int sg_count;
306
307 u32 req_type;
308 u8 srb_status;
309 u8 scsi_status;
310 u8 reserved[2];
311};
312
313struct st_hba {
314 void __iomem *mmio_base; /* iomapped PCI memory space */
315 void *dma_mem;
316 dma_addr_t dma_handle;
317 size_t dma_size;
318
319 struct Scsi_Host *host;
320 struct pci_dev *pdev;
321
322 struct req_msg * (*alloc_rq) (struct st_hba *);
323 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
324 void (*send) (struct st_hba *, struct req_msg *, u16);
325
326 u32 req_head;
327 u32 req_tail;
328 u32 status_head;
329 u32 status_tail;
330
331 struct status_msg *status_buffer;
332 void *copy_buffer; /* temp buffer for driver-handled commands */
333 struct st_ccb *ccb;
334 struct st_ccb *wait_ccb;
335 __le32 *scratch;
336
337 struct workqueue_struct *work_q;
338 struct work_struct reset_work;
339 wait_queue_head_t reset_waitq;
340 unsigned int mu_status;
341 unsigned int cardtype;
342 int msi_enabled;
343 int out_req_cnt;
344 u32 extra_offset;
345 u16 rq_count;
346 u16 rq_size;
347 u16 sts_count;
348 u8 supports_pm;
349 int msi_lock;
350};
351
352struct st_card_info {
353 struct req_msg * (*alloc_rq) (struct st_hba *);
354 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
355 void (*send) (struct st_hba *, struct req_msg *, u16);
356 unsigned int max_id;
357 unsigned int max_lun;
358 unsigned int max_channel;
359 u16 rq_count;
360 u16 rq_size;
361 u16 sts_count;
362};
363
364static int S6flag;
365static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
366static struct notifier_block stex_notifier = {
367 stex_halt, NULL, 0
368};
369
370static int msi;
371module_param(msi, int, 0);
372MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
373
374static const char console_inq_page[] =
375{
376 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
377 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
378 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
379 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
380 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
381 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
382 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
383 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
384};
385
386MODULE_AUTHOR("Ed Lin");
387MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
388MODULE_LICENSE("GPL");
389MODULE_VERSION(ST_DRIVER_VERSION);
390
391static struct status_msg *stex_get_status(struct st_hba *hba)
392{
393 struct status_msg *status = hba->status_buffer + hba->status_tail;
394
395 ++hba->status_tail;
396 hba->status_tail %= hba->sts_count+1;
397
398 return status;
399}
400
401static void stex_invalid_field(struct scsi_cmnd *cmd,
402 void (*done)(struct scsi_cmnd *))
403{
404 /* "Invalid field in cdb" */
405 scsi_build_sense(cmd, 0, ILLEGAL_REQUEST, 0x24, 0x0);
406 done(cmd);
407}
408
409static struct req_msg *stex_alloc_req(struct st_hba *hba)
410{
411 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
412
413 ++hba->req_head;
414 hba->req_head %= hba->rq_count+1;
415
416 return req;
417}
418
419static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
420{
421 return (struct req_msg *)(hba->dma_mem +
422 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
423}
424
425static int stex_map_sg(struct st_hba *hba,
426 struct req_msg *req, struct st_ccb *ccb)
427{
428 struct scsi_cmnd *cmd;
429 struct scatterlist *sg;
430 struct st_sgtable *dst;
431 struct st_sgitem *table;
432 int i, nseg;
433
434 cmd = ccb->cmd;
435 nseg = scsi_dma_map(cmd);
436 BUG_ON(nseg < 0);
437 if (nseg) {
438 dst = (struct st_sgtable *)req->variable;
439
440 ccb->sg_count = nseg;
441 dst->sg_count = cpu_to_le16((u16)nseg);
442 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
443 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
444
445 table = (struct st_sgitem *)(dst + 1);
446 scsi_for_each_sg(cmd, sg, nseg, i) {
447 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
448 table[i].addr = cpu_to_le64(sg_dma_address(sg));
449 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
450 }
451 table[--i].ctrl |= SG_CF_EOT;
452 }
453
454 return nseg;
455}
456
457static int stex_ss_map_sg(struct st_hba *hba,
458 struct req_msg *req, struct st_ccb *ccb)
459{
460 struct scsi_cmnd *cmd;
461 struct scatterlist *sg;
462 struct st_sgtable *dst;
463 struct st_ss_sgitem *table;
464 int i, nseg;
465
466 cmd = ccb->cmd;
467 nseg = scsi_dma_map(cmd);
468 BUG_ON(nseg < 0);
469 if (nseg) {
470 dst = (struct st_sgtable *)req->variable;
471
472 ccb->sg_count = nseg;
473 dst->sg_count = cpu_to_le16((u16)nseg);
474 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
475 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
476
477 table = (struct st_ss_sgitem *)(dst + 1);
478 scsi_for_each_sg(cmd, sg, nseg, i) {
479 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
480 table[i].addr =
481 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
482 table[i].addr_hi =
483 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
484 }
485 }
486
487 return nseg;
488}
489
490static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
491{
492 struct st_frame *p;
493 size_t count = sizeof(struct st_frame);
494
495 p = hba->copy_buffer;
496 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
497 memset(p->base, 0, sizeof(u32)*6);
498 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
499 p->rom_addr = 0;
500
501 p->drv_ver.major = ST_VER_MAJOR;
502 p->drv_ver.minor = ST_VER_MINOR;
503 p->drv_ver.oem = ST_OEM;
504 p->drv_ver.build = ST_BUILD_VER;
505
506 p->bus = hba->pdev->bus->number;
507 p->slot = hba->pdev->devfn;
508 p->irq_level = 0;
509 p->irq_vec = hba->pdev->irq;
510 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
511 p->subid =
512 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
513
514 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
515}
516
517static void
518stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
519{
520 req->tag = cpu_to_le16(tag);
521
522 hba->ccb[tag].req = req;
523 hba->out_req_cnt++;
524
525 writel(hba->req_head, hba->mmio_base + IMR0);
526 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
527 readl(hba->mmio_base + IDBL); /* flush */
528}
529
530static void
531stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
532{
533 struct scsi_cmnd *cmd;
534 struct st_msg_header *msg_h;
535 dma_addr_t addr;
536
537 req->tag = cpu_to_le16(tag);
538
539 hba->ccb[tag].req = req;
540 hba->out_req_cnt++;
541
542 cmd = hba->ccb[tag].cmd;
543 msg_h = (struct st_msg_header *)req - 1;
544 if (likely(cmd)) {
545 msg_h->channel = (u8)cmd->device->channel;
546 msg_h->timeout = cpu_to_le16(scsi_cmd_to_rq(cmd)->timeout / HZ);
547 }
548 addr = hba->dma_handle + hba->req_head * hba->rq_size;
549 addr += (hba->ccb[tag].sg_count+4)/11;
550 msg_h->handle = cpu_to_le64(addr);
551
552 ++hba->req_head;
553 hba->req_head %= hba->rq_count+1;
554 if (hba->cardtype == st_P3) {
555 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
556 writel(addr, hba->mmio_base + YH2I_REQ);
557 } else {
558 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
559 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
560 writel(addr, hba->mmio_base + YH2I_REQ);
561 readl(hba->mmio_base + YH2I_REQ); /* flush */
562 }
563}
564
565static void return_abnormal_state(struct st_hba *hba, int status)
566{
567 struct st_ccb *ccb;
568 unsigned long flags;
569 u16 tag;
570
571 spin_lock_irqsave(hba->host->host_lock, flags);
572 for (tag = 0; tag < hba->host->can_queue; tag++) {
573 ccb = &hba->ccb[tag];
574 if (ccb->req == NULL)
575 continue;
576 ccb->req = NULL;
577 if (ccb->cmd) {
578 scsi_dma_unmap(ccb->cmd);
579 ccb->cmd->result = status << 16;
580 scsi_done(ccb->cmd);
581 ccb->cmd = NULL;
582 }
583 }
584 spin_unlock_irqrestore(hba->host->host_lock, flags);
585}
586static int
587stex_slave_config(struct scsi_device *sdev)
588{
589 sdev->use_10_for_rw = 1;
590 sdev->use_10_for_ms = 1;
591 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
592
593 return 0;
594}
595
596static int stex_queuecommand_lck(struct scsi_cmnd *cmd)
597{
598 void (*done)(struct scsi_cmnd *) = scsi_done;
599 struct st_hba *hba;
600 struct Scsi_Host *host;
601 unsigned int id, lun;
602 struct req_msg *req;
603 u16 tag;
604
605 host = cmd->device->host;
606 id = cmd->device->id;
607 lun = cmd->device->lun;
608 hba = (struct st_hba *) &host->hostdata[0];
609 if (hba->mu_status == MU_STATE_NOCONNECT) {
610 cmd->result = DID_NO_CONNECT;
611 done(cmd);
612 return 0;
613 }
614 if (unlikely(hba->mu_status != MU_STATE_STARTED))
615 return SCSI_MLQUEUE_HOST_BUSY;
616
617 switch (cmd->cmnd[0]) {
618 case MODE_SENSE_10:
619 {
620 static char ms10_caching_page[12] =
621 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
622 unsigned char page;
623
624 page = cmd->cmnd[2] & 0x3f;
625 if (page == 0x8 || page == 0x3f) {
626 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
627 sizeof(ms10_caching_page));
628 cmd->result = DID_OK << 16;
629 done(cmd);
630 } else
631 stex_invalid_field(cmd, done);
632 return 0;
633 }
634 case REPORT_LUNS:
635 /*
636 * The shasta firmware does not report actual luns in the
637 * target, so fail the command to force sequential lun scan.
638 * Also, the console device does not support this command.
639 */
640 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
641 stex_invalid_field(cmd, done);
642 return 0;
643 }
644 break;
645 case TEST_UNIT_READY:
646 if (id == host->max_id - 1) {
647 cmd->result = DID_OK << 16;
648 done(cmd);
649 return 0;
650 }
651 break;
652 case INQUIRY:
653 if (lun >= host->max_lun) {
654 cmd->result = DID_NO_CONNECT << 16;
655 done(cmd);
656 return 0;
657 }
658 if (id != host->max_id - 1)
659 break;
660 if (!lun && !cmd->device->channel &&
661 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
662 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
663 sizeof(console_inq_page));
664 cmd->result = DID_OK << 16;
665 done(cmd);
666 } else
667 stex_invalid_field(cmd, done);
668 return 0;
669 case PASSTHRU_CMD:
670 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
671 const struct st_drvver ver = {
672 .major = ST_VER_MAJOR,
673 .minor = ST_VER_MINOR,
674 .oem = ST_OEM,
675 .build = ST_BUILD_VER,
676 .signature[0] = PASSTHRU_SIGNATURE,
677 .console_id = host->max_id - 1,
678 .host_no = hba->host->host_no,
679 };
680 size_t cp_len = sizeof(ver);
681
682 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
683 if (sizeof(ver) == cp_len)
684 cmd->result = DID_OK << 16;
685 else
686 cmd->result = DID_ERROR << 16;
687 done(cmd);
688 return 0;
689 }
690 break;
691 default:
692 break;
693 }
694
695 tag = scsi_cmd_to_rq(cmd)->tag;
696
697 if (unlikely(tag >= host->can_queue))
698 return SCSI_MLQUEUE_HOST_BUSY;
699
700 req = hba->alloc_rq(hba);
701
702 req->lun = lun;
703 req->target = id;
704
705 /* cdb */
706 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
707
708 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
709 req->data_dir = MSG_DATA_DIR_IN;
710 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
711 req->data_dir = MSG_DATA_DIR_OUT;
712 else
713 req->data_dir = MSG_DATA_DIR_ND;
714
715 hba->ccb[tag].cmd = cmd;
716 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
717 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
718
719 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
720 hba->ccb[tag].sg_count = 0;
721 memset(&req->variable[0], 0, 8);
722 }
723
724 hba->send(hba, req, tag);
725 return 0;
726}
727
728static DEF_SCSI_QCMD(stex_queuecommand)
729
730static void stex_scsi_done(struct st_ccb *ccb)
731{
732 struct scsi_cmnd *cmd = ccb->cmd;
733 int result;
734
735 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
736 result = ccb->scsi_status;
737 switch (ccb->scsi_status) {
738 case SAM_STAT_GOOD:
739 result |= DID_OK << 16;
740 break;
741 case SAM_STAT_CHECK_CONDITION:
742 result |= DID_OK << 16;
743 break;
744 case SAM_STAT_BUSY:
745 result |= DID_BUS_BUSY << 16;
746 break;
747 default:
748 result |= DID_ERROR << 16;
749 break;
750 }
751 }
752 else if (ccb->srb_status & SRB_SEE_SENSE)
753 result = SAM_STAT_CHECK_CONDITION;
754 else switch (ccb->srb_status) {
755 case SRB_STATUS_SELECTION_TIMEOUT:
756 result = DID_NO_CONNECT << 16;
757 break;
758 case SRB_STATUS_BUSY:
759 result = DID_BUS_BUSY << 16;
760 break;
761 case SRB_STATUS_INVALID_REQUEST:
762 case SRB_STATUS_ERROR:
763 default:
764 result = DID_ERROR << 16;
765 break;
766 }
767
768 cmd->result = result;
769 scsi_done(cmd);
770}
771
772static void stex_copy_data(struct st_ccb *ccb,
773 struct status_msg *resp, unsigned int variable)
774{
775 if (resp->scsi_status != SAM_STAT_GOOD) {
776 if (ccb->sense_buffer != NULL)
777 memcpy(ccb->sense_buffer, resp->variable,
778 min(variable, ccb->sense_bufflen));
779 return;
780 }
781
782 if (ccb->cmd == NULL)
783 return;
784 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
785}
786
787static void stex_check_cmd(struct st_hba *hba,
788 struct st_ccb *ccb, struct status_msg *resp)
789{
790 if (ccb->cmd->cmnd[0] == MGT_CMD &&
791 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
792 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
793 le32_to_cpu(*(__le32 *)&resp->variable[0]));
794}
795
796static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
797{
798 void __iomem *base = hba->mmio_base;
799 struct status_msg *resp;
800 struct st_ccb *ccb;
801 unsigned int size;
802 u16 tag;
803
804 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
805 return;
806
807 /* status payloads */
808 hba->status_head = readl(base + OMR1);
809 if (unlikely(hba->status_head > hba->sts_count)) {
810 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
811 pci_name(hba->pdev));
812 return;
813 }
814
815 /*
816 * it's not a valid status payload if:
817 * 1. there are no pending requests(e.g. during init stage)
818 * 2. there are some pending requests, but the controller is in
819 * reset status, and its type is not st_yosemite
820 * firmware of st_yosemite in reset status will return pending requests
821 * to driver, so we allow it to pass
822 */
823 if (unlikely(hba->out_req_cnt <= 0 ||
824 (hba->mu_status == MU_STATE_RESETTING &&
825 hba->cardtype != st_yosemite))) {
826 hba->status_tail = hba->status_head;
827 goto update_status;
828 }
829
830 while (hba->status_tail != hba->status_head) {
831 resp = stex_get_status(hba);
832 tag = le16_to_cpu(resp->tag);
833 if (unlikely(tag >= hba->host->can_queue)) {
834 printk(KERN_WARNING DRV_NAME
835 "(%s): invalid tag\n", pci_name(hba->pdev));
836 continue;
837 }
838
839 hba->out_req_cnt--;
840 ccb = &hba->ccb[tag];
841 if (unlikely(hba->wait_ccb == ccb))
842 hba->wait_ccb = NULL;
843 if (unlikely(ccb->req == NULL)) {
844 printk(KERN_WARNING DRV_NAME
845 "(%s): lagging req\n", pci_name(hba->pdev));
846 continue;
847 }
848
849 size = resp->payload_sz * sizeof(u32); /* payload size */
850 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
851 size > sizeof(*resp))) {
852 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
853 pci_name(hba->pdev));
854 } else {
855 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
856 if (size)
857 stex_copy_data(ccb, resp, size);
858 }
859
860 ccb->req = NULL;
861 ccb->srb_status = resp->srb_status;
862 ccb->scsi_status = resp->scsi_status;
863
864 if (likely(ccb->cmd != NULL)) {
865 if (hba->cardtype == st_yosemite)
866 stex_check_cmd(hba, ccb, resp);
867
868 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
869 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
870 stex_controller_info(hba, ccb);
871
872 scsi_dma_unmap(ccb->cmd);
873 stex_scsi_done(ccb);
874 } else
875 ccb->req_type = 0;
876 }
877
878update_status:
879 writel(hba->status_head, base + IMR1);
880 readl(base + IMR1); /* flush */
881}
882
883static irqreturn_t stex_intr(int irq, void *__hba)
884{
885 struct st_hba *hba = __hba;
886 void __iomem *base = hba->mmio_base;
887 u32 data;
888 unsigned long flags;
889
890 spin_lock_irqsave(hba->host->host_lock, flags);
891
892 data = readl(base + ODBL);
893
894 if (data && data != 0xffffffff) {
895 /* clear the interrupt */
896 writel(data, base + ODBL);
897 readl(base + ODBL); /* flush */
898 stex_mu_intr(hba, data);
899 spin_unlock_irqrestore(hba->host->host_lock, flags);
900 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
901 hba->cardtype == st_shasta))
902 queue_work(hba->work_q, &hba->reset_work);
903 return IRQ_HANDLED;
904 }
905
906 spin_unlock_irqrestore(hba->host->host_lock, flags);
907
908 return IRQ_NONE;
909}
910
911static void stex_ss_mu_intr(struct st_hba *hba)
912{
913 struct status_msg *resp;
914 struct st_ccb *ccb;
915 __le32 *scratch;
916 unsigned int size;
917 int count = 0;
918 u32 value;
919 u16 tag;
920
921 if (unlikely(hba->out_req_cnt <= 0 ||
922 hba->mu_status == MU_STATE_RESETTING))
923 return;
924
925 while (count < hba->sts_count) {
926 scratch = hba->scratch + hba->status_tail;
927 value = le32_to_cpu(*scratch);
928 if (unlikely(!(value & SS_STS_NORMAL)))
929 return;
930
931 resp = hba->status_buffer + hba->status_tail;
932 *scratch = 0;
933 ++count;
934 ++hba->status_tail;
935 hba->status_tail %= hba->sts_count+1;
936
937 tag = (u16)value;
938 if (unlikely(tag >= hba->host->can_queue)) {
939 printk(KERN_WARNING DRV_NAME
940 "(%s): invalid tag\n", pci_name(hba->pdev));
941 continue;
942 }
943
944 hba->out_req_cnt--;
945 ccb = &hba->ccb[tag];
946 if (unlikely(hba->wait_ccb == ccb))
947 hba->wait_ccb = NULL;
948 if (unlikely(ccb->req == NULL)) {
949 printk(KERN_WARNING DRV_NAME
950 "(%s): lagging req\n", pci_name(hba->pdev));
951 continue;
952 }
953
954 ccb->req = NULL;
955 if (likely(value & SS_STS_DONE)) { /* normal case */
956 ccb->srb_status = SRB_STATUS_SUCCESS;
957 ccb->scsi_status = SAM_STAT_GOOD;
958 } else {
959 ccb->srb_status = resp->srb_status;
960 ccb->scsi_status = resp->scsi_status;
961 size = resp->payload_sz * sizeof(u32);
962 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
963 size > sizeof(*resp))) {
964 printk(KERN_WARNING DRV_NAME
965 "(%s): bad status size\n",
966 pci_name(hba->pdev));
967 } else {
968 size -= sizeof(*resp) - STATUS_VAR_LEN;
969 if (size)
970 stex_copy_data(ccb, resp, size);
971 }
972 if (likely(ccb->cmd != NULL))
973 stex_check_cmd(hba, ccb, resp);
974 }
975
976 if (likely(ccb->cmd != NULL)) {
977 scsi_dma_unmap(ccb->cmd);
978 stex_scsi_done(ccb);
979 } else
980 ccb->req_type = 0;
981 }
982}
983
984static irqreturn_t stex_ss_intr(int irq, void *__hba)
985{
986 struct st_hba *hba = __hba;
987 void __iomem *base = hba->mmio_base;
988 u32 data;
989 unsigned long flags;
990
991 spin_lock_irqsave(hba->host->host_lock, flags);
992
993 if (hba->cardtype == st_yel) {
994 data = readl(base + YI2H_INT);
995 if (data && data != 0xffffffff) {
996 /* clear the interrupt */
997 writel(data, base + YI2H_INT_C);
998 stex_ss_mu_intr(hba);
999 spin_unlock_irqrestore(hba->host->host_lock, flags);
1000 if (unlikely(data & SS_I2H_REQUEST_RESET))
1001 queue_work(hba->work_q, &hba->reset_work);
1002 return IRQ_HANDLED;
1003 }
1004 } else {
1005 data = readl(base + PSCRATCH4);
1006 if (data != 0xffffffff) {
1007 if (data != 0) {
1008 /* clear the interrupt */
1009 writel(data, base + PSCRATCH1);
1010 writel((1 << 22), base + YH2I_INT);
1011 }
1012 stex_ss_mu_intr(hba);
1013 spin_unlock_irqrestore(hba->host->host_lock, flags);
1014 if (unlikely(data & SS_I2H_REQUEST_RESET))
1015 queue_work(hba->work_q, &hba->reset_work);
1016 return IRQ_HANDLED;
1017 }
1018 }
1019
1020 spin_unlock_irqrestore(hba->host->host_lock, flags);
1021
1022 return IRQ_NONE;
1023}
1024
1025static int stex_common_handshake(struct st_hba *hba)
1026{
1027 void __iomem *base = hba->mmio_base;
1028 struct handshake_frame *h;
1029 dma_addr_t status_phys;
1030 u32 data;
1031 unsigned long before;
1032
1033 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1034 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1035 readl(base + IDBL);
1036 before = jiffies;
1037 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1038 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1039 printk(KERN_ERR DRV_NAME
1040 "(%s): no handshake signature\n",
1041 pci_name(hba->pdev));
1042 return -1;
1043 }
1044 rmb();
1045 msleep(1);
1046 }
1047 }
1048
1049 udelay(10);
1050
1051 data = readl(base + OMR1);
1052 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1053 data &= 0x0000ffff;
1054 if (hba->host->can_queue > data) {
1055 hba->host->can_queue = data;
1056 hba->host->cmd_per_lun = data;
1057 }
1058 }
1059
1060 h = (struct handshake_frame *)hba->status_buffer;
1061 h->rb_phy = cpu_to_le64(hba->dma_handle);
1062 h->req_sz = cpu_to_le16(hba->rq_size);
1063 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1064 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1065 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1066 h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1067 h->partner_type = HMU_PARTNER_TYPE;
1068 if (hba->extra_offset) {
1069 h->extra_offset = cpu_to_le32(hba->extra_offset);
1070 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1071 } else
1072 h->extra_offset = h->extra_size = 0;
1073
1074 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1075 writel(status_phys, base + IMR0);
1076 readl(base + IMR0);
1077 writel((status_phys >> 16) >> 16, base + IMR1);
1078 readl(base + IMR1);
1079
1080 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1081 readl(base + OMR0);
1082 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1083 readl(base + IDBL); /* flush */
1084
1085 udelay(10);
1086 before = jiffies;
1087 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1088 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1089 printk(KERN_ERR DRV_NAME
1090 "(%s): no signature after handshake frame\n",
1091 pci_name(hba->pdev));
1092 return -1;
1093 }
1094 rmb();
1095 msleep(1);
1096 }
1097
1098 writel(0, base + IMR0);
1099 readl(base + IMR0);
1100 writel(0, base + OMR0);
1101 readl(base + OMR0);
1102 writel(0, base + IMR1);
1103 readl(base + IMR1);
1104 writel(0, base + OMR1);
1105 readl(base + OMR1); /* flush */
1106 return 0;
1107}
1108
1109static int stex_ss_handshake(struct st_hba *hba)
1110{
1111 void __iomem *base = hba->mmio_base;
1112 struct st_msg_header *msg_h;
1113 struct handshake_frame *h;
1114 __le32 *scratch;
1115 u32 data, scratch_size, mailboxdata, operationaldata;
1116 unsigned long before;
1117 int ret = 0;
1118
1119 before = jiffies;
1120
1121 if (hba->cardtype == st_yel) {
1122 operationaldata = readl(base + YIOA_STATUS);
1123 while (operationaldata != SS_MU_OPERATIONAL) {
1124 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1125 printk(KERN_ERR DRV_NAME
1126 "(%s): firmware not operational\n",
1127 pci_name(hba->pdev));
1128 return -1;
1129 }
1130 msleep(1);
1131 operationaldata = readl(base + YIOA_STATUS);
1132 }
1133 } else {
1134 operationaldata = readl(base + PSCRATCH3);
1135 while (operationaldata != SS_MU_OPERATIONAL) {
1136 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1137 printk(KERN_ERR DRV_NAME
1138 "(%s): firmware not operational\n",
1139 pci_name(hba->pdev));
1140 return -1;
1141 }
1142 msleep(1);
1143 operationaldata = readl(base + PSCRATCH3);
1144 }
1145 }
1146
1147 msg_h = (struct st_msg_header *)hba->dma_mem;
1148 msg_h->handle = cpu_to_le64(hba->dma_handle);
1149 msg_h->flag = SS_HEAD_HANDSHAKE;
1150
1151 h = (struct handshake_frame *)(msg_h + 1);
1152 h->rb_phy = cpu_to_le64(hba->dma_handle);
1153 h->req_sz = cpu_to_le16(hba->rq_size);
1154 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1155 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1156 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1157 h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1158 h->partner_type = HMU_PARTNER_TYPE;
1159 h->extra_offset = h->extra_size = 0;
1160 scratch_size = (hba->sts_count+1)*sizeof(u32);
1161 h->scratch_size = cpu_to_le32(scratch_size);
1162
1163 if (hba->cardtype == st_yel) {
1164 data = readl(base + YINT_EN);
1165 data &= ~4;
1166 writel(data, base + YINT_EN);
1167 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1168 readl(base + YH2I_REQ_HI);
1169 writel(hba->dma_handle, base + YH2I_REQ);
1170 readl(base + YH2I_REQ); /* flush */
1171 } else {
1172 data = readl(base + YINT_EN);
1173 data &= ~(1 << 0);
1174 data &= ~(1 << 2);
1175 writel(data, base + YINT_EN);
1176 if (hba->msi_lock == 0) {
1177 /* P3 MSI Register cannot access twice */
1178 writel((1 << 6), base + YH2I_INT);
1179 hba->msi_lock = 1;
1180 }
1181 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1182 writel(hba->dma_handle, base + YH2I_REQ);
1183 }
1184
1185 before = jiffies;
1186 scratch = hba->scratch;
1187 if (hba->cardtype == st_yel) {
1188 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1189 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1190 printk(KERN_ERR DRV_NAME
1191 "(%s): no signature after handshake frame\n",
1192 pci_name(hba->pdev));
1193 ret = -1;
1194 break;
1195 }
1196 rmb();
1197 msleep(1);
1198 }
1199 } else {
1200 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1201 while (mailboxdata != SS_STS_HANDSHAKE) {
1202 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1203 printk(KERN_ERR DRV_NAME
1204 "(%s): no signature after handshake frame\n",
1205 pci_name(hba->pdev));
1206 ret = -1;
1207 break;
1208 }
1209 rmb();
1210 msleep(1);
1211 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1212 }
1213 }
1214 memset(scratch, 0, scratch_size);
1215 msg_h->flag = 0;
1216
1217 return ret;
1218}
1219
1220static int stex_handshake(struct st_hba *hba)
1221{
1222 int err;
1223 unsigned long flags;
1224 unsigned int mu_status;
1225
1226 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1227 err = stex_ss_handshake(hba);
1228 else
1229 err = stex_common_handshake(hba);
1230 spin_lock_irqsave(hba->host->host_lock, flags);
1231 mu_status = hba->mu_status;
1232 if (err == 0) {
1233 hba->req_head = 0;
1234 hba->req_tail = 0;
1235 hba->status_head = 0;
1236 hba->status_tail = 0;
1237 hba->out_req_cnt = 0;
1238 hba->mu_status = MU_STATE_STARTED;
1239 } else
1240 hba->mu_status = MU_STATE_FAILED;
1241 if (mu_status == MU_STATE_RESETTING)
1242 wake_up_all(&hba->reset_waitq);
1243 spin_unlock_irqrestore(hba->host->host_lock, flags);
1244 return err;
1245}
1246
1247static int stex_abort(struct scsi_cmnd *cmd)
1248{
1249 struct Scsi_Host *host = cmd->device->host;
1250 struct st_hba *hba = (struct st_hba *)host->hostdata;
1251 u16 tag = scsi_cmd_to_rq(cmd)->tag;
1252 void __iomem *base;
1253 u32 data;
1254 int result = SUCCESS;
1255 unsigned long flags;
1256
1257 scmd_printk(KERN_INFO, cmd, "aborting command\n");
1258
1259 base = hba->mmio_base;
1260 spin_lock_irqsave(host->host_lock, flags);
1261 if (tag < host->can_queue &&
1262 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1263 hba->wait_ccb = &hba->ccb[tag];
1264 else
1265 goto out;
1266
1267 if (hba->cardtype == st_yel) {
1268 data = readl(base + YI2H_INT);
1269 if (data == 0 || data == 0xffffffff)
1270 goto fail_out;
1271
1272 writel(data, base + YI2H_INT_C);
1273 stex_ss_mu_intr(hba);
1274 } else if (hba->cardtype == st_P3) {
1275 data = readl(base + PSCRATCH4);
1276 if (data == 0xffffffff)
1277 goto fail_out;
1278 if (data != 0) {
1279 writel(data, base + PSCRATCH1);
1280 writel((1 << 22), base + YH2I_INT);
1281 }
1282 stex_ss_mu_intr(hba);
1283 } else {
1284 data = readl(base + ODBL);
1285 if (data == 0 || data == 0xffffffff)
1286 goto fail_out;
1287
1288 writel(data, base + ODBL);
1289 readl(base + ODBL); /* flush */
1290 stex_mu_intr(hba, data);
1291 }
1292 if (hba->wait_ccb == NULL) {
1293 printk(KERN_WARNING DRV_NAME
1294 "(%s): lost interrupt\n", pci_name(hba->pdev));
1295 goto out;
1296 }
1297
1298fail_out:
1299 scsi_dma_unmap(cmd);
1300 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1301 hba->wait_ccb = NULL;
1302 result = FAILED;
1303out:
1304 spin_unlock_irqrestore(host->host_lock, flags);
1305 return result;
1306}
1307
1308static void stex_hard_reset(struct st_hba *hba)
1309{
1310 struct pci_bus *bus;
1311 int i;
1312 u16 pci_cmd;
1313 u8 pci_bctl;
1314
1315 for (i = 0; i < 16; i++)
1316 pci_read_config_dword(hba->pdev, i * 4,
1317 &hba->pdev->saved_config_space[i]);
1318
1319 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1320 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1321 bus = hba->pdev->bus;
1322 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1323 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1324 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1325
1326 /*
1327 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1328 * require more time to finish bus reset. Use 100 ms here for safety
1329 */
1330 msleep(100);
1331 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1332 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1333
1334 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1335 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1336 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1337 break;
1338 msleep(1);
1339 }
1340
1341 ssleep(5);
1342 for (i = 0; i < 16; i++)
1343 pci_write_config_dword(hba->pdev, i * 4,
1344 hba->pdev->saved_config_space[i]);
1345}
1346
1347static int stex_yos_reset(struct st_hba *hba)
1348{
1349 void __iomem *base;
1350 unsigned long flags, before;
1351 int ret = 0;
1352
1353 base = hba->mmio_base;
1354 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1355 readl(base + IDBL); /* flush */
1356 before = jiffies;
1357 while (hba->out_req_cnt > 0) {
1358 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1359 printk(KERN_WARNING DRV_NAME
1360 "(%s): reset timeout\n", pci_name(hba->pdev));
1361 ret = -1;
1362 break;
1363 }
1364 msleep(1);
1365 }
1366
1367 spin_lock_irqsave(hba->host->host_lock, flags);
1368 if (ret == -1)
1369 hba->mu_status = MU_STATE_FAILED;
1370 else
1371 hba->mu_status = MU_STATE_STARTED;
1372 wake_up_all(&hba->reset_waitq);
1373 spin_unlock_irqrestore(hba->host->host_lock, flags);
1374
1375 return ret;
1376}
1377
1378static void stex_ss_reset(struct st_hba *hba)
1379{
1380 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1381 readl(hba->mmio_base + YH2I_INT);
1382 ssleep(5);
1383}
1384
1385static void stex_p3_reset(struct st_hba *hba)
1386{
1387 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1388 ssleep(5);
1389}
1390
1391static int stex_do_reset(struct st_hba *hba)
1392{
1393 unsigned long flags;
1394 unsigned int mu_status = MU_STATE_RESETTING;
1395
1396 spin_lock_irqsave(hba->host->host_lock, flags);
1397 if (hba->mu_status == MU_STATE_STARTING) {
1398 spin_unlock_irqrestore(hba->host->host_lock, flags);
1399 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1400 pci_name(hba->pdev));
1401 return 0;
1402 }
1403 while (hba->mu_status == MU_STATE_RESETTING) {
1404 spin_unlock_irqrestore(hba->host->host_lock, flags);
1405 wait_event_timeout(hba->reset_waitq,
1406 hba->mu_status != MU_STATE_RESETTING,
1407 MU_MAX_DELAY * HZ);
1408 spin_lock_irqsave(hba->host->host_lock, flags);
1409 mu_status = hba->mu_status;
1410 }
1411
1412 if (mu_status != MU_STATE_RESETTING) {
1413 spin_unlock_irqrestore(hba->host->host_lock, flags);
1414 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1415 }
1416
1417 hba->mu_status = MU_STATE_RESETTING;
1418 spin_unlock_irqrestore(hba->host->host_lock, flags);
1419
1420 if (hba->cardtype == st_yosemite)
1421 return stex_yos_reset(hba);
1422
1423 if (hba->cardtype == st_shasta)
1424 stex_hard_reset(hba);
1425 else if (hba->cardtype == st_yel)
1426 stex_ss_reset(hba);
1427 else if (hba->cardtype == st_P3)
1428 stex_p3_reset(hba);
1429
1430 return_abnormal_state(hba, DID_RESET);
1431
1432 if (stex_handshake(hba) == 0)
1433 return 0;
1434
1435 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1436 pci_name(hba->pdev));
1437 return -1;
1438}
1439
1440static int stex_reset(struct scsi_cmnd *cmd)
1441{
1442 struct st_hba *hba;
1443
1444 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1445
1446 shost_printk(KERN_INFO, cmd->device->host,
1447 "resetting host\n");
1448
1449 return stex_do_reset(hba) ? FAILED : SUCCESS;
1450}
1451
1452static void stex_reset_work(struct work_struct *work)
1453{
1454 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1455
1456 stex_do_reset(hba);
1457}
1458
1459static int stex_biosparam(struct scsi_device *sdev,
1460 struct block_device *bdev, sector_t capacity, int geom[])
1461{
1462 int heads = 255, sectors = 63;
1463
1464 if (capacity < 0x200000) {
1465 heads = 64;
1466 sectors = 32;
1467 }
1468
1469 sector_div(capacity, heads * sectors);
1470
1471 geom[0] = heads;
1472 geom[1] = sectors;
1473 geom[2] = capacity;
1474
1475 return 0;
1476}
1477
1478static const struct scsi_host_template driver_template = {
1479 .module = THIS_MODULE,
1480 .name = DRV_NAME,
1481 .proc_name = DRV_NAME,
1482 .bios_param = stex_biosparam,
1483 .queuecommand = stex_queuecommand,
1484 .slave_configure = stex_slave_config,
1485 .eh_abort_handler = stex_abort,
1486 .eh_host_reset_handler = stex_reset,
1487 .this_id = -1,
1488 .dma_boundary = PAGE_SIZE - 1,
1489};
1490
1491static struct pci_device_id stex_pci_tbl[] = {
1492 /* st_shasta */
1493 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1494 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1495 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1496 st_shasta }, /* SuperTrak EX12350 */
1497 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1498 st_shasta }, /* SuperTrak EX4350 */
1499 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1500 st_shasta }, /* SuperTrak EX24350 */
1501
1502 /* st_vsc */
1503 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1504
1505 /* st_yosemite */
1506 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1507
1508 /* st_seq */
1509 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1510
1511 /* st_yel */
1512 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1513 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1514
1515 /* st_P3, pluto */
1516 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1517 0x8870, 0, 0, st_P3 },
1518 /* st_P3, p3 */
1519 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1520 0x4300, 0, 0, st_P3 },
1521
1522 /* st_P3, SymplyStor4E */
1523 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1524 0x4311, 0, 0, st_P3 },
1525 /* st_P3, SymplyStor8E */
1526 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1527 0x4312, 0, 0, st_P3 },
1528 /* st_P3, SymplyStor4 */
1529 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1530 0x4321, 0, 0, st_P3 },
1531 /* st_P3, SymplyStor8 */
1532 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1533 0x4322, 0, 0, st_P3 },
1534 { } /* terminate list */
1535};
1536
1537static struct st_card_info stex_card_info[] = {
1538 /* st_shasta */
1539 {
1540 .max_id = 17,
1541 .max_lun = 8,
1542 .max_channel = 0,
1543 .rq_count = 32,
1544 .rq_size = 1048,
1545 .sts_count = 32,
1546 .alloc_rq = stex_alloc_req,
1547 .map_sg = stex_map_sg,
1548 .send = stex_send_cmd,
1549 },
1550
1551 /* st_vsc */
1552 {
1553 .max_id = 129,
1554 .max_lun = 1,
1555 .max_channel = 0,
1556 .rq_count = 32,
1557 .rq_size = 1048,
1558 .sts_count = 32,
1559 .alloc_rq = stex_alloc_req,
1560 .map_sg = stex_map_sg,
1561 .send = stex_send_cmd,
1562 },
1563
1564 /* st_yosemite */
1565 {
1566 .max_id = 2,
1567 .max_lun = 256,
1568 .max_channel = 0,
1569 .rq_count = 256,
1570 .rq_size = 1048,
1571 .sts_count = 256,
1572 .alloc_rq = stex_alloc_req,
1573 .map_sg = stex_map_sg,
1574 .send = stex_send_cmd,
1575 },
1576
1577 /* st_seq */
1578 {
1579 .max_id = 129,
1580 .max_lun = 1,
1581 .max_channel = 0,
1582 .rq_count = 32,
1583 .rq_size = 1048,
1584 .sts_count = 32,
1585 .alloc_rq = stex_alloc_req,
1586 .map_sg = stex_map_sg,
1587 .send = stex_send_cmd,
1588 },
1589
1590 /* st_yel */
1591 {
1592 .max_id = 129,
1593 .max_lun = 256,
1594 .max_channel = 3,
1595 .rq_count = 801,
1596 .rq_size = 512,
1597 .sts_count = 801,
1598 .alloc_rq = stex_ss_alloc_req,
1599 .map_sg = stex_ss_map_sg,
1600 .send = stex_ss_send_cmd,
1601 },
1602
1603 /* st_P3 */
1604 {
1605 .max_id = 129,
1606 .max_lun = 256,
1607 .max_channel = 0,
1608 .rq_count = 801,
1609 .rq_size = 512,
1610 .sts_count = 801,
1611 .alloc_rq = stex_ss_alloc_req,
1612 .map_sg = stex_ss_map_sg,
1613 .send = stex_ss_send_cmd,
1614 },
1615};
1616
1617static int stex_request_irq(struct st_hba *hba)
1618{
1619 struct pci_dev *pdev = hba->pdev;
1620 int status;
1621
1622 if (msi || hba->cardtype == st_P3) {
1623 status = pci_enable_msi(pdev);
1624 if (status != 0)
1625 printk(KERN_ERR DRV_NAME
1626 "(%s): error %d setting up MSI\n",
1627 pci_name(pdev), status);
1628 else
1629 hba->msi_enabled = 1;
1630 } else
1631 hba->msi_enabled = 0;
1632
1633 status = request_irq(pdev->irq,
1634 (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1635 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1636
1637 if (status != 0) {
1638 if (hba->msi_enabled)
1639 pci_disable_msi(pdev);
1640 }
1641 return status;
1642}
1643
1644static void stex_free_irq(struct st_hba *hba)
1645{
1646 struct pci_dev *pdev = hba->pdev;
1647
1648 free_irq(pdev->irq, hba);
1649 if (hba->msi_enabled)
1650 pci_disable_msi(pdev);
1651}
1652
1653static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1654{
1655 struct st_hba *hba;
1656 struct Scsi_Host *host;
1657 const struct st_card_info *ci = NULL;
1658 u32 sts_offset, cp_offset, scratch_offset;
1659 int err;
1660
1661 err = pci_enable_device(pdev);
1662 if (err)
1663 return err;
1664
1665 pci_set_master(pdev);
1666
1667 S6flag = 0;
1668 register_reboot_notifier(&stex_notifier);
1669
1670 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1671
1672 if (!host) {
1673 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1674 pci_name(pdev));
1675 err = -ENOMEM;
1676 goto out_disable;
1677 }
1678
1679 hba = (struct st_hba *)host->hostdata;
1680 memset(hba, 0, sizeof(struct st_hba));
1681
1682 err = pci_request_regions(pdev, DRV_NAME);
1683 if (err < 0) {
1684 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1685 pci_name(pdev));
1686 goto out_scsi_host_put;
1687 }
1688
1689 hba->mmio_base = pci_ioremap_bar(pdev, 0);
1690 if ( !hba->mmio_base) {
1691 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1692 pci_name(pdev));
1693 err = -ENOMEM;
1694 goto out_release_regions;
1695 }
1696
1697 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1698 if (err)
1699 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1700 if (err) {
1701 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1702 pci_name(pdev));
1703 goto out_iounmap;
1704 }
1705
1706 hba->cardtype = (unsigned int) id->driver_data;
1707 ci = &stex_card_info[hba->cardtype];
1708 switch (id->subdevice) {
1709 case 0x4221:
1710 case 0x4222:
1711 case 0x4223:
1712 case 0x4224:
1713 case 0x4225:
1714 case 0x4226:
1715 case 0x4227:
1716 case 0x4261:
1717 case 0x4262:
1718 case 0x4263:
1719 case 0x4264:
1720 case 0x4265:
1721 break;
1722 default:
1723 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1724 hba->supports_pm = 1;
1725 }
1726
1727 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1728 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1729 sts_offset += (ci->sts_count+1) * sizeof(u32);
1730 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1731 hba->dma_size = cp_offset + sizeof(struct st_frame);
1732 if (hba->cardtype == st_seq ||
1733 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1734 hba->extra_offset = hba->dma_size;
1735 hba->dma_size += ST_ADDITIONAL_MEM;
1736 }
1737 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1738 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1739 if (!hba->dma_mem) {
1740 /* Retry minimum coherent mapping for st_seq and st_vsc */
1741 if (hba->cardtype == st_seq ||
1742 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1743 printk(KERN_WARNING DRV_NAME
1744 "(%s): allocating min buffer for controller\n",
1745 pci_name(pdev));
1746 hba->dma_size = hba->extra_offset
1747 + ST_ADDITIONAL_MEM_MIN;
1748 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1749 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1750 }
1751
1752 if (!hba->dma_mem) {
1753 err = -ENOMEM;
1754 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1755 pci_name(pdev));
1756 goto out_iounmap;
1757 }
1758 }
1759
1760 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1761 if (!hba->ccb) {
1762 err = -ENOMEM;
1763 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1764 pci_name(pdev));
1765 goto out_pci_free;
1766 }
1767
1768 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1769 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1770 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1771 hba->copy_buffer = hba->dma_mem + cp_offset;
1772 hba->rq_count = ci->rq_count;
1773 hba->rq_size = ci->rq_size;
1774 hba->sts_count = ci->sts_count;
1775 hba->alloc_rq = ci->alloc_rq;
1776 hba->map_sg = ci->map_sg;
1777 hba->send = ci->send;
1778 hba->mu_status = MU_STATE_STARTING;
1779 hba->msi_lock = 0;
1780
1781 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1782 host->sg_tablesize = 38;
1783 else
1784 host->sg_tablesize = 32;
1785 host->can_queue = ci->rq_count;
1786 host->cmd_per_lun = ci->rq_count;
1787 host->max_id = ci->max_id;
1788 host->max_lun = ci->max_lun;
1789 host->max_channel = ci->max_channel;
1790 host->unique_id = host->host_no;
1791 host->max_cmd_len = STEX_CDB_LENGTH;
1792
1793 hba->host = host;
1794 hba->pdev = pdev;
1795 init_waitqueue_head(&hba->reset_waitq);
1796
1797 hba->work_q = alloc_ordered_workqueue("stex_wq_%d", WQ_MEM_RECLAIM,
1798 host->host_no);
1799 if (!hba->work_q) {
1800 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1801 pci_name(pdev));
1802 err = -ENOMEM;
1803 goto out_ccb_free;
1804 }
1805 INIT_WORK(&hba->reset_work, stex_reset_work);
1806
1807 err = stex_request_irq(hba);
1808 if (err) {
1809 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1810 pci_name(pdev));
1811 goto out_free_wq;
1812 }
1813
1814 err = stex_handshake(hba);
1815 if (err)
1816 goto out_free_irq;
1817
1818 pci_set_drvdata(pdev, hba);
1819
1820 err = scsi_add_host(host, &pdev->dev);
1821 if (err) {
1822 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1823 pci_name(pdev));
1824 goto out_free_irq;
1825 }
1826
1827 scsi_scan_host(host);
1828
1829 return 0;
1830
1831out_free_irq:
1832 stex_free_irq(hba);
1833out_free_wq:
1834 destroy_workqueue(hba->work_q);
1835out_ccb_free:
1836 kfree(hba->ccb);
1837out_pci_free:
1838 dma_free_coherent(&pdev->dev, hba->dma_size,
1839 hba->dma_mem, hba->dma_handle);
1840out_iounmap:
1841 iounmap(hba->mmio_base);
1842out_release_regions:
1843 pci_release_regions(pdev);
1844out_scsi_host_put:
1845 scsi_host_put(host);
1846out_disable:
1847 pci_disable_device(pdev);
1848
1849 return err;
1850}
1851
1852static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1853{
1854 struct req_msg *req;
1855 struct st_msg_header *msg_h;
1856 unsigned long flags;
1857 unsigned long before;
1858 u16 tag = 0;
1859
1860 spin_lock_irqsave(hba->host->host_lock, flags);
1861
1862 if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1863 hba->supports_pm == 1) {
1864 if (st_sleep_mic == ST_NOTHANDLED) {
1865 spin_unlock_irqrestore(hba->host->host_lock, flags);
1866 return;
1867 }
1868 }
1869 req = hba->alloc_rq(hba);
1870 if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1871 msg_h = (struct st_msg_header *)req - 1;
1872 memset(msg_h, 0, hba->rq_size);
1873 } else
1874 memset(req, 0, hba->rq_size);
1875
1876 if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1877 || hba->cardtype == st_P3)
1878 && st_sleep_mic == ST_IGNORED) {
1879 req->cdb[0] = MGT_CMD;
1880 req->cdb[1] = MGT_CMD_SIGNATURE;
1881 req->cdb[2] = CTLR_CONFIG_CMD;
1882 req->cdb[3] = CTLR_SHUTDOWN;
1883 } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1884 && st_sleep_mic != ST_IGNORED) {
1885 req->cdb[0] = MGT_CMD;
1886 req->cdb[1] = MGT_CMD_SIGNATURE;
1887 req->cdb[2] = CTLR_CONFIG_CMD;
1888 req->cdb[3] = PMIC_SHUTDOWN;
1889 req->cdb[4] = st_sleep_mic;
1890 } else {
1891 req->cdb[0] = CONTROLLER_CMD;
1892 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1893 req->cdb[2] = CTLR_POWER_SAVING;
1894 }
1895 hba->ccb[tag].cmd = NULL;
1896 hba->ccb[tag].sg_count = 0;
1897 hba->ccb[tag].sense_bufflen = 0;
1898 hba->ccb[tag].sense_buffer = NULL;
1899 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1900 hba->send(hba, req, tag);
1901 spin_unlock_irqrestore(hba->host->host_lock, flags);
1902 before = jiffies;
1903 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1904 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1905 hba->ccb[tag].req_type = 0;
1906 hba->mu_status = MU_STATE_STOP;
1907 return;
1908 }
1909 msleep(1);
1910 }
1911 hba->mu_status = MU_STATE_STOP;
1912}
1913
1914static void stex_hba_free(struct st_hba *hba)
1915{
1916 stex_free_irq(hba);
1917
1918 destroy_workqueue(hba->work_q);
1919
1920 iounmap(hba->mmio_base);
1921
1922 pci_release_regions(hba->pdev);
1923
1924 kfree(hba->ccb);
1925
1926 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1927 hba->dma_mem, hba->dma_handle);
1928}
1929
1930static void stex_remove(struct pci_dev *pdev)
1931{
1932 struct st_hba *hba = pci_get_drvdata(pdev);
1933
1934 hba->mu_status = MU_STATE_NOCONNECT;
1935 return_abnormal_state(hba, DID_NO_CONNECT);
1936 scsi_remove_host(hba->host);
1937
1938 scsi_block_requests(hba->host);
1939
1940 stex_hba_free(hba);
1941
1942 scsi_host_put(hba->host);
1943
1944 pci_disable_device(pdev);
1945
1946 unregister_reboot_notifier(&stex_notifier);
1947}
1948
1949static void stex_shutdown(struct pci_dev *pdev)
1950{
1951 struct st_hba *hba = pci_get_drvdata(pdev);
1952
1953 if (hba->supports_pm == 0) {
1954 stex_hba_stop(hba, ST_IGNORED);
1955 } else if (hba->supports_pm == 1 && S6flag) {
1956 unregister_reboot_notifier(&stex_notifier);
1957 stex_hba_stop(hba, ST_S6);
1958 } else
1959 stex_hba_stop(hba, ST_S5);
1960}
1961
1962static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1963{
1964 switch (state.event) {
1965 case PM_EVENT_SUSPEND:
1966 return ST_S3;
1967 case PM_EVENT_HIBERNATE:
1968 hba->msi_lock = 0;
1969 return ST_S4;
1970 default:
1971 return ST_NOTHANDLED;
1972 }
1973}
1974
1975static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1976{
1977 struct st_hba *hba = pci_get_drvdata(pdev);
1978
1979 if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1980 && hba->supports_pm == 1)
1981 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1982 else
1983 stex_hba_stop(hba, ST_IGNORED);
1984 return 0;
1985}
1986
1987static int stex_resume(struct pci_dev *pdev)
1988{
1989 struct st_hba *hba = pci_get_drvdata(pdev);
1990
1991 hba->mu_status = MU_STATE_STARTING;
1992 stex_handshake(hba);
1993 return 0;
1994}
1995
1996static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
1997{
1998 S6flag = 1;
1999 return NOTIFY_OK;
2000}
2001MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2002
2003static struct pci_driver stex_pci_driver = {
2004 .name = DRV_NAME,
2005 .id_table = stex_pci_tbl,
2006 .probe = stex_probe,
2007 .remove = stex_remove,
2008 .shutdown = stex_shutdown,
2009 .suspend = stex_suspend,
2010 .resume = stex_resume,
2011};
2012
2013static int __init stex_init(void)
2014{
2015 printk(KERN_INFO DRV_NAME
2016 ": Promise SuperTrak EX Driver version: %s\n",
2017 ST_DRIVER_VERSION);
2018
2019 return pci_register_driver(&stex_pci_driver);
2020}
2021
2022static void __exit stex_exit(void)
2023{
2024 pci_unregister_driver(&stex_pci_driver);
2025}
2026
2027module_init(stex_init);
2028module_exit(stex_exit);