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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2016-2023 Broadcom Inc. All rights reserved.
4 */
5#ifndef MPI30_IOC_H
6#define MPI30_IOC_H 1
7struct mpi3_ioc_init_request {
8 __le16 host_tag;
9 u8 ioc_use_only02;
10 u8 function;
11 __le16 ioc_use_only04;
12 u8 ioc_use_only06;
13 u8 msg_flags;
14 __le16 change_count;
15 __le16 reserved0a;
16 union mpi3_version_union mpi_version;
17 __le64 time_stamp;
18 u8 reserved18;
19 u8 who_init;
20 __le16 reserved1a;
21 __le16 reply_free_queue_depth;
22 __le16 reserved1e;
23 __le64 reply_free_queue_address;
24 __le32 reserved28;
25 __le16 sense_buffer_free_queue_depth;
26 __le16 sense_buffer_length;
27 __le64 sense_buffer_free_queue_address;
28 __le64 driver_information_address;
29};
30#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08)
31#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04)
32#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
33#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
34#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01)
35#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02)
36#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03)
37#define MPI3_WHOINIT_NOT_INITIALIZED (0x00)
38#define MPI3_WHOINIT_ROM_BIOS (0x02)
39#define MPI3_WHOINIT_HOST_DRIVER (0x03)
40#define MPI3_WHOINIT_MANUFACTURER (0x04)
41
42#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003)
43#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000)
44#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001)
45#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002)
46#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003)
47
48struct mpi3_ioc_facts_request {
49 __le16 host_tag;
50 u8 ioc_use_only02;
51 u8 function;
52 __le16 ioc_use_only04;
53 u8 ioc_use_only06;
54 u8 msg_flags;
55 __le16 change_count;
56 __le16 reserved0a;
57 __le32 reserved0c;
58 union mpi3_sge_union sgl;
59};
60
61struct mpi3_ioc_facts_data {
62 __le16 ioc_facts_data_length;
63 __le16 reserved02;
64 union mpi3_version_union mpi_version;
65 struct mpi3_comp_image_version fw_version;
66 __le32 ioc_capabilities;
67 u8 ioc_number;
68 u8 who_init;
69 __le16 max_msix_vectors;
70 __le16 max_outstanding_requests;
71 __le16 product_id;
72 __le16 ioc_request_frame_size;
73 __le16 reply_frame_size;
74 __le16 ioc_exceptions;
75 __le16 max_persistent_id;
76 u8 sge_modifier_mask;
77 u8 sge_modifier_value;
78 u8 sge_modifier_shift;
79 u8 protocol_flags;
80 __le16 max_sas_initiators;
81 __le16 max_data_length;
82 __le16 max_sas_expanders;
83 __le16 max_enclosures;
84 __le16 min_dev_handle;
85 __le16 max_dev_handle;
86 __le16 max_pcie_switches;
87 __le16 max_nvme;
88 __le16 reserved38;
89 __le16 max_vds;
90 __le16 max_host_pds;
91 __le16 max_adv_host_pds;
92 __le16 max_raid_pds;
93 __le16 max_posted_cmd_buffers;
94 __le32 flags;
95 __le16 max_operational_request_queues;
96 __le16 max_operational_reply_queues;
97 __le16 shutdown_timeout;
98 __le16 reserved4e;
99 __le32 diag_trace_size;
100 __le32 diag_fw_size;
101 __le32 diag_driver_size;
102 u8 max_host_pd_ns_count;
103 u8 max_adv_host_pd_ns_count;
104 u8 max_raidpd_ns_count;
105 u8 max_devices_per_throttle_group;
106 __le16 io_throttle_data_length;
107 __le16 max_io_throttle_group;
108 __le16 io_throttle_low;
109 __le16 io_throttle_high;
110 __le32 diag_fdl_size;
111 __le32 diag_tty_size;
112};
113#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
114#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
115#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000)
116#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600)
117#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
118#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200)
119#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100)
120#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080)
121#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040)
122#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020)
123#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010)
124#define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008)
125#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002)
126#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001)
127#define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000)
128#define MPI3_IOCFACTS_PID_TYPE_SHIFT (12)
129#define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00)
130#define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8)
131#define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff)
132#define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0)
133#define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000)
134#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000)
135#define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800)
136#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700)
137#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000)
138#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100)
139#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200)
140#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300)
141#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400)
142#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500)
143#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600)
144#define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080)
145#define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040)
146#define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020)
147#define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010)
148#define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008)
149#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004)
150#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002)
151#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001)
152#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000)
153#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001)
154#define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010)
155#define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008)
156#define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004)
157#define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
158#define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
159#define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000)
160#define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000)
161#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00)
162#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8)
163#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030)
164#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000)
165#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010)
166#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020)
167#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f)
168#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000)
169#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
170#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
171#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000)
172#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000)
173#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000)
174struct mpi3_mgmt_passthrough_request {
175 __le16 host_tag;
176 u8 ioc_use_only02;
177 u8 function;
178 __le16 ioc_use_only04;
179 u8 ioc_use_only06;
180 u8 msg_flags;
181 __le16 change_count;
182 __le16 reserved0a;
183 __le32 reserved0c[5];
184 union mpi3_sge_union command_sgl;
185 union mpi3_sge_union response_sgl;
186};
187
188struct mpi3_create_request_queue_request {
189 __le16 host_tag;
190 u8 ioc_use_only02;
191 u8 function;
192 __le16 ioc_use_only04;
193 u8 ioc_use_only06;
194 u8 msg_flags;
195 __le16 change_count;
196 u8 flags;
197 u8 burst;
198 __le16 size;
199 __le16 queue_id;
200 __le16 reply_queue_id;
201 __le16 reserved12;
202 __le32 reserved14;
203 __le64 base_address;
204};
205
206#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
207#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
208#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
209#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2)
210struct mpi3_delete_request_queue_request {
211 __le16 host_tag;
212 u8 ioc_use_only02;
213 u8 function;
214 __le16 ioc_use_only04;
215 u8 ioc_use_only06;
216 u8 msg_flags;
217 __le16 change_count;
218 __le16 queue_id;
219};
220
221struct mpi3_create_reply_queue_request {
222 __le16 host_tag;
223 u8 ioc_use_only02;
224 u8 function;
225 __le16 ioc_use_only04;
226 u8 ioc_use_only06;
227 u8 msg_flags;
228 __le16 change_count;
229 u8 flags;
230 u8 reserved0b;
231 __le16 size;
232 __le16 queue_id;
233 __le16 msix_index;
234 __le16 reserved12;
235 __le32 reserved14;
236 __le64 base_address;
237};
238
239#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
240#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
241#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
242#define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02)
243#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01)
244#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00)
245#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01)
246#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2)
247struct mpi3_delete_reply_queue_request {
248 __le16 host_tag;
249 u8 ioc_use_only02;
250 u8 function;
251 __le16 ioc_use_only04;
252 u8 ioc_use_only06;
253 u8 msg_flags;
254 __le16 change_count;
255 __le16 queue_id;
256};
257
258struct mpi3_port_enable_request {
259 __le16 host_tag;
260 u8 ioc_use_only02;
261 u8 function;
262 __le16 ioc_use_only04;
263 u8 ioc_use_only06;
264 u8 msg_flags;
265 __le16 change_count;
266 __le16 reserved0a;
267};
268
269#define MPI3_EVENT_LOG_DATA (0x01)
270#define MPI3_EVENT_CHANGE (0x02)
271#define MPI3_EVENT_GPIO_INTERRUPT (0x04)
272#define MPI3_EVENT_CABLE_MGMT (0x06)
273#define MPI3_EVENT_DEVICE_ADDED (0x07)
274#define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08)
275#define MPI3_EVENT_PREPARE_FOR_RESET (0x09)
276#define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a)
277#define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b)
278#define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c)
279#define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d)
280#define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e)
281#define MPI3_EVENT_SAS_DISCOVERY (0x11)
282#define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12)
283#define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13)
284#define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14)
285#define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15)
286#define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16)
287#define MPI3_EVENT_SAS_PHY_COUNTER (0x18)
288#define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19)
289#define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20)
290#define MPI3_EVENT_PCIE_ENUMERATION (0x22)
291#define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23)
292#define MPI3_EVENT_HARD_RESET_RECEIVED (0x40)
293#define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50)
294#define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60)
295#define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f)
296#define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4)
297struct mpi3_event_notification_request {
298 __le16 host_tag;
299 u8 ioc_use_only02;
300 u8 function;
301 __le16 ioc_use_only04;
302 u8 ioc_use_only06;
303 u8 msg_flags;
304 __le16 change_count;
305 __le16 reserved0a;
306 __le16 sas_broadcast_primitive_masks;
307 __le16 sas_notify_primitive_masks;
308 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
309};
310
311struct mpi3_event_notification_reply {
312 __le16 host_tag;
313 u8 ioc_use_only02;
314 u8 function;
315 __le16 ioc_use_only04;
316 u8 ioc_use_only06;
317 u8 msg_flags;
318 __le16 ioc_use_only08;
319 __le16 ioc_status;
320 __le32 ioc_log_info;
321 u8 event_data_length;
322 u8 event;
323 __le16 ioc_change_count;
324 __le32 event_context;
325 __le32 event_data[1];
326};
327
328#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01)
329#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01)
330#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00)
331#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02)
332#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00)
333#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02)
334struct mpi3_event_data_gpio_interrupt {
335 u8 gpio_num;
336 u8 reserved01[3];
337};
338struct mpi3_event_data_cable_management {
339 __le32 active_cable_power_requirement;
340 u8 status;
341 u8 receptacle_id;
342 __le16 reserved06;
343};
344
345#define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff)
346#define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00)
347#define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01)
348#define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02)
349struct mpi3_event_ack_request {
350 __le16 host_tag;
351 u8 ioc_use_only02;
352 u8 function;
353 __le16 ioc_use_only04;
354 u8 ioc_use_only06;
355 u8 msg_flags;
356 __le16 change_count;
357 __le16 reserved0a;
358 u8 event;
359 u8 reserved0d[3];
360 __le32 event_context;
361};
362
363struct mpi3_event_data_prepare_for_reset {
364 u8 reason_code;
365 u8 reserved01;
366 __le16 reserved02;
367};
368
369#define MPI3_EVENT_PREPARE_RESET_RC_START (0x01)
370#define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02)
371struct mpi3_event_data_comp_image_activation {
372 __le32 reserved00;
373};
374
375struct mpi3_event_data_device_status_change {
376 __le16 task_tag;
377 u8 reason_code;
378 u8 io_unit_port;
379 __le16 parent_dev_handle;
380 __le16 dev_handle;
381 __le64 wwid;
382 u8 lun[8];
383};
384
385#define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01)
386#define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02)
387#define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03)
388#define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04)
389#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20)
390#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21)
391#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22)
392#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23)
393#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24)
394#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25)
395#define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30)
396#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40)
397#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41)
398#define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50)
399struct mpi3_event_data_energy_pack_change {
400 __le32 reserved00;
401 __le16 shutdown_timeout;
402 __le16 reserved06;
403};
404
405struct mpi3_event_data_sas_discovery {
406 u8 flags;
407 u8 reason_code;
408 u8 io_unit_port;
409 u8 reserved03;
410 __le32 discovery_status;
411};
412
413#define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02)
414#define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01)
415#define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01)
416#define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02)
417#define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000)
418#define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000)
419#define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000)
420#define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000)
421#define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000)
422#define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000)
423#define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000)
424#define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000)
425#define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000)
426#define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800)
427#define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400)
428#define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200)
429#define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100)
430#define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080)
431#define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040)
432#define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020)
433#define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010)
434#define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008)
435#define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004)
436#define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002)
437#define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001)
438struct mpi3_event_data_sas_broadcast_primitive {
439 u8 phy_num;
440 u8 io_unit_port;
441 u8 port_width;
442 u8 primitive;
443};
444
445#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01)
446#define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02)
447#define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03)
448#define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
449#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05)
450#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06)
451#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07)
452#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08)
453struct mpi3_event_data_sas_notify_primitive {
454 u8 phy_num;
455 u8 io_unit_port;
456 u8 reserved02;
457 u8 primitive;
458};
459
460#define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01)
461#define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02)
462#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03)
463#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04)
464struct mpi3_event_sas_topo_phy_entry {
465 __le16 attached_dev_handle;
466 u8 link_rate;
467 u8 status;
468};
469
470#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0)
471#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
472#define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f)
473#define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
474#define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
475#define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
476#define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
477#define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
478#define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
479#define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
480#define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
481#define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a)
482#define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b)
483#define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c)
484#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0)
485#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6)
486#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00)
487#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40)
488#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80)
489#define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f)
490#define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02)
491#define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03)
492#define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04)
493#define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05)
494#define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06)
495struct mpi3_event_data_sas_topology_change_list {
496 __le16 enclosure_handle;
497 __le16 expander_dev_handle;
498 u8 num_phys;
499 u8 reserved05[3];
500 u8 num_entries;
501 u8 start_phy_num;
502 u8 exp_status;
503 u8 io_unit_port;
504 struct mpi3_event_sas_topo_phy_entry phy_entry[] __counted_by(num_entries);
505};
506
507#define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
508#define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
509#define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
510#define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
511struct mpi3_event_data_sas_phy_counter {
512 __le64 time_stamp;
513 __le32 reserved08;
514 u8 phy_event_code;
515 u8 phy_num;
516 __le16 reserved0e;
517 __le32 phy_event_info;
518 u8 counter_type;
519 u8 threshold_window;
520 u8 time_units;
521 u8 reserved17;
522 __le32 event_threshold;
523 __le16 threshold_flags;
524 __le16 reserved1e;
525};
526
527struct mpi3_event_data_sas_device_disc_err {
528 __le16 dev_handle;
529 u8 reason_code;
530 u8 io_unit_port;
531 __le32 reserved04;
532 __le64 sas_address;
533};
534
535#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01)
536#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02)
537struct mpi3_event_data_pcie_enumeration {
538 u8 flags;
539 u8 reason_code;
540 u8 io_unit_port;
541 u8 reserved03;
542 __le32 enumeration_status;
543};
544
545#define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02)
546#define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01)
547#define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01)
548#define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
549#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000)
550#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
551#define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
552#define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
553struct mpi3_event_pcie_topo_port_entry {
554 __le16 attached_dev_handle;
555 u8 port_status;
556 u8 reserved03;
557 u8 current_port_info;
558 u8 reserved05;
559 u8 previous_port_info;
560 u8 reserved07;
561};
562
563#define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
564#define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
565#define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
566#define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
567#define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06)
568#define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0)
569#define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
570#define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10)
571#define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20)
572#define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30)
573#define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40)
574#define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50)
575#define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f)
576#define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
577#define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
578#define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
579#define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
580#define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
581#define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
582#define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06)
583struct mpi3_event_data_pcie_topology_change_list {
584 __le16 enclosure_handle;
585 __le16 switch_dev_handle;
586 u8 num_ports;
587 u8 reserved05[3];
588 u8 num_entries;
589 u8 start_port_num;
590 u8 switch_status;
591 u8 io_unit_port;
592 __le32 reserved0c;
593 struct mpi3_event_pcie_topo_port_entry port_entry[] __counted_by(num_entries);
594};
595
596#define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
597#define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
598#define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
599#define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
600struct mpi3_event_data_pcie_error_threshold {
601 __le64 timestamp;
602 u8 reason_code;
603 u8 port;
604 __le16 switch_dev_handle;
605 u8 error;
606 u8 action;
607 __le16 threshold_count;
608 __le16 attached_dev_handle;
609 __le16 reserved12;
610 __le32 reserved14;
611};
612
613#define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00)
614#define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01)
615struct mpi3_event_data_sas_init_dev_status_change {
616 u8 reason_code;
617 u8 io_unit_port;
618 __le16 dev_handle;
619 __le32 reserved04;
620 __le64 sas_address;
621};
622
623#define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01)
624#define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
625struct mpi3_event_data_sas_init_table_overflow {
626 __le16 max_init;
627 __le16 current_init;
628 __le32 reserved04;
629 __le64 sas_address;
630};
631
632struct mpi3_event_data_hard_reset_received {
633 u8 reserved00;
634 u8 io_unit_port;
635 __le16 reserved02;
636};
637
638struct mpi3_event_data_diag_buffer_status_change {
639 u8 type;
640 u8 reason_code;
641 __le16 reserved02;
642 __le32 reserved04;
643};
644
645#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01)
646#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02)
647#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03)
648#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200)
649#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100)
650#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080)
651#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040)
652#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020)
653#define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010)
654#define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008)
655#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004)
656#define MPI3_PEL_LOCALE_FLAGS_PD (0x0002)
657#define MPI3_PEL_LOCALE_FLAGS_VD (0x0001)
658#define MPI3_PEL_CLASS_DEBUG (0x00)
659#define MPI3_PEL_CLASS_PROGRESS (0x01)
660#define MPI3_PEL_CLASS_INFORMATIONAL (0x02)
661#define MPI3_PEL_CLASS_WARNING (0x03)
662#define MPI3_PEL_CLASS_CRITICAL (0x04)
663#define MPI3_PEL_CLASS_FATAL (0x05)
664#define MPI3_PEL_CLASS_FAULT (0x06)
665#define MPI3_PEL_CLEARTYPE_CLEAR (0x00)
666#define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00)
667#define MPI3_PEL_ACTION_GET_SEQNUM (0x01)
668#define MPI3_PEL_ACTION_MARK_CLEAR (0x02)
669#define MPI3_PEL_ACTION_GET_LOG (0x03)
670#define MPI3_PEL_ACTION_GET_COUNT (0x04)
671#define MPI3_PEL_ACTION_WAIT (0x05)
672#define MPI3_PEL_ACTION_ABORT (0x06)
673#define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07)
674#define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08)
675#define MPI3_PEL_STATUS_SUCCESS (0x00)
676#define MPI3_PEL_STATUS_NOT_FOUND (0x01)
677#define MPI3_PEL_STATUS_ABORTED (0x02)
678#define MPI3_PEL_STATUS_NOT_READY (0x03)
679struct mpi3_pel_seq {
680 __le32 newest;
681 __le32 oldest;
682 __le32 clear;
683 __le32 shutdown;
684 __le32 boot;
685 __le32 last_acknowledged;
686};
687
688struct mpi3_pel_entry {
689 __le64 time_stamp;
690 __le32 sequence_number;
691 __le16 log_code;
692 __le16 arg_type;
693 __le16 locale;
694 u8 class;
695 u8 flags;
696 u8 ext_num;
697 u8 num_exts;
698 u8 arg_data_size;
699 u8 fixed_format_strings_size;
700 __le32 reserved18[2];
701 __le32 pel_info[24];
702};
703
704#define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02)
705#define MPI3_PEL_FLAGS_ACK_NEEDED (0x01)
706struct mpi3_pel_list {
707 __le32 log_count;
708 __le32 reserved04;
709 struct mpi3_pel_entry entry[1];
710};
711
712struct mpi3_pel_arg_map {
713 u8 arg_type;
714 u8 length;
715 __le16 start_location;
716};
717
718#define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00)
719#define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01)
720#define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02)
721#define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03)
722struct mpi3_pel_print_string {
723 __le16 log_code;
724 __le16 string_length;
725 u8 num_arg_map;
726 u8 reserved05[3];
727 struct mpi3_pel_arg_map arg_map[1];
728};
729
730struct mpi3_pel_print_string_list {
731 __le32 num_print_strings;
732 __le32 residual_bytes_remain;
733 __le32 reserved08[2];
734 struct mpi3_pel_print_string print_string[1];
735};
736
737#ifndef MPI3_PEL_ACTION_SPECIFIC_MAX
738#define MPI3_PEL_ACTION_SPECIFIC_MAX (1)
739#endif
740struct mpi3_pel_request {
741 __le16 host_tag;
742 u8 ioc_use_only02;
743 u8 function;
744 __le16 ioc_use_only04;
745 u8 ioc_use_only06;
746 u8 msg_flags;
747 __le16 change_count;
748 u8 action;
749 u8 reserved0b;
750 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX];
751};
752
753struct mpi3_pel_req_action_get_sequence_numbers {
754 __le16 host_tag;
755 u8 ioc_use_only02;
756 u8 function;
757 __le16 ioc_use_only04;
758 u8 ioc_use_only06;
759 u8 msg_flags;
760 __le16 change_count;
761 u8 action;
762 u8 reserved0b;
763 __le32 reserved0c[5];
764 union mpi3_sge_union sgl;
765};
766
767struct mpi3_pel_req_action_clear_log_marker {
768 __le16 host_tag;
769 u8 ioc_use_only02;
770 u8 function;
771 __le16 ioc_use_only04;
772 u8 ioc_use_only06;
773 u8 msg_flags;
774 __le16 change_count;
775 u8 action;
776 u8 reserved0b;
777 u8 clear_type;
778 u8 reserved0d[3];
779};
780
781struct mpi3_pel_req_action_get_log {
782 __le16 host_tag;
783 u8 ioc_use_only02;
784 u8 function;
785 __le16 ioc_use_only04;
786 u8 ioc_use_only06;
787 u8 msg_flags;
788 __le16 change_count;
789 u8 action;
790 u8 reserved0b;
791 __le32 starting_sequence_number;
792 __le16 locale;
793 u8 class;
794 u8 reserved13;
795 __le32 reserved14[3];
796 union mpi3_sge_union sgl;
797};
798
799struct mpi3_pel_req_action_get_count {
800 __le16 host_tag;
801 u8 ioc_use_only02;
802 u8 function;
803 __le16 ioc_use_only04;
804 u8 ioc_use_only06;
805 u8 msg_flags;
806 __le16 change_count;
807 u8 action;
808 u8 reserved0b;
809 __le32 starting_sequence_number;
810 __le16 locale;
811 u8 class;
812 u8 reserved13;
813 __le32 reserved14[3];
814 union mpi3_sge_union sgl;
815};
816
817struct mpi3_pel_req_action_wait {
818 __le16 host_tag;
819 u8 ioc_use_only02;
820 u8 function;
821 __le16 ioc_use_only04;
822 u8 ioc_use_only06;
823 u8 msg_flags;
824 __le16 change_count;
825 u8 action;
826 u8 reserved0b;
827 __le32 starting_sequence_number;
828 __le16 locale;
829 u8 class;
830 u8 reserved13;
831 __le16 wait_time;
832 __le16 reserved16;
833 __le32 reserved18[2];
834};
835
836struct mpi3_pel_req_action_abort {
837 __le16 host_tag;
838 u8 ioc_use_only02;
839 u8 function;
840 __le16 ioc_use_only04;
841 u8 ioc_use_only06;
842 u8 msg_flags;
843 __le16 change_count;
844 u8 action;
845 u8 reserved0b;
846 __le32 reserved0c;
847 __le16 abort_host_tag;
848 __le16 reserved12;
849 __le32 reserved14;
850};
851
852struct mpi3_pel_req_action_get_print_strings {
853 __le16 host_tag;
854 u8 ioc_use_only02;
855 u8 function;
856 __le16 ioc_use_only04;
857 u8 ioc_use_only06;
858 u8 msg_flags;
859 __le16 change_count;
860 u8 action;
861 u8 reserved0b;
862 __le32 reserved0c;
863 __le16 start_log_code;
864 __le16 reserved12;
865 __le32 reserved14[3];
866 union mpi3_sge_union sgl;
867};
868
869struct mpi3_pel_req_action_acknowledge {
870 __le16 host_tag;
871 u8 ioc_use_only02;
872 u8 function;
873 __le16 ioc_use_only04;
874 u8 ioc_use_only06;
875 u8 msg_flags;
876 __le16 change_count;
877 u8 action;
878 u8 reserved0b;
879 __le32 sequence_number;
880 __le32 reserved10;
881};
882
883#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03)
884#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00)
885#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01)
886#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02)
887struct mpi3_pel_reply {
888 __le16 host_tag;
889 u8 ioc_use_only02;
890 u8 function;
891 __le16 ioc_use_only04;
892 u8 ioc_use_only06;
893 u8 msg_flags;
894 __le16 ioc_use_only08;
895 __le16 ioc_status;
896 __le32 ioc_log_info;
897 u8 action;
898 u8 reserved11;
899 __le16 reserved12;
900 __le16 pe_log_status;
901 __le16 reserved16;
902 __le32 transfer_length;
903};
904
905struct mpi3_ci_download_request {
906 __le16 host_tag;
907 u8 ioc_use_only02;
908 u8 function;
909 __le16 ioc_use_only04;
910 u8 ioc_use_only06;
911 u8 msg_flags;
912 __le16 change_count;
913 u8 action;
914 u8 reserved0b;
915 __le32 signature1;
916 __le32 total_image_size;
917 __le32 image_offset;
918 __le32 segment_size;
919 __le32 reserved1c;
920 union mpi3_sge_union sgl;
921};
922
923#define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80)
924#define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40)
925#define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20)
926#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03)
927#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00)
928#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01)
929#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02)
930#define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01)
931#define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02)
932#define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03)
933#define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04)
934#define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05)
935struct mpi3_ci_download_reply {
936 __le16 host_tag;
937 u8 ioc_use_only02;
938 u8 function;
939 __le16 ioc_use_only04;
940 u8 ioc_use_only06;
941 u8 msg_flags;
942 __le16 ioc_use_only08;
943 __le16 ioc_status;
944 __le32 ioc_log_info;
945 u8 flags;
946 u8 cache_dirty;
947 u8 pending_count;
948 u8 reserved13;
949};
950
951#define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80)
952#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40)
953#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
954#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
955#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
956#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00)
957#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02)
958#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04)
959#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06)
960#define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01)
961struct mpi3_ci_upload_request {
962 __le16 host_tag;
963 u8 ioc_use_only02;
964 u8 function;
965 __le16 ioc_use_only04;
966 u8 ioc_use_only06;
967 u8 msg_flags;
968 __le16 change_count;
969 __le16 reserved0a;
970 __le32 signature1;
971 __le32 reserved10;
972 __le32 image_offset;
973 __le32 segment_size;
974 __le32 reserved1c;
975 union mpi3_sge_union sgl;
976};
977
978#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01)
979#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00)
980#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01)
981#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02)
982#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00)
983#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02)
984#define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01)
985#define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02)
986#define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04)
987#define MPI3_CTRL_OP_GET_TIMESTAMP (0x05)
988#define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06)
989#define MPI3_CTRL_OP_CHANGE_PROFILE (0x07)
990#define MPI3_CTRL_OP_REMOVE_DEVICE (0x10)
991#define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11)
992#define MPI3_CTRL_OP_HIDDEN_ACK (0x12)
993#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13)
994#define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20)
995#define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21)
996#define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23)
997#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24)
998#define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30)
999#define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00)
1000#define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00)
1001#define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00)
1002#define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00)
1003#define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00)
1004#define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00)
1005#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00)
1006#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00)
1007#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01)
1008#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00)
1009#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00)
1010#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01)
1011#define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
1012#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
1013#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00)
1014#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00)
1015#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01)
1016#define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1017#define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1018#define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1019#define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04)
1020#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0)
1021#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0)
1022#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0)
1023#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0)
1024#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0)
1025#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0)
1026#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0)
1027#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1)
1028#define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0)
1029#define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0)
1030#define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0)
1031#define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0)
1032#define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01)
1033#define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03)
1034#define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06)
1035#define MPI3_CTRL_ACTION_NOP (0x00)
1036#define MPI3_CTRL_ACTION_LINK_RESET (0x01)
1037#define MPI3_CTRL_ACTION_HARD_RESET (0x02)
1038#define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05)
1039struct mpi3_iounit_control_request {
1040 __le16 host_tag;
1041 u8 ioc_use_only02;
1042 u8 function;
1043 __le16 ioc_use_only04;
1044 u8 ioc_use_only06;
1045 u8 msg_flags;
1046 __le16 change_count;
1047 u8 reserved0a;
1048 u8 operation;
1049 __le32 reserved0c;
1050 __le64 param64[2];
1051 __le32 param32[4];
1052 __le16 param16[4];
1053 u8 param8[8];
1054};
1055
1056struct mpi3_iounit_control_reply {
1057 __le16 host_tag;
1058 u8 ioc_use_only02;
1059 u8 function;
1060 __le16 ioc_use_only04;
1061 u8 ioc_use_only06;
1062 u8 msg_flags;
1063 __le16 ioc_use_only08;
1064 __le16 ioc_status;
1065 __le32 ioc_log_info;
1066 __le64 value64[2];
1067 __le32 value32[4];
1068 __le16 value16[4];
1069 u8 value8[8];
1070};
1071#endif