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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 */
5
6#include <dt-bindings/firmware/imx/rsrc.h>
7#include <linux/arm-smccc.h>
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/firmware/imx/sci.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/mailbox_client.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/platform_device.h>
20#include <linux/pm_domain.h>
21#include <linux/reboot.h>
22#include <linux/regmap.h>
23#include <linux/remoteproc.h>
24#include <linux/workqueue.h>
25
26#include "imx_rproc.h"
27#include "remoteproc_internal.h"
28
29#define IMX7D_SRC_SCR 0x0C
30#define IMX7D_ENABLE_M4 BIT(3)
31#define IMX7D_SW_M4P_RST BIT(2)
32#define IMX7D_SW_M4C_RST BIT(1)
33#define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
34
35#define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
36 | IMX7D_SW_M4C_RST \
37 | IMX7D_SW_M4C_NON_SCLR_RST)
38
39#define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
40 | IMX7D_SW_M4C_RST)
41#define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \
42 IMX7D_SW_M4C_NON_SCLR_RST)
43
44#define IMX8M_M7_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST)
45#define IMX8M_M7_POLL IMX7D_ENABLE_M4
46
47#define IMX8M_GPR22 0x58
48#define IMX8M_GPR22_CM7_CPUWAIT BIT(0)
49
50/* Address: 0x020D8000 */
51#define IMX6SX_SRC_SCR 0x00
52#define IMX6SX_ENABLE_M4 BIT(22)
53#define IMX6SX_SW_M4P_RST BIT(12)
54#define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4)
55#define IMX6SX_SW_M4C_RST BIT(3)
56
57#define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
58 | IMX6SX_SW_M4C_RST)
59#define IMX6SX_M4_STOP (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4C_RST | \
60 IMX6SX_SW_M4C_NON_SCLR_RST)
61#define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
62 | IMX6SX_SW_M4C_NON_SCLR_RST \
63 | IMX6SX_SW_M4C_RST)
64
65#define IMX_RPROC_MEM_MAX 32
66
67#define IMX_SIP_RPROC 0xC2000005
68#define IMX_SIP_RPROC_START 0x00
69#define IMX_SIP_RPROC_STARTED 0x01
70#define IMX_SIP_RPROC_STOP 0x02
71
72#define IMX_SC_IRQ_GROUP_REBOOTED 5
73
74/**
75 * struct imx_rproc_mem - slim internal memory structure
76 * @cpu_addr: MPU virtual address of the memory region
77 * @sys_addr: Bus address used to access the memory region
78 * @size: Size of the memory region
79 */
80struct imx_rproc_mem {
81 void __iomem *cpu_addr;
82 phys_addr_t sys_addr;
83 size_t size;
84};
85
86/* att flags: lower 16 bits specifying core, higher 16 bits for flags */
87/* M4 own area. Can be mapped at probe */
88#define ATT_OWN BIT(31)
89#define ATT_IOMEM BIT(30)
90
91#define ATT_CORE_MASK 0xffff
92#define ATT_CORE(I) BIT((I))
93
94static int imx_rproc_xtr_mbox_init(struct rproc *rproc, bool tx_block);
95static void imx_rproc_free_mbox(struct rproc *rproc);
96
97struct imx_rproc {
98 struct device *dev;
99 struct regmap *regmap;
100 struct regmap *gpr;
101 struct rproc *rproc;
102 const struct imx_rproc_dcfg *dcfg;
103 struct imx_rproc_mem mem[IMX_RPROC_MEM_MAX];
104 struct clk *clk;
105 struct mbox_client cl;
106 struct mbox_chan *tx_ch;
107 struct mbox_chan *rx_ch;
108 struct work_struct rproc_work;
109 struct workqueue_struct *workqueue;
110 void __iomem *rsc_table;
111 struct imx_sc_ipc *ipc_handle;
112 struct notifier_block rproc_nb;
113 u32 rproc_pt; /* partition id */
114 u32 rsrc_id; /* resource id */
115 u32 entry; /* cpu start address */
116 u32 core_index;
117 struct dev_pm_domain_list *pd_list;
118};
119
120static const struct imx_rproc_att imx_rproc_att_imx93[] = {
121 /* dev addr , sys addr , size , flags */
122 /* TCM CODE NON-SECURE */
123 { 0x0FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
124
125 /* TCM CODE SECURE */
126 { 0x1FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
127
128 /* TCM SYS NON-SECURE*/
129 { 0x20000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
130
131 /* TCM SYS SECURE*/
132 { 0x30000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
133
134 /* DDR */
135 { 0x80000000, 0x80000000, 0x10000000, 0 },
136 { 0x90000000, 0x80000000, 0x10000000, 0 },
137
138 { 0xC0000000, 0xC0000000, 0x10000000, 0 },
139 { 0xD0000000, 0xC0000000, 0x10000000, 0 },
140};
141
142static const struct imx_rproc_att imx_rproc_att_imx8qm[] = {
143 /* dev addr , sys addr , size , flags */
144 { 0x08000000, 0x08000000, 0x10000000, 0},
145 /* TCML */
146 { 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
147 { 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
148 /* TCMU */
149 { 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
150 { 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
151 /* DDR (Data) */
152 { 0x80000000, 0x80000000, 0x60000000, 0 },
153};
154
155static const struct imx_rproc_att imx_rproc_att_imx8qxp[] = {
156 { 0x08000000, 0x08000000, 0x10000000, 0 },
157 /* TCML/U */
158 { 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM },
159 /* OCRAM(Low 96KB) */
160 { 0x21000000, 0x00100000, 0x00018000, 0 },
161 /* OCRAM */
162 { 0x21100000, 0x00100000, 0x00040000, 0 },
163 /* DDR (Data) */
164 { 0x80000000, 0x80000000, 0x60000000, 0 },
165};
166
167static const struct imx_rproc_att imx_rproc_att_imx8mn[] = {
168 /* dev addr , sys addr , size , flags */
169 /* ITCM */
170 { 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
171 /* OCRAM_S */
172 { 0x00180000, 0x00180000, 0x00009000, 0 },
173 /* OCRAM */
174 { 0x00900000, 0x00900000, 0x00020000, 0 },
175 /* OCRAM */
176 { 0x00920000, 0x00920000, 0x00020000, 0 },
177 /* OCRAM */
178 { 0x00940000, 0x00940000, 0x00050000, 0 },
179 /* QSPI Code - alias */
180 { 0x08000000, 0x08000000, 0x08000000, 0 },
181 /* DDR (Code) - alias */
182 { 0x10000000, 0x40000000, 0x0FFE0000, 0 },
183 /* DTCM */
184 { 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM },
185 /* OCRAM_S - alias */
186 { 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
187 /* OCRAM */
188 { 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
189 /* OCRAM */
190 { 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
191 /* OCRAM */
192 { 0x20240000, 0x00940000, 0x00040000, ATT_OWN },
193 /* DDR (Data) */
194 { 0x40000000, 0x40000000, 0x80000000, 0 },
195};
196
197static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
198 /* dev addr , sys addr , size , flags */
199 /* TCML - alias */
200 { 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM},
201 /* OCRAM_S */
202 { 0x00180000, 0x00180000, 0x00008000, 0 },
203 /* OCRAM */
204 { 0x00900000, 0x00900000, 0x00020000, 0 },
205 /* OCRAM */
206 { 0x00920000, 0x00920000, 0x00020000, 0 },
207 /* QSPI Code - alias */
208 { 0x08000000, 0x08000000, 0x08000000, 0 },
209 /* DDR (Code) - alias */
210 { 0x10000000, 0x40000000, 0x0FFE0000, 0 },
211 /* TCML/U */
212 { 0x1FFE0000, 0x007E0000, 0x00040000, ATT_OWN | ATT_IOMEM},
213 /* OCRAM_S */
214 { 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
215 /* OCRAM */
216 { 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
217 /* OCRAM */
218 { 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
219 /* DDR (Data) */
220 { 0x40000000, 0x40000000, 0x80000000, 0 },
221};
222
223static const struct imx_rproc_att imx_rproc_att_imx8ulp[] = {
224 {0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN},
225 {0x21000000, 0x21000000, 0x10000, ATT_OWN},
226 {0x80000000, 0x80000000, 0x60000000, 0}
227};
228
229static const struct imx_rproc_att imx_rproc_att_imx7ulp[] = {
230 {0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN},
231 {0x20000000, 0x20000000, 0x10000, ATT_OWN},
232 {0x2F000000, 0x2F000000, 0x20000, ATT_OWN},
233 {0x2F020000, 0x2F020000, 0x20000, ATT_OWN},
234 {0x60000000, 0x60000000, 0x40000000, 0}
235};
236
237static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
238 /* dev addr , sys addr , size , flags */
239 /* OCRAM_S (M4 Boot code) - alias */
240 { 0x00000000, 0x00180000, 0x00008000, 0 },
241 /* OCRAM_S (Code) */
242 { 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
243 /* OCRAM (Code) - alias */
244 { 0x00900000, 0x00900000, 0x00020000, 0 },
245 /* OCRAM_EPDC (Code) - alias */
246 { 0x00920000, 0x00920000, 0x00020000, 0 },
247 /* OCRAM_PXP (Code) - alias */
248 { 0x00940000, 0x00940000, 0x00008000, 0 },
249 /* TCML (Code) */
250 { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
251 /* DDR (Code) - alias, first part of DDR (Data) */
252 { 0x10000000, 0x80000000, 0x0FFF0000, 0 },
253
254 /* TCMU (Data) */
255 { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
256 /* OCRAM (Data) */
257 { 0x20200000, 0x00900000, 0x00020000, 0 },
258 /* OCRAM_EPDC (Data) */
259 { 0x20220000, 0x00920000, 0x00020000, 0 },
260 /* OCRAM_PXP (Data) */
261 { 0x20240000, 0x00940000, 0x00008000, 0 },
262 /* DDR (Data) */
263 { 0x80000000, 0x80000000, 0x60000000, 0 },
264};
265
266static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
267 /* dev addr , sys addr , size , flags */
268 /* TCML (M4 Boot Code) - alias */
269 { 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM },
270 /* OCRAM_S (Code) */
271 { 0x00180000, 0x008F8000, 0x00004000, 0 },
272 /* OCRAM_S (Code) - alias */
273 { 0x00180000, 0x008FC000, 0x00004000, 0 },
274 /* TCML (Code) */
275 { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
276 /* DDR (Code) - alias, first part of DDR (Data) */
277 { 0x10000000, 0x80000000, 0x0FFF8000, 0 },
278
279 /* TCMU (Data) */
280 { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
281 /* OCRAM_S (Data) - alias? */
282 { 0x208F8000, 0x008F8000, 0x00004000, 0 },
283 /* DDR (Data) */
284 { 0x80000000, 0x80000000, 0x60000000, 0 },
285};
286
287static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn_mmio = {
288 .src_reg = IMX7D_SRC_SCR,
289 .src_mask = IMX7D_M4_RST_MASK,
290 .src_start = IMX7D_M4_START,
291 .src_stop = IMX8M_M7_STOP,
292 .gpr_reg = IMX8M_GPR22,
293 .gpr_wait = IMX8M_GPR22_CM7_CPUWAIT,
294 .att = imx_rproc_att_imx8mn,
295 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mn),
296 .method = IMX_RPROC_MMIO,
297};
298
299static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn = {
300 .att = imx_rproc_att_imx8mn,
301 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mn),
302 .method = IMX_RPROC_SMC,
303};
304
305static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
306 .src_reg = IMX7D_SRC_SCR,
307 .src_mask = IMX7D_M4_RST_MASK,
308 .src_start = IMX7D_M4_START,
309 .src_stop = IMX7D_M4_STOP,
310 .att = imx_rproc_att_imx8mq,
311 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mq),
312 .method = IMX_RPROC_MMIO,
313};
314
315static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qm = {
316 .att = imx_rproc_att_imx8qm,
317 .att_size = ARRAY_SIZE(imx_rproc_att_imx8qm),
318 .method = IMX_RPROC_SCU_API,
319};
320
321static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qxp = {
322 .att = imx_rproc_att_imx8qxp,
323 .att_size = ARRAY_SIZE(imx_rproc_att_imx8qxp),
324 .method = IMX_RPROC_SCU_API,
325};
326
327static const struct imx_rproc_dcfg imx_rproc_cfg_imx8ulp = {
328 .att = imx_rproc_att_imx8ulp,
329 .att_size = ARRAY_SIZE(imx_rproc_att_imx8ulp),
330 .method = IMX_RPROC_NONE,
331};
332
333static const struct imx_rproc_dcfg imx_rproc_cfg_imx7ulp = {
334 .att = imx_rproc_att_imx7ulp,
335 .att_size = ARRAY_SIZE(imx_rproc_att_imx7ulp),
336 .method = IMX_RPROC_NONE,
337 .flags = IMX_RPROC_NEED_SYSTEM_OFF,
338};
339
340static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
341 .src_reg = IMX7D_SRC_SCR,
342 .src_mask = IMX7D_M4_RST_MASK,
343 .src_start = IMX7D_M4_START,
344 .src_stop = IMX7D_M4_STOP,
345 .att = imx_rproc_att_imx7d,
346 .att_size = ARRAY_SIZE(imx_rproc_att_imx7d),
347 .method = IMX_RPROC_MMIO,
348};
349
350static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
351 .src_reg = IMX6SX_SRC_SCR,
352 .src_mask = IMX6SX_M4_RST_MASK,
353 .src_start = IMX6SX_M4_START,
354 .src_stop = IMX6SX_M4_STOP,
355 .att = imx_rproc_att_imx6sx,
356 .att_size = ARRAY_SIZE(imx_rproc_att_imx6sx),
357 .method = IMX_RPROC_MMIO,
358};
359
360static const struct imx_rproc_dcfg imx_rproc_cfg_imx93 = {
361 .att = imx_rproc_att_imx93,
362 .att_size = ARRAY_SIZE(imx_rproc_att_imx93),
363 .method = IMX_RPROC_SMC,
364};
365
366static int imx_rproc_start(struct rproc *rproc)
367{
368 struct imx_rproc *priv = rproc->priv;
369 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
370 struct device *dev = priv->dev;
371 struct arm_smccc_res res;
372 int ret;
373
374 ret = imx_rproc_xtr_mbox_init(rproc, true);
375 if (ret)
376 return ret;
377
378 switch (dcfg->method) {
379 case IMX_RPROC_MMIO:
380 if (priv->gpr) {
381 ret = regmap_clear_bits(priv->gpr, dcfg->gpr_reg,
382 dcfg->gpr_wait);
383 } else {
384 ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
385 dcfg->src_mask,
386 dcfg->src_start);
387 }
388 break;
389 case IMX_RPROC_SMC:
390 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res);
391 ret = res.a0;
392 break;
393 case IMX_RPROC_SCU_API:
394 ret = imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, true, priv->entry);
395 break;
396 default:
397 return -EOPNOTSUPP;
398 }
399
400 if (ret)
401 dev_err(dev, "Failed to enable remote core!\n");
402
403 return ret;
404}
405
406static int imx_rproc_stop(struct rproc *rproc)
407{
408 struct imx_rproc *priv = rproc->priv;
409 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
410 struct device *dev = priv->dev;
411 struct arm_smccc_res res;
412 int ret;
413
414 switch (dcfg->method) {
415 case IMX_RPROC_MMIO:
416 if (priv->gpr) {
417 ret = regmap_set_bits(priv->gpr, dcfg->gpr_reg,
418 dcfg->gpr_wait);
419 if (ret) {
420 dev_err(priv->dev,
421 "Failed to quiescence M4 platform!\n");
422 return ret;
423 }
424 }
425
426 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask,
427 dcfg->src_stop);
428 break;
429 case IMX_RPROC_SMC:
430 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res);
431 ret = res.a0;
432 if (res.a1)
433 dev_info(dev, "Not in wfi, force stopped\n");
434 break;
435 case IMX_RPROC_SCU_API:
436 ret = imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, false, priv->entry);
437 break;
438 default:
439 return -EOPNOTSUPP;
440 }
441
442 if (ret)
443 dev_err(dev, "Failed to stop remote core\n");
444 else
445 imx_rproc_free_mbox(rproc);
446
447 return ret;
448}
449
450static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
451 size_t len, u64 *sys, bool *is_iomem)
452{
453 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
454 int i;
455
456 /* parse address translation table */
457 for (i = 0; i < dcfg->att_size; i++) {
458 const struct imx_rproc_att *att = &dcfg->att[i];
459
460 /*
461 * Ignore entries not belong to current core:
462 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries
463 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has
464 * "ATT_CORE(1) & BIT(1)" true.
465 */
466 if (att->flags & ATT_CORE_MASK) {
467 if (!((BIT(priv->core_index)) & (att->flags & ATT_CORE_MASK)))
468 continue;
469 }
470
471 if (da >= att->da && da + len < att->da + att->size) {
472 unsigned int offset = da - att->da;
473
474 *sys = att->sa + offset;
475 if (is_iomem)
476 *is_iomem = att->flags & ATT_IOMEM;
477 return 0;
478 }
479 }
480
481 dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",
482 da, len);
483 return -ENOENT;
484}
485
486static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
487{
488 struct imx_rproc *priv = rproc->priv;
489 void *va = NULL;
490 u64 sys;
491 int i;
492
493 if (len == 0)
494 return NULL;
495
496 /*
497 * On device side we have many aliases, so we need to convert device
498 * address (M4) to system bus address first.
499 */
500 if (imx_rproc_da_to_sys(priv, da, len, &sys, is_iomem))
501 return NULL;
502
503 for (i = 0; i < IMX_RPROC_MEM_MAX; i++) {
504 if (sys >= priv->mem[i].sys_addr && sys + len <
505 priv->mem[i].sys_addr + priv->mem[i].size) {
506 unsigned int offset = sys - priv->mem[i].sys_addr;
507 /* __force to make sparse happy with type conversion */
508 va = (__force void *)(priv->mem[i].cpu_addr + offset);
509 break;
510 }
511 }
512
513 dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",
514 da, len, va);
515
516 return va;
517}
518
519static int imx_rproc_mem_alloc(struct rproc *rproc,
520 struct rproc_mem_entry *mem)
521{
522 struct device *dev = rproc->dev.parent;
523 void *va;
524
525 dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len);
526 va = ioremap_wc(mem->dma, mem->len);
527 if (IS_ERR_OR_NULL(va)) {
528 dev_err(dev, "Unable to map memory region: %p+%zx\n",
529 &mem->dma, mem->len);
530 return -ENOMEM;
531 }
532
533 /* Update memory entry va */
534 mem->va = va;
535
536 return 0;
537}
538
539static int imx_rproc_mem_release(struct rproc *rproc,
540 struct rproc_mem_entry *mem)
541{
542 dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma);
543 iounmap(mem->va);
544
545 return 0;
546}
547
548static int imx_rproc_prepare(struct rproc *rproc)
549{
550 struct imx_rproc *priv = rproc->priv;
551 struct device_node *np = priv->dev->of_node;
552 struct of_phandle_iterator it;
553 struct rproc_mem_entry *mem;
554 struct reserved_mem *rmem;
555 u32 da;
556
557 /* Register associated reserved memory regions */
558 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
559 while (of_phandle_iterator_next(&it) == 0) {
560 /*
561 * Ignore the first memory region which will be used vdev buffer.
562 * No need to do extra handlings, rproc_add_virtio_dev will handle it.
563 */
564 if (!strcmp(it.node->name, "vdev0buffer"))
565 continue;
566
567 if (!strcmp(it.node->name, "rsc-table"))
568 continue;
569
570 rmem = of_reserved_mem_lookup(it.node);
571 if (!rmem) {
572 of_node_put(it.node);
573 dev_err(priv->dev, "unable to acquire memory-region\n");
574 return -EINVAL;
575 }
576
577 /* No need to translate pa to da, i.MX use same map */
578 da = rmem->base;
579
580 /* Register memory region */
581 mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da,
582 imx_rproc_mem_alloc, imx_rproc_mem_release,
583 it.node->name);
584
585 if (mem) {
586 rproc_coredump_add_segment(rproc, da, rmem->size);
587 } else {
588 of_node_put(it.node);
589 return -ENOMEM;
590 }
591
592 rproc_add_carveout(rproc, mem);
593 }
594
595 return 0;
596}
597
598static int imx_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
599{
600 int ret;
601
602 ret = rproc_elf_load_rsc_table(rproc, fw);
603 if (ret)
604 dev_info(&rproc->dev, "No resource table in elf\n");
605
606 return 0;
607}
608
609static void imx_rproc_kick(struct rproc *rproc, int vqid)
610{
611 struct imx_rproc *priv = rproc->priv;
612 int err;
613 __u32 mmsg;
614
615 if (!priv->tx_ch) {
616 dev_err(priv->dev, "No initialized mbox tx channel\n");
617 return;
618 }
619
620 /*
621 * Send the index of the triggered virtqueue as the mu payload.
622 * Let remote processor know which virtqueue is used.
623 */
624 mmsg = vqid << 16;
625
626 err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
627 if (err < 0)
628 dev_err(priv->dev, "%s: failed (%d, err:%d)\n",
629 __func__, vqid, err);
630}
631
632static int imx_rproc_attach(struct rproc *rproc)
633{
634 return imx_rproc_xtr_mbox_init(rproc, true);
635}
636
637static int imx_rproc_detach(struct rproc *rproc)
638{
639 struct imx_rproc *priv = rproc->priv;
640 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
641
642 if (dcfg->method != IMX_RPROC_SCU_API)
643 return -EOPNOTSUPP;
644
645 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
646 return -EOPNOTSUPP;
647
648 imx_rproc_free_mbox(rproc);
649
650 return 0;
651}
652
653static struct resource_table *imx_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz)
654{
655 struct imx_rproc *priv = rproc->priv;
656
657 /* The resource table has already been mapped in imx_rproc_addr_init */
658 if (!priv->rsc_table)
659 return NULL;
660
661 *table_sz = SZ_1K;
662 return (struct resource_table *)priv->rsc_table;
663}
664
665static struct resource_table *
666imx_rproc_elf_find_loaded_rsc_table(struct rproc *rproc, const struct firmware *fw)
667{
668 struct imx_rproc *priv = rproc->priv;
669
670 if (priv->rsc_table)
671 return (struct resource_table *)priv->rsc_table;
672
673 return rproc_elf_find_loaded_rsc_table(rproc, fw);
674}
675
676static const struct rproc_ops imx_rproc_ops = {
677 .prepare = imx_rproc_prepare,
678 .attach = imx_rproc_attach,
679 .detach = imx_rproc_detach,
680 .start = imx_rproc_start,
681 .stop = imx_rproc_stop,
682 .kick = imx_rproc_kick,
683 .da_to_va = imx_rproc_da_to_va,
684 .load = rproc_elf_load_segments,
685 .parse_fw = imx_rproc_parse_fw,
686 .find_loaded_rsc_table = imx_rproc_elf_find_loaded_rsc_table,
687 .get_loaded_rsc_table = imx_rproc_get_loaded_rsc_table,
688 .sanity_check = rproc_elf_sanity_check,
689 .get_boot_addr = rproc_elf_get_boot_addr,
690};
691
692static int imx_rproc_addr_init(struct imx_rproc *priv,
693 struct platform_device *pdev)
694{
695 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
696 struct device *dev = &pdev->dev;
697 struct device_node *np = dev->of_node;
698 int a, b = 0, err, nph;
699
700 /* remap required addresses */
701 for (a = 0; a < dcfg->att_size; a++) {
702 const struct imx_rproc_att *att = &dcfg->att[a];
703
704 if (!(att->flags & ATT_OWN))
705 continue;
706
707 if (b >= IMX_RPROC_MEM_MAX)
708 break;
709
710 if (att->flags & ATT_IOMEM)
711 priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
712 att->sa, att->size);
713 else
714 priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev,
715 att->sa, att->size);
716 if (!priv->mem[b].cpu_addr) {
717 dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa);
718 return -ENOMEM;
719 }
720 priv->mem[b].sys_addr = att->sa;
721 priv->mem[b].size = att->size;
722 b++;
723 }
724
725 /* memory-region is optional property */
726 nph = of_count_phandle_with_args(np, "memory-region", NULL);
727 if (nph <= 0)
728 return 0;
729
730 /* remap optional addresses */
731 for (a = 0; a < nph; a++) {
732 struct device_node *node;
733 struct resource res;
734
735 node = of_parse_phandle(np, "memory-region", a);
736 if (!node)
737 continue;
738 /* Not map vdevbuffer, vdevring region */
739 if (!strncmp(node->name, "vdev", strlen("vdev"))) {
740 of_node_put(node);
741 continue;
742 }
743 err = of_address_to_resource(node, 0, &res);
744 if (err) {
745 dev_err(dev, "unable to resolve memory region\n");
746 of_node_put(node);
747 return err;
748 }
749
750 if (b >= IMX_RPROC_MEM_MAX) {
751 of_node_put(node);
752 break;
753 }
754
755 /* Not use resource version, because we might share region */
756 priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev, res.start, resource_size(&res));
757 if (!priv->mem[b].cpu_addr) {
758 dev_err(dev, "failed to remap %pr\n", &res);
759 of_node_put(node);
760 return -ENOMEM;
761 }
762 priv->mem[b].sys_addr = res.start;
763 priv->mem[b].size = resource_size(&res);
764 if (!strcmp(node->name, "rsc-table"))
765 priv->rsc_table = priv->mem[b].cpu_addr;
766 of_node_put(node);
767 b++;
768 }
769
770 return 0;
771}
772
773static int imx_rproc_notified_idr_cb(int id, void *ptr, void *data)
774{
775 struct rproc *rproc = data;
776
777 rproc_vq_interrupt(rproc, id);
778
779 return 0;
780}
781
782static void imx_rproc_vq_work(struct work_struct *work)
783{
784 struct imx_rproc *priv = container_of(work, struct imx_rproc,
785 rproc_work);
786 struct rproc *rproc = priv->rproc;
787
788 idr_for_each(&rproc->notifyids, imx_rproc_notified_idr_cb, rproc);
789}
790
791static void imx_rproc_rx_callback(struct mbox_client *cl, void *msg)
792{
793 struct rproc *rproc = dev_get_drvdata(cl->dev);
794 struct imx_rproc *priv = rproc->priv;
795
796 queue_work(priv->workqueue, &priv->rproc_work);
797}
798
799static int imx_rproc_xtr_mbox_init(struct rproc *rproc, bool tx_block)
800{
801 struct imx_rproc *priv = rproc->priv;
802 struct device *dev = priv->dev;
803 struct mbox_client *cl;
804
805 /*
806 * stop() and detach() will free the mbox channels, so need
807 * to request mbox channels in start() and attach().
808 *
809 * Because start() and attach() not able to handle mbox defer
810 * probe, imx_rproc_xtr_mbox_init is also called in probe().
811 * The check is to avoid request mbox again when start() or
812 * attach() after probe() returns success.
813 */
814 if (priv->tx_ch && priv->rx_ch)
815 return 0;
816
817 if (!of_property_present(dev->of_node, "mbox-names"))
818 return 0;
819
820 cl = &priv->cl;
821 cl->dev = dev;
822 cl->tx_block = tx_block;
823 cl->tx_tout = 100;
824 cl->knows_txdone = false;
825 cl->rx_callback = imx_rproc_rx_callback;
826
827 priv->tx_ch = mbox_request_channel_byname(cl, "tx");
828 if (IS_ERR(priv->tx_ch))
829 return dev_err_probe(cl->dev, PTR_ERR(priv->tx_ch),
830 "failed to request tx mailbox channel\n");
831
832 priv->rx_ch = mbox_request_channel_byname(cl, "rx");
833 if (IS_ERR(priv->rx_ch)) {
834 mbox_free_channel(priv->tx_ch);
835 return dev_err_probe(cl->dev, PTR_ERR(priv->rx_ch),
836 "failed to request rx mailbox channel\n");
837 }
838
839 return 0;
840}
841
842static void imx_rproc_free_mbox(struct rproc *rproc)
843{
844 struct imx_rproc *priv = rproc->priv;
845
846 if (priv->tx_ch) {
847 mbox_free_channel(priv->tx_ch);
848 priv->tx_ch = NULL;
849 }
850
851 if (priv->rx_ch) {
852 mbox_free_channel(priv->rx_ch);
853 priv->rx_ch = NULL;
854 }
855}
856
857static void imx_rproc_put_scu(struct rproc *rproc)
858{
859 struct imx_rproc *priv = rproc->priv;
860 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
861
862 if (dcfg->method != IMX_RPROC_SCU_API)
863 return;
864
865 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) {
866 dev_pm_domain_detach_list(priv->pd_list);
867 return;
868 }
869
870 imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt), false);
871 imx_scu_irq_unregister_notifier(&priv->rproc_nb);
872}
873
874static int imx_rproc_partition_notify(struct notifier_block *nb,
875 unsigned long event, void *group)
876{
877 struct imx_rproc *priv = container_of(nb, struct imx_rproc, rproc_nb);
878
879 /* Ignore other irqs */
880 if (!((event & BIT(priv->rproc_pt)) && (*(u8 *)group == IMX_SC_IRQ_GROUP_REBOOTED)))
881 return 0;
882
883 rproc_report_crash(priv->rproc, RPROC_WATCHDOG);
884
885 pr_info("Partition%d reset!\n", priv->rproc_pt);
886
887 return 0;
888}
889
890static int imx_rproc_attach_pd(struct imx_rproc *priv)
891{
892 struct device *dev = priv->dev;
893 int ret;
894 struct dev_pm_domain_attach_data pd_data = {
895 .pd_flags = PD_FLAG_DEV_LINK_ON,
896 };
897
898 /*
899 * If there is only one power-domain entry, the platform driver framework
900 * will handle it, no need handle it in this driver.
901 */
902 if (dev->pm_domain)
903 return 0;
904
905 ret = dev_pm_domain_attach_list(dev, &pd_data, &priv->pd_list);
906 return ret < 0 ? ret : 0;
907}
908
909static int imx_rproc_detect_mode(struct imx_rproc *priv)
910{
911 struct regmap_config config = { .name = "imx-rproc" };
912 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
913 struct device *dev = priv->dev;
914 struct regmap *regmap;
915 struct arm_smccc_res res;
916 int ret;
917 u32 val;
918 u8 pt;
919
920 switch (dcfg->method) {
921 case IMX_RPROC_NONE:
922 priv->rproc->state = RPROC_DETACHED;
923 return 0;
924 case IMX_RPROC_SMC:
925 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res);
926 if (res.a0)
927 priv->rproc->state = RPROC_DETACHED;
928 return 0;
929 case IMX_RPROC_SCU_API:
930 ret = imx_scu_get_handle(&priv->ipc_handle);
931 if (ret)
932 return ret;
933 ret = of_property_read_u32(dev->of_node, "fsl,resource-id", &priv->rsrc_id);
934 if (ret) {
935 dev_err(dev, "No fsl,resource-id property\n");
936 return ret;
937 }
938
939 if (priv->rsrc_id == IMX_SC_R_M4_1_PID0)
940 priv->core_index = 1;
941 else
942 priv->core_index = 0;
943
944 /*
945 * If Mcore resource is not owned by Acore partition, It is kicked by ROM,
946 * and Linux could only do IPC with Mcore and nothing else.
947 */
948 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) {
949 if (of_property_read_u32(dev->of_node, "fsl,entry-address", &priv->entry))
950 return -EINVAL;
951
952 return imx_rproc_attach_pd(priv);
953 }
954
955 priv->rproc->state = RPROC_DETACHED;
956 priv->rproc->recovery_disabled = false;
957 rproc_set_feature(priv->rproc, RPROC_FEAT_ATTACH_ON_RECOVERY);
958
959 /* Get partition id and enable irq in SCFW */
960 ret = imx_sc_rm_get_resource_owner(priv->ipc_handle, priv->rsrc_id, &pt);
961 if (ret) {
962 dev_err(dev, "not able to get resource owner\n");
963 return ret;
964 }
965
966 priv->rproc_pt = pt;
967 priv->rproc_nb.notifier_call = imx_rproc_partition_notify;
968
969 ret = imx_scu_irq_register_notifier(&priv->rproc_nb);
970 if (ret) {
971 dev_err(dev, "register scu notifier failed, %d\n", ret);
972 return ret;
973 }
974
975 ret = imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt),
976 true);
977 if (ret) {
978 imx_scu_irq_unregister_notifier(&priv->rproc_nb);
979 dev_err(dev, "Enable irq failed, %d\n", ret);
980 return ret;
981 }
982
983 return 0;
984 default:
985 break;
986 }
987
988 priv->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,iomuxc-gpr");
989 if (IS_ERR(priv->gpr))
990 priv->gpr = NULL;
991
992 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
993 if (IS_ERR(regmap)) {
994 dev_err(dev, "failed to find syscon\n");
995 return PTR_ERR(regmap);
996 }
997
998 priv->regmap = regmap;
999 regmap_attach_dev(dev, regmap, &config);
1000
1001 if (priv->gpr) {
1002 ret = regmap_read(priv->gpr, dcfg->gpr_reg, &val);
1003 if (val & dcfg->gpr_wait) {
1004 /*
1005 * After cold boot, the CM indicates its in wait
1006 * state, but not fully powered off. Power it off
1007 * fully so firmware can be loaded into it.
1008 */
1009 imx_rproc_stop(priv->rproc);
1010 return 0;
1011 }
1012 }
1013
1014 ret = regmap_read(regmap, dcfg->src_reg, &val);
1015 if (ret) {
1016 dev_err(dev, "Failed to read src\n");
1017 return ret;
1018 }
1019
1020 if ((val & dcfg->src_mask) != dcfg->src_stop)
1021 priv->rproc->state = RPROC_DETACHED;
1022
1023 return 0;
1024}
1025
1026static int imx_rproc_clk_enable(struct imx_rproc *priv)
1027{
1028 const struct imx_rproc_dcfg *dcfg = priv->dcfg;
1029 struct device *dev = priv->dev;
1030 int ret;
1031
1032 /* Remote core is not under control of Linux */
1033 if (dcfg->method == IMX_RPROC_NONE)
1034 return 0;
1035
1036 priv->clk = devm_clk_get(dev, NULL);
1037 if (IS_ERR(priv->clk)) {
1038 dev_err(dev, "Failed to get clock\n");
1039 return PTR_ERR(priv->clk);
1040 }
1041
1042 /*
1043 * clk for M4 block including memory. Should be
1044 * enabled before .start for FW transfer.
1045 */
1046 ret = clk_prepare_enable(priv->clk);
1047 if (ret) {
1048 dev_err(dev, "Failed to enable clock\n");
1049 return ret;
1050 }
1051
1052 return 0;
1053}
1054
1055static int imx_rproc_sys_off_handler(struct sys_off_data *data)
1056{
1057 struct rproc *rproc = data->cb_data;
1058 int ret;
1059
1060 imx_rproc_free_mbox(rproc);
1061
1062 ret = imx_rproc_xtr_mbox_init(rproc, false);
1063 if (ret) {
1064 dev_err(&rproc->dev, "Failed to request non-blocking mbox\n");
1065 return NOTIFY_BAD;
1066 }
1067
1068 return NOTIFY_DONE;
1069}
1070
1071static int imx_rproc_probe(struct platform_device *pdev)
1072{
1073 struct device *dev = &pdev->dev;
1074 struct device_node *np = dev->of_node;
1075 struct imx_rproc *priv;
1076 struct rproc *rproc;
1077 const struct imx_rproc_dcfg *dcfg;
1078 int ret;
1079
1080 /* set some other name then imx */
1081 rproc = devm_rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
1082 NULL, sizeof(*priv));
1083 if (!rproc)
1084 return -ENOMEM;
1085
1086 dcfg = of_device_get_match_data(dev);
1087 if (!dcfg)
1088 return -EINVAL;
1089
1090 priv = rproc->priv;
1091 priv->rproc = rproc;
1092 priv->dcfg = dcfg;
1093 priv->dev = dev;
1094
1095 dev_set_drvdata(dev, rproc);
1096 priv->workqueue = create_workqueue(dev_name(dev));
1097 if (!priv->workqueue) {
1098 dev_err(dev, "cannot create workqueue\n");
1099 return -ENOMEM;
1100 }
1101
1102 INIT_WORK(&priv->rproc_work, imx_rproc_vq_work);
1103
1104 ret = imx_rproc_xtr_mbox_init(rproc, true);
1105 if (ret)
1106 goto err_put_wkq;
1107
1108 ret = imx_rproc_addr_init(priv, pdev);
1109 if (ret) {
1110 dev_err(dev, "failed on imx_rproc_addr_init\n");
1111 goto err_put_mbox;
1112 }
1113
1114 ret = imx_rproc_detect_mode(priv);
1115 if (ret)
1116 goto err_put_mbox;
1117
1118 ret = imx_rproc_clk_enable(priv);
1119 if (ret)
1120 goto err_put_scu;
1121
1122 if (rproc->state != RPROC_DETACHED)
1123 rproc->auto_boot = of_property_read_bool(np, "fsl,auto-boot");
1124
1125 if (dcfg->flags & IMX_RPROC_NEED_SYSTEM_OFF) {
1126 /*
1127 * setup mailbox to non-blocking mode in
1128 * [SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_MODE_RESTART_PREPARE]
1129 * phase before invoking [SYS_OFF_MODE_POWER_OFF, SYS_OFF_MODE_RESTART]
1130 * atomic chain, see kernel/reboot.c.
1131 */
1132 ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_POWER_OFF_PREPARE,
1133 SYS_OFF_PRIO_DEFAULT,
1134 imx_rproc_sys_off_handler, rproc);
1135 if (ret) {
1136 dev_err(dev, "register power off handler failure\n");
1137 goto err_put_clk;
1138 }
1139
1140 ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART_PREPARE,
1141 SYS_OFF_PRIO_DEFAULT,
1142 imx_rproc_sys_off_handler, rproc);
1143 if (ret) {
1144 dev_err(dev, "register restart handler failure\n");
1145 goto err_put_clk;
1146 }
1147 }
1148
1149 ret = rproc_add(rproc);
1150 if (ret) {
1151 dev_err(dev, "rproc_add failed\n");
1152 goto err_put_clk;
1153 }
1154
1155 return 0;
1156
1157err_put_clk:
1158 clk_disable_unprepare(priv->clk);
1159err_put_scu:
1160 imx_rproc_put_scu(rproc);
1161err_put_mbox:
1162 imx_rproc_free_mbox(rproc);
1163err_put_wkq:
1164 destroy_workqueue(priv->workqueue);
1165
1166 return ret;
1167}
1168
1169static void imx_rproc_remove(struct platform_device *pdev)
1170{
1171 struct rproc *rproc = platform_get_drvdata(pdev);
1172 struct imx_rproc *priv = rproc->priv;
1173
1174 clk_disable_unprepare(priv->clk);
1175 rproc_del(rproc);
1176 imx_rproc_put_scu(rproc);
1177 imx_rproc_free_mbox(rproc);
1178 destroy_workqueue(priv->workqueue);
1179}
1180
1181static const struct of_device_id imx_rproc_of_match[] = {
1182 { .compatible = "fsl,imx7ulp-cm4", .data = &imx_rproc_cfg_imx7ulp },
1183 { .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
1184 { .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
1185 { .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq },
1186 { .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq },
1187 { .compatible = "fsl,imx8mn-cm7", .data = &imx_rproc_cfg_imx8mn },
1188 { .compatible = "fsl,imx8mp-cm7", .data = &imx_rproc_cfg_imx8mn },
1189 { .compatible = "fsl,imx8mn-cm7-mmio", .data = &imx_rproc_cfg_imx8mn_mmio },
1190 { .compatible = "fsl,imx8mp-cm7-mmio", .data = &imx_rproc_cfg_imx8mn_mmio },
1191 { .compatible = "fsl,imx8qxp-cm4", .data = &imx_rproc_cfg_imx8qxp },
1192 { .compatible = "fsl,imx8qm-cm4", .data = &imx_rproc_cfg_imx8qm },
1193 { .compatible = "fsl,imx8ulp-cm33", .data = &imx_rproc_cfg_imx8ulp },
1194 { .compatible = "fsl,imx93-cm33", .data = &imx_rproc_cfg_imx93 },
1195 {},
1196};
1197MODULE_DEVICE_TABLE(of, imx_rproc_of_match);
1198
1199static struct platform_driver imx_rproc_driver = {
1200 .probe = imx_rproc_probe,
1201 .remove = imx_rproc_remove,
1202 .driver = {
1203 .name = "imx-rproc",
1204 .of_match_table = imx_rproc_of_match,
1205 },
1206};
1207
1208module_platform_driver(imx_rproc_driver);
1209
1210MODULE_LICENSE("GPL v2");
1211MODULE_DESCRIPTION("i.MX remote processor control driver");
1212MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");