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1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2009 - 2019 Broadcom */
3
4#include <linux/bitfield.h>
5#include <linux/bitops.h>
6#include <linux/clk.h>
7#include <linux/compiler.h>
8#include <linux/delay.h>
9#include <linux/init.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/ioport.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/log2.h>
19#include <linux/module.h>
20#include <linux/msi.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/of_pci.h>
24#include <linux/of_platform.h>
25#include <linux/pci.h>
26#include <linux/pci-ecam.h>
27#include <linux/printk.h>
28#include <linux/regulator/consumer.h>
29#include <linux/reset.h>
30#include <linux/sizes.h>
31#include <linux/slab.h>
32#include <linux/string.h>
33#include <linux/types.h>
34
35#include "../pci.h"
36
37/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
38#define BRCM_PCIE_CAP_REGS 0x00ac
39
40/* Broadcom STB PCIe Register Offsets */
41#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
44
45#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
46#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
47
48#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
49#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
50
51#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
52#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
53
54#define PCIE_RC_DL_MDIO_ADDR 0x1100
55#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
56#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
57
58#define PCIE_MISC_MISC_CTRL 0x4008
59#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
60#define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
61#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
62#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
63#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
64
65#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
66#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
67#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
68#define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
69
70#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
71#define PCIE_MEM_WIN0_LO(win) \
72 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
73
74#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
75#define PCIE_MEM_WIN0_HI(win) \
76 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
77
78/*
79 * NOTE: You may see the term "BAR" in a number of register names used by
80 * this driver. The term is an artifact of when the HW core was an
81 * endpoint device (EP). Now it is a root complex (RC) and anywhere a
82 * register has the term "BAR" it is related to an inbound window.
83 */
84
85#define PCIE_BRCM_MAX_INBOUND_WINS 16
86#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
87#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
88
89#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
90
91
92#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
93#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
94
95#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
96#define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
97#define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
98
99#define PCIE_MISC_PCIE_CTRL 0x4064
100#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
101#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
102
103#define PCIE_MISC_PCIE_STATUS 0x4068
104#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
105#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
106#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
107#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
108
109#define PCIE_MISC_REVISION 0x406c
110#define BRCM_PCIE_HW_REV_33 0x0303
111#define BRCM_PCIE_HW_REV_3_20 0x0320
112
113#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
114#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
115#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
116#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
117 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
118
119#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
120#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
121#define PCIE_MEM_WIN0_BASE_HI(win) \
122 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
123
124#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
125#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
126#define PCIE_MEM_WIN0_LIMIT_HI(win) \
127 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
128
129#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
130#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
131#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
132#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
133#define PCIE_CLKREQ_MASK \
134 (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
135 PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
136
137#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
138#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0)
139#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c
140
141#define PCIE_MSI_INTR2_BASE 0x4500
142
143/* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */
144#define MSI_INT_STATUS 0x0
145#define MSI_INT_CLR 0x8
146#define MSI_INT_MASK_SET 0x10
147#define MSI_INT_MASK_CLR 0x14
148
149#define PCIE_EXT_CFG_DATA 0x8000
150#define PCIE_EXT_CFG_INDEX 0x9000
151
152#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
153#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
154
155#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
156#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
157#define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
158#define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
159
160/* PCIe parameters */
161#define BRCM_NUM_PCIE_OUT_WINS 0x4
162#define BRCM_INT_PCI_MSI_NR 32
163#define BRCM_INT_PCI_MSI_LEGACY_NR 8
164#define BRCM_INT_PCI_MSI_SHIFT 0
165#define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
166#define BRCM_INT_PCI_MSI_LEGACY_MASK GENMASK(31, \
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
168
169/* MSI target addresses */
170#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
171#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
172
173/* MDIO registers */
174#define MDIO_PORT0 0x0
175#define MDIO_DATA_MASK 0x7fffffff
176#define MDIO_PORT_MASK 0xf0000
177#define MDIO_REGAD_MASK 0xffff
178#define MDIO_CMD_MASK 0xfff00000
179#define MDIO_CMD_READ 0x1
180#define MDIO_CMD_WRITE 0x0
181#define MDIO_DATA_DONE_MASK 0x80000000
182#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
184#define SSC_REGS_ADDR 0x1100
185#define SET_ADDR_OFFSET 0x1f
186#define SSC_CNTL_OFFSET 0x2
187#define SSC_CNTL_OVRD_EN_MASK 0x8000
188#define SSC_CNTL_OVRD_VAL_MASK 0x4000
189#define SSC_STATUS_OFFSET 0x1
190#define SSC_STATUS_SSC_MASK 0x400
191#define SSC_STATUS_PLL_LOCK_MASK 0x800
192#define PCIE_BRCM_MAX_MEMC 3
193
194#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
195#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
196#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
197#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
198#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE])
199
200/* Rescal registers */
201#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
202#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
203#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
204#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
205#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
206#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
207#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
208#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
209
210/* Forward declarations */
211struct brcm_pcie;
212
213enum {
214 RGR1_SW_INIT_1,
215 EXT_CFG_INDEX,
216 EXT_CFG_DATA,
217 PCIE_HARD_DEBUG,
218 PCIE_INTR2_CPU_BASE,
219};
220
221enum pcie_soc_base {
222 GENERIC,
223 BCM2711,
224 BCM4908,
225 BCM7278,
226 BCM7425,
227 BCM7435,
228 BCM7712,
229};
230
231struct inbound_win {
232 u64 size;
233 u64 pci_offset;
234 u64 cpu_addr;
235};
236
237struct pcie_cfg_data {
238 const int *offsets;
239 const enum pcie_soc_base soc_base;
240 const bool has_phy;
241 u8 num_inbound_wins;
242 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
243 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
244};
245
246struct subdev_regulators {
247 unsigned int num_supplies;
248 struct regulator_bulk_data supplies[];
249};
250
251struct brcm_msi {
252 struct device *dev;
253 void __iomem *base;
254 struct device_node *np;
255 struct irq_domain *msi_domain;
256 struct irq_domain *inner_domain;
257 struct mutex lock; /* guards the alloc/free operations */
258 u64 target_addr;
259 int irq;
260 DECLARE_BITMAP(used, BRCM_INT_PCI_MSI_NR);
261 bool legacy;
262 /* Some chips have MSIs in bits [31..24] of a shared register. */
263 int legacy_shift;
264 int nr; /* No. of MSI available, depends on chip */
265 /* This is the base pointer for interrupt status/set/clr regs */
266 void __iomem *intr_base;
267};
268
269/* Internal PCIe Host Controller Information.*/
270struct brcm_pcie {
271 struct device *dev;
272 void __iomem *base;
273 struct clk *clk;
274 struct device_node *np;
275 bool ssc;
276 int gen;
277 u64 msi_target_addr;
278 struct brcm_msi *msi;
279 const int *reg_offsets;
280 enum pcie_soc_base soc_base;
281 struct reset_control *rescal;
282 struct reset_control *perst_reset;
283 struct reset_control *bridge_reset;
284 struct reset_control *swinit_reset;
285 int num_memc;
286 u64 memc_size[PCIE_BRCM_MAX_MEMC];
287 u32 hw_rev;
288 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
289 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
290 struct subdev_regulators *sr;
291 bool ep_wakeup_capable;
292 bool has_phy;
293 u8 num_inbound_wins;
294};
295
296static inline bool is_bmips(const struct brcm_pcie *pcie)
297{
298 return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425;
299}
300
301/*
302 * This is to convert the size of the inbound "BAR" region to the
303 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
304 */
305static int brcm_pcie_encode_ibar_size(u64 size)
306{
307 int log2_in = ilog2(size);
308
309 if (log2_in >= 12 && log2_in <= 15)
310 /* Covers 4KB to 32KB (inclusive) */
311 return (log2_in - 12) + 0x1c;
312 else if (log2_in >= 16 && log2_in <= 35)
313 /* Covers 64KB to 32GB, (inclusive) */
314 return log2_in - 15;
315 /* Something is awry so disable */
316 return 0;
317}
318
319static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
320{
321 u32 pkt = 0;
322
323 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
324 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
325 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
326
327 return pkt;
328}
329
330/* negative return value indicates error */
331static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
332{
333 u32 data;
334 int err;
335
336 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
337 base + PCIE_RC_DL_MDIO_ADDR);
338 readl(base + PCIE_RC_DL_MDIO_ADDR);
339 err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_RD_DATA, data,
340 MDIO_RD_DONE(data), 10, 100);
341 *val = FIELD_GET(MDIO_DATA_MASK, data);
342
343 return err;
344}
345
346/* negative return value indicates error */
347static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
348 u8 regad, u16 wrdata)
349{
350 u32 data;
351 int err;
352
353 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
354 base + PCIE_RC_DL_MDIO_ADDR);
355 readl(base + PCIE_RC_DL_MDIO_ADDR);
356 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
357
358 err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data,
359 MDIO_WT_DONE(data), 10, 100);
360 return err;
361}
362
363/*
364 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
365 * return value indicates error.
366 */
367static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
368{
369 int pll, ssc;
370 int ret;
371 u32 tmp;
372
373 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
374 SSC_REGS_ADDR);
375 if (ret < 0)
376 return ret;
377
378 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
379 SSC_CNTL_OFFSET, &tmp);
380 if (ret < 0)
381 return ret;
382
383 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
384 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
385 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
386 SSC_CNTL_OFFSET, tmp);
387 if (ret < 0)
388 return ret;
389
390 usleep_range(1000, 2000);
391 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
392 SSC_STATUS_OFFSET, &tmp);
393 if (ret < 0)
394 return ret;
395
396 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
397 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
398
399 return ssc && pll ? 0 : -EIO;
400}
401
402/* Limits operation to a specific generation (1, 2, or 3) */
403static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
404{
405 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
406 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
407
408 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
409 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
410
411 lnkctl2 = (lnkctl2 & ~0xf) | gen;
412 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
413}
414
415static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
416 u8 win, u64 cpu_addr,
417 u64 pcie_addr, u64 size)
418{
419 u32 cpu_addr_mb_high, limit_addr_mb_high;
420 phys_addr_t cpu_addr_mb, limit_addr_mb;
421 int high_addr_shift;
422 u32 tmp;
423
424 /* Set the base of the pcie_addr window */
425 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
426 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
427
428 /* Write the addr base & limit lower bits (in MBs) */
429 cpu_addr_mb = cpu_addr / SZ_1M;
430 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
431
432 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
433 u32p_replace_bits(&tmp, cpu_addr_mb,
434 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
435 u32p_replace_bits(&tmp, limit_addr_mb,
436 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
438
439 if (is_bmips(pcie))
440 return;
441
442 /* Write the cpu & limit addr upper bits */
443 high_addr_shift =
444 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
445
446 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
447 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
448 u32p_replace_bits(&tmp, cpu_addr_mb_high,
449 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
450 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
451
452 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
453 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
454 u32p_replace_bits(&tmp, limit_addr_mb_high,
455 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
456 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
457}
458
459static struct irq_chip brcm_msi_irq_chip = {
460 .name = "BRCM STB PCIe MSI",
461 .irq_ack = irq_chip_ack_parent,
462 .irq_mask = pci_msi_mask_irq,
463 .irq_unmask = pci_msi_unmask_irq,
464};
465
466static struct msi_domain_info brcm_msi_domain_info = {
467 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
468 MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
469 .chip = &brcm_msi_irq_chip,
470};
471
472static void brcm_pcie_msi_isr(struct irq_desc *desc)
473{
474 struct irq_chip *chip = irq_desc_get_chip(desc);
475 unsigned long status;
476 struct brcm_msi *msi;
477 struct device *dev;
478 u32 bit;
479
480 chained_irq_enter(chip, desc);
481 msi = irq_desc_get_handler_data(desc);
482 dev = msi->dev;
483
484 status = readl(msi->intr_base + MSI_INT_STATUS);
485 status >>= msi->legacy_shift;
486
487 for_each_set_bit(bit, &status, msi->nr) {
488 int ret;
489 ret = generic_handle_domain_irq(msi->inner_domain, bit);
490 if (ret)
491 dev_dbg(dev, "unexpected MSI\n");
492 }
493
494 chained_irq_exit(chip, desc);
495}
496
497static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
498{
499 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
500
501 msg->address_lo = lower_32_bits(msi->target_addr);
502 msg->address_hi = upper_32_bits(msi->target_addr);
503 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
504}
505
506static void brcm_msi_ack_irq(struct irq_data *data)
507{
508 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
509 const int shift_amt = data->hwirq + msi->legacy_shift;
510
511 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
512}
513
514
515static struct irq_chip brcm_msi_bottom_irq_chip = {
516 .name = "BRCM STB MSI",
517 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
518 .irq_ack = brcm_msi_ack_irq,
519};
520
521static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs)
522{
523 int hwirq;
524
525 mutex_lock(&msi->lock);
526 hwirq = bitmap_find_free_region(msi->used, msi->nr,
527 order_base_2(nr_irqs));
528 mutex_unlock(&msi->lock);
529
530 return hwirq;
531}
532
533static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq,
534 unsigned int nr_irqs)
535{
536 mutex_lock(&msi->lock);
537 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs));
538 mutex_unlock(&msi->lock);
539}
540
541static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
542 unsigned int nr_irqs, void *args)
543{
544 struct brcm_msi *msi = domain->host_data;
545 int hwirq, i;
546
547 hwirq = brcm_msi_alloc(msi, nr_irqs);
548
549 if (hwirq < 0)
550 return hwirq;
551
552 for (i = 0; i < nr_irqs; i++)
553 irq_domain_set_info(domain, virq + i, hwirq + i,
554 &brcm_msi_bottom_irq_chip, domain->host_data,
555 handle_edge_irq, NULL, NULL);
556 return 0;
557}
558
559static void brcm_irq_domain_free(struct irq_domain *domain,
560 unsigned int virq, unsigned int nr_irqs)
561{
562 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
563 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
564
565 brcm_msi_free(msi, d->hwirq, nr_irqs);
566}
567
568static const struct irq_domain_ops msi_domain_ops = {
569 .alloc = brcm_irq_domain_alloc,
570 .free = brcm_irq_domain_free,
571};
572
573static int brcm_allocate_domains(struct brcm_msi *msi)
574{
575 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
576 struct device *dev = msi->dev;
577
578 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
579 if (!msi->inner_domain) {
580 dev_err(dev, "failed to create IRQ domain\n");
581 return -ENOMEM;
582 }
583
584 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
585 &brcm_msi_domain_info,
586 msi->inner_domain);
587 if (!msi->msi_domain) {
588 dev_err(dev, "failed to create MSI domain\n");
589 irq_domain_remove(msi->inner_domain);
590 return -ENOMEM;
591 }
592
593 return 0;
594}
595
596static void brcm_free_domains(struct brcm_msi *msi)
597{
598 irq_domain_remove(msi->msi_domain);
599 irq_domain_remove(msi->inner_domain);
600}
601
602static void brcm_msi_remove(struct brcm_pcie *pcie)
603{
604 struct brcm_msi *msi = pcie->msi;
605
606 if (!msi)
607 return;
608 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
609 brcm_free_domains(msi);
610}
611
612static void brcm_msi_set_regs(struct brcm_msi *msi)
613{
614 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK :
615 BRCM_INT_PCI_MSI_MASK;
616
617 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
618 writel(val, msi->intr_base + MSI_INT_CLR);
619
620 /*
621 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
622 * enable, which we set to 1.
623 */
624 writel(lower_32_bits(msi->target_addr) | 0x1,
625 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
626 writel(upper_32_bits(msi->target_addr),
627 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
628
629 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
630 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
631}
632
633static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
634{
635 struct brcm_msi *msi;
636 int irq, ret;
637 struct device *dev = pcie->dev;
638
639 irq = irq_of_parse_and_map(dev->of_node, 1);
640 if (irq <= 0) {
641 dev_err(dev, "cannot map MSI interrupt\n");
642 return -ENODEV;
643 }
644
645 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
646 if (!msi)
647 return -ENOMEM;
648
649 mutex_init(&msi->lock);
650 msi->dev = dev;
651 msi->base = pcie->base;
652 msi->np = pcie->np;
653 msi->target_addr = pcie->msi_target_addr;
654 msi->irq = irq;
655 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
656
657 /*
658 * Sanity check to make sure that the 'used' bitmap in struct brcm_msi
659 * is large enough.
660 */
661 BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR);
662
663 if (msi->legacy) {
664 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie);
665 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
666 msi->legacy_shift = 24;
667 } else {
668 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
669 msi->nr = BRCM_INT_PCI_MSI_NR;
670 msi->legacy_shift = 0;
671 }
672
673 ret = brcm_allocate_domains(msi);
674 if (ret)
675 return ret;
676
677 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
678
679 brcm_msi_set_regs(msi);
680 pcie->msi = msi;
681
682 return 0;
683}
684
685/* The controller is capable of serving in both RC and EP roles */
686static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
687{
688 void __iomem *base = pcie->base;
689 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
690
691 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
692}
693
694static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
695{
696 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
697 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
698 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
699
700 return dla && plu;
701}
702
703static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
704 unsigned int devfn, int where)
705{
706 struct brcm_pcie *pcie = bus->sysdata;
707 void __iomem *base = pcie->base;
708 int idx;
709
710 /* Accesses to the RC go right to the RC registers if !devfn */
711 if (pci_is_root_bus(bus))
712 return devfn ? NULL : base + PCIE_ECAM_REG(where);
713
714 /* An access to our HW w/o link-up will cause a CPU Abort */
715 if (!brcm_pcie_link_up(pcie))
716 return NULL;
717
718 /* For devices, write to the config space index register */
719 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
721 return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
722}
723
724static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
725 unsigned int devfn, int where)
726{
727 struct brcm_pcie *pcie = bus->sysdata;
728 void __iomem *base = pcie->base;
729 int idx;
730
731 /* Accesses to the RC go right to the RC registers if !devfn */
732 if (pci_is_root_bus(bus))
733 return devfn ? NULL : base + PCIE_ECAM_REG(where);
734
735 /* An access to our HW w/o link-up will cause a CPU Abort */
736 if (!brcm_pcie_link_up(pcie))
737 return NULL;
738
739 /* For devices, write to the config space index register */
740 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where);
741 writel(idx, base + IDX_ADDR(pcie));
742 return base + DATA_ADDR(pcie);
743}
744
745static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
746{
747 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
748 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
749 int ret = 0;
750
751 if (pcie->bridge_reset) {
752 if (val)
753 ret = reset_control_assert(pcie->bridge_reset);
754 else
755 ret = reset_control_deassert(pcie->bridge_reset);
756
757 if (ret)
758 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n",
759 val ? "assert" : "deassert", ret);
760
761 return ret;
762 }
763
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
765 tmp = (tmp & ~mask) | ((val << shift) & mask);
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
767
768 return ret;
769}
770
771static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
772{
773 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
774 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
775
776 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
777 tmp = (tmp & ~mask) | ((val << shift) & mask);
778 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
779
780 return 0;
781}
782
783static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
784{
785 int ret;
786
787 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
788 return -EINVAL;
789
790 if (val)
791 ret = reset_control_assert(pcie->perst_reset);
792 else
793 ret = reset_control_deassert(pcie->perst_reset);
794
795 if (ret)
796 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n",
797 val ? "assert" : "deassert", ret);
798 return ret;
799}
800
801static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
802{
803 u32 tmp;
804
805 /* Perst bit has moved and assert value is 0 */
806 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
807 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
808 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
809
810 return 0;
811}
812
813static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
814{
815 u32 tmp;
816
817 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
818 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
819 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
820
821 return 0;
822}
823
824static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size,
825 u64 cpu_addr, u64 pci_offset)
826{
827 b->size = size;
828 b->cpu_addr = cpu_addr;
829 b->pci_offset = pci_offset;
830 (*count)++;
831}
832
833static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
834 struct inbound_win inbound_wins[])
835{
836 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
837 u64 pci_offset, cpu_addr, size = 0, tot_size = 0;
838 struct resource_entry *entry;
839 struct device *dev = pcie->dev;
840 u64 lowest_pcie_addr = ~(u64)0;
841 int ret, i = 0;
842 u8 n = 0;
843
844 /*
845 * The HW registers (and PCIe) use order-1 numbering for BARs. As such,
846 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1].
847 */
848 struct inbound_win *b_begin = &inbound_wins[1];
849 struct inbound_win *b = b_begin;
850
851 /*
852 * STB chips beside 7712 disable the first inbound window default.
853 * Rather being mapped to system memory it is mapped to the
854 * internal registers of the SoC. This feature is deprecated, has
855 * security considerations, and is not implemented in our modern
856 * SoCs.
857 */
858 if (pcie->soc_base != BCM7712)
859 add_inbound_win(b++, &n, 0, 0, 0);
860
861 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
862 u64 pcie_start = entry->res->start - entry->offset;
863 u64 cpu_start = entry->res->start;
864
865 size = resource_size(entry->res);
866 tot_size += size;
867 if (pcie_start < lowest_pcie_addr)
868 lowest_pcie_addr = pcie_start;
869 /*
870 * 7712 and newer chips may have many BARs, with each
871 * offering a non-overlapping viewport to system memory.
872 * That being said, each BARs size must still be a power of
873 * two.
874 */
875 if (pcie->soc_base == BCM7712)
876 add_inbound_win(b++, &n, size, cpu_start, pcie_start);
877
878 if (n > pcie->num_inbound_wins)
879 break;
880 }
881
882 if (lowest_pcie_addr == ~(u64)0) {
883 dev_err(dev, "DT node has no dma-ranges\n");
884 return -EINVAL;
885 }
886
887 /*
888 * 7712 and newer chips do not have an internal memory mapping system
889 * that enables multiple memory controllers. As such, it can return
890 * now w/o doing special configuration.
891 */
892 if (pcie->soc_base == BCM7712)
893 return n;
894
895 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
896 PCIE_BRCM_MAX_MEMC);
897 if (ret <= 0) {
898 /* Make an educated guess */
899 pcie->num_memc = 1;
900 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1);
901 } else {
902 pcie->num_memc = ret;
903 }
904
905 /* Each memc is viewed through a "port" that is a power of 2 */
906 for (i = 0, size = 0; i < pcie->num_memc; i++)
907 size += pcie->memc_size[i];
908
909 /* Our HW mandates that the window size must be a power of 2 */
910 size = 1ULL << fls64(size - 1);
911
912 /*
913 * For STB chips, the BAR2 cpu_addr is hardwired to the start
914 * of system memory, so we set it to 0.
915 */
916 cpu_addr = 0;
917 pci_offset = lowest_pcie_addr;
918
919 /*
920 * We validate the inbound memory view even though we should trust
921 * whatever the device-tree provides. This is because of an HW issue on
922 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
923 * firmware has to dynamically edit dma-ranges due to a bug on the
924 * PCIe controller integration, which prohibits any access above the
925 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
926 * in check, avoiding hard to debug device-tree related issues in the
927 * future:
928 *
929 * The PCIe host controller by design must set the inbound viewport to
930 * be a contiguous arrangement of all of the system's memory. In
931 * addition, its size mut be a power of two. To further complicate
932 * matters, the viewport must start on a pcie-address that is aligned
933 * on a multiple of its size. If a portion of the viewport does not
934 * represent system memory -- e.g. 3GB of memory requires a 4GB
935 * viewport -- we can map the outbound memory in or after 3GB and even
936 * though the viewport will overlap the outbound memory the controller
937 * will know to send outbound memory downstream and everything else
938 * upstream.
939 *
940 * For example:
941 *
942 * - The best-case scenario, memory up to 3GB, is to place the inbound
943 * region in the first 4GB of pcie-space, as some legacy devices can
944 * only address 32bits. We would also like to put the MSI under 4GB
945 * as well, since some devices require a 32bit MSI target address.
946 *
947 * - If the system memory is 4GB or larger we cannot start the inbound
948 * region at location 0 (since we have to allow some space for
949 * outbound memory @ 3GB). So instead it will start at the 1x
950 * multiple of its size
951 */
952 if (!size || (pci_offset & (size - 1)) ||
953 (pci_offset < SZ_4G && pci_offset > SZ_2G)) {
954 dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\n",
955 size, pci_offset);
956 return -EINVAL;
957 }
958
959 /* Enable inbound window 2, the main inbound window for STB chips */
960 add_inbound_win(b++, &n, size, cpu_addr, pci_offset);
961
962 /*
963 * Disable inbound window 3. On some chips presents the same
964 * window as #2 but the data appears in a settable endianness.
965 */
966 add_inbound_win(b++, &n, 0, 0, 0);
967
968 return n;
969}
970
971static u32 brcm_bar_reg_offset(int bar)
972{
973 if (bar <= 3)
974 return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1);
975 else
976 return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4);
977}
978
979static u32 brcm_ubus_reg_offset(int bar)
980{
981 if (bar <= 3)
982 return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1);
983 else
984 return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4);
985}
986
987static void set_inbound_win_registers(struct brcm_pcie *pcie,
988 const struct inbound_win *inbound_wins,
989 u8 num_inbound_wins)
990{
991 void __iomem *base = pcie->base;
992 int i;
993
994 for (i = 1; i <= num_inbound_wins; i++) {
995 u64 pci_offset = inbound_wins[i].pci_offset;
996 u64 cpu_addr = inbound_wins[i].cpu_addr;
997 u64 size = inbound_wins[i].size;
998 u32 reg_offset = brcm_bar_reg_offset(i);
999 u32 tmp = lower_32_bits(pci_offset);
1000
1001 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size),
1002 PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK);
1003
1004 /* Write low */
1005 writel_relaxed(tmp, base + reg_offset);
1006 /* Write high */
1007 writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4);
1008
1009 /*
1010 * Most STB chips:
1011 * Do nothing.
1012 * 7712:
1013 * All of their BARs need to be set.
1014 */
1015 if (pcie->soc_base == BCM7712) {
1016 /* BUS remap register settings */
1017 reg_offset = brcm_ubus_reg_offset(i);
1018 tmp = lower_32_bits(cpu_addr) & ~0xfff;
1019 tmp |= PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK;
1020 writel_relaxed(tmp, base + reg_offset);
1021 tmp = upper_32_bits(cpu_addr);
1022 writel_relaxed(tmp, base + reg_offset + 4);
1023 }
1024 }
1025}
1026
1027static int brcm_pcie_setup(struct brcm_pcie *pcie)
1028{
1029 struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS];
1030 void __iomem *base = pcie->base;
1031 struct pci_host_bridge *bridge;
1032 struct resource_entry *entry;
1033 u32 tmp, burst, aspm_support;
1034 u8 num_out_wins = 0;
1035 int num_inbound_wins = 0;
1036 int memc, ret;
1037
1038 /* Reset the bridge */
1039 ret = pcie->bridge_sw_init_set(pcie, 1);
1040 if (ret)
1041 return ret;
1042
1043 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */
1044 if (pcie->soc_base == BCM2711) {
1045 ret = pcie->perst_set(pcie, 1);
1046 if (ret) {
1047 pcie->bridge_sw_init_set(pcie, 0);
1048 return ret;
1049 }
1050 }
1051
1052 usleep_range(100, 200);
1053
1054 /* Take the bridge out of reset */
1055 ret = pcie->bridge_sw_init_set(pcie, 0);
1056 if (ret)
1057 return ret;
1058
1059 tmp = readl(base + HARD_DEBUG(pcie));
1060 if (is_bmips(pcie))
1061 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
1062 else
1063 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
1064 writel(tmp, base + HARD_DEBUG(pcie));
1065 /* Wait for SerDes to be stable */
1066 usleep_range(100, 200);
1067
1068 /*
1069 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
1070 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
1071 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
1072 */
1073 if (is_bmips(pcie))
1074 burst = 0x1; /* 256 bytes */
1075 else if (pcie->soc_base == BCM2711)
1076 burst = 0x0; /* 128 bytes */
1077 else if (pcie->soc_base == BCM7278)
1078 burst = 0x3; /* 512 bytes */
1079 else
1080 burst = 0x2; /* 512 bytes */
1081
1082 /*
1083 * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN,
1084 * RCB_MPS_MODE, RCB_64B_MODE
1085 */
1086 tmp = readl(base + PCIE_MISC_MISC_CTRL);
1087 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
1088 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
1089 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
1090 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK);
1091 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK);
1092 writel(tmp, base + PCIE_MISC_MISC_CTRL);
1093
1094 num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins);
1095 if (num_inbound_wins < 0)
1096 return num_inbound_wins;
1097
1098 set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins);
1099
1100 if (!brcm_pcie_rc_mode(pcie)) {
1101 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
1102 return -EINVAL;
1103 }
1104
1105 tmp = readl(base + PCIE_MISC_MISC_CTRL);
1106 for (memc = 0; memc < pcie->num_memc; memc++) {
1107 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
1108
1109 if (memc == 0)
1110 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
1111 else if (memc == 1)
1112 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
1113 else if (memc == 2)
1114 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
1115 }
1116 writel(tmp, base + PCIE_MISC_MISC_CTRL);
1117
1118 /*
1119 * We ideally want the MSI target address to be located in the 32bit
1120 * addressable memory area. Some devices might depend on it. This is
1121 * possible either when the inbound window is located above the lower
1122 * 4GB or when the inbound area is smaller than 4GB (taking into
1123 * account the rounding-up we're forced to perform).
1124 */
1125 if (inbound_wins[2].pci_offset >= SZ_4G ||
1126 (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G)
1127 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
1128 else
1129 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
1130
1131
1132 /* Don't advertise L0s capability if 'aspm-no-l0s' */
1133 aspm_support = PCIE_LINK_STATE_L1;
1134 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1135 aspm_support |= PCIE_LINK_STATE_L0S;
1136 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1137 u32p_replace_bits(&tmp, aspm_support,
1138 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1139 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1140
1141 /*
1142 * For config space accesses on the RC, show the right class for
1143 * a PCIe-PCIe bridge (the default setting is to be EP mode).
1144 */
1145 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1146 u32p_replace_bits(&tmp, 0x060400,
1147 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
1148 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1149
1150 bridge = pci_host_bridge_from_priv(pcie);
1151 resource_list_for_each_entry(entry, &bridge->windows) {
1152 struct resource *res = entry->res;
1153
1154 if (resource_type(res) != IORESOURCE_MEM)
1155 continue;
1156
1157 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
1158 dev_err(pcie->dev, "too many outbound wins\n");
1159 return -EINVAL;
1160 }
1161
1162 if (is_bmips(pcie)) {
1163 u64 start = res->start;
1164 unsigned int j, nwins = resource_size(res) / SZ_128M;
1165
1166 /* bmips PCIe outbound windows have a 128MB max size */
1167 if (nwins > BRCM_NUM_PCIE_OUT_WINS)
1168 nwins = BRCM_NUM_PCIE_OUT_WINS;
1169 for (j = 0; j < nwins; j++, start += SZ_128M)
1170 brcm_pcie_set_outbound_win(pcie, j, start,
1171 start - entry->offset,
1172 SZ_128M);
1173 break;
1174 }
1175 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1176 res->start - entry->offset,
1177 resource_size(res));
1178 num_out_wins++;
1179 }
1180
1181 /* PCIe->SCB endian mode for inbound window */
1182 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1183 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1184 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1185 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1186
1187 return 0;
1188}
1189
1190/*
1191 * This extends the timeout period for an access to an internal bus. This
1192 * access timeout may occur during L1SS sleep periods, even without the
1193 * presence of a PCIe access.
1194 */
1195static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
1196{
1197 /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
1198 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
1199 u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
1200
1201 /* 7712 does not have this (RGR1) timer */
1202 if (pcie->soc_base == BCM7712)
1203 return;
1204
1205 /* Each unit in timeout register is 1/216,000,000 seconds */
1206 writel(216 * timeout_us, pcie->base + REG_OFFSET);
1207}
1208
1209static void brcm_config_clkreq(struct brcm_pcie *pcie)
1210{
1211 static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n";
1212 const char *mode = "default";
1213 u32 clkreq_cntl;
1214 int ret, tmp;
1215
1216 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode);
1217 if (ret && ret != -EINVAL) {
1218 dev_err(pcie->dev, err_msg);
1219 mode = "safe";
1220 }
1221
1222 /* Start out assuming safe mode (both mode bits cleared) */
1223 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie));
1224 clkreq_cntl &= ~PCIE_CLKREQ_MASK;
1225
1226 if (strcmp(mode, "no-l1ss") == 0) {
1227 /*
1228 * "no-l1ss" -- Provides Clock Power Management, L0s, and
1229 * L1, but cannot provide L1 substate (L1SS) power
1230 * savings. If the downstream device connected to the RC is
1231 * L1SS capable AND the OS enables L1SS, all PCIe traffic
1232 * may abruptly halt, potentially hanging the system.
1233 */
1234 clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1235 /*
1236 * We want to un-advertise L1 substates because if the OS
1237 * tries to configure the controller into using L1 substate
1238 * power savings it may fail or hang when the RC HW is in
1239 * "no-l1ss" mode.
1240 */
1241 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1242 u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK);
1243 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1244
1245 } else if (strcmp(mode, "default") == 0) {
1246 /*
1247 * "default" -- Provides L0s, L1, and L1SS, but not
1248 * compliant to provide Clock Power Management;
1249 * specifically, may not be able to meet the Tclron max
1250 * timing of 400ns as specified in "Dynamic Clock Control",
1251 * section 3.2.5.2.2 of the PCIe spec. This situation is
1252 * atypical and should happen only with older devices.
1253 */
1254 clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
1255 brcm_extend_rbus_timeout(pcie);
1256
1257 } else {
1258 /*
1259 * "safe" -- No power savings; refclk is driven by RC
1260 * unconditionally.
1261 */
1262 if (strcmp(mode, "safe") != 0)
1263 dev_err(pcie->dev, err_msg);
1264 mode = "safe";
1265 }
1266 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie));
1267
1268 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode);
1269}
1270
1271static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1272{
1273 struct device *dev = pcie->dev;
1274 void __iomem *base = pcie->base;
1275 u16 nlw, cls, lnksta;
1276 bool ssc_good = false;
1277 int ret, i;
1278
1279 /* Unassert the fundamental reset */
1280 ret = pcie->perst_set(pcie, 0);
1281 if (ret)
1282 return ret;
1283
1284 /*
1285 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
1286 * sections 2.2, PCIe r5.0, 6.6.1.
1287 */
1288 msleep(100);
1289
1290 /*
1291 * Give the RC/EP even more time to wake up, before trying to
1292 * configure RC. Intermittently check status for link-up, up to a
1293 * total of 100ms.
1294 */
1295 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1296 msleep(5);
1297
1298 if (!brcm_pcie_link_up(pcie)) {
1299 dev_err(dev, "link down\n");
1300 return -ENODEV;
1301 }
1302
1303 brcm_config_clkreq(pcie);
1304
1305 if (pcie->gen)
1306 brcm_pcie_set_gen(pcie, pcie->gen);
1307
1308 if (pcie->ssc) {
1309 ret = brcm_pcie_set_ssc(pcie);
1310 if (ret == 0)
1311 ssc_good = true;
1312 else
1313 dev_err(dev, "failed attempt to enter ssc mode\n");
1314 }
1315
1316 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1317 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1318 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1319 dev_info(dev, "link up, %s x%u %s\n",
1320 pci_speed_string(pcie_link_speed[cls]), nlw,
1321 ssc_good ? "(SSC)" : "(!SSC)");
1322
1323 return 0;
1324}
1325
1326static const char * const supplies[] = {
1327 "vpcie3v3",
1328 "vpcie3v3aux",
1329 "vpcie12v",
1330};
1331
1332static void *alloc_subdev_regulators(struct device *dev)
1333{
1334 const size_t size = sizeof(struct subdev_regulators) +
1335 sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
1336 struct subdev_regulators *sr;
1337 int i;
1338
1339 sr = devm_kzalloc(dev, size, GFP_KERNEL);
1340 if (sr) {
1341 sr->num_supplies = ARRAY_SIZE(supplies);
1342 for (i = 0; i < ARRAY_SIZE(supplies); i++)
1343 sr->supplies[i].supply = supplies[i];
1344 }
1345
1346 return sr;
1347}
1348
1349static int brcm_pcie_add_bus(struct pci_bus *bus)
1350{
1351 struct brcm_pcie *pcie = bus->sysdata;
1352 struct device *dev = &bus->dev;
1353 struct subdev_regulators *sr;
1354 int ret;
1355
1356 if (!bus->parent || !pci_is_root_bus(bus->parent))
1357 return 0;
1358
1359 if (dev->of_node) {
1360 sr = alloc_subdev_regulators(dev);
1361 if (!sr) {
1362 dev_info(dev, "Can't allocate regulators for downstream device\n");
1363 goto no_regulators;
1364 }
1365
1366 pcie->sr = sr;
1367
1368 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
1369 if (ret) {
1370 dev_info(dev, "No regulators for downstream device\n");
1371 goto no_regulators;
1372 }
1373
1374 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
1375 if (ret) {
1376 dev_err(dev, "Can't enable regulators for downstream device\n");
1377 regulator_bulk_free(sr->num_supplies, sr->supplies);
1378 pcie->sr = NULL;
1379 }
1380 }
1381
1382no_regulators:
1383 brcm_pcie_start_link(pcie);
1384 return 0;
1385}
1386
1387static void brcm_pcie_remove_bus(struct pci_bus *bus)
1388{
1389 struct brcm_pcie *pcie = bus->sysdata;
1390 struct subdev_regulators *sr = pcie->sr;
1391 struct device *dev = &bus->dev;
1392
1393 if (!sr)
1394 return;
1395
1396 if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
1397 dev_err(dev, "Failed to disable regulators for downstream device\n");
1398 regulator_bulk_free(sr->num_supplies, sr->supplies);
1399 pcie->sr = NULL;
1400}
1401
1402/* L23 is a low-power PCIe link state */
1403static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1404{
1405 void __iomem *base = pcie->base;
1406 int l23, i;
1407 u32 tmp;
1408
1409 /* Assert request for L23 */
1410 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1411 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1412 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1413
1414 /* Wait up to 36 msec for L23 */
1415 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1416 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1417 for (i = 0; i < 15 && !l23; i++) {
1418 usleep_range(2000, 2400);
1419 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1420 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1421 tmp);
1422 }
1423
1424 if (!l23)
1425 dev_err(pcie->dev, "failed to enter low-power link state\n");
1426}
1427
1428static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1429{
1430 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1431 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1432 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1433 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1434 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1435 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1436 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1437 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1438 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1439 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1440 u32 tmp, combined_mask = 0;
1441 u32 val;
1442 void __iomem *base = pcie->base;
1443 int i, ret;
1444
1445 for (i = beg; i != end; start ? i++ : i--) {
1446 val = start ? BIT_MASK(shifts[i]) : 0;
1447 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1448 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1449 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1450 usleep_range(50, 200);
1451 combined_mask |= masks[i];
1452 }
1453
1454 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1455 val = start ? combined_mask : 0;
1456
1457 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1458 if (ret)
1459 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1460
1461 return ret;
1462}
1463
1464static inline int brcm_phy_start(struct brcm_pcie *pcie)
1465{
1466 return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0;
1467}
1468
1469static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1470{
1471 return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0;
1472}
1473
1474static int brcm_pcie_turn_off(struct brcm_pcie *pcie)
1475{
1476 void __iomem *base = pcie->base;
1477 int tmp, ret;
1478
1479 if (brcm_pcie_link_up(pcie))
1480 brcm_pcie_enter_l23(pcie);
1481 /* Assert fundamental reset */
1482 ret = pcie->perst_set(pcie, 1);
1483 if (ret)
1484 return ret;
1485
1486 /* Deassert request for L23 in case it was asserted */
1487 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1488 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1489 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1490
1491 /* Turn off SerDes */
1492 tmp = readl(base + HARD_DEBUG(pcie));
1493 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1494 writel(tmp, base + HARD_DEBUG(pcie));
1495
1496 /* Shutdown PCIe bridge */
1497 ret = pcie->bridge_sw_init_set(pcie, 1);
1498
1499 return ret;
1500}
1501
1502static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
1503{
1504 bool *ret = data;
1505
1506 if (device_may_wakeup(&dev->dev)) {
1507 *ret = true;
1508 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n");
1509 }
1510 return (int) *ret;
1511}
1512
1513static int brcm_pcie_suspend_noirq(struct device *dev)
1514{
1515 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1516 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1517 int ret, rret;
1518
1519 ret = brcm_pcie_turn_off(pcie);
1520 if (ret)
1521 return ret;
1522
1523 /*
1524 * If brcm_phy_stop() returns an error, just dev_err(). If we
1525 * return the error it will cause the suspend to fail and this is a
1526 * forgivable offense that will probably be erased on resume.
1527 */
1528 if (brcm_phy_stop(pcie))
1529 dev_err(dev, "Could not stop phy for suspend\n");
1530
1531 ret = reset_control_rearm(pcie->rescal);
1532 if (ret) {
1533 dev_err(dev, "Could not rearm rescal reset\n");
1534 return ret;
1535 }
1536
1537 if (pcie->sr) {
1538 /*
1539 * Now turn off the regulators, but if at least one
1540 * downstream device is enabled as a wake-up source, do not
1541 * turn off regulators.
1542 */
1543 pcie->ep_wakeup_capable = false;
1544 pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
1545 &pcie->ep_wakeup_capable);
1546 if (!pcie->ep_wakeup_capable) {
1547 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1548 pcie->sr->supplies);
1549 if (ret) {
1550 dev_err(dev, "Could not turn off regulators\n");
1551 rret = reset_control_reset(pcie->rescal);
1552 if (rret)
1553 dev_err(dev, "failed to reset 'rascal' controller ret=%d\n",
1554 rret);
1555 return ret;
1556 }
1557 }
1558 }
1559 clk_disable_unprepare(pcie->clk);
1560
1561 return 0;
1562}
1563
1564static int brcm_pcie_resume_noirq(struct device *dev)
1565{
1566 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1567 void __iomem *base;
1568 u32 tmp;
1569 int ret, rret;
1570
1571 base = pcie->base;
1572 ret = clk_prepare_enable(pcie->clk);
1573 if (ret)
1574 return ret;
1575
1576 ret = reset_control_reset(pcie->rescal);
1577 if (ret)
1578 goto err_disable_clk;
1579
1580 ret = brcm_phy_start(pcie);
1581 if (ret)
1582 goto err_reset;
1583
1584 /* Take bridge out of reset so we can access the SERDES reg */
1585 pcie->bridge_sw_init_set(pcie, 0);
1586
1587 /* SERDES_IDDQ = 0 */
1588 tmp = readl(base + HARD_DEBUG(pcie));
1589 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1590 writel(tmp, base + HARD_DEBUG(pcie));
1591
1592 /* wait for serdes to be stable */
1593 udelay(100);
1594
1595 ret = brcm_pcie_setup(pcie);
1596 if (ret)
1597 goto err_reset;
1598
1599 if (pcie->sr) {
1600 if (pcie->ep_wakeup_capable) {
1601 /*
1602 * We are resuming from a suspend. In the suspend we
1603 * did not disable the power supplies, so there is
1604 * no need to enable them (and falsely increase their
1605 * usage count).
1606 */
1607 pcie->ep_wakeup_capable = false;
1608 } else {
1609 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1610 pcie->sr->supplies);
1611 if (ret) {
1612 dev_err(dev, "Could not turn on regulators\n");
1613 goto err_reset;
1614 }
1615 }
1616 }
1617
1618 ret = brcm_pcie_start_link(pcie);
1619 if (ret)
1620 goto err_regulator;
1621
1622 if (pcie->msi)
1623 brcm_msi_set_regs(pcie->msi);
1624
1625 return 0;
1626
1627err_regulator:
1628 if (pcie->sr)
1629 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1630err_reset:
1631 rret = reset_control_rearm(pcie->rescal);
1632 if (rret)
1633 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret);
1634err_disable_clk:
1635 clk_disable_unprepare(pcie->clk);
1636 return ret;
1637}
1638
1639static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1640{
1641 brcm_msi_remove(pcie);
1642 brcm_pcie_turn_off(pcie);
1643 if (brcm_phy_stop(pcie))
1644 dev_err(pcie->dev, "Could not stop phy\n");
1645 if (reset_control_rearm(pcie->rescal))
1646 dev_err(pcie->dev, "Could not rearm rescal reset\n");
1647 clk_disable_unprepare(pcie->clk);
1648}
1649
1650static void brcm_pcie_remove(struct platform_device *pdev)
1651{
1652 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1653 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1654
1655 pci_stop_root_bus(bridge->bus);
1656 pci_remove_root_bus(bridge->bus);
1657 __brcm_pcie_remove(pcie);
1658}
1659
1660static const int pcie_offsets[] = {
1661 [RGR1_SW_INIT_1] = 0x9210,
1662 [EXT_CFG_INDEX] = 0x9000,
1663 [EXT_CFG_DATA] = 0x9004,
1664 [PCIE_HARD_DEBUG] = 0x4204,
1665 [PCIE_INTR2_CPU_BASE] = 0x4300,
1666};
1667
1668static const int pcie_offsets_bcm7278[] = {
1669 [RGR1_SW_INIT_1] = 0xc010,
1670 [EXT_CFG_INDEX] = 0x9000,
1671 [EXT_CFG_DATA] = 0x9004,
1672 [PCIE_HARD_DEBUG] = 0x4204,
1673 [PCIE_INTR2_CPU_BASE] = 0x4300,
1674};
1675
1676static const int pcie_offsets_bcm7425[] = {
1677 [RGR1_SW_INIT_1] = 0x8010,
1678 [EXT_CFG_INDEX] = 0x8300,
1679 [EXT_CFG_DATA] = 0x8304,
1680 [PCIE_HARD_DEBUG] = 0x4204,
1681 [PCIE_INTR2_CPU_BASE] = 0x4300,
1682};
1683
1684static const int pcie_offsets_bcm7712[] = {
1685 [EXT_CFG_INDEX] = 0x9000,
1686 [EXT_CFG_DATA] = 0x9004,
1687 [PCIE_HARD_DEBUG] = 0x4304,
1688 [PCIE_INTR2_CPU_BASE] = 0x4400,
1689};
1690
1691static const struct pcie_cfg_data generic_cfg = {
1692 .offsets = pcie_offsets,
1693 .soc_base = GENERIC,
1694 .perst_set = brcm_pcie_perst_set_generic,
1695 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1696 .num_inbound_wins = 3,
1697};
1698
1699static const struct pcie_cfg_data bcm2711_cfg = {
1700 .offsets = pcie_offsets,
1701 .soc_base = BCM2711,
1702 .perst_set = brcm_pcie_perst_set_generic,
1703 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1704 .num_inbound_wins = 3,
1705};
1706
1707static const struct pcie_cfg_data bcm4908_cfg = {
1708 .offsets = pcie_offsets,
1709 .soc_base = BCM4908,
1710 .perst_set = brcm_pcie_perst_set_4908,
1711 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1712 .num_inbound_wins = 3,
1713};
1714
1715static const struct pcie_cfg_data bcm7278_cfg = {
1716 .offsets = pcie_offsets_bcm7278,
1717 .soc_base = BCM7278,
1718 .perst_set = brcm_pcie_perst_set_7278,
1719 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
1720 .num_inbound_wins = 3,
1721};
1722
1723static const struct pcie_cfg_data bcm7425_cfg = {
1724 .offsets = pcie_offsets_bcm7425,
1725 .soc_base = BCM7425,
1726 .perst_set = brcm_pcie_perst_set_generic,
1727 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1728 .num_inbound_wins = 3,
1729};
1730
1731static const struct pcie_cfg_data bcm7435_cfg = {
1732 .offsets = pcie_offsets,
1733 .soc_base = BCM7435,
1734 .perst_set = brcm_pcie_perst_set_generic,
1735 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1736 .num_inbound_wins = 3,
1737};
1738
1739static const struct pcie_cfg_data bcm7216_cfg = {
1740 .offsets = pcie_offsets_bcm7278,
1741 .soc_base = BCM7278,
1742 .perst_set = brcm_pcie_perst_set_7278,
1743 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
1744 .has_phy = true,
1745 .num_inbound_wins = 3,
1746};
1747
1748static const struct pcie_cfg_data bcm7712_cfg = {
1749 .offsets = pcie_offsets_bcm7712,
1750 .perst_set = brcm_pcie_perst_set_7278,
1751 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1752 .soc_base = BCM7712,
1753 .num_inbound_wins = 10,
1754};
1755
1756static const struct of_device_id brcm_pcie_match[] = {
1757 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1758 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1759 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1760 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1761 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1762 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1763 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1764 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1765 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1766 {},
1767};
1768
1769static struct pci_ops brcm_pcie_ops = {
1770 .map_bus = brcm_pcie_map_bus,
1771 .read = pci_generic_config_read,
1772 .write = pci_generic_config_write,
1773 .add_bus = brcm_pcie_add_bus,
1774 .remove_bus = brcm_pcie_remove_bus,
1775};
1776
1777static struct pci_ops brcm7425_pcie_ops = {
1778 .map_bus = brcm7425_pcie_map_bus,
1779 .read = pci_generic_config_read32,
1780 .write = pci_generic_config_write32,
1781 .add_bus = brcm_pcie_add_bus,
1782 .remove_bus = brcm_pcie_remove_bus,
1783};
1784
1785static int brcm_pcie_probe(struct platform_device *pdev)
1786{
1787 struct device_node *np = pdev->dev.of_node, *msi_np;
1788 struct pci_host_bridge *bridge;
1789 const struct pcie_cfg_data *data;
1790 struct brcm_pcie *pcie;
1791 int ret;
1792
1793 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1794 if (!bridge)
1795 return -ENOMEM;
1796
1797 data = of_device_get_match_data(&pdev->dev);
1798 if (!data) {
1799 pr_err("failed to look up compatible string\n");
1800 return -EINVAL;
1801 }
1802
1803 pcie = pci_host_bridge_priv(bridge);
1804 pcie->dev = &pdev->dev;
1805 pcie->np = np;
1806 pcie->reg_offsets = data->offsets;
1807 pcie->soc_base = data->soc_base;
1808 pcie->perst_set = data->perst_set;
1809 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1810 pcie->has_phy = data->has_phy;
1811 pcie->num_inbound_wins = data->num_inbound_wins;
1812
1813 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1814 if (IS_ERR(pcie->base))
1815 return PTR_ERR(pcie->base);
1816
1817 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1818 if (IS_ERR(pcie->clk))
1819 return PTR_ERR(pcie->clk);
1820
1821 ret = of_pci_get_max_link_speed(np);
1822 pcie->gen = (ret < 0) ? 0 : ret;
1823
1824 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1825
1826 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1827 if (IS_ERR(pcie->rescal))
1828 return PTR_ERR(pcie->rescal);
1829
1830 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1831 if (IS_ERR(pcie->perst_reset))
1832 return PTR_ERR(pcie->perst_reset);
1833
1834 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge");
1835 if (IS_ERR(pcie->bridge_reset))
1836 return PTR_ERR(pcie->bridge_reset);
1837
1838 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit");
1839 if (IS_ERR(pcie->swinit_reset))
1840 return PTR_ERR(pcie->swinit_reset);
1841
1842 ret = clk_prepare_enable(pcie->clk);
1843 if (ret)
1844 return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
1845
1846 pcie->bridge_sw_init_set(pcie, 0);
1847
1848 if (pcie->swinit_reset) {
1849 ret = reset_control_assert(pcie->swinit_reset);
1850 if (ret) {
1851 clk_disable_unprepare(pcie->clk);
1852 return dev_err_probe(&pdev->dev, ret,
1853 "could not assert reset 'swinit'\n");
1854 }
1855
1856 /* HW team recommends 1us for proper sync and propagation of reset */
1857 udelay(1);
1858
1859 ret = reset_control_deassert(pcie->swinit_reset);
1860 if (ret) {
1861 clk_disable_unprepare(pcie->clk);
1862 return dev_err_probe(&pdev->dev, ret,
1863 "could not de-assert reset 'swinit'\n");
1864 }
1865 }
1866
1867 ret = reset_control_reset(pcie->rescal);
1868 if (ret) {
1869 clk_disable_unprepare(pcie->clk);
1870 return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n");
1871 }
1872
1873 ret = brcm_phy_start(pcie);
1874 if (ret) {
1875 reset_control_rearm(pcie->rescal);
1876 clk_disable_unprepare(pcie->clk);
1877 return ret;
1878 }
1879
1880 ret = brcm_pcie_setup(pcie);
1881 if (ret)
1882 goto fail;
1883
1884 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1885 if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1886 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1887 ret = -ENODEV;
1888 goto fail;
1889 }
1890
1891 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1892 if (pci_msi_enabled() && msi_np == pcie->np) {
1893 ret = brcm_pcie_enable_msi(pcie);
1894 if (ret) {
1895 dev_err(pcie->dev, "probe of internal MSI failed");
1896 goto fail;
1897 }
1898 }
1899
1900 bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1901 bridge->sysdata = pcie;
1902
1903 platform_set_drvdata(pdev, pcie);
1904
1905 ret = pci_host_probe(bridge);
1906 if (!ret && !brcm_pcie_link_up(pcie))
1907 ret = -ENODEV;
1908
1909 if (ret) {
1910 brcm_pcie_remove(pdev);
1911 return ret;
1912 }
1913
1914 return 0;
1915
1916fail:
1917 __brcm_pcie_remove(pcie);
1918
1919 return ret;
1920}
1921
1922MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1923
1924static const struct dev_pm_ops brcm_pcie_pm_ops = {
1925 .suspend_noirq = brcm_pcie_suspend_noirq,
1926 .resume_noirq = brcm_pcie_resume_noirq,
1927};
1928
1929static struct platform_driver brcm_pcie_driver = {
1930 .probe = brcm_pcie_probe,
1931 .remove = brcm_pcie_remove,
1932 .driver = {
1933 .name = "brcm-pcie",
1934 .of_match_table = brcm_pcie_match,
1935 .pm = &brcm_pcie_pm_ops,
1936 },
1937};
1938module_platform_driver(brcm_pcie_driver);
1939
1940MODULE_LICENSE("GPL");
1941MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1942MODULE_AUTHOR("Broadcom");