1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/* Copyright(c) 2018-2019  Realtek Corporation
  3 */
  4
  5#ifndef __RTW8822B_H__
  6#define __RTW8822B_H__
  7
  8#include <asm/byteorder.h>
  9
 10#define RCR_VHT_ACK		BIT(26)
 11
 12struct rtw8822bu_efuse {
 13	u8 res4[4];			/* 0xd0 */
 14	u8 usb_optional_function;
 15	u8 res5[0x1e];
 16	u8 res6[2];
 17	u8 serial[0x0b];		/* 0xf5 */
 18	u8 vid;				/* 0x100 */
 19	u8 res7;
 20	u8 pid;
 21	u8 res8[4];
 22	u8 mac_addr[ETH_ALEN];		/* 0x107 */
 23	u8 res9[2];
 24	u8 vendor_name[0x07];
 25	u8 res10[2];
 26	u8 device_name[0x14];
 27	u8 res11[0xcf];
 28	u8 package_type;		/* 0x1fb */
 29	u8 res12[0x4];
 30} __packed;
 31
 32struct rtw8822be_efuse {
 33	u8 mac_addr[ETH_ALEN];		/* 0xd0 */
 34	u8 vender_id[2];
 35	u8 device_id[2];
 36	u8 sub_vender_id[2];
 37	u8 sub_device_id[2];
 38	u8 pmc[2];
 39	u8 exp_device_cap[2];
 40	u8 msi_cap;
 41	u8 ltr_cap;			/* 0xe3 */
 42	u8 exp_link_control[2];
 43	u8 link_cap[4];
 44	u8 link_control[2];
 45	u8 serial_number[8];
 46	u8 res0:2;			/* 0xf4 */
 47	u8 ltr_en:1;
 48	u8 res1:2;
 49	u8 obff:2;
 50	u8 res2_1:1;
 51	u8 res2_2:2;
 52	u8 obff_cap:2;
 53	u8 res3:4;
 54	u8 res4[3];
 55	u8 class_code[3];
 56	u8 pci_pm_L1_2_supp:1;
 57	u8 pci_pm_L1_1_supp:1;
 58	u8 aspm_pm_L1_2_supp:1;
 59	u8 aspm_pm_L1_1_supp:1;
 60	u8 L1_pm_substates_supp:1;
 61	u8 res5:3;
 62	u8 port_common_mode_restore_time;
 63	u8 port_t_power_on_scale:2;
 64	u8 res6:1;
 65	u8 port_t_power_on_value:5;
 66	u8 res7;
 67} __packed;
 68
 69struct rtw8822bs_efuse {
 70	u8 res4[0x4a];			/* 0xd0 */
 71	u8 mac_addr[ETH_ALEN];		/* 0x11a */
 72} __packed;
 73
 74struct rtw8822b_efuse {
 75	__le16 rtl_id;
 76	u8 res0[4];
 77	u8 usb_mode;
 78	u8 res1[0x09];
 79
 80	/* power index for four RF paths */
 81	struct rtw_txpwr_idx txpwr_idx_table[4];
 82
 83	u8 channel_plan;		/* 0xb8 */
 84	u8 xtal_k;
 85	u8 thermal_meter;
 86	u8 iqk_lck;
 87	u8 pa_type;			/* 0xbc */
 88	u8 lna_type_2g[2];		/* 0xbd */
 89	u8 lna_type_5g[2];
 90	u8 rf_board_option;
 91	u8 rf_feature_option;
 92	u8 rf_bt_setting;
 93	u8 eeprom_version;
 94	u8 eeprom_customer_id;
 95	u8 tx_bb_swing_setting_2g;
 96	u8 tx_bb_swing_setting_5g;
 97	u8 tx_pwr_calibrate_rate;
 98	u8 rf_antenna_option;		/* 0xc9 */
 99	u8 rfe_option;
100	u8 country_code[2];
101	u8 res[3];
102	union {
103		struct rtw8822be_efuse e;
104		struct rtw8822bu_efuse u;
105		struct rtw8822bs_efuse s;
106	};
107} __packed;
108
109static inline void
110_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
111{
112	/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
113	rtw_write32_mask(rtwdev, addr, mask, data);
114	rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
115}
116
117#define rtw_write32s_mask(rtwdev, addr, mask, data)			       \
118	do {								       \
119		BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);	       \
120									       \
121		_rtw_write32s_mask(rtwdev, addr, mask, data);		       \
122	} while (0)
123
124/* phy status page0 */
125#define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
126	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
127
128/* phy status page1 */
129#define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
130	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
131#define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
132	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
133#define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
134	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
135#define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
136	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
137#define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
138	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
139#define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
140	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
141#define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
142	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
143#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
144	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
145#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
146	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
147#define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
148	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
149#define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
150	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
151
152#define RTW8822B_EDCCA_MAX	0x7f
153#define RTW8822B_EDCCA_SRC_DEF	1
154#define REG_HTSTFWT	0x800
155#define REG_RXCCAMSK	0x814
156#define REG_L1WT	0x83c
157#define REG_L1PKWT	0x840
158#define REG_MRC		0x850
159#define REG_EDCCA_POW_MA	0x8a0
160#define BIT_MA_LEVEL	GENMASK(1, 0)
161#define REG_ADC40	0x8c8
162#define REG_EDCCA_DECISION	0x8dc
163#define BIT_EDCCA_OPTION	BIT(5)
164#define REG_CDDTXP	0x93c
165#define REG_TXPSEL1	0x940
166#define REG_EDCCA_SOURCE	0x944
167#define BIT_SOURCE_OPTION	GENMASK(29, 28)
168#define REG_ACBB0	0x948
169#define REG_ACBBRXFIR	0x94c
170#define REG_ACGG2TBL	0x958
171#define REG_ADCINI	0xa04
172#define REG_TXSF2	0xa24
173#define REG_TXSF6	0xa28
174#define REG_RXDESC	0xa2c
175#define REG_ENTXCCK	0xa80
176#define REG_AGCTR_A	0xc08
177#define REG_TXDFIR	0xc20
178#define REG_TRSW	0xca0
179#define REG_RFESEL0	0xcb0
180#define REG_RFESEL8	0xcb4
181#define REG_RFECTL	0xcb8
182#define REG_RFEINV	0xcbc
183#define REG_AGCTR_B	0xe08
184#define REG_ANTWT	0x1904
185#define REG_IQKFAILMSK	0x1bf0
186
187extern const struct rtw_chip_info rtw8822b_hw_spec;
188
189#endif