1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
  4 *
  5 * Authors: Inha Song <ideal.song@samsung.com>
  6 *          Sylwester Nawrocki <s.nawrocki@samsung.com>
  7 *
  8 * Samsung Exynos SoC series Low Power Audio Subsystem driver.
  9 *
 10 * This module provides regmap for the Top SFR region and instantiates
 11 * devices for IP blocks like DMAC, I2S, UART.
 12 */
 13
 14#include <linux/clk.h>
 15#include <linux/delay.h>
 16#include <linux/io.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/of_platform.h>
 20#include <linux/platform_device.h>
 21#include <linux/pm_runtime.h>
 22#include <linux/regmap.h>
 23#include <linux/soc/samsung/exynos-regs-pmu.h>
 24#include <linux/types.h>
 25
 26/* LPASS Top register definitions */
 27#define SFR_LPASS_CORE_SW_RESET		0x08
 28#define  LPASS_SB_SW_RESET		BIT(11)
 29#define  LPASS_UART_SW_RESET		BIT(10)
 30#define  LPASS_PCM_SW_RESET		BIT(9)
 31#define  LPASS_I2S_SW_RESET		BIT(8)
 32#define  LPASS_WDT1_SW_RESET		BIT(4)
 33#define  LPASS_WDT0_SW_RESET		BIT(3)
 34#define  LPASS_TIMER_SW_RESET		BIT(2)
 35#define  LPASS_MEM_SW_RESET		BIT(1)
 36#define  LPASS_DMA_SW_RESET		BIT(0)
 37
 38#define SFR_LPASS_INTR_CA5_MASK		0x48
 39#define SFR_LPASS_INTR_CPU_MASK		0x58
 40#define  LPASS_INTR_APM			BIT(9)
 41#define  LPASS_INTR_MIF			BIT(8)
 42#define  LPASS_INTR_TIMER		BIT(7)
 43#define  LPASS_INTR_DMA			BIT(6)
 44#define  LPASS_INTR_GPIO		BIT(5)
 45#define  LPASS_INTR_I2S			BIT(4)
 46#define  LPASS_INTR_PCM			BIT(3)
 47#define  LPASS_INTR_SLIMBUS		BIT(2)
 48#define  LPASS_INTR_UART		BIT(1)
 49#define  LPASS_INTR_SFR			BIT(0)
 50
 51struct exynos_lpass {
 52	/* pointer to the LPASS TOP regmap */
 53	struct regmap *top;
 54	struct clk *sfr0_clk;
 55};
 56
 57static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
 58{
 59	unsigned int val = 0;
 60
 61	regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
 62
 63	val &= ~mask;
 64	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
 65
 66	usleep_range(100, 150);
 67
 68	val |= mask;
 69	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
 70}
 71
 72static void exynos_lpass_enable(struct exynos_lpass *lpass)
 73{
 74	clk_prepare_enable(lpass->sfr0_clk);
 75
 76	/* Unmask SFR, DMA and I2S interrupt */
 77	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
 78		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
 79
 80	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
 81		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
 82		     LPASS_INTR_UART);
 83
 84	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
 85	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
 86	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
 87	exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
 88}
 89
 90static void exynos_lpass_disable(struct exynos_lpass *lpass)
 91{
 92	/* Mask any unmasked IP interrupt sources */
 93	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 94	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
 95
 96	clk_disable_unprepare(lpass->sfr0_clk);
 97}
 98
 99static const struct regmap_config exynos_lpass_reg_conf = {
100	.reg_bits	= 32,
101	.reg_stride	= 4,
102	.val_bits	= 32,
103	.max_register	= 0xfc,
104	.fast_io	= true,
105};
106
107static int exynos_lpass_probe(struct platform_device *pdev)
108{
109	struct device *dev = &pdev->dev;
110	struct exynos_lpass *lpass;
111	void __iomem *base_top;
112
113	lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
114	if (!lpass)
115		return -ENOMEM;
116
117	base_top = devm_platform_ioremap_resource(pdev, 0);
118	if (IS_ERR(base_top))
119		return PTR_ERR(base_top);
120
121	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
122	if (IS_ERR(lpass->sfr0_clk))
123		return PTR_ERR(lpass->sfr0_clk);
124
125	lpass->top = regmap_init_mmio(dev, base_top,
126					&exynos_lpass_reg_conf);
127	if (IS_ERR(lpass->top)) {
128		dev_err(dev, "LPASS top regmap initialization failed\n");
129		return PTR_ERR(lpass->top);
130	}
131
132	platform_set_drvdata(pdev, lpass);
133	pm_runtime_set_active(dev);
134	pm_runtime_enable(dev);
135	exynos_lpass_enable(lpass);
136
137	return devm_of_platform_populate(dev);
138}
139
140static void exynos_lpass_remove(struct platform_device *pdev)
141{
142	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
143
144	exynos_lpass_disable(lpass);
145	pm_runtime_disable(&pdev->dev);
146	if (!pm_runtime_status_suspended(&pdev->dev))
147		exynos_lpass_disable(lpass);
148	regmap_exit(lpass->top);
149}
150
151static int __maybe_unused exynos_lpass_suspend(struct device *dev)
152{
153	struct exynos_lpass *lpass = dev_get_drvdata(dev);
154
155	exynos_lpass_disable(lpass);
156
157	return 0;
158}
159
160static int __maybe_unused exynos_lpass_resume(struct device *dev)
161{
162	struct exynos_lpass *lpass = dev_get_drvdata(dev);
163
164	exynos_lpass_enable(lpass);
165
166	return 0;
167}
168
169static const struct dev_pm_ops lpass_pm_ops = {
170	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
171	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
172				     pm_runtime_force_resume)
173};
174
175static const struct of_device_id exynos_lpass_of_match[] = {
176	{ .compatible = "samsung,exynos5433-lpass" },
177	{ },
178};
179MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
180
181static struct platform_driver exynos_lpass_driver = {
182	.driver	= {
183		.name		= "exynos-lpass",
184		.pm		= &lpass_pm_ops,
185		.of_match_table	= exynos_lpass_of_match,
186	},
187	.probe	= exynos_lpass_probe,
188	.remove	= exynos_lpass_remove,
189};
190module_platform_driver(exynos_lpass_driver);
191
192MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
193MODULE_LICENSE("GPL v2");