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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright (C) 2020 Google, Inc.
4 *
5 * Authors:
6 * Sean Paul <seanpaul@chromium.org>
7 */
8
9#include <drm/display/drm_dp_helper.h>
10#include <drm/display/drm_dp_mst_helper.h>
11#include <drm/display/drm_hdcp_helper.h>
12#include <drm/drm_print.h>
13
14#include "i915_reg.h"
15#include "intel_ddi.h"
16#include "intel_de.h"
17#include "intel_display_types.h"
18#include "intel_dp.h"
19#include "intel_dp_hdcp.h"
20#include "intel_hdcp.h"
21#include "intel_hdcp_regs.h"
22#include "intel_hdcp_shim.h"
23
24static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
25{
26 switch (cpu_transcoder) {
27 case TRANSCODER_A:
28 return HDCP_STATUS_STREAM_A_ENC;
29 case TRANSCODER_B:
30 return HDCP_STATUS_STREAM_B_ENC;
31 case TRANSCODER_C:
32 return HDCP_STATUS_STREAM_C_ENC;
33 case TRANSCODER_D:
34 return HDCP_STATUS_STREAM_D_ENC;
35 default:
36 return 0;
37 }
38}
39
40static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector,
41 int timeout)
42{
43 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
44 struct intel_dp *dp = &dig_port->dp;
45 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
46 long ret;
47
48#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
49 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
50 msecs_to_jiffies(timeout));
51
52 if (!ret)
53 drm_dbg_kms(connector->base.dev,
54 "Timedout at waiting for CP_IRQ\n");
55}
56
57static
58int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
59 u8 *an)
60{
61 struct intel_display *display = to_intel_display(dig_port);
62 u8 aksv[DRM_HDCP_KSV_LEN] = {};
63 ssize_t dpcd_ret;
64
65 /* Output An first, that's easy */
66 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
67 an, DRM_HDCP_AN_LEN);
68 if (dpcd_ret != DRM_HDCP_AN_LEN) {
69 drm_dbg_kms(display->drm,
70 "Failed to write An over DP/AUX (%zd)\n",
71 dpcd_ret);
72 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
73 }
74
75 /*
76 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
77 * send an empty buffer of the correct length through the DP helpers. On
78 * the other side, in the transfer hook, we'll generate a flag based on
79 * the destination address which will tickle the hardware to output the
80 * Aksv on our behalf after the header is sent.
81 */
82 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
83 aksv, DRM_HDCP_KSV_LEN);
84 if (dpcd_ret != DRM_HDCP_KSV_LEN) {
85 drm_dbg_kms(display->drm,
86 "Failed to write Aksv over DP/AUX (%zd)\n",
87 dpcd_ret);
88 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
89 }
90 return 0;
91}
92
93static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
94 u8 *bksv)
95{
96 struct intel_display *display = to_intel_display(dig_port);
97 ssize_t ret;
98
99 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
100 DRM_HDCP_KSV_LEN);
101 if (ret != DRM_HDCP_KSV_LEN) {
102 drm_dbg_kms(display->drm,
103 "Read Bksv from DP/AUX failed (%zd)\n", ret);
104 return ret >= 0 ? -EIO : ret;
105 }
106 return 0;
107}
108
109static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
110 u8 *bstatus)
111{
112 struct intel_display *display = to_intel_display(dig_port);
113 ssize_t ret;
114
115 /*
116 * For some reason the HDMI and DP HDCP specs call this register
117 * definition by different names. In the HDMI spec, it's called BSTATUS,
118 * but in DP it's called BINFO.
119 */
120 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
121 bstatus, DRM_HDCP_BSTATUS_LEN);
122 if (ret != DRM_HDCP_BSTATUS_LEN) {
123 drm_dbg_kms(display->drm,
124 "Read bstatus from DP/AUX failed (%zd)\n", ret);
125 return ret >= 0 ? -EIO : ret;
126 }
127 return 0;
128}
129
130static
131int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
132 struct intel_display *display,
133 u8 *bcaps)
134{
135 ssize_t ret;
136
137 ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
138 bcaps, 1);
139 if (ret != 1) {
140 drm_dbg_kms(display->drm,
141 "Read bcaps from DP/AUX failed (%zd)\n", ret);
142 return ret >= 0 ? -EIO : ret;
143 }
144
145 return 0;
146}
147
148static
149int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
150 bool *repeater_present)
151{
152 struct intel_display *display = to_intel_display(dig_port);
153 ssize_t ret;
154 u8 bcaps;
155
156 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
157 if (ret)
158 return ret;
159
160 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
161 return 0;
162}
163
164static
165int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
166 u8 *ri_prime)
167{
168 struct intel_display *display = to_intel_display(dig_port);
169 ssize_t ret;
170
171 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
172 ri_prime, DRM_HDCP_RI_LEN);
173 if (ret != DRM_HDCP_RI_LEN) {
174 drm_dbg_kms(display->drm,
175 "Read Ri' from DP/AUX failed (%zd)\n",
176 ret);
177 return ret >= 0 ? -EIO : ret;
178 }
179 return 0;
180}
181
182static
183int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
184 bool *ksv_ready)
185{
186 struct intel_display *display = to_intel_display(dig_port);
187 ssize_t ret;
188 u8 bstatus;
189
190 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
191 &bstatus, 1);
192 if (ret != 1) {
193 drm_dbg_kms(display->drm,
194 "Read bstatus from DP/AUX failed (%zd)\n", ret);
195 return ret >= 0 ? -EIO : ret;
196 }
197 *ksv_ready = bstatus & DP_BSTATUS_READY;
198 return 0;
199}
200
201static
202int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
203 int num_downstream, u8 *ksv_fifo)
204{
205 struct intel_display *display = to_intel_display(dig_port);
206 ssize_t ret;
207 int i;
208
209 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
210 for (i = 0; i < num_downstream; i += 3) {
211 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
212 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
213 DP_AUX_HDCP_KSV_FIFO,
214 ksv_fifo + i * DRM_HDCP_KSV_LEN,
215 len);
216 if (ret != len) {
217 drm_dbg_kms(display->drm,
218 "Read ksv[%d] from DP/AUX failed (%zd)\n",
219 i, ret);
220 return ret >= 0 ? -EIO : ret;
221 }
222 }
223 return 0;
224}
225
226static
227int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
228 int i, u32 *part)
229{
230 struct intel_display *display = to_intel_display(dig_port);
231 ssize_t ret;
232
233 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
234 return -EINVAL;
235
236 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
237 DP_AUX_HDCP_V_PRIME(i), part,
238 DRM_HDCP_V_PRIME_PART_LEN);
239 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
240 drm_dbg_kms(display->drm,
241 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
242 return ret >= 0 ? -EIO : ret;
243 }
244 return 0;
245}
246
247static
248int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
249 enum transcoder cpu_transcoder,
250 bool enable)
251{
252 /* Not used for single stream DisplayPort setups */
253 return 0;
254}
255
256static
257bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
258 struct intel_connector *connector)
259{
260 struct intel_display *display = to_intel_display(dig_port);
261 ssize_t ret;
262 u8 bstatus;
263
264 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
265 &bstatus, 1);
266 if (ret != 1) {
267 drm_dbg_kms(display->drm,
268 "Read bstatus from DP/AUX failed (%zd)\n", ret);
269 return false;
270 }
271
272 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
273}
274
275static
276int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
277 bool *hdcp_capable)
278{
279 struct intel_display *display = to_intel_display(dig_port);
280 ssize_t ret;
281 u8 bcaps;
282
283 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
284 if (ret)
285 return ret;
286
287 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
288 return 0;
289}
290
291struct hdcp2_dp_errata_stream_type {
292 u8 msg_id;
293 u8 stream_type;
294} __packed;
295
296struct hdcp2_dp_msg_data {
297 u8 msg_id;
298 u32 offset;
299 bool msg_detectable;
300 u32 timeout;
301 u32 timeout2; /* Added for non_paired situation */
302 /* Timeout to read entire msg */
303 u32 msg_read_timeout;
304};
305
306static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
307 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
308 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
309 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
310 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
311 false, 0, 0, 0 },
312 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
313 false, 0, 0, 0 },
314 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
315 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
316 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
317 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
318 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
319 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
320 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
321 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
322 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
323 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
324 0, 0, 0 },
325 { HDCP_2_2_REP_SEND_RECVID_LIST,
326 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
327 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
328 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
329 0, 0, 0 },
330 { HDCP_2_2_REP_STREAM_MANAGE,
331 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
332 0, 0, 0},
333 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
334 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
335/* local define to shovel this through the write_2_2 interface */
336#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
337 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
338 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
339 0, 0 },
340};
341
342static int
343intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
344 u8 *rx_status)
345{
346 struct intel_display *display = to_intel_display(connector);
347 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
348 struct drm_dp_aux *aux = &dig_port->dp.aux;
349 ssize_t ret;
350
351 ret = drm_dp_dpcd_read(aux,
352 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
353 HDCP_2_2_DP_RXSTATUS_LEN);
354 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
355 drm_dbg_kms(display->drm,
356 "Read bstatus from DP/AUX failed (%zd)\n", ret);
357 return ret >= 0 ? -EIO : ret;
358 }
359
360 return 0;
361}
362
363static
364int hdcp2_detect_msg_availability(struct intel_connector *connector,
365 u8 msg_id, bool *msg_ready)
366{
367 u8 rx_status;
368 int ret;
369
370 *msg_ready = false;
371 ret = intel_dp_hdcp2_read_rx_status(connector, &rx_status);
372 if (ret < 0)
373 return ret;
374
375 switch (msg_id) {
376 case HDCP_2_2_AKE_SEND_HPRIME:
377 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
378 *msg_ready = true;
379 break;
380 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
381 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
382 *msg_ready = true;
383 break;
384 case HDCP_2_2_REP_SEND_RECVID_LIST:
385 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
386 *msg_ready = true;
387 break;
388 default:
389 drm_err(connector->base.dev,
390 "Unidentified msg_id: %d\n", msg_id);
391 return -EINVAL;
392 }
393
394 return 0;
395}
396
397static ssize_t
398intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
399 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
400{
401 struct intel_display *display = to_intel_display(connector);
402 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
403 struct intel_dp *dp = &dig_port->dp;
404 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
405 u8 msg_id = hdcp2_msg_data->msg_id;
406 int ret, timeout;
407 bool msg_ready = false;
408
409 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
410 timeout = hdcp2_msg_data->timeout2;
411 else
412 timeout = hdcp2_msg_data->timeout;
413
414 /*
415 * There is no way to detect the CERT, LPRIME and STREAM_READY
416 * availability. So Wait for timeout and read the msg.
417 */
418 if (!hdcp2_msg_data->msg_detectable) {
419 mdelay(timeout);
420 ret = 0;
421 } else {
422 /*
423 * As we want to check the msg availability at timeout, Ignoring
424 * the timeout at wait for CP_IRQ.
425 */
426 intel_dp_hdcp_wait_for_cp_irq(connector, timeout);
427 ret = hdcp2_detect_msg_availability(connector, msg_id,
428 &msg_ready);
429 if (!msg_ready)
430 ret = -ETIMEDOUT;
431 }
432
433 if (ret)
434 drm_dbg_kms(display->drm,
435 "msg_id %d, ret %d, timeout(mSec): %d\n",
436 hdcp2_msg_data->msg_id, ret, timeout);
437
438 return ret;
439}
440
441static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
442{
443 int i;
444
445 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
446 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
447 return &hdcp2_dp_msg_data[i];
448
449 return NULL;
450}
451
452static
453int intel_dp_hdcp2_write_msg(struct intel_connector *connector,
454 void *buf, size_t size)
455{
456 unsigned int offset;
457 u8 *byte = buf;
458 ssize_t ret, bytes_to_write, len;
459 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
460 struct drm_dp_aux *aux = &dig_port->dp.aux;
461 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
462
463 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
464 if (!hdcp2_msg_data)
465 return -EINVAL;
466
467 offset = hdcp2_msg_data->offset;
468
469 /* No msg_id in DP HDCP2.2 msgs */
470 bytes_to_write = size - 1;
471 byte++;
472
473 while (bytes_to_write) {
474 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
475 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
476
477 ret = drm_dp_dpcd_write(aux,
478 offset, (void *)byte, len);
479 if (ret < 0)
480 return ret;
481
482 bytes_to_write -= ret;
483 byte += ret;
484 offset += ret;
485 }
486
487 return size;
488}
489
490static
491ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector,
492 u32 *dev_cnt, u8 *byte)
493{
494 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
495 struct drm_dp_aux *aux = &dig_port->dp.aux;
496 ssize_t ret;
497 u8 *rx_info = byte;
498
499 ret = drm_dp_dpcd_read(aux,
500 DP_HDCP_2_2_REG_RXINFO_OFFSET,
501 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
502 if (ret != HDCP_2_2_RXINFO_LEN)
503 return ret >= 0 ? -EIO : ret;
504
505 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
506 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
507
508 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
509 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
510
511 return ret;
512}
513
514static
515int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
516 u8 msg_id, void *buf, size_t size)
517{
518 struct intel_display *display = to_intel_display(connector);
519 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
520 struct drm_dp_aux *aux = &dig_port->dp.aux;
521 struct intel_dp *dp = &dig_port->dp;
522 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
523 unsigned int offset;
524 u8 *byte = buf;
525 ssize_t ret, bytes_to_recv, len;
526 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
527 ktime_t msg_end = ktime_set(0, 0);
528 bool msg_expired;
529 u32 dev_cnt;
530
531 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
532 if (!hdcp2_msg_data)
533 return -EINVAL;
534 offset = hdcp2_msg_data->offset;
535
536 ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data);
537 if (ret < 0)
538 return ret;
539
540 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
541
542 /* DP adaptation msgs has no msg_id */
543 byte++;
544
545 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
546 ret = get_receiver_id_list_rx_info(connector, &dev_cnt, byte);
547 if (ret < 0)
548 return ret;
549
550 byte += ret;
551 size = sizeof(struct hdcp2_rep_send_receiverid_list) -
552 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
553 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
554 offset += HDCP_2_2_RXINFO_LEN;
555 }
556
557 bytes_to_recv = size - 1;
558
559 while (bytes_to_recv) {
560 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
561 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
562
563 /* Entire msg read timeout since initiate of msg read */
564 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) {
565 msg_end = ktime_add_ms(ktime_get_raw(),
566 hdcp2_msg_data->msg_read_timeout);
567 }
568
569 ret = drm_dp_dpcd_read(aux, offset,
570 (void *)byte, len);
571 if (ret < 0) {
572 drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
573 msg_id, ret);
574 return ret;
575 }
576
577 bytes_to_recv -= ret;
578 byte += ret;
579 offset += ret;
580 }
581
582 if (hdcp2_msg_data->msg_read_timeout > 0) {
583 msg_expired = ktime_after(ktime_get_raw(), msg_end);
584 if (msg_expired) {
585 drm_dbg_kms(display->drm,
586 "msg_id %d, entire msg read timeout(mSec): %d\n",
587 msg_id, hdcp2_msg_data->msg_read_timeout);
588 return -ETIMEDOUT;
589 }
590 }
591
592 byte = buf;
593 *byte = msg_id;
594
595 return size;
596}
597
598static
599int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector,
600 bool is_repeater, u8 content_type)
601{
602 int ret;
603 struct hdcp2_dp_errata_stream_type stream_type_msg;
604
605 if (is_repeater)
606 return 0;
607
608 /*
609 * Errata for DP: As Stream type is used for encryption, Receiver
610 * should be communicated with stream type for the decryption of the
611 * content.
612 * Repeater will be communicated with stream type as a part of it's
613 * auth later in time.
614 */
615 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
616 stream_type_msg.stream_type = content_type;
617
618 ret = intel_dp_hdcp2_write_msg(connector, &stream_type_msg,
619 sizeof(stream_type_msg));
620
621 return ret < 0 ? ret : 0;
622
623}
624
625static
626int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
627 struct intel_connector *connector)
628{
629 u8 rx_status;
630 int ret;
631
632 ret = intel_dp_hdcp2_read_rx_status(connector,
633 &rx_status);
634 if (ret)
635 return ret;
636
637 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
638 ret = HDCP_REAUTH_REQUEST;
639 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
640 ret = HDCP_LINK_INTEGRITY_FAILURE;
641 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
642 ret = HDCP_TOPOLOGY_CHANGE;
643
644 return ret;
645}
646
647static
648int _intel_dp_hdcp2_get_capability(struct drm_dp_aux *aux,
649 bool *capable)
650{
651 u8 rx_caps[3];
652 int ret, i;
653
654 *capable = false;
655
656 /*
657 * Some HDCP monitors act really shady by not giving the correct hdcp
658 * capability on the first rx_caps read and usually take an extra read
659 * to give the capability. We read rx_caps three times before we
660 * declare a monitor not capable of HDCP 2.2.
661 */
662 for (i = 0; i < 3; i++) {
663 ret = drm_dp_dpcd_read(aux,
664 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
665 rx_caps, HDCP_2_2_RXCAPS_LEN);
666 if (ret != HDCP_2_2_RXCAPS_LEN)
667 return ret >= 0 ? -EIO : ret;
668
669 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
670 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) {
671 *capable = true;
672 break;
673 }
674 }
675
676 return 0;
677}
678
679static
680int intel_dp_hdcp2_get_capability(struct intel_connector *connector,
681 bool *capable)
682{
683 struct intel_digital_port *dig_port;
684 struct drm_dp_aux *aux;
685
686 *capable = false;
687 if (!intel_attached_encoder(connector))
688 return -EINVAL;
689
690 dig_port = intel_attached_dig_port(connector);
691 aux = &dig_port->dp.aux;
692
693 return _intel_dp_hdcp2_get_capability(aux, capable);
694}
695
696static
697int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
698 bool *hdcp_capable,
699 bool *hdcp2_capable)
700{
701 struct intel_display *display = to_intel_display(connector);
702 struct drm_dp_aux *aux;
703 u8 bcaps;
704 int ret;
705
706 *hdcp_capable = false;
707 *hdcp2_capable = false;
708 if (!connector->mst_port)
709 return -EINVAL;
710
711 aux = &connector->port->aux;
712 ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
713 if (ret)
714 drm_dbg_kms(display->drm,
715 "HDCP2 DPCD capability read failed err: %d\n", ret);
716
717 ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
718 if (ret)
719 return ret;
720
721 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
722
723 return 0;
724}
725
726static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
727 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
728 .read_bksv = intel_dp_hdcp_read_bksv,
729 .read_bstatus = intel_dp_hdcp_read_bstatus,
730 .repeater_present = intel_dp_hdcp_repeater_present,
731 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
732 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
733 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
734 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
735 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
736 .check_link = intel_dp_hdcp_check_link,
737 .hdcp_get_capability = intel_dp_hdcp_get_capability,
738 .write_2_2_msg = intel_dp_hdcp2_write_msg,
739 .read_2_2_msg = intel_dp_hdcp2_read_msg,
740 .config_stream_type = intel_dp_hdcp2_config_stream_type,
741 .check_2_2_link = intel_dp_hdcp2_check_link,
742 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability,
743 .protocol = HDCP_PROTOCOL_DP,
744};
745
746static int
747intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
748 bool enable)
749{
750 struct intel_display *display = to_intel_display(connector);
751 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
752 struct intel_hdcp *hdcp = &connector->hdcp;
753 int ret;
754
755 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
756 hdcp->stream_transcoder, enable,
757 TRANS_DDI_HDCP_SELECT);
758 if (ret)
759 drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
760 enable ? "Enable" : "Disable", ret);
761 return ret;
762}
763
764static int
765intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
766 bool enable)
767{
768 struct intel_display *display = to_intel_display(connector);
769 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
770 struct intel_hdcp *hdcp = &connector->hdcp;
771 enum port port = dig_port->base.port;
772 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
773 u32 stream_enc_status;
774 int ret;
775
776 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
777 if (ret)
778 return ret;
779
780 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder);
781 if (!stream_enc_status)
782 return -EINVAL;
783
784 /* Wait for encryption confirmation */
785 if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
786 stream_enc_status, enable ? stream_enc_status : 0,
787 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
788 drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
789 transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
790 return -ETIMEDOUT;
791 }
792
793 return 0;
794}
795
796static int
797intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
798 bool enable)
799{
800 struct intel_display *display = to_intel_display(connector);
801 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
802 struct hdcp_port_data *data = &dig_port->hdcp_port_data;
803 struct intel_hdcp *hdcp = &connector->hdcp;
804 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
805 enum pipe pipe = (enum pipe)cpu_transcoder;
806 enum port port = dig_port->base.port;
807 int ret;
808
809 drm_WARN_ON(display->drm, enable &&
810 !!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
811 & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
812
813 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
814 if (ret)
815 return ret;
816
817 /* Wait for encryption confirmation */
818 if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
819 STREAM_ENCRYPTION_STATUS,
820 enable ? STREAM_ENCRYPTION_STATUS : 0,
821 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
822 drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
823 transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
824 return -ETIMEDOUT;
825 }
826
827 return 0;
828}
829
830static
831int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
832 struct intel_connector *connector)
833{
834 struct intel_hdcp *hdcp = &connector->hdcp;
835 int ret;
836
837 /*
838 * We do need to do the Link Check only for the connector involved with
839 * HDCP port authentication and encryption.
840 * We can re-use the hdcp->is_repeater flag to know that the connector
841 * involved with HDCP port authentication and encryption.
842 */
843 if (hdcp->is_repeater) {
844 ret = intel_dp_hdcp2_check_link(dig_port, connector);
845 if (ret)
846 return ret;
847 }
848
849 return 0;
850}
851
852static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
853 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
854 .read_bksv = intel_dp_hdcp_read_bksv,
855 .read_bstatus = intel_dp_hdcp_read_bstatus,
856 .repeater_present = intel_dp_hdcp_repeater_present,
857 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
858 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
859 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
860 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
861 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
862 .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
863 .check_link = intel_dp_hdcp_check_link,
864 .hdcp_get_capability = intel_dp_hdcp_get_capability,
865 .write_2_2_msg = intel_dp_hdcp2_write_msg,
866 .read_2_2_msg = intel_dp_hdcp2_read_msg,
867 .config_stream_type = intel_dp_hdcp2_config_stream_type,
868 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
869 .check_2_2_link = intel_dp_mst_hdcp2_check_link,
870 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability,
871 .get_remote_hdcp_capability = intel_dp_hdcp_get_remote_capability,
872 .protocol = HDCP_PROTOCOL_DP,
873};
874
875int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
876 struct intel_connector *intel_connector)
877{
878 struct intel_display *display = to_intel_display(dig_port);
879 struct intel_encoder *intel_encoder = &dig_port->base;
880 enum port port = intel_encoder->port;
881 struct intel_dp *intel_dp = &dig_port->dp;
882
883 if (!is_hdcp_supported(display, port))
884 return 0;
885
886 if (intel_connector->mst_port)
887 return intel_hdcp_init(intel_connector, dig_port,
888 &intel_dp_mst_hdcp_shim);
889 else if (!intel_dp_is_edp(intel_dp))
890 return intel_hdcp_init(intel_connector, dig_port,
891 &intel_dp_hdcp_shim);
892
893 return 0;
894}