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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/gpio/consumer.h>
10#include <linux/i2c.h>
11#include <linux/kernel.h>
12#include <linux/math64.h>
13#include <linux/media-bus-format.h>
14#include <linux/minmax.h>
15#include <linux/module.h>
16#include <linux/regmap.h>
17#include <linux/regulator/consumer.h>
18#include <linux/slab.h>
19#include <linux/units.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_drv.h>
23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_of.h>
25#include <drm/drm_panel.h>
26#include <video/mipi_display.h>
27#include <video/videomode.h>
28
29/* Global (16-bit addressable) */
30#define TC358768_CHIPID 0x0000
31#define TC358768_SYSCTL 0x0002
32#define TC358768_CONFCTL 0x0004
33#define TC358768_VSDLY 0x0006
34#define TC358768_DATAFMT 0x0008
35#define TC358768_GPIOEN 0x000E
36#define TC358768_GPIODIR 0x0010
37#define TC358768_GPIOIN 0x0012
38#define TC358768_GPIOOUT 0x0014
39#define TC358768_PLLCTL0 0x0016
40#define TC358768_PLLCTL1 0x0018
41#define TC358768_CMDBYTE 0x0022
42#define TC358768_PP_MISC 0x0032
43#define TC358768_DSITX_DT 0x0050
44#define TC358768_FIFOSTATUS 0x00F8
45
46/* Debug (16-bit addressable) */
47#define TC358768_VBUFCTRL 0x00E0
48#define TC358768_DBG_WIDTH 0x00E2
49#define TC358768_DBG_VBLANK 0x00E4
50#define TC358768_DBG_DATA 0x00E8
51
52/* TX PHY (32-bit addressable) */
53#define TC358768_CLW_DPHYCONTTX 0x0100
54#define TC358768_D0W_DPHYCONTTX 0x0104
55#define TC358768_D1W_DPHYCONTTX 0x0108
56#define TC358768_D2W_DPHYCONTTX 0x010C
57#define TC358768_D3W_DPHYCONTTX 0x0110
58#define TC358768_CLW_CNTRL 0x0140
59#define TC358768_D0W_CNTRL 0x0144
60#define TC358768_D1W_CNTRL 0x0148
61#define TC358768_D2W_CNTRL 0x014C
62#define TC358768_D3W_CNTRL 0x0150
63
64/* TX PPI (32-bit addressable) */
65#define TC358768_STARTCNTRL 0x0204
66#define TC358768_DSITXSTATUS 0x0208
67#define TC358768_LINEINITCNT 0x0210
68#define TC358768_LPTXTIMECNT 0x0214
69#define TC358768_TCLK_HEADERCNT 0x0218
70#define TC358768_TCLK_TRAILCNT 0x021C
71#define TC358768_THS_HEADERCNT 0x0220
72#define TC358768_TWAKEUP 0x0224
73#define TC358768_TCLK_POSTCNT 0x0228
74#define TC358768_THS_TRAILCNT 0x022C
75#define TC358768_HSTXVREGCNT 0x0230
76#define TC358768_HSTXVREGEN 0x0234
77#define TC358768_TXOPTIONCNTRL 0x0238
78#define TC358768_BTACNTRL1 0x023C
79
80/* TX CTRL (32-bit addressable) */
81#define TC358768_DSI_CONTROL 0x040C
82#define TC358768_DSI_STATUS 0x0410
83#define TC358768_DSI_INT 0x0414
84#define TC358768_DSI_INT_ENA 0x0418
85#define TC358768_DSICMD_RDFIFO 0x0430
86#define TC358768_DSI_ACKERR 0x0434
87#define TC358768_DSI_ACKERR_INTENA 0x0438
88#define TC358768_DSI_ACKERR_HALT 0x043c
89#define TC358768_DSI_RXERR 0x0440
90#define TC358768_DSI_RXERR_INTENA 0x0444
91#define TC358768_DSI_RXERR_HALT 0x0448
92#define TC358768_DSI_ERR 0x044C
93#define TC358768_DSI_ERR_INTENA 0x0450
94#define TC358768_DSI_ERR_HALT 0x0454
95#define TC358768_DSI_CONFW 0x0500
96#define TC358768_DSI_LPCMD 0x0500
97#define TC358768_DSI_RESET 0x0504
98#define TC358768_DSI_INT_CLR 0x050C
99#define TC358768_DSI_START 0x0518
100
101/* DSITX CTRL (16-bit addressable) */
102#define TC358768_DSICMD_TX 0x0600
103#define TC358768_DSICMD_TYPE 0x0602
104#define TC358768_DSICMD_WC 0x0604
105#define TC358768_DSICMD_WD0 0x0610
106#define TC358768_DSICMD_WD1 0x0612
107#define TC358768_DSICMD_WD2 0x0614
108#define TC358768_DSICMD_WD3 0x0616
109#define TC358768_DSI_EVENT 0x0620
110#define TC358768_DSI_VSW 0x0622
111#define TC358768_DSI_VBPR 0x0624
112#define TC358768_DSI_VACT 0x0626
113#define TC358768_DSI_HSW 0x0628
114#define TC358768_DSI_HBPR 0x062A
115#define TC358768_DSI_HACT 0x062C
116
117/* TC358768_DSI_CONTROL (0x040C) register */
118#define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
119#define TC358768_DSI_CONTROL_TXMD BIT(7)
120#define TC358768_DSI_CONTROL_HSCKMD BIT(5)
121#define TC358768_DSI_CONTROL_EOTDIS BIT(0)
122
123/* TC358768_DSI_CONFW (0x0500) register */
124#define TC358768_DSI_CONFW_MODE_SET (5 << 29)
125#define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
126#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
127
128/* TC358768_DSICMD_TX (0x0600) register */
129#define TC358768_DSI_CMDTX_DC_START BIT(0)
130
131static const char * const tc358768_supplies[] = {
132 "vddc", "vddmipi", "vddio"
133};
134
135struct tc358768_dsi_output {
136 struct mipi_dsi_device *dev;
137 struct drm_panel *panel;
138 struct drm_bridge *bridge;
139};
140
141struct tc358768_priv {
142 struct device *dev;
143 struct regmap *regmap;
144 struct gpio_desc *reset_gpio;
145 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
146 struct clk *refclk;
147 int enabled;
148 int error;
149
150 struct mipi_dsi_host dsi_host;
151 struct drm_bridge bridge;
152 struct tc358768_dsi_output output;
153
154 u32 pd_lines; /* number of Parallel Port Input Data Lines */
155 u32 dsi_lanes; /* number of DSI Lanes */
156 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
157
158 /* Parameters for PLL programming */
159 u32 fbd; /* PLL feedback divider */
160 u32 prd; /* PLL input divider */
161 u32 frs; /* PLL Freqency range for HSCK (post divider) */
162
163 u32 dsiclk; /* pll_clk / 2 */
164 u32 pclk; /* incoming pclk rate */
165};
166
167static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
168 *host)
169{
170 return container_of(host, struct tc358768_priv, dsi_host);
171}
172
173static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
174 *bridge)
175{
176 return container_of(bridge, struct tc358768_priv, bridge);
177}
178
179static int tc358768_clear_error(struct tc358768_priv *priv)
180{
181 int ret = priv->error;
182
183 priv->error = 0;
184 return ret;
185}
186
187static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
188{
189 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
190 int tmpval = val;
191 size_t count = 2;
192
193 if (priv->error)
194 return;
195
196 /* 16-bit register? */
197 if (reg < 0x100 || reg >= 0x600)
198 count = 1;
199
200 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
201}
202
203static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
204{
205 size_t count = 2;
206
207 if (priv->error)
208 return;
209
210 /* 16-bit register? */
211 if (reg < 0x100 || reg >= 0x600) {
212 *val = 0;
213 count = 1;
214 }
215
216 priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
217}
218
219static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
220 u32 val)
221{
222 u32 tmp, orig;
223
224 tc358768_read(priv, reg, &orig);
225
226 if (priv->error)
227 return;
228
229 tmp = orig & ~mask;
230 tmp |= val & mask;
231 if (tmp != orig)
232 tc358768_write(priv, reg, tmp);
233}
234
235static void tc358768_dsicmd_tx(struct tc358768_priv *priv)
236{
237 u32 val;
238
239 /* start transfer */
240 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START);
241 if (priv->error)
242 return;
243
244 /* wait transfer completion */
245 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
246 (val & TC358768_DSI_CMDTX_DC_START) == 0,
247 100, 100000);
248}
249
250static int tc358768_sw_reset(struct tc358768_priv *priv)
251{
252 /* Assert Reset */
253 tc358768_write(priv, TC358768_SYSCTL, 1);
254 /* Release Reset, Exit Sleep */
255 tc358768_write(priv, TC358768_SYSCTL, 0);
256
257 return tc358768_clear_error(priv);
258}
259
260static void tc358768_hw_enable(struct tc358768_priv *priv)
261{
262 int ret;
263
264 if (priv->enabled)
265 return;
266
267 ret = clk_prepare_enable(priv->refclk);
268 if (ret < 0)
269 dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
270
271 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
272 if (ret < 0)
273 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
274
275 if (priv->reset_gpio)
276 usleep_range(200, 300);
277
278 /*
279 * The RESX is active low (GPIO_ACTIVE_LOW).
280 * DEASSERT (value = 0) the reset_gpio to enable the chip
281 */
282 gpiod_set_value_cansleep(priv->reset_gpio, 0);
283
284 /* wait for encoder clocks to stabilize */
285 usleep_range(1000, 2000);
286
287 priv->enabled = true;
288}
289
290static void tc358768_hw_disable(struct tc358768_priv *priv)
291{
292 int ret;
293
294 if (!priv->enabled)
295 return;
296
297 /*
298 * The RESX is active low (GPIO_ACTIVE_LOW).
299 * ASSERT (value = 1) the reset_gpio to disable the chip
300 */
301 gpiod_set_value_cansleep(priv->reset_gpio, 1);
302
303 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
304 priv->supplies);
305 if (ret < 0)
306 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
307
308 clk_disable_unprepare(priv->refclk);
309
310 priv->enabled = false;
311}
312
313static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
314{
315 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
316}
317
318static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
319{
320 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
321}
322
323static int tc358768_calc_pll(struct tc358768_priv *priv,
324 const struct drm_display_mode *mode,
325 bool verify_only)
326{
327 static const u32 frs_limits[] = {
328 1000000000,
329 500000000,
330 250000000,
331 125000000,
332 62500000
333 };
334 unsigned long refclk;
335 u32 prd, target_pll, i, max_pll, min_pll;
336 u32 frs, best_diff, best_pll, best_prd, best_fbd;
337
338 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
339
340 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */
341
342 for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
343 if (target_pll >= frs_limits[i])
344 break;
345
346 if (i == ARRAY_SIZE(frs_limits) || i == 0)
347 return -EINVAL;
348
349 frs = i - 1;
350 max_pll = frs_limits[i - 1];
351 min_pll = frs_limits[i];
352
353 refclk = clk_get_rate(priv->refclk);
354
355 best_diff = UINT_MAX;
356 best_pll = 0;
357 best_prd = 0;
358 best_fbd = 0;
359
360 for (prd = 1; prd <= 16; ++prd) {
361 u32 divisor = prd * (1 << frs);
362 u32 fbd;
363
364 for (fbd = 1; fbd <= 512; ++fbd) {
365 u32 pll, diff, pll_in;
366
367 pll = (u32)div_u64((u64)refclk * fbd, divisor);
368
369 if (pll >= max_pll || pll < min_pll)
370 continue;
371
372 pll_in = (u32)div_u64((u64)refclk, prd);
373 if (pll_in < 4000000)
374 continue;
375
376 diff = max(pll, target_pll) - min(pll, target_pll);
377
378 if (diff < best_diff) {
379 best_diff = diff;
380 best_pll = pll;
381 best_prd = prd;
382 best_fbd = fbd;
383
384 if (best_diff == 0)
385 goto found;
386 }
387 }
388 }
389
390 if (best_diff == UINT_MAX) {
391 dev_err(priv->dev, "could not find suitable PLL setup\n");
392 return -EINVAL;
393 }
394
395found:
396 if (verify_only)
397 return 0;
398
399 priv->fbd = best_fbd;
400 priv->prd = best_prd;
401 priv->frs = frs;
402 priv->dsiclk = best_pll / 2;
403 priv->pclk = mode->clock * 1000;
404
405 return 0;
406}
407
408static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
409 struct mipi_dsi_device *dev)
410{
411 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
412 struct drm_bridge *bridge;
413 struct drm_panel *panel;
414 struct device_node *ep;
415 int ret;
416
417 if (dev->lanes > 4) {
418 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
419 dev->lanes);
420 return -EINVAL;
421 }
422
423 /*
424 * tc358768 supports both Video and Pulse mode, but the driver only
425 * implements Video (event) mode currently
426 */
427 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
428 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
429 return -ENOTSUPP;
430 }
431
432 /*
433 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
434 * RGB888 is verified.
435 */
436 if (dev->format != MIPI_DSI_FMT_RGB888) {
437 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
438 return -ENOTSUPP;
439 }
440
441 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
442 &bridge);
443 if (ret)
444 return ret;
445
446 if (panel) {
447 bridge = drm_panel_bridge_add_typed(panel,
448 DRM_MODE_CONNECTOR_DSI);
449 if (IS_ERR(bridge))
450 return PTR_ERR(bridge);
451 }
452
453 priv->output.dev = dev;
454 priv->output.bridge = bridge;
455 priv->output.panel = panel;
456
457 priv->dsi_lanes = dev->lanes;
458 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
459
460 /* get input ep (port0/endpoint0) */
461 ret = -EINVAL;
462 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
463 if (ep) {
464 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines);
465 if (ret)
466 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
467
468 of_node_put(ep);
469 }
470
471 if (ret)
472 priv->pd_lines = priv->dsi_bpp;
473
474 drm_bridge_add(&priv->bridge);
475
476 return 0;
477}
478
479static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
480 struct mipi_dsi_device *dev)
481{
482 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
483
484 drm_bridge_remove(&priv->bridge);
485 if (priv->output.panel)
486 drm_panel_bridge_remove(priv->output.bridge);
487
488 return 0;
489}
490
491static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
492 const struct mipi_dsi_msg *msg)
493{
494 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
495 struct mipi_dsi_packet packet;
496 int ret;
497
498 if (!priv->enabled) {
499 dev_err(priv->dev, "Bridge is not enabled\n");
500 return -ENODEV;
501 }
502
503 if (msg->rx_len) {
504 dev_warn(priv->dev, "MIPI rx is not supported\n");
505 return -ENOTSUPP;
506 }
507
508 if (msg->tx_len > 8) {
509 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
510 return -ENOTSUPP;
511 }
512
513 ret = mipi_dsi_create_packet(&packet, msg);
514 if (ret)
515 return ret;
516
517 if (mipi_dsi_packet_format_is_short(msg->type)) {
518 tc358768_write(priv, TC358768_DSICMD_TYPE,
519 (0x10 << 8) | (packet.header[0] & 0x3f));
520 tc358768_write(priv, TC358768_DSICMD_WC, 0);
521 tc358768_write(priv, TC358768_DSICMD_WD0,
522 (packet.header[2] << 8) | packet.header[1]);
523 } else {
524 int i;
525
526 tc358768_write(priv, TC358768_DSICMD_TYPE,
527 (0x40 << 8) | (packet.header[0] & 0x3f));
528 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
529 for (i = 0; i < packet.payload_length; i += 2) {
530 u16 val = packet.payload[i];
531
532 if (i + 1 < packet.payload_length)
533 val |= packet.payload[i + 1] << 8;
534
535 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
536 }
537 }
538
539 tc358768_dsicmd_tx(priv);
540
541 ret = tc358768_clear_error(priv);
542 if (ret)
543 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
544 else
545 ret = packet.size;
546
547 return ret;
548}
549
550static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
551 .attach = tc358768_dsi_host_attach,
552 .detach = tc358768_dsi_host_detach,
553 .transfer = tc358768_dsi_host_transfer,
554};
555
556static int tc358768_bridge_attach(struct drm_bridge *bridge,
557 enum drm_bridge_attach_flags flags)
558{
559 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
560
561 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
562 dev_err(priv->dev, "needs atomic updates support\n");
563 return -ENOTSUPP;
564 }
565
566 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
567 flags);
568}
569
570static enum drm_mode_status
571tc358768_bridge_mode_valid(struct drm_bridge *bridge,
572 const struct drm_display_info *info,
573 const struct drm_display_mode *mode)
574{
575 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
576
577 if (tc358768_calc_pll(priv, mode, true))
578 return MODE_CLOCK_RANGE;
579
580 return MODE_OK;
581}
582
583static void tc358768_bridge_disable(struct drm_bridge *bridge)
584{
585 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
586 int ret;
587
588 /* set FrmStop */
589 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
590
591 /* wait at least for one frame */
592 msleep(50);
593
594 /* clear PP_en */
595 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
596
597 /* set RstPtr */
598 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
599
600 ret = tc358768_clear_error(priv);
601 if (ret)
602 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
603}
604
605static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
606{
607 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
608
609 tc358768_hw_disable(priv);
610}
611
612static int tc358768_setup_pll(struct tc358768_priv *priv,
613 const struct drm_display_mode *mode)
614{
615 u32 fbd, prd, frs;
616 int ret;
617
618 ret = tc358768_calc_pll(priv, mode, false);
619 if (ret) {
620 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
621 return ret;
622 }
623
624 fbd = priv->fbd;
625 prd = priv->prd;
626 frs = priv->frs;
627
628 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
629 clk_get_rate(priv->refclk), fbd, prd, frs);
630 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n",
631 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
632 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
633 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
634 mode->clock * 1000);
635
636 /* PRD[15:12] FBD[8:0] */
637 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1));
638
639 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
640 tc358768_write(priv, TC358768_PLLCTL1,
641 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
642
643 /* wait for lock */
644 usleep_range(1000, 2000);
645
646 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
647 tc358768_write(priv, TC358768_PLLCTL1,
648 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
649
650 return tc358768_clear_error(priv);
651}
652
653static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps)
654{
655 return DIV_ROUND_UP(ns * 1000, period_ps);
656}
657
658static u32 tc358768_ps_to_ns(u32 ps)
659{
660 return ps / 1000;
661}
662
663static u32 tc358768_dpi_to_ns(u32 val, u32 pclk)
664{
665 return (u32)div_u64((u64)val * NANO, pclk);
666}
667
668/* Convert value in DPI pixel clock units to DSI byte count */
669static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val)
670{
671 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;
672 u64 n = priv->pclk;
673
674 return (u32)div_u64(m + n - 1, n);
675}
676
677static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val)
678{
679 u64 m = (u64)val * NANO;
680 u64 n = priv->dsiclk / 4 * priv->dsi_lanes;
681
682 return (u32)div_u64(m, n);
683}
684
685static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
686{
687 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
688 struct mipi_dsi_device *dsi_dev = priv->output.dev;
689 unsigned long mode_flags = dsi_dev->mode_flags;
690 u32 val, val2, lptxcnt, hact, data_type;
691 s32 raw_val;
692 const struct drm_display_mode *mode;
693 u32 hsbyteclk_ps, dsiclk_ps, ui_ps;
694 u32 dsiclk, hsbyteclk;
695 int ret, i;
696 struct videomode vm;
697 struct device *dev = priv->dev;
698 /* In pixelclock units */
699 u32 dpi_htot, dpi_data_start;
700 /* In byte units */
701 u32 dsi_dpi_htot, dsi_dpi_data_start;
702 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp;
703 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */
704 /* In hsbyteclk units */
705 u32 dsi_vsdly;
706 const u32 internal_dly = 40;
707
708 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
709 dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n");
710 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
711 }
712
713 tc358768_hw_enable(priv);
714
715 ret = tc358768_sw_reset(priv);
716 if (ret) {
717 dev_err(dev, "Software reset failed: %d\n", ret);
718 tc358768_hw_disable(priv);
719 return;
720 }
721
722 mode = &bridge->encoder->crtc->state->adjusted_mode;
723 ret = tc358768_setup_pll(priv, mode);
724 if (ret) {
725 dev_err(dev, "PLL setup failed: %d\n", ret);
726 tc358768_hw_disable(priv);
727 return;
728 }
729
730 drm_display_mode_to_videomode(mode, &vm);
731
732 dsiclk = priv->dsiclk;
733 hsbyteclk = dsiclk / 4;
734
735 /* Data Format Control Register */
736 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
737 switch (dsi_dev->format) {
738 case MIPI_DSI_FMT_RGB888:
739 val |= (0x3 << 4);
740 hact = vm.hactive * 3;
741 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
742 break;
743 case MIPI_DSI_FMT_RGB666:
744 val |= (0x4 << 4);
745 hact = vm.hactive * 3;
746 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
747 break;
748
749 case MIPI_DSI_FMT_RGB666_PACKED:
750 val |= (0x4 << 4) | BIT(3);
751 hact = vm.hactive * 18 / 8;
752 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
753 break;
754
755 case MIPI_DSI_FMT_RGB565:
756 val |= (0x5 << 4);
757 hact = vm.hactive * 2;
758 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
759 break;
760 default:
761 dev_err(dev, "Invalid data format (%u)\n",
762 dsi_dev->format);
763 tc358768_hw_disable(priv);
764 return;
765 }
766
767 /*
768 * There are three important things to make TC358768 work correctly,
769 * which are not trivial to manage:
770 *
771 * 1. Keep the DPI line-time and the DSI line-time as close to each
772 * other as possible.
773 * 2. TC358768 goes to LP mode after each line's active area. The DSI
774 * HFP period has to be long enough for entering and exiting LP mode.
775 * But it is not clear how to calculate this.
776 * 3. VSDly (video start delay) has to be long enough to ensure that the
777 * DSI TX does not start transmitting until we have started receiving
778 * pixel data from the DPI input. It is not clear how to calculate
779 * this either.
780 */
781
782 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch;
783 dpi_data_start = vm.hsync_len + vm.hback_porch;
784
785 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n",
786 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch,
787 dpi_htot);
788
789 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n",
790 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
791 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
792 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock),
793 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock),
794 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock));
795
796 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n",
797 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
798 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
799 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock));
800
801 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot);
802 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start);
803
804 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
805 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len);
806 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch);
807 } else {
808 /* HBP is included in HSW in event mode */
809 dsi_hbp = 0;
810 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv,
811 vm.hsync_len +
812 vm.hback_porch);
813
814 /*
815 * The pixel packet includes the actual pixel data, and:
816 * DSI packet header = 4 bytes
817 * DCS code = 1 byte
818 * DSI packet footer = 2 bytes
819 */
820 dsi_hact = hact + 4 + 1 + 2;
821
822 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
823
824 /*
825 * Here we should check if HFP is long enough for entering LP
826 * and exiting LP, but it's not clear how to calculate that.
827 * Instead, this is a naive algorithm that just adjusts the HFP
828 * and HSW so that HFP is (at least) roughly 2/3 of the total
829 * blanking time.
830 */
831 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) {
832 u32 old_hfp = dsi_hfp;
833 u32 old_hsw = dsi_hsw;
834 u32 tot = dsi_hfp + dsi_hsw + dsi_hss;
835
836 dsi_hsw = tot / 3;
837
838 /*
839 * Seems like sometimes HSW has to be divisible by num-lanes, but
840 * not always...
841 */
842 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes);
843
844 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
845
846 dev_dbg(dev,
847 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n",
848 old_hfp, old_hsw, dsi_hfp, dsi_hsw);
849 }
850
851 dev_dbg(dev,
852 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n",
853 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp,
854 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp);
855
856 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n",
857 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
858 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
859 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
860 tc358768_dsi_bytes_to_ns(priv, dsi_hact),
861 tc358768_dsi_bytes_to_ns(priv, dsi_hfp),
862 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw +
863 dsi_hbp + dsi_hact + dsi_hfp));
864 }
865
866 /* VSDly calculation */
867
868 /* Start with the HW internal delay */
869 dsi_vsdly = internal_dly;
870
871 /* Convert to byte units as the other variables are in byte units */
872 dsi_vsdly *= priv->dsi_lanes;
873
874 /* Do we need more delay, in addition to the internal? */
875 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) {
876 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp;
877 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes);
878 }
879
880 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n",
881 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp,
882 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp);
883
884 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n",
885 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly),
886 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
887 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
888 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
889 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp));
890
891 /* Convert back to hsbyteclk */
892 dsi_vsdly /= priv->dsi_lanes;
893
894 /*
895 * The docs say that there is an internal delay of 40 cycles.
896 * However, we get underflows if we follow that rule. If we
897 * instead ignore the internal delay, things work. So either
898 * the docs are wrong or the calculations are wrong.
899 *
900 * As a temporary fix, add the internal delay here, to counter
901 * the subtraction when writing the register.
902 */
903 dsi_vsdly += internal_dly;
904
905 /* Clamp to the register max */
906 if (dsi_vsdly - internal_dly > 0x3ff) {
907 dev_warn(dev, "VSDly too high, underflows likely\n");
908 dsi_vsdly = 0x3ff + internal_dly;
909 }
910
911 /* VSDly[9:0] */
912 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly);
913
914 tc358768_write(priv, TC358768_DATAFMT, val);
915 tc358768_write(priv, TC358768_DSITX_DT, data_type);
916
917 /* Enable D-PHY (HiZ->LP11) */
918 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
919 /* Enable lanes */
920 for (i = 0; i < dsi_dev->lanes; i++)
921 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
922
923 /* DSI Timings */
924 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk);
925 dsiclk_ps = (u32)div_u64(PICO, dsiclk);
926 ui_ps = dsiclk_ps / 2;
927 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps,
928 ui_ps, hsbyteclk_ps);
929
930 /* LP11 > 100us for D-PHY Rx Init */
931 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
932 dev_dbg(dev, "LINEINITCNT: %u\n", val);
933 tc358768_write(priv, TC358768_LINEINITCNT, val);
934
935 /* LPTimeCnt > 50ns */
936 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
937 lptxcnt = val;
938 dev_dbg(dev, "LPTXTIMECNT: %u\n", val);
939 tc358768_write(priv, TC358768_LPTXTIMECNT, val);
940
941 /* 38ns < TCLK_PREPARE < 95ns */
942 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
943 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val);
944 /* TCLK_PREPARE + TCLK_ZERO > 300ns */
945 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
946 hsbyteclk_ps) - 2;
947 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2);
948 val |= val2 << 8;
949 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
950
951 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
952 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5;
953 val = clamp(raw_val, 0, 127);
954 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val);
955 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
956
957 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
958 val = 50 + tc358768_ps_to_ns(4 * ui_ps);
959 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
960 dev_dbg(dev, "THS_PREPARECNT %u\n", val);
961 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
962 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10;
963 val2 = clamp(raw_val, 0, 127);
964 dev_dbg(dev, "THS_ZEROCNT %u\n", val2);
965 val |= val2 << 8;
966 tc358768_write(priv, TC358768_THS_HEADERCNT, val);
967
968 /* TWAKEUP > 1ms in lptxcnt steps */
969 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps);
970 val = val / (lptxcnt + 1) - 1;
971 dev_dbg(dev, "TWAKEUP: %u\n", val);
972 tc358768_write(priv, TC358768_TWAKEUP, val);
973
974 /* TCLK_POSTCNT > 60ns + 52*UI */
975 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps),
976 hsbyteclk_ps) - 3;
977 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val);
978 tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
979
980 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
981 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps),
982 hsbyteclk_ps) - 4;
983 val = clamp(raw_val, 0, 15);
984 dev_dbg(dev, "THS_TRAILCNT: %u\n", val);
985 tc358768_write(priv, TC358768_THS_TRAILCNT, val);
986
987 val = BIT(0);
988 for (i = 0; i < dsi_dev->lanes; i++)
989 val |= BIT(i + 1);
990 tc358768_write(priv, TC358768_HSTXVREGEN, val);
991
992 tc358768_write(priv, TC358768_TXOPTIONCNTRL,
993 (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
994
995 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
996 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4);
997 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
998 dev_dbg(dev, "TXTAGOCNT: %u\n", val);
999 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps),
1000 hsbyteclk_ps) - 2;
1001 dev_dbg(dev, "RXTASURECNT: %u\n", val2);
1002 val = val << 16 | val2;
1003 tc358768_write(priv, TC358768_BTACNTRL1, val);
1004
1005 /* START[0] */
1006 tc358768_write(priv, TC358768_STARTCNTRL, 1);
1007
1008 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
1009 /* Set pulse mode */
1010 tc358768_write(priv, TC358768_DSI_EVENT, 0);
1011
1012 /* vact */
1013 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1014
1015 /* vsw */
1016 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len);
1017
1018 /* vbp */
1019 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch);
1020 } else {
1021 /* Set event mode */
1022 tc358768_write(priv, TC358768_DSI_EVENT, 1);
1023
1024 /* vact */
1025 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1026
1027 /* vsw (+ vbp) */
1028 tc358768_write(priv, TC358768_DSI_VSW,
1029 vm.vsync_len + vm.vback_porch);
1030
1031 /* vbp (not used in event mode) */
1032 tc358768_write(priv, TC358768_DSI_VBPR, 0);
1033 }
1034
1035 /* hsw (bytes) */
1036 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw);
1037
1038 /* hbp (bytes) */
1039 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp);
1040
1041 /* hact (bytes) */
1042 tc358768_write(priv, TC358768_DSI_HACT, hact);
1043
1044 /* VSYNC polarity */
1045 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
1046 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
1047
1048 /* HSYNC polarity */
1049 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
1050 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
1051
1052 /* Start DSI Tx */
1053 tc358768_write(priv, TC358768_DSI_START, 0x1);
1054
1055 /* Configure DSI_Control register */
1056 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1057 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
1058 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
1059 tc358768_write(priv, TC358768_DSI_CONFW, val);
1060
1061 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1062 val |= (dsi_dev->lanes - 1) << 1;
1063
1064 val |= TC358768_DSI_CONTROL_TXMD;
1065
1066 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
1067 val |= TC358768_DSI_CONTROL_HSCKMD;
1068
1069 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
1070 val |= TC358768_DSI_CONTROL_EOTDIS;
1071
1072 tc358768_write(priv, TC358768_DSI_CONFW, val);
1073
1074 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1075 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
1076 tc358768_write(priv, TC358768_DSI_CONFW, val);
1077
1078 ret = tc358768_clear_error(priv);
1079 if (ret) {
1080 dev_err(dev, "Bridge pre_enable failed: %d\n", ret);
1081 tc358768_bridge_disable(bridge);
1082 tc358768_bridge_post_disable(bridge);
1083 }
1084}
1085
1086static void tc358768_bridge_enable(struct drm_bridge *bridge)
1087{
1088 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1089 int ret;
1090
1091 if (!priv->enabled) {
1092 dev_err(priv->dev, "Bridge is not enabled\n");
1093 return;
1094 }
1095
1096 /* clear FrmStop and RstPtr */
1097 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
1098
1099 /* set PP_en */
1100 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
1101
1102 ret = tc358768_clear_error(priv);
1103 if (ret) {
1104 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
1105 tc358768_bridge_disable(bridge);
1106 tc358768_bridge_post_disable(bridge);
1107 }
1108}
1109
1110#define MAX_INPUT_SEL_FORMATS 1
1111
1112static u32 *
1113tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1114 struct drm_bridge_state *bridge_state,
1115 struct drm_crtc_state *crtc_state,
1116 struct drm_connector_state *conn_state,
1117 u32 output_fmt,
1118 unsigned int *num_input_fmts)
1119{
1120 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1121 u32 *input_fmts;
1122
1123 *num_input_fmts = 0;
1124
1125 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1126 GFP_KERNEL);
1127 if (!input_fmts)
1128 return NULL;
1129
1130 switch (priv->pd_lines) {
1131 case 16:
1132 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
1133 break;
1134 case 18:
1135 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
1136 break;
1137 default:
1138 case 24:
1139 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1140 break;
1141 }
1142
1143 *num_input_fmts = MAX_INPUT_SEL_FORMATS;
1144
1145 return input_fmts;
1146}
1147
1148static bool tc358768_mode_fixup(struct drm_bridge *bridge,
1149 const struct drm_display_mode *mode,
1150 struct drm_display_mode *adjusted_mode)
1151{
1152 /* Default to positive sync */
1153
1154 if (!(adjusted_mode->flags &
1155 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
1156 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
1157
1158 if (!(adjusted_mode->flags &
1159 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
1160 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;
1161
1162 return true;
1163}
1164
1165static const struct drm_bridge_funcs tc358768_bridge_funcs = {
1166 .attach = tc358768_bridge_attach,
1167 .mode_valid = tc358768_bridge_mode_valid,
1168 .mode_fixup = tc358768_mode_fixup,
1169 .pre_enable = tc358768_bridge_pre_enable,
1170 .enable = tc358768_bridge_enable,
1171 .disable = tc358768_bridge_disable,
1172 .post_disable = tc358768_bridge_post_disable,
1173
1174 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1175 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1176 .atomic_reset = drm_atomic_helper_bridge_reset,
1177 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
1178};
1179
1180static const struct drm_bridge_timings default_tc358768_timings = {
1181 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
1182 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
1183 | DRM_BUS_FLAG_DE_HIGH,
1184};
1185
1186static bool tc358768_is_reserved_reg(unsigned int reg)
1187{
1188 switch (reg) {
1189 case 0x114 ... 0x13f:
1190 case 0x200:
1191 case 0x20c:
1192 case 0x400 ... 0x408:
1193 case 0x41c ... 0x42f:
1194 return true;
1195 default:
1196 return false;
1197 }
1198}
1199
1200static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
1201{
1202 if (tc358768_is_reserved_reg(reg))
1203 return false;
1204
1205 switch (reg) {
1206 case TC358768_CHIPID:
1207 case TC358768_FIFOSTATUS:
1208 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
1209 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
1210 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
1211 return false;
1212 default:
1213 return true;
1214 }
1215}
1216
1217static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
1218{
1219 if (tc358768_is_reserved_reg(reg))
1220 return false;
1221
1222 switch (reg) {
1223 case TC358768_STARTCNTRL:
1224 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
1225 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
1226 case TC358768_DSI_START ... (TC358768_DSI_START + 2):
1227 case TC358768_DBG_DATA:
1228 return false;
1229 default:
1230 return true;
1231 }
1232}
1233
1234static const struct regmap_config tc358768_regmap_config = {
1235 .name = "tc358768",
1236 .reg_bits = 16,
1237 .val_bits = 16,
1238 .max_register = TC358768_DSI_HACT,
1239 .cache_type = REGCACHE_NONE,
1240 .writeable_reg = tc358768_writeable_reg,
1241 .readable_reg = tc358768_readable_reg,
1242 .reg_format_endian = REGMAP_ENDIAN_BIG,
1243 .val_format_endian = REGMAP_ENDIAN_BIG,
1244};
1245
1246static const struct i2c_device_id tc358768_i2c_ids[] = {
1247 { "tc358768", 0 },
1248 { "tc358778", 0 },
1249 { }
1250};
1251MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1252
1253static const struct of_device_id tc358768_of_ids[] = {
1254 { .compatible = "toshiba,tc358768", },
1255 { .compatible = "toshiba,tc358778", },
1256 { }
1257};
1258MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1259
1260static int tc358768_get_regulators(struct tc358768_priv *priv)
1261{
1262 int i, ret;
1263
1264 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1265 priv->supplies[i].supply = tc358768_supplies[i];
1266
1267 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1268 priv->supplies);
1269 if (ret < 0)
1270 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1271
1272 return ret;
1273}
1274
1275static int tc358768_i2c_probe(struct i2c_client *client)
1276{
1277 struct tc358768_priv *priv;
1278 struct device *dev = &client->dev;
1279 struct device_node *np = dev->of_node;
1280 int ret;
1281
1282 if (!np)
1283 return -ENODEV;
1284
1285 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1286 if (!priv)
1287 return -ENOMEM;
1288
1289 dev_set_drvdata(dev, priv);
1290 priv->dev = dev;
1291
1292 ret = tc358768_get_regulators(priv);
1293 if (ret)
1294 return ret;
1295
1296 priv->refclk = devm_clk_get(dev, "refclk");
1297 if (IS_ERR(priv->refclk))
1298 return PTR_ERR(priv->refclk);
1299
1300 /*
1301 * RESX is low active, to disable tc358768 initially (keep in reset)
1302 * the gpio line must be LOW. This is the ASSERTED state of
1303 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1304 */
1305 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1306 GPIOD_OUT_HIGH);
1307 if (IS_ERR(priv->reset_gpio))
1308 return PTR_ERR(priv->reset_gpio);
1309
1310 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1311 if (IS_ERR(priv->regmap)) {
1312 dev_err(dev, "Failed to init regmap\n");
1313 return PTR_ERR(priv->regmap);
1314 }
1315
1316 priv->dsi_host.dev = dev;
1317 priv->dsi_host.ops = &tc358768_dsi_host_ops;
1318
1319 priv->bridge.funcs = &tc358768_bridge_funcs;
1320 priv->bridge.timings = &default_tc358768_timings;
1321 priv->bridge.of_node = np;
1322
1323 i2c_set_clientdata(client, priv);
1324
1325 return mipi_dsi_host_register(&priv->dsi_host);
1326}
1327
1328static void tc358768_i2c_remove(struct i2c_client *client)
1329{
1330 struct tc358768_priv *priv = i2c_get_clientdata(client);
1331
1332 mipi_dsi_host_unregister(&priv->dsi_host);
1333}
1334
1335static struct i2c_driver tc358768_driver = {
1336 .driver = {
1337 .name = "tc358768",
1338 .of_match_table = tc358768_of_ids,
1339 },
1340 .id_table = tc358768_i2c_ids,
1341 .probe = tc358768_i2c_probe,
1342 .remove = tc358768_i2c_remove,
1343};
1344module_i2c_driver(tc358768_driver);
1345
1346MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1347MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1348MODULE_LICENSE("GPL v2");