Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
4 *
5 * The TC358767/TC358867/TC9595 can operate in multiple modes.
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
7 *
8 * Copyright (C) 2016 CogentEmbedded Inc
9 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
10 *
11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
12 *
13 * Copyright (C) 2016 Zodiac Inflight Innovations
14 *
15 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
16 *
17 * Copyright (C) 2012 Texas Instruments
18 * Author: Rob Clark <robdclark@gmail.com>
19 */
20
21#include <linux/bitfield.h>
22#include <linux/clk.h>
23#include <linux/device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/i2c.h>
26#include <linux/kernel.h>
27#include <linux/media-bus-format.h>
28#include <linux/module.h>
29#include <linux/regmap.h>
30#include <linux/slab.h>
31
32#include <drm/display/drm_dp_helper.h>
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_print.h>
40#include <drm/drm_probe_helper.h>
41
42/* Registers */
43
44/* DSI D-PHY Layer registers */
45#define D0W_DPHYCONTTX 0x0004
46#define CLW_DPHYCONTTX 0x0020
47#define D0W_DPHYCONTRX 0x0024
48#define D1W_DPHYCONTRX 0x0028
49#define D2W_DPHYCONTRX 0x002c
50#define D3W_DPHYCONTRX 0x0030
51#define COM_DPHYCONTRX 0x0038
52#define CLW_CNTRL 0x0040
53#define D0W_CNTRL 0x0044
54#define D1W_CNTRL 0x0048
55#define D2W_CNTRL 0x004c
56#define D3W_CNTRL 0x0050
57#define TESTMODE_CNTRL 0x0054
58
59/* PPI layer registers */
60#define PPI_STARTPPI 0x0104 /* START control bit */
61#define PPI_BUSYPPI 0x0108 /* PPI busy status */
62#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
63#define LPX_PERIOD 3
64#define PPI_LANEENABLE 0x0134
65#define PPI_TX_RX_TA 0x013c
66#define TTA_GET 0x40000
67#define TTA_SURE 6
68#define PPI_D0S_ATMR 0x0144
69#define PPI_D1S_ATMR 0x0148
70#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
71#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
72#define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */
73#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
74#define PPI_START_FUNCTION BIT(0)
75
76/* DSI layer registers */
77#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
78#define DSI_BUSYDSI 0x0208 /* DSI busy status */
79#define DSI_LANEENABLE 0x0210 /* Enables each lane */
80#define DSI_RX_START BIT(0)
81
82/* Lane enable PPI and DSI register bits */
83#define LANEENABLE_CLEN BIT(0)
84#define LANEENABLE_L0EN BIT(1)
85#define LANEENABLE_L1EN BIT(2)
86#define LANEENABLE_L2EN BIT(1)
87#define LANEENABLE_L3EN BIT(2)
88
89#define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */
90#define DSI_LANESTATUS1 0x0218 /* DSI lane status 1 */
91#define DSI_INTSTATUS 0x0220 /* Interrupt Status */
92#define DSI_INTMASK 0x0224 /* Interrupt Mask */
93#define DSI_INTCLR 0x0228 /* Interrupt Clear */
94#define DSI_LPTXTO 0x0230 /* LPTX Time Out Counter */
95
96/* DSI General Registers */
97#define DSIERRCNT 0x0300 /* DSI Error Count Register */
98
99/* DSI Application Layer Registers */
100#define APLCTRL 0x0400 /* Application layer Control Register */
101#define RDPKTLN 0x0404 /* DSI Read packet Length Register */
102
103/* Display Parallel Input Interface */
104#define DPIPXLFMT 0x0440
105#define VS_POL_ACTIVE_LOW (1 << 10)
106#define HS_POL_ACTIVE_LOW (1 << 9)
107#define DE_POL_ACTIVE_HIGH (0 << 8)
108#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
109#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
110#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
111#define DPI_BPP_RGB888 (0 << 0)
112#define DPI_BPP_RGB666 (1 << 0)
113#define DPI_BPP_RGB565 (2 << 0)
114
115/* Display Parallel Output Interface */
116#define POCTRL 0x0448
117#define POCTRL_S2P BIT(7)
118#define POCTRL_PCLK_POL BIT(3)
119#define POCTRL_VS_POL BIT(2)
120#define POCTRL_HS_POL BIT(1)
121#define POCTRL_DE_POL BIT(0)
122
123/* Video Path */
124#define VPCTRL0 0x0450
125#define VSDELAY GENMASK(31, 20)
126#define OPXLFMT_RGB666 (0 << 8)
127#define OPXLFMT_RGB888 (1 << 8)
128#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
129#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
130#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
131#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
132#define HTIM01 0x0454
133#define HPW GENMASK(8, 0)
134#define HBPR GENMASK(24, 16)
135#define HTIM02 0x0458
136#define HDISPR GENMASK(10, 0)
137#define HFPR GENMASK(24, 16)
138#define VTIM01 0x045c
139#define VSPR GENMASK(7, 0)
140#define VBPR GENMASK(23, 16)
141#define VTIM02 0x0460
142#define VFPR GENMASK(23, 16)
143#define VDISPR GENMASK(10, 0)
144#define VFUEN0 0x0464
145#define VFUEN BIT(0) /* Video Frame Timing Upload */
146
147/* System */
148#define TC_IDREG 0x0500 /* Chip ID and Revision ID */
149#define SYSBOOT 0x0504 /* System BootStrap Status Register */
150#define SYSSTAT 0x0508 /* System Status Register */
151#define SYSRSTENB 0x050c /* System Reset/Enable Register */
152#define ENBI2C (1 << 0)
153#define ENBLCD0 (1 << 2)
154#define ENBBM (1 << 3)
155#define ENBDSIRX (1 << 4)
156#define ENBREG (1 << 5)
157#define ENBHDCP (1 << 8)
158#define SYSCTRL 0x0510 /* System Control Register */
159#define DP0_AUDSRC_NO_INPUT (0 << 3)
160#define DP0_AUDSRC_I2S_RX (1 << 3)
161#define DP0_VIDSRC_NO_INPUT (0 << 0)
162#define DP0_VIDSRC_DSI_RX (1 << 0)
163#define DP0_VIDSRC_DPI_RX (2 << 0)
164#define DP0_VIDSRC_COLOR_BAR (3 << 0)
165#define GPIOM 0x0540 /* GPIO Mode Control Register */
166#define GPIOC 0x0544 /* GPIO Direction Control Register */
167#define GPIOO 0x0548 /* GPIO Output Register */
168#define GPIOI 0x054c /* GPIO Input Register */
169#define INTCTL_G 0x0560 /* General Interrupts Control Register */
170#define INTSTS_G 0x0564 /* General Interrupts Status Register */
171
172#define INT_SYSERR BIT(16)
173#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
174#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
175
176#define TEST_INT_C 0x0570 /* Test Interrupts Control Register */
177#define TEST_INT_S 0x0574 /* Test Interrupts Status Register */
178
179#define INT_GP0_LCNT 0x0584 /* Interrupt GPIO0 Low Count Value Register */
180#define INT_GP1_LCNT 0x0588 /* Interrupt GPIO1 Low Count Value Register */
181
182/* Control */
183#define DP0CTL 0x0600
184#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
185#define EF_EN BIT(5) /* Enable Enhanced Framing */
186#define VID_EN BIT(1) /* Video transmission enable */
187#define DP_EN BIT(0) /* Enable DPTX function */
188
189/* Clocks */
190#define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */
191#define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */
192#define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */
193#define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */
194#define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */
195#define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */
196
197/* Main Channel */
198#define DP0_SECSAMPLE 0x0640
199#define DP0_VIDSYNCDELAY 0x0644
200#define VID_SYNC_DLY GENMASK(15, 0)
201#define THRESH_DLY GENMASK(31, 16)
202
203#define DP0_TOTALVAL 0x0648
204#define H_TOTAL GENMASK(15, 0)
205#define V_TOTAL GENMASK(31, 16)
206#define DP0_STARTVAL 0x064c
207#define H_START GENMASK(15, 0)
208#define V_START GENMASK(31, 16)
209#define DP0_ACTIVEVAL 0x0650
210#define H_ACT GENMASK(15, 0)
211#define V_ACT GENMASK(31, 16)
212
213#define DP0_SYNCVAL 0x0654
214#define VS_WIDTH GENMASK(30, 16)
215#define HS_WIDTH GENMASK(14, 0)
216#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
217#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
218#define DP0_MISC 0x0658
219#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
220#define MAX_TU_SYMBOL GENMASK(28, 23)
221#define TU_SIZE GENMASK(21, 16)
222#define BPC_6 (0 << 5)
223#define BPC_8 (1 << 5)
224
225/* AUX channel */
226#define DP0_AUXCFG0 0x0660
227#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
228#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
229#define DP0_AUXCFG1 0x0664
230#define AUX_RX_FILTER_EN BIT(16)
231
232#define DP0_AUXADDR 0x0668
233#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
234#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
235#define DP0_AUXSTATUS 0x068c
236#define AUX_BYTES GENMASK(15, 8)
237#define AUX_STATUS GENMASK(7, 4)
238#define AUX_TIMEOUT BIT(1)
239#define AUX_BUSY BIT(0)
240#define DP0_AUXI2CADR 0x0698
241
242/* Link Training */
243#define DP0_SRCCTRL 0x06a0
244#define DP0_SRCCTRL_PRE1 GENMASK(29, 28)
245#define DP0_SRCCTRL_SWG1 GENMASK(25, 24)
246#define DP0_SRCCTRL_PRE0 GENMASK(21, 20)
247#define DP0_SRCCTRL_SWG0 GENMASK(17, 16)
248#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
249#define DP0_SRCCTRL_EN810B BIT(12)
250#define DP0_SRCCTRL_NOTP (0 << 8)
251#define DP0_SRCCTRL_TP1 (1 << 8)
252#define DP0_SRCCTRL_TP2 (2 << 8)
253#define DP0_SRCCTRL_LANESKEW BIT(7)
254#define DP0_SRCCTRL_SSCG BIT(3)
255#define DP0_SRCCTRL_LANES_1 (0 << 2)
256#define DP0_SRCCTRL_LANES_2 (1 << 2)
257#define DP0_SRCCTRL_BW27 (1 << 1)
258#define DP0_SRCCTRL_BW162 (0 << 1)
259#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
260#define DP0_LTSTAT 0x06d0
261#define LT_LOOPDONE BIT(13)
262#define LT_STATUS_MASK (0x1f << 8)
263#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
264#define LT_INTERLANE_ALIGN_DONE BIT(3)
265#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
266#define DP0_SNKLTCHGREQ 0x06d4
267#define DP0_LTLOOPCTRL 0x06d8
268#define DP0_SNKLTCTRL 0x06e4
269#define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */
270#define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */
271#define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */
272#define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */
273
274#define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */
275#define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */
276#define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */
277#define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */
278#define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */
279#define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */
280#define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */
281#define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */
282#define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */
283
284#define DP1_SRCCTRL 0x07a0 /* DP1 Control Register */
285#define DP1_SRCCTRL_PRE GENMASK(21, 20)
286#define DP1_SRCCTRL_SWG GENMASK(17, 16)
287
288/* PHY */
289#define DP_PHY_CTRL 0x0800
290#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
291#define BGREN BIT(25) /* AUX PHY BGR Enable */
292#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
293#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
294#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
295#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
296#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
297#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
298#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
299#define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */
300#define DP_PHY_CFG_RD 0x0814 /* DP PHY Configuration Test Read Register */
301#define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */
302#define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */
303
304/* I2S */
305#define I2SCFG 0x0880 /* I2S Audio Config 0 Register */
306#define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */
307#define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */
308#define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */
309#define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */
310#define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */
311#define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */
312#define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */
313#define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */
314#define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */
315#define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */
316#define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */
317#define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */
318
319/* PLL */
320#define DP0_PLLCTRL 0x0900
321#define DP1_PLLCTRL 0x0904 /* not defined in DS */
322#define PXL_PLLCTRL 0x0908
323#define PLLUPDATE BIT(2)
324#define PLLBYP BIT(1)
325#define PLLEN BIT(0)
326#define PXL_PLLPARAM 0x0914
327#define IN_SEL_REFCLK (0 << 14)
328#define SYS_PLLPARAM 0x0918
329#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
330#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
331#define REF_FREQ_26M (2 << 8) /* 26 MHz */
332#define REF_FREQ_13M (3 << 8) /* 13 MHz */
333#define SYSCLK_SEL_LSCLK (0 << 4)
334#define LSCLK_DIV_1 (0 << 0)
335#define LSCLK_DIV_2 (1 << 0)
336
337/* Test & Debug */
338#define TSTCTL 0x0a00
339#define COLOR_R GENMASK(31, 24)
340#define COLOR_G GENMASK(23, 16)
341#define COLOR_B GENMASK(15, 8)
342#define ENI2CFILTER BIT(4)
343#define COLOR_BAR_MODE GENMASK(1, 0)
344#define COLOR_BAR_MODE_BARS 2
345#define PLL_DBG 0x0a04
346
347static bool tc_test_pattern;
348module_param_named(test, tc_test_pattern, bool, 0644);
349
350struct tc_edp_link {
351 u8 dpcd[DP_RECEIVER_CAP_SIZE];
352 unsigned int rate;
353 u8 num_lanes;
354 u8 assr;
355 bool scrambler_dis;
356 bool spread;
357};
358
359struct tc_data {
360 struct device *dev;
361 struct regmap *regmap;
362 struct drm_dp_aux aux;
363
364 struct drm_bridge bridge;
365 struct drm_bridge *panel_bridge;
366 struct drm_connector connector;
367
368 struct mipi_dsi_device *dsi;
369
370 /* link settings */
371 struct tc_edp_link link;
372
373 /* current mode */
374 struct drm_display_mode mode;
375
376 u32 rev;
377 u8 assr;
378 u8 pre_emphasis[2];
379
380 struct gpio_desc *sd_gpio;
381 struct gpio_desc *reset_gpio;
382 struct clk *refclk;
383
384 /* do we have IRQ */
385 bool have_irq;
386
387 /* Input connector type, DSI and not DPI. */
388 bool input_connector_dsi;
389
390 /* HPD pin number (0 or 1) or -ENODEV */
391 int hpd_pin;
392};
393
394static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
395{
396 return container_of(a, struct tc_data, aux);
397}
398
399static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
400{
401 return container_of(b, struct tc_data, bridge);
402}
403
404static inline struct tc_data *connector_to_tc(struct drm_connector *c)
405{
406 return container_of(c, struct tc_data, connector);
407}
408
409static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
410 unsigned int cond_mask,
411 unsigned int cond_value,
412 unsigned long sleep_us, u64 timeout_us)
413{
414 unsigned int val;
415
416 return regmap_read_poll_timeout(tc->regmap, addr, val,
417 (val & cond_mask) == cond_value,
418 sleep_us, timeout_us);
419}
420
421static int tc_aux_wait_busy(struct tc_data *tc)
422{
423 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
424}
425
426static int tc_aux_write_data(struct tc_data *tc, const void *data,
427 size_t size)
428{
429 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
430 int ret, count = ALIGN(size, sizeof(u32));
431
432 memcpy(auxwdata, data, size);
433
434 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
435 if (ret)
436 return ret;
437
438 return size;
439}
440
441static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
442{
443 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
444 int ret, count = ALIGN(size, sizeof(u32));
445
446 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
447 if (ret)
448 return ret;
449
450 memcpy(data, auxrdata, size);
451
452 return size;
453}
454
455static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
456{
457 u32 auxcfg0 = msg->request;
458
459 if (size)
460 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
461 else
462 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
463
464 return auxcfg0;
465}
466
467static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
468 struct drm_dp_aux_msg *msg)
469{
470 struct tc_data *tc = aux_to_tc(aux);
471 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
472 u8 request = msg->request & ~DP_AUX_I2C_MOT;
473 u32 auxstatus;
474 int ret;
475
476 ret = tc_aux_wait_busy(tc);
477 if (ret)
478 return ret;
479
480 switch (request) {
481 case DP_AUX_NATIVE_READ:
482 case DP_AUX_I2C_READ:
483 break;
484 case DP_AUX_NATIVE_WRITE:
485 case DP_AUX_I2C_WRITE:
486 if (size) {
487 ret = tc_aux_write_data(tc, msg->buffer, size);
488 if (ret < 0)
489 return ret;
490 }
491 break;
492 default:
493 return -EINVAL;
494 }
495
496 /* Store address */
497 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
498 if (ret)
499 return ret;
500 /* Start transfer */
501 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
502 if (ret)
503 return ret;
504
505 ret = tc_aux_wait_busy(tc);
506 if (ret)
507 return ret;
508
509 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
510 if (ret)
511 return ret;
512
513 if (auxstatus & AUX_TIMEOUT)
514 return -ETIMEDOUT;
515 /*
516 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
517 * reports 1 byte transferred in its status. To deal we that
518 * we ignore aux_bytes field if we know that this was an
519 * address-only transfer
520 */
521 if (size)
522 size = FIELD_GET(AUX_BYTES, auxstatus);
523 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
524
525 switch (request) {
526 case DP_AUX_NATIVE_READ:
527 case DP_AUX_I2C_READ:
528 if (size)
529 return tc_aux_read_data(tc, msg->buffer, size);
530 break;
531 }
532
533 return size;
534}
535
536static const char * const training_pattern1_errors[] = {
537 "No errors",
538 "Aux write error",
539 "Aux read error",
540 "Max voltage reached error",
541 "Loop counter expired error",
542 "res", "res", "res"
543};
544
545static const char * const training_pattern2_errors[] = {
546 "No errors",
547 "Aux write error",
548 "Aux read error",
549 "Clock recovery failed error",
550 "Loop counter expired error",
551 "res", "res", "res"
552};
553
554static u32 tc_srcctrl(struct tc_data *tc)
555{
556 /*
557 * No training pattern, skew lane 1 data by two LSCLK cycles with
558 * respect to lane 0 data, AutoCorrect Mode = 0
559 */
560 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
561
562 if (tc->link.scrambler_dis)
563 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
564 if (tc->link.spread)
565 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
566 if (tc->link.num_lanes == 2)
567 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
568 if (tc->link.rate != 162000)
569 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
570 return reg;
571}
572
573static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
574{
575 int ret;
576
577 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
578 if (ret)
579 return ret;
580
581 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
582 usleep_range(15000, 20000);
583
584 return 0;
585}
586
587static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
588 int *out_best_pixelclock, u32 *out_pxl_pllparam)
589{
590 int i_pre, best_pre = 1;
591 int i_post, best_post = 1;
592 int div, best_div = 1;
593 int mul, best_mul = 1;
594 int delta, best_delta;
595 int ext_div[] = {1, 2, 3, 5, 7};
596 int clk_min, clk_max;
597 int best_pixelclock = 0;
598 int vco_hi = 0;
599 u32 pxl_pllparam;
600
601 /*
602 * refclk * mul / (ext_pre_div * pre_div) should be in range:
603 * - DPI ..... 0 to 100 MHz
604 * - (e)DP ... 150 to 650 MHz
605 */
606 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
607 clk_min = 0;
608 clk_max = 100000000;
609 } else {
610 clk_min = 150000000;
611 clk_max = 650000000;
612 }
613
614 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
615 refclk);
616 best_delta = pixelclock;
617 /* Loop over all possible ext_divs, skipping invalid configurations */
618 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
619 /*
620 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
621 * We don't allow any refclk > 200 MHz, only check lower bounds.
622 */
623 if (refclk / ext_div[i_pre] < 1000000)
624 continue;
625 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
626 for (div = 1; div <= 16; div++) {
627 u32 clk, iclk;
628 u64 tmp;
629
630 /* PCLK PLL input unit clock ... 6..40 MHz */
631 iclk = refclk / (div * ext_div[i_pre]);
632 if (iclk < 6000000 || iclk > 40000000)
633 continue;
634
635 tmp = pixelclock * ext_div[i_pre] *
636 ext_div[i_post] * div;
637 do_div(tmp, refclk);
638 mul = tmp;
639
640 /* Check limits */
641 if ((mul < 1) || (mul > 128))
642 continue;
643
644 clk = (refclk / ext_div[i_pre] / div) * mul;
645 if ((clk > clk_max) || (clk < clk_min))
646 continue;
647
648 clk = clk / ext_div[i_post];
649 delta = clk - pixelclock;
650
651 if (abs(delta) < abs(best_delta)) {
652 best_pre = i_pre;
653 best_post = i_post;
654 best_div = div;
655 best_mul = mul;
656 best_delta = delta;
657 best_pixelclock = clk;
658 }
659 }
660 }
661 }
662 if (best_pixelclock == 0) {
663 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
664 pixelclock);
665 return -EINVAL;
666 }
667
668 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta);
669 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
670 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
671
672 /* if VCO >= 300 MHz */
673 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
674 vco_hi = 1;
675 /* see DS */
676 if (best_div == 16)
677 best_div = 0;
678 if (best_mul == 128)
679 best_mul = 0;
680
681 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
682 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
683 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
684 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
685 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
686 pxl_pllparam |= best_mul; /* Multiplier for PLL */
687
688 if (out_best_pixelclock)
689 *out_best_pixelclock = best_pixelclock;
690
691 if (out_pxl_pllparam)
692 *out_pxl_pllparam = pxl_pllparam;
693
694 return 0;
695}
696
697static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
698{
699 u32 pxl_pllparam = 0;
700 int ret;
701
702 ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam);
703 if (ret)
704 return ret;
705
706 /* Power up PLL and switch to bypass */
707 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
708 if (ret)
709 return ret;
710
711 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
712 if (ret)
713 return ret;
714
715 /* Force PLL parameter update and disable bypass */
716 return tc_pllupdate(tc, PXL_PLLCTRL);
717}
718
719static int tc_pxl_pll_dis(struct tc_data *tc)
720{
721 /* Enable PLL bypass, power down PLL */
722 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
723}
724
725static int tc_stream_clock_calc(struct tc_data *tc)
726{
727 /*
728 * If the Stream clock and Link Symbol clock are
729 * asynchronous with each other, the value of M changes over
730 * time. This way of generating link clock and stream
731 * clock is called Asynchronous Clock mode. The value M
732 * must change while the value N stays constant. The
733 * value of N in this Asynchronous Clock mode must be set
734 * to 2^15 or 32,768.
735 *
736 * LSCLK = 1/10 of high speed link clock
737 *
738 * f_STRMCLK = M/N * f_LSCLK
739 * M/N = f_STRMCLK / f_LSCLK
740 *
741 */
742 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
743}
744
745static int tc_set_syspllparam(struct tc_data *tc)
746{
747 unsigned long rate;
748 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;
749
750 rate = clk_get_rate(tc->refclk);
751 switch (rate) {
752 case 38400000:
753 pllparam |= REF_FREQ_38M4;
754 break;
755 case 26000000:
756 pllparam |= REF_FREQ_26M;
757 break;
758 case 19200000:
759 pllparam |= REF_FREQ_19M2;
760 break;
761 case 13000000:
762 pllparam |= REF_FREQ_13M;
763 break;
764 default:
765 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
766 return -EINVAL;
767 }
768
769 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
770}
771
772static int tc_aux_link_setup(struct tc_data *tc)
773{
774 int ret;
775 u32 dp0_auxcfg1;
776
777 /* Setup DP-PHY / PLL */
778 ret = tc_set_syspllparam(tc);
779 if (ret)
780 goto err;
781
782 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
783 BGREN | PWR_SW_EN | PHY_A0_EN);
784 if (ret)
785 goto err;
786 /*
787 * Initially PLLs are in bypass. Force PLL parameter update,
788 * disable PLL bypass, enable PLL
789 */
790 ret = tc_pllupdate(tc, DP0_PLLCTRL);
791 if (ret)
792 goto err;
793
794 ret = tc_pllupdate(tc, DP1_PLLCTRL);
795 if (ret)
796 goto err;
797
798 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
799 if (ret == -ETIMEDOUT) {
800 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
801 return ret;
802 } else if (ret) {
803 goto err;
804 }
805
806 /* Setup AUX link */
807 dp0_auxcfg1 = AUX_RX_FILTER_EN;
808 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
809 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
810
811 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
812 if (ret)
813 goto err;
814
815 /* Register DP AUX channel */
816 tc->aux.name = "TC358767 AUX i2c adapter";
817 tc->aux.dev = tc->dev;
818 tc->aux.transfer = tc_aux_transfer;
819 drm_dp_aux_init(&tc->aux);
820
821 return 0;
822err:
823 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
824 return ret;
825}
826
827static int tc_get_display_props(struct tc_data *tc)
828{
829 u8 revision, num_lanes;
830 unsigned int rate;
831 int ret;
832 u8 reg;
833
834 /* Read DP Rx Link Capability */
835 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
836 DP_RECEIVER_CAP_SIZE);
837 if (ret < 0)
838 goto err_dpcd_read;
839
840 revision = tc->link.dpcd[DP_DPCD_REV];
841 rate = drm_dp_max_link_rate(tc->link.dpcd);
842 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
843
844 if (rate != 162000 && rate != 270000) {
845 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
846 rate = 270000;
847 }
848
849 tc->link.rate = rate;
850
851 if (num_lanes > 2) {
852 dev_dbg(tc->dev, "Falling to 2 lanes\n");
853 num_lanes = 2;
854 }
855
856 tc->link.num_lanes = num_lanes;
857
858 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
859 if (ret < 0)
860 goto err_dpcd_read;
861 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
862
863 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
864 if (ret < 0)
865 goto err_dpcd_read;
866
867 tc->link.scrambler_dis = false;
868 /* read assr */
869 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
870 if (ret < 0)
871 goto err_dpcd_read;
872 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
873
874 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
875 revision >> 4, revision & 0x0f,
876 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
877 tc->link.num_lanes,
878 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
879 "enhanced" : "default");
880 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
881 tc->link.spread ? "0.5%" : "0.0%",
882 tc->link.scrambler_dis ? "disabled" : "enabled");
883 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
884 tc->link.assr, tc->assr);
885
886 return 0;
887
888err_dpcd_read:
889 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
890 return ret;
891}
892
893static int tc_set_common_video_mode(struct tc_data *tc,
894 const struct drm_display_mode *mode)
895{
896 int left_margin = mode->htotal - mode->hsync_end;
897 int right_margin = mode->hsync_start - mode->hdisplay;
898 int hsync_len = mode->hsync_end - mode->hsync_start;
899 int upper_margin = mode->vtotal - mode->vsync_end;
900 int lower_margin = mode->vsync_start - mode->vdisplay;
901 int vsync_len = mode->vsync_end - mode->vsync_start;
902 int ret;
903
904 dev_dbg(tc->dev, "set mode %dx%d\n",
905 mode->hdisplay, mode->vdisplay);
906 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
907 left_margin, right_margin, hsync_len);
908 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
909 upper_margin, lower_margin, vsync_len);
910 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
911
912 /*
913 * LCD Ctl Frame Size
914 * datasheet is not clear of vsdelay in case of DPI
915 * assume we do not need any delay when DPI is a source of
916 * sync signals
917 */
918 ret = regmap_write(tc->regmap, VPCTRL0,
919 FIELD_PREP(VSDELAY, right_margin + 10) |
920 OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED);
921 if (ret)
922 return ret;
923
924 ret = regmap_write(tc->regmap, HTIM01,
925 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
926 FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
927 if (ret)
928 return ret;
929
930 ret = regmap_write(tc->regmap, HTIM02,
931 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
932 FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
933 if (ret)
934 return ret;
935
936 ret = regmap_write(tc->regmap, VTIM01,
937 FIELD_PREP(VBPR, upper_margin) |
938 FIELD_PREP(VSPR, vsync_len));
939 if (ret)
940 return ret;
941
942 ret = regmap_write(tc->regmap, VTIM02,
943 FIELD_PREP(VFPR, lower_margin) |
944 FIELD_PREP(VDISPR, mode->vdisplay));
945 if (ret)
946 return ret;
947
948 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
949 if (ret)
950 return ret;
951
952 /* Test pattern settings */
953 ret = regmap_write(tc->regmap, TSTCTL,
954 FIELD_PREP(COLOR_R, 120) |
955 FIELD_PREP(COLOR_G, 20) |
956 FIELD_PREP(COLOR_B, 99) |
957 ENI2CFILTER |
958 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
959
960 return ret;
961}
962
963static int tc_set_dpi_video_mode(struct tc_data *tc,
964 const struct drm_display_mode *mode)
965{
966 u32 value = POCTRL_S2P;
967
968 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
969 value |= POCTRL_HS_POL;
970
971 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
972 value |= POCTRL_VS_POL;
973
974 return regmap_write(tc->regmap, POCTRL, value);
975}
976
977static int tc_set_edp_video_mode(struct tc_data *tc,
978 const struct drm_display_mode *mode)
979{
980 int ret;
981 int vid_sync_dly;
982 int max_tu_symbol;
983
984 int left_margin = mode->htotal - mode->hsync_end;
985 int hsync_len = mode->hsync_end - mode->hsync_start;
986 int upper_margin = mode->vtotal - mode->vsync_end;
987 int vsync_len = mode->vsync_end - mode->vsync_start;
988 u32 dp0_syncval;
989 u32 bits_per_pixel = 24;
990 u32 in_bw, out_bw;
991 u32 dpipxlfmt;
992
993 /*
994 * Recommended maximum number of symbols transferred in a transfer unit:
995 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
996 * (output active video bandwidth in bytes))
997 * Must be less than tu_size.
998 */
999
1000 in_bw = mode->clock * bits_per_pixel / 8;
1001 out_bw = tc->link.num_lanes * tc->link.rate;
1002 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
1003
1004 /* DP Main Stream Attributes */
1005 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
1006 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
1007 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
1008 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
1009
1010 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
1011 FIELD_PREP(H_TOTAL, mode->htotal) |
1012 FIELD_PREP(V_TOTAL, mode->vtotal));
1013 if (ret)
1014 return ret;
1015
1016 ret = regmap_write(tc->regmap, DP0_STARTVAL,
1017 FIELD_PREP(H_START, left_margin + hsync_len) |
1018 FIELD_PREP(V_START, upper_margin + vsync_len));
1019 if (ret)
1020 return ret;
1021
1022 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
1023 FIELD_PREP(V_ACT, mode->vdisplay) |
1024 FIELD_PREP(H_ACT, mode->hdisplay));
1025 if (ret)
1026 return ret;
1027
1028 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
1029 FIELD_PREP(HS_WIDTH, hsync_len);
1030
1031 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1032 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
1033
1034 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1035 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
1036
1037 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
1038 if (ret)
1039 return ret;
1040
1041 dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888;
1042
1043 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1044 dpipxlfmt |= VS_POL_ACTIVE_LOW;
1045
1046 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1047 dpipxlfmt |= HS_POL_ACTIVE_LOW;
1048
1049 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
1050 if (ret)
1051 return ret;
1052
1053 ret = regmap_write(tc->regmap, DP0_MISC,
1054 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
1055 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
1056 BPC_8);
1057 return ret;
1058}
1059
1060static int tc_wait_link_training(struct tc_data *tc)
1061{
1062 u32 value;
1063 int ret;
1064
1065 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
1066 LT_LOOPDONE, 500, 100000);
1067 if (ret) {
1068 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
1069 return ret;
1070 }
1071
1072 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
1073 if (ret)
1074 return ret;
1075
1076 return (value >> 8) & 0x7;
1077}
1078
1079static int tc_main_link_enable(struct tc_data *tc)
1080{
1081 struct drm_dp_aux *aux = &tc->aux;
1082 struct device *dev = tc->dev;
1083 u32 dp_phy_ctrl;
1084 u32 value;
1085 int ret;
1086 u8 tmp[DP_LINK_STATUS_SIZE];
1087
1088 dev_dbg(tc->dev, "link enable\n");
1089
1090 ret = regmap_read(tc->regmap, DP0CTL, &value);
1091 if (ret)
1092 return ret;
1093
1094 if (WARN_ON(value & DP_EN)) {
1095 ret = regmap_write(tc->regmap, DP0CTL, 0);
1096 if (ret)
1097 return ret;
1098 }
1099
1100 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1101 tc_srcctrl(tc) |
1102 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1103 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1104 if (ret)
1105 return ret;
1106 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
1107 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1108 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1109 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) |
1110 FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1]));
1111 if (ret)
1112 return ret;
1113
1114 ret = tc_set_syspllparam(tc);
1115 if (ret)
1116 return ret;
1117
1118 /* Setup Main Link */
1119 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
1120 if (tc->link.num_lanes == 2)
1121 dp_phy_ctrl |= PHY_2LANE;
1122
1123 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1124 if (ret)
1125 return ret;
1126
1127 /* PLL setup */
1128 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1129 if (ret)
1130 return ret;
1131
1132 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1133 if (ret)
1134 return ret;
1135
1136 /* Reset/Enable Main Links */
1137 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
1138 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1139 usleep_range(100, 200);
1140 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
1141 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1142
1143 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
1144 if (ret) {
1145 dev_err(dev, "timeout waiting for phy become ready");
1146 return ret;
1147 }
1148
1149 /* Set misc: 8 bits per color */
1150 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1151 if (ret)
1152 return ret;
1153
1154 /*
1155 * ASSR mode
1156 * on TC358767 side ASSR configured through strap pin
1157 * seems there is no way to change this setting from SW
1158 *
1159 * check is tc configured for same mode
1160 */
1161 if (tc->assr != tc->link.assr) {
1162 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
1163 tc->assr);
1164 /* try to set ASSR on display side */
1165 tmp[0] = tc->assr;
1166 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
1167 if (ret < 0)
1168 goto err_dpcd_read;
1169 /* read back */
1170 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
1171 if (ret < 0)
1172 goto err_dpcd_read;
1173
1174 if (tmp[0] != tc->assr) {
1175 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
1176 tc->assr);
1177 /* trying with disabled scrambler */
1178 tc->link.scrambler_dis = true;
1179 }
1180 }
1181
1182 /* Setup Link & DPRx Config for Training */
1183 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1184 tmp[1] = tc->link.num_lanes;
1185
1186 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1187 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1188
1189 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1190 if (ret < 0)
1191 goto err_dpcd_write;
1192
1193 /* DOWNSPREAD_CTRL */
1194 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1195 /* MAIN_LINK_CHANNEL_CODING_SET */
1196 tmp[1] = DP_SET_ANSI_8B10B;
1197 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1198 if (ret < 0)
1199 goto err_dpcd_write;
1200
1201 /* Reset voltage-swing & pre-emphasis */
1202 tmp[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1203 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]);
1204 tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1205 FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]);
1206 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1207 if (ret < 0)
1208 goto err_dpcd_write;
1209
1210 /* Clock-Recovery */
1211
1212 /* Set DPCD 0x102 for Training Pattern 1 */
1213 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1214 DP_LINK_SCRAMBLING_DISABLE |
1215 DP_TRAINING_PATTERN_1);
1216 if (ret)
1217 return ret;
1218
1219 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1220 (15 << 28) | /* Defer Iteration Count */
1221 (15 << 24) | /* Loop Iteration Count */
1222 (0xd << 0)); /* Loop Timer Delay */
1223 if (ret)
1224 return ret;
1225
1226 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1227 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1228 DP0_SRCCTRL_AUTOCORRECT |
1229 DP0_SRCCTRL_TP1 |
1230 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1231 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1232 if (ret)
1233 return ret;
1234
1235 /* Enable DP0 to start Link Training */
1236 ret = regmap_write(tc->regmap, DP0CTL,
1237 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1238 EF_EN : 0) | DP_EN);
1239 if (ret)
1240 return ret;
1241
1242 /* wait */
1243
1244 ret = tc_wait_link_training(tc);
1245 if (ret < 0)
1246 return ret;
1247
1248 if (ret) {
1249 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1250 training_pattern1_errors[ret]);
1251 return -ENODEV;
1252 }
1253
1254 /* Channel Equalization */
1255
1256 /* Set DPCD 0x102 for Training Pattern 2 */
1257 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1258 DP_LINK_SCRAMBLING_DISABLE |
1259 DP_TRAINING_PATTERN_2);
1260 if (ret)
1261 return ret;
1262
1263 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1264 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1265 DP0_SRCCTRL_AUTOCORRECT |
1266 DP0_SRCCTRL_TP2 |
1267 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1268 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1269 if (ret)
1270 return ret;
1271
1272 /* wait */
1273 ret = tc_wait_link_training(tc);
1274 if (ret < 0)
1275 return ret;
1276
1277 if (ret) {
1278 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1279 training_pattern2_errors[ret]);
1280 return -ENODEV;
1281 }
1282
1283 /*
1284 * Toshiba's documentation suggests to first clear DPCD 0x102, then
1285 * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1286 * that the link sometimes drops if those steps are done in that order,
1287 * but if the steps are done in reverse order, the link stays up.
1288 *
1289 * So we do the steps differently than documented here.
1290 */
1291
1292 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1293 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1294 DP0_SRCCTRL_AUTOCORRECT |
1295 FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1296 FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1297 if (ret)
1298 return ret;
1299
1300 /* Clear DPCD 0x102 */
1301 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1302 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1303 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1304 if (ret < 0)
1305 goto err_dpcd_write;
1306
1307 /* Check link status */
1308 ret = drm_dp_dpcd_read_link_status(aux, tmp);
1309 if (ret < 0)
1310 goto err_dpcd_read;
1311
1312 ret = 0;
1313
1314 value = tmp[0] & DP_CHANNEL_EQ_BITS;
1315
1316 if (value != DP_CHANNEL_EQ_BITS) {
1317 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1318 ret = -ENODEV;
1319 }
1320
1321 if (tc->link.num_lanes == 2) {
1322 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1323
1324 if (value != DP_CHANNEL_EQ_BITS) {
1325 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1326 ret = -ENODEV;
1327 }
1328
1329 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1330 dev_err(tc->dev, "Interlane align failed\n");
1331 ret = -ENODEV;
1332 }
1333 }
1334
1335 if (ret) {
1336 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1337 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1338 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1339 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1340 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1341 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1342 return ret;
1343 }
1344
1345 return 0;
1346err_dpcd_read:
1347 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1348 return ret;
1349err_dpcd_write:
1350 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1351 return ret;
1352}
1353
1354static int tc_main_link_disable(struct tc_data *tc)
1355{
1356 int ret;
1357
1358 dev_dbg(tc->dev, "link disable\n");
1359
1360 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1361 if (ret)
1362 return ret;
1363
1364 ret = regmap_write(tc->regmap, DP0CTL, 0);
1365 if (ret)
1366 return ret;
1367
1368 return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1369 PHY_M0_RST | PHY_M1_RST | PHY_M0_EN,
1370 PHY_M0_RST | PHY_M1_RST);
1371}
1372
1373static int tc_dsi_rx_enable(struct tc_data *tc)
1374{
1375 u32 value;
1376 int ret;
1377
1378 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
1379 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
1380 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
1381 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
1382 regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1383 regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1384 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1385 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1386
1387 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1388 LANEENABLE_CLEN;
1389 regmap_write(tc->regmap, PPI_LANEENABLE, value);
1390 regmap_write(tc->regmap, DSI_LANEENABLE, value);
1391
1392 /* Set input interface */
1393 value = DP0_AUDSRC_NO_INPUT;
1394 if (tc_test_pattern)
1395 value |= DP0_VIDSRC_COLOR_BAR;
1396 else
1397 value |= DP0_VIDSRC_DSI_RX;
1398 ret = regmap_write(tc->regmap, SYSCTRL, value);
1399 if (ret)
1400 return ret;
1401
1402 usleep_range(120, 150);
1403
1404 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1405 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1406
1407 return 0;
1408}
1409
1410static int tc_dpi_rx_enable(struct tc_data *tc)
1411{
1412 u32 value;
1413
1414 /* Set input interface */
1415 value = DP0_AUDSRC_NO_INPUT;
1416 if (tc_test_pattern)
1417 value |= DP0_VIDSRC_COLOR_BAR;
1418 else
1419 value |= DP0_VIDSRC_DPI_RX;
1420 return regmap_write(tc->regmap, SYSCTRL, value);
1421}
1422
1423static int tc_dpi_stream_enable(struct tc_data *tc)
1424{
1425 int ret;
1426
1427 dev_dbg(tc->dev, "enable video stream\n");
1428
1429 /* Setup PLL */
1430 ret = tc_set_syspllparam(tc);
1431 if (ret)
1432 return ret;
1433
1434 /*
1435 * Initially PLLs are in bypass. Force PLL parameter update,
1436 * disable PLL bypass, enable PLL
1437 */
1438 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1439 if (ret)
1440 return ret;
1441
1442 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1443 if (ret)
1444 return ret;
1445
1446 /* Pixel PLL must always be enabled for DPI mode */
1447 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1448 1000 * tc->mode.clock);
1449 if (ret)
1450 return ret;
1451
1452 ret = tc_set_common_video_mode(tc, &tc->mode);
1453 if (ret)
1454 return ret;
1455
1456 ret = tc_set_dpi_video_mode(tc, &tc->mode);
1457 if (ret)
1458 return ret;
1459
1460 return tc_dsi_rx_enable(tc);
1461}
1462
1463static int tc_dpi_stream_disable(struct tc_data *tc)
1464{
1465 dev_dbg(tc->dev, "disable video stream\n");
1466
1467 tc_pxl_pll_dis(tc);
1468
1469 return 0;
1470}
1471
1472static int tc_edp_stream_enable(struct tc_data *tc)
1473{
1474 int ret;
1475 u32 value;
1476
1477 dev_dbg(tc->dev, "enable video stream\n");
1478
1479 /*
1480 * Pixel PLL must be enabled for DSI input mode and test pattern.
1481 *
1482 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1483 * "Clock Mode Selection and Clock Sources", either Pixel PLL
1484 * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in
1485 * case valid Pixel Clock are supplied to the chip DPI input.
1486 * In case built-in test pattern is desired OR DSI input mode
1487 * is used, DPI_PCLK is not available and thus Pixel PLL must
1488 * be used instead.
1489 */
1490 if (tc->input_connector_dsi || tc_test_pattern) {
1491 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1492 1000 * tc->mode.clock);
1493 if (ret)
1494 return ret;
1495 }
1496
1497 ret = tc_set_common_video_mode(tc, &tc->mode);
1498 if (ret)
1499 return ret;
1500
1501 ret = tc_set_edp_video_mode(tc, &tc->mode);
1502 if (ret)
1503 return ret;
1504
1505 /* Set M/N */
1506 ret = tc_stream_clock_calc(tc);
1507 if (ret)
1508 return ret;
1509
1510 value = VID_MN_GEN | DP_EN;
1511 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1512 value |= EF_EN;
1513 ret = regmap_write(tc->regmap, DP0CTL, value);
1514 if (ret)
1515 return ret;
1516 /*
1517 * VID_EN assertion should be delayed by at least N * LSCLK
1518 * cycles from the time VID_MN_GEN is enabled in order to
1519 * generate stable values for VID_M. LSCLK is 270 MHz or
1520 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1521 * so a delay of at least 203 us should suffice.
1522 */
1523 usleep_range(500, 1000);
1524 value |= VID_EN;
1525 ret = regmap_write(tc->regmap, DP0CTL, value);
1526 if (ret)
1527 return ret;
1528
1529 /* Set input interface */
1530 if (tc->input_connector_dsi)
1531 return tc_dsi_rx_enable(tc);
1532 else
1533 return tc_dpi_rx_enable(tc);
1534}
1535
1536static int tc_edp_stream_disable(struct tc_data *tc)
1537{
1538 int ret;
1539
1540 dev_dbg(tc->dev, "disable video stream\n");
1541
1542 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1543 if (ret)
1544 return ret;
1545
1546 tc_pxl_pll_dis(tc);
1547
1548 return 0;
1549}
1550
1551static void
1552tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge,
1553 struct drm_bridge_state *old_bridge_state)
1554
1555{
1556 struct tc_data *tc = bridge_to_tc(bridge);
1557 int ret;
1558
1559 ret = tc_dpi_stream_enable(tc);
1560 if (ret < 0) {
1561 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1562 tc_main_link_disable(tc);
1563 return;
1564 }
1565}
1566
1567static void
1568tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge,
1569 struct drm_bridge_state *old_bridge_state)
1570{
1571 struct tc_data *tc = bridge_to_tc(bridge);
1572 int ret;
1573
1574 ret = tc_dpi_stream_disable(tc);
1575 if (ret < 0)
1576 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1577}
1578
1579static void
1580tc_edp_bridge_atomic_enable(struct drm_bridge *bridge,
1581 struct drm_bridge_state *old_bridge_state)
1582{
1583 struct tc_data *tc = bridge_to_tc(bridge);
1584 int ret;
1585
1586 ret = tc_get_display_props(tc);
1587 if (ret < 0) {
1588 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1589 return;
1590 }
1591
1592 ret = tc_main_link_enable(tc);
1593 if (ret < 0) {
1594 dev_err(tc->dev, "main link enable error: %d\n", ret);
1595 return;
1596 }
1597
1598 ret = tc_edp_stream_enable(tc);
1599 if (ret < 0) {
1600 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1601 tc_main_link_disable(tc);
1602 return;
1603 }
1604}
1605
1606static void
1607tc_edp_bridge_atomic_disable(struct drm_bridge *bridge,
1608 struct drm_bridge_state *old_bridge_state)
1609{
1610 struct tc_data *tc = bridge_to_tc(bridge);
1611 int ret;
1612
1613 ret = tc_edp_stream_disable(tc);
1614 if (ret < 0)
1615 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1616
1617 ret = tc_main_link_disable(tc);
1618 if (ret < 0)
1619 dev_err(tc->dev, "main link disable error: %d\n", ret);
1620}
1621
1622static int tc_dpi_atomic_check(struct drm_bridge *bridge,
1623 struct drm_bridge_state *bridge_state,
1624 struct drm_crtc_state *crtc_state,
1625 struct drm_connector_state *conn_state)
1626{
1627 struct tc_data *tc = bridge_to_tc(bridge);
1628 int adjusted_clock = 0;
1629 int ret;
1630
1631 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
1632 crtc_state->mode.clock * 1000,
1633 &adjusted_clock, NULL);
1634 if (ret)
1635 return ret;
1636
1637 crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1638
1639 /* DSI->DPI interface clock limitation: upto 100 MHz */
1640 if (crtc_state->adjusted_mode.clock > 100000)
1641 return -EINVAL;
1642
1643 return 0;
1644}
1645
1646static int tc_edp_atomic_check(struct drm_bridge *bridge,
1647 struct drm_bridge_state *bridge_state,
1648 struct drm_crtc_state *crtc_state,
1649 struct drm_connector_state *conn_state)
1650{
1651 struct tc_data *tc = bridge_to_tc(bridge);
1652 int adjusted_clock = 0;
1653 int ret;
1654
1655 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
1656 crtc_state->mode.clock * 1000,
1657 &adjusted_clock, NULL);
1658 if (ret)
1659 return ret;
1660
1661 crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1662
1663 /* DPI->(e)DP interface clock limitation: upto 154 MHz */
1664 if (crtc_state->adjusted_mode.clock > 154000)
1665 return -EINVAL;
1666
1667 return 0;
1668}
1669
1670static enum drm_mode_status
1671tc_dpi_mode_valid(struct drm_bridge *bridge,
1672 const struct drm_display_info *info,
1673 const struct drm_display_mode *mode)
1674{
1675 /* DPI interface clock limitation: upto 100 MHz */
1676 if (mode->clock > 100000)
1677 return MODE_CLOCK_HIGH;
1678
1679 return MODE_OK;
1680}
1681
1682static enum drm_mode_status
1683tc_edp_mode_valid(struct drm_bridge *bridge,
1684 const struct drm_display_info *info,
1685 const struct drm_display_mode *mode)
1686{
1687 struct tc_data *tc = bridge_to_tc(bridge);
1688 u32 req, avail;
1689 u32 bits_per_pixel = 24;
1690
1691 /* DPI->(e)DP interface clock limitation: up to 154 MHz */
1692 if (mode->clock > 154000)
1693 return MODE_CLOCK_HIGH;
1694
1695 req = mode->clock * bits_per_pixel / 8;
1696 avail = tc->link.num_lanes * tc->link.rate;
1697
1698 if (req > avail)
1699 return MODE_BAD;
1700
1701 return MODE_OK;
1702}
1703
1704static void tc_bridge_mode_set(struct drm_bridge *bridge,
1705 const struct drm_display_mode *mode,
1706 const struct drm_display_mode *adj)
1707{
1708 struct tc_data *tc = bridge_to_tc(bridge);
1709
1710 drm_mode_copy(&tc->mode, adj);
1711}
1712
1713static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge,
1714 struct drm_connector *connector)
1715{
1716 struct tc_data *tc = bridge_to_tc(bridge);
1717 int ret;
1718
1719 ret = tc_get_display_props(tc);
1720 if (ret < 0) {
1721 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1722 return 0;
1723 }
1724
1725 return drm_edid_read_ddc(connector, &tc->aux.ddc);
1726}
1727
1728static int tc_connector_get_modes(struct drm_connector *connector)
1729{
1730 struct tc_data *tc = connector_to_tc(connector);
1731 int num_modes;
1732 const struct drm_edid *drm_edid;
1733 int ret;
1734
1735 ret = tc_get_display_props(tc);
1736 if (ret < 0) {
1737 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1738 return 0;
1739 }
1740
1741 if (tc->panel_bridge) {
1742 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1743 if (num_modes > 0)
1744 return num_modes;
1745 }
1746
1747 drm_edid = tc_edid_read(&tc->bridge, connector);
1748 drm_edid_connector_update(connector, drm_edid);
1749 num_modes = drm_edid_connector_add_modes(connector);
1750 drm_edid_free(drm_edid);
1751
1752 return num_modes;
1753}
1754
1755static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1756 .get_modes = tc_connector_get_modes,
1757};
1758
1759static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
1760{
1761 struct tc_data *tc = bridge_to_tc(bridge);
1762 bool conn;
1763 u32 val;
1764 int ret;
1765
1766 ret = regmap_read(tc->regmap, GPIOI, &val);
1767 if (ret)
1768 return connector_status_unknown;
1769
1770 conn = val & BIT(tc->hpd_pin);
1771
1772 if (conn)
1773 return connector_status_connected;
1774 else
1775 return connector_status_disconnected;
1776}
1777
1778static enum drm_connector_status
1779tc_connector_detect(struct drm_connector *connector, bool force)
1780{
1781 struct tc_data *tc = connector_to_tc(connector);
1782
1783 if (tc->hpd_pin >= 0)
1784 return tc_bridge_detect(&tc->bridge);
1785
1786 if (tc->panel_bridge)
1787 return connector_status_connected;
1788 else
1789 return connector_status_unknown;
1790}
1791
1792static const struct drm_connector_funcs tc_connector_funcs = {
1793 .detect = tc_connector_detect,
1794 .fill_modes = drm_helper_probe_single_connector_modes,
1795 .destroy = drm_connector_cleanup,
1796 .reset = drm_atomic_helper_connector_reset,
1797 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1798 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1799};
1800
1801static int tc_dpi_bridge_attach(struct drm_bridge *bridge,
1802 enum drm_bridge_attach_flags flags)
1803{
1804 struct tc_data *tc = bridge_to_tc(bridge);
1805
1806 if (!tc->panel_bridge)
1807 return 0;
1808
1809 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1810 &tc->bridge, flags);
1811}
1812
1813static int tc_edp_bridge_attach(struct drm_bridge *bridge,
1814 enum drm_bridge_attach_flags flags)
1815{
1816 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1817 struct tc_data *tc = bridge_to_tc(bridge);
1818 struct drm_device *drm = bridge->dev;
1819 int ret;
1820
1821 if (tc->panel_bridge) {
1822 /* If a connector is required then this driver shall create it */
1823 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1824 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1825 if (ret)
1826 return ret;
1827 }
1828
1829 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1830 return 0;
1831
1832 tc->aux.drm_dev = drm;
1833 ret = drm_dp_aux_register(&tc->aux);
1834 if (ret < 0)
1835 return ret;
1836
1837 /* Create DP/eDP connector */
1838 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1839 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1840 if (ret)
1841 goto aux_unregister;
1842
1843 /* Don't poll if don't have HPD connected */
1844 if (tc->hpd_pin >= 0) {
1845 if (tc->have_irq)
1846 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1847 else
1848 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1849 DRM_CONNECTOR_POLL_DISCONNECT;
1850 }
1851
1852 drm_display_info_set_bus_formats(&tc->connector.display_info,
1853 &bus_format, 1);
1854 tc->connector.display_info.bus_flags =
1855 DRM_BUS_FLAG_DE_HIGH |
1856 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1857 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1858 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1859
1860 return 0;
1861aux_unregister:
1862 drm_dp_aux_unregister(&tc->aux);
1863 return ret;
1864}
1865
1866static void tc_edp_bridge_detach(struct drm_bridge *bridge)
1867{
1868 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux);
1869}
1870
1871#define MAX_INPUT_SEL_FORMATS 1
1872#define MAX_OUTPUT_SEL_FORMATS 1
1873
1874static u32 *
1875tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1876 struct drm_bridge_state *bridge_state,
1877 struct drm_crtc_state *crtc_state,
1878 struct drm_connector_state *conn_state,
1879 u32 output_fmt,
1880 unsigned int *num_input_fmts)
1881{
1882 u32 *input_fmts;
1883
1884 *num_input_fmts = 0;
1885
1886 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1887 GFP_KERNEL);
1888 if (!input_fmts)
1889 return NULL;
1890
1891 /* This is the DSI-end bus format */
1892 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1893 *num_input_fmts = 1;
1894
1895 return input_fmts;
1896}
1897
1898static u32 *
1899tc_edp_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
1900 struct drm_bridge_state *bridge_state,
1901 struct drm_crtc_state *crtc_state,
1902 struct drm_connector_state *conn_state,
1903 unsigned int *num_output_fmts)
1904{
1905 u32 *output_fmts;
1906
1907 *num_output_fmts = 0;
1908
1909 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
1910 GFP_KERNEL);
1911 if (!output_fmts)
1912 return NULL;
1913
1914 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1915 *num_output_fmts = 1;
1916
1917 return output_fmts;
1918}
1919
1920static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
1921 .attach = tc_dpi_bridge_attach,
1922 .mode_valid = tc_dpi_mode_valid,
1923 .mode_set = tc_bridge_mode_set,
1924 .atomic_check = tc_dpi_atomic_check,
1925 .atomic_enable = tc_dpi_bridge_atomic_enable,
1926 .atomic_disable = tc_dpi_bridge_atomic_disable,
1927 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1928 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1929 .atomic_reset = drm_atomic_helper_bridge_reset,
1930 .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts,
1931};
1932
1933static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
1934 .attach = tc_edp_bridge_attach,
1935 .detach = tc_edp_bridge_detach,
1936 .mode_valid = tc_edp_mode_valid,
1937 .mode_set = tc_bridge_mode_set,
1938 .atomic_check = tc_edp_atomic_check,
1939 .atomic_enable = tc_edp_bridge_atomic_enable,
1940 .atomic_disable = tc_edp_bridge_atomic_disable,
1941 .detect = tc_bridge_detect,
1942 .edid_read = tc_edid_read,
1943 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1944 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1945 .atomic_reset = drm_atomic_helper_bridge_reset,
1946 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
1947 .atomic_get_output_bus_fmts = tc_edp_atomic_get_output_bus_fmts,
1948};
1949
1950static bool tc_readable_reg(struct device *dev, unsigned int reg)
1951{
1952 switch (reg) {
1953 /* DSI D-PHY Layer */
1954 case 0x004:
1955 case 0x020:
1956 case 0x024:
1957 case 0x028:
1958 case 0x02c:
1959 case 0x030:
1960 case 0x038:
1961 case 0x040:
1962 case 0x044:
1963 case 0x048:
1964 case 0x04c:
1965 case 0x050:
1966 case 0x054:
1967 /* DSI PPI Layer */
1968 case PPI_STARTPPI:
1969 case 0x108:
1970 case 0x110:
1971 case PPI_LPTXTIMECNT:
1972 case PPI_LANEENABLE:
1973 case PPI_TX_RX_TA:
1974 case 0x140:
1975 case PPI_D0S_ATMR:
1976 case PPI_D1S_ATMR:
1977 case 0x14c:
1978 case 0x150:
1979 case PPI_D0S_CLRSIPOCOUNT:
1980 case PPI_D1S_CLRSIPOCOUNT:
1981 case PPI_D2S_CLRSIPOCOUNT:
1982 case PPI_D3S_CLRSIPOCOUNT:
1983 case 0x180:
1984 case 0x184:
1985 case 0x188:
1986 case 0x18c:
1987 case 0x190:
1988 case 0x1a0:
1989 case 0x1a4:
1990 case 0x1a8:
1991 case 0x1ac:
1992 case 0x1b0:
1993 case 0x1c0:
1994 case 0x1c4:
1995 case 0x1c8:
1996 case 0x1cc:
1997 case 0x1d0:
1998 case 0x1e0:
1999 case 0x1e4:
2000 case 0x1f0:
2001 case 0x1f4:
2002 /* DSI Protocol Layer */
2003 case DSI_STARTDSI:
2004 case DSI_BUSYDSI:
2005 case DSI_LANEENABLE:
2006 case DSI_LANESTATUS0:
2007 case DSI_LANESTATUS1:
2008 case DSI_INTSTATUS:
2009 case 0x224:
2010 case 0x228:
2011 case 0x230:
2012 /* DSI General */
2013 case DSIERRCNT:
2014 /* DSI Application Layer */
2015 case 0x400:
2016 case 0x404:
2017 /* DPI */
2018 case DPIPXLFMT:
2019 /* Parallel Output */
2020 case POCTRL:
2021 /* Video Path0 Configuration */
2022 case VPCTRL0:
2023 case HTIM01:
2024 case HTIM02:
2025 case VTIM01:
2026 case VTIM02:
2027 case VFUEN0:
2028 /* System */
2029 case TC_IDREG:
2030 case 0x504:
2031 case SYSSTAT:
2032 case SYSRSTENB:
2033 case SYSCTRL:
2034 /* I2C */
2035 case 0x520:
2036 /* GPIO */
2037 case GPIOM:
2038 case GPIOC:
2039 case GPIOO:
2040 case GPIOI:
2041 /* Interrupt */
2042 case INTCTL_G:
2043 case INTSTS_G:
2044 case 0x570:
2045 case 0x574:
2046 case INT_GP0_LCNT:
2047 case INT_GP1_LCNT:
2048 /* DisplayPort Control */
2049 case DP0CTL:
2050 /* DisplayPort Clock */
2051 case DP0_VIDMNGEN0:
2052 case DP0_VIDMNGEN1:
2053 case DP0_VMNGENSTATUS:
2054 case 0x628:
2055 case 0x62c:
2056 case 0x630:
2057 /* DisplayPort Main Channel */
2058 case DP0_SECSAMPLE:
2059 case DP0_VIDSYNCDELAY:
2060 case DP0_TOTALVAL:
2061 case DP0_STARTVAL:
2062 case DP0_ACTIVEVAL:
2063 case DP0_SYNCVAL:
2064 case DP0_MISC:
2065 /* DisplayPort Aux Channel */
2066 case DP0_AUXCFG0:
2067 case DP0_AUXCFG1:
2068 case DP0_AUXADDR:
2069 case 0x66c:
2070 case 0x670:
2071 case 0x674:
2072 case 0x678:
2073 case 0x67c:
2074 case 0x680:
2075 case 0x684:
2076 case 0x688:
2077 case DP0_AUXSTATUS:
2078 case DP0_AUXI2CADR:
2079 /* DisplayPort Link Training */
2080 case DP0_SRCCTRL:
2081 case DP0_LTSTAT:
2082 case DP0_SNKLTCHGREQ:
2083 case DP0_LTLOOPCTRL:
2084 case DP0_SNKLTCTRL:
2085 case 0x6e8:
2086 case 0x6ec:
2087 case 0x6f0:
2088 case 0x6f4:
2089 /* DisplayPort Audio */
2090 case 0x700:
2091 case 0x704:
2092 case 0x708:
2093 case 0x70c:
2094 case 0x710:
2095 case 0x714:
2096 case 0x718:
2097 case 0x71c:
2098 case 0x720:
2099 /* DisplayPort Source Control */
2100 case DP1_SRCCTRL:
2101 /* DisplayPort PHY */
2102 case DP_PHY_CTRL:
2103 case 0x810:
2104 case 0x814:
2105 case 0x820:
2106 case 0x840:
2107 /* I2S */
2108 case 0x880:
2109 case 0x888:
2110 case 0x88c:
2111 case 0x890:
2112 case 0x894:
2113 case 0x898:
2114 case 0x89c:
2115 case 0x8a0:
2116 case 0x8a4:
2117 case 0x8a8:
2118 case 0x8ac:
2119 case 0x8b0:
2120 case 0x8b4:
2121 /* PLL */
2122 case DP0_PLLCTRL:
2123 case DP1_PLLCTRL:
2124 case PXL_PLLCTRL:
2125 case PXL_PLLPARAM:
2126 case SYS_PLLPARAM:
2127 /* HDCP */
2128 case 0x980:
2129 case 0x984:
2130 case 0x988:
2131 case 0x98c:
2132 case 0x990:
2133 case 0x994:
2134 case 0x998:
2135 case 0x99c:
2136 case 0x9a0:
2137 case 0x9a4:
2138 case 0x9a8:
2139 case 0x9ac:
2140 /* Debug */
2141 case TSTCTL:
2142 case PLL_DBG:
2143 return true;
2144 }
2145 return false;
2146}
2147
2148static const struct regmap_range tc_volatile_ranges[] = {
2149 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI),
2150 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI),
2151 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS),
2152 regmap_reg_range(DSIERRCNT, DSIERRCNT),
2153 regmap_reg_range(VFUEN0, VFUEN0),
2154 regmap_reg_range(SYSSTAT, SYSSTAT),
2155 regmap_reg_range(GPIOI, GPIOI),
2156 regmap_reg_range(INTSTS_G, INTSTS_G),
2157 regmap_reg_range(DP0_VMNGENSTATUS, DP0_VMNGENSTATUS),
2158 regmap_reg_range(DP0_AMNGENSTATUS, DP0_AMNGENSTATUS),
2159 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
2160 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
2161 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
2162 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
2163};
2164
2165static const struct regmap_access_table tc_volatile_table = {
2166 .yes_ranges = tc_volatile_ranges,
2167 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
2168};
2169
2170static const struct regmap_range tc_precious_ranges[] = {
2171 regmap_reg_range(SYSSTAT, SYSSTAT),
2172};
2173
2174static const struct regmap_access_table tc_precious_table = {
2175 .yes_ranges = tc_precious_ranges,
2176 .n_yes_ranges = ARRAY_SIZE(tc_precious_ranges),
2177};
2178
2179static bool tc_writeable_reg(struct device *dev, unsigned int reg)
2180{
2181 /* RO reg */
2182 switch (reg) {
2183 case PPI_BUSYPPI:
2184 case DSI_BUSYDSI:
2185 case DSI_LANESTATUS0:
2186 case DSI_LANESTATUS1:
2187 case DSI_INTSTATUS:
2188 case TC_IDREG:
2189 case SYSBOOT:
2190 case SYSSTAT:
2191 case GPIOI:
2192 case DP0_LTSTAT:
2193 case DP0_SNKLTCHGREQ:
2194 return false;
2195 }
2196 /* WO reg */
2197 switch (reg) {
2198 case DSI_STARTDSI:
2199 case DSI_INTCLR:
2200 return true;
2201 }
2202 return tc_readable_reg(dev, reg);
2203}
2204
2205static const struct regmap_config tc_regmap_config = {
2206 .name = "tc358767",
2207 .reg_bits = 16,
2208 .val_bits = 32,
2209 .reg_stride = 4,
2210 .max_register = PLL_DBG,
2211 .cache_type = REGCACHE_MAPLE,
2212 .readable_reg = tc_readable_reg,
2213 .writeable_reg = tc_writeable_reg,
2214 .volatile_table = &tc_volatile_table,
2215 .precious_table = &tc_precious_table,
2216 .reg_format_endian = REGMAP_ENDIAN_BIG,
2217 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2218};
2219
2220static irqreturn_t tc_irq_handler(int irq, void *arg)
2221{
2222 struct tc_data *tc = arg;
2223 u32 val;
2224 int r;
2225
2226 r = regmap_read(tc->regmap, INTSTS_G, &val);
2227 if (r)
2228 return IRQ_NONE;
2229
2230 if (!val)
2231 return IRQ_NONE;
2232
2233 if (val & INT_SYSERR) {
2234 u32 stat = 0;
2235
2236 regmap_read(tc->regmap, SYSSTAT, &stat);
2237
2238 dev_err(tc->dev, "syserr %x\n", stat);
2239 }
2240
2241 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) {
2242 /*
2243 * H is triggered when the GPIO goes high.
2244 *
2245 * LC is triggered when the GPIO goes low and stays low for
2246 * the duration of LCNT
2247 */
2248 bool h = val & INT_GPIO_H(tc->hpd_pin);
2249 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2250
2251 if (h || lc) {
2252 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2253 h ? "H" : "", lc ? "LC" : "");
2254 drm_kms_helper_hotplug_event(tc->bridge.dev);
2255 }
2256 }
2257
2258 regmap_write(tc->regmap, INTSTS_G, val);
2259
2260 return IRQ_HANDLED;
2261}
2262
2263static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2264{
2265 struct device *dev = tc->dev;
2266 struct device_node *host_node;
2267 struct device_node *endpoint;
2268 struct mipi_dsi_device *dsi;
2269 struct mipi_dsi_host *host;
2270 const struct mipi_dsi_device_info info = {
2271 .type = "tc358767",
2272 .channel = 0,
2273 .node = NULL,
2274 };
2275 int dsi_lanes, ret;
2276
2277 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2278 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
2279 host_node = of_graph_get_remote_port_parent(endpoint);
2280 host = of_find_mipi_dsi_host_by_node(host_node);
2281 of_node_put(host_node);
2282 of_node_put(endpoint);
2283
2284 if (!host)
2285 return -EPROBE_DEFER;
2286
2287 if (dsi_lanes < 0)
2288 return dsi_lanes;
2289
2290 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2291 if (IS_ERR(dsi))
2292 return dev_err_probe(dev, PTR_ERR(dsi),
2293 "failed to create dsi device\n");
2294
2295 tc->dsi = dsi;
2296 dsi->lanes = dsi_lanes;
2297 dsi->format = MIPI_DSI_FMT_RGB888;
2298 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2299 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
2300
2301 ret = devm_mipi_dsi_attach(dev, dsi);
2302 if (ret < 0) {
2303 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
2304 return ret;
2305 }
2306
2307 return 0;
2308}
2309
2310static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2311{
2312 struct device *dev = tc->dev;
2313 struct drm_bridge *bridge;
2314 struct drm_panel *panel;
2315 int ret;
2316
2317 /* port@1 is the DPI input/output port */
2318 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
2319 if (ret && ret != -ENODEV)
2320 return dev_err_probe(dev, ret,
2321 "Could not find DPI panel or bridge\n");
2322
2323 if (panel) {
2324 bridge = devm_drm_panel_bridge_add(dev, panel);
2325 if (IS_ERR(bridge))
2326 return PTR_ERR(bridge);
2327 }
2328
2329 if (bridge) {
2330 tc->panel_bridge = bridge;
2331 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2332 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2333
2334 return 0;
2335 }
2336
2337 return ret;
2338}
2339
2340static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2341{
2342 struct device *dev = tc->dev;
2343 struct drm_panel *panel;
2344 int ret;
2345
2346 /* port@2 is the output port */
2347 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
2348 if (ret && ret != -ENODEV)
2349 return dev_err_probe(dev, ret,
2350 "Could not find DSI panel or bridge\n");
2351
2352 if (panel) {
2353 struct drm_bridge *panel_bridge;
2354
2355 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
2356 if (IS_ERR(panel_bridge))
2357 return PTR_ERR(panel_bridge);
2358
2359 tc->panel_bridge = panel_bridge;
2360 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2361 } else {
2362 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2363 }
2364
2365 tc->bridge.funcs = &tc_edp_bridge_funcs;
2366 if (tc->hpd_pin >= 0)
2367 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2368 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2369
2370 return 0;
2371}
2372
2373static int tc_probe_bridge_endpoint(struct tc_data *tc)
2374{
2375 struct device *dev = tc->dev;
2376 struct of_endpoint endpoint;
2377 struct device_node *node = NULL;
2378 const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
2379 const u8 mode_dpi_to_dp = BIT(1);
2380 const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
2381 const u8 mode_dsi_to_dp = BIT(0);
2382 const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
2383 u8 mode = 0;
2384
2385 /*
2386 * Determine bridge configuration.
2387 *
2388 * Port allocation:
2389 * port@0 - DSI input
2390 * port@1 - DPI input/output
2391 * port@2 - eDP output
2392 *
2393 * Possible connections:
2394 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2395 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2396 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2397 */
2398
2399 for_each_endpoint_of_node(dev->of_node, node) {
2400 of_graph_parse_endpoint(node, &endpoint);
2401 if (endpoint.port > 2) {
2402 of_node_put(node);
2403 return -EINVAL;
2404 }
2405 mode |= BIT(endpoint.port);
2406
2407 if (endpoint.port == 2) {
2408 of_property_read_u8_array(node, "toshiba,pre-emphasis",
2409 tc->pre_emphasis,
2410 ARRAY_SIZE(tc->pre_emphasis));
2411
2412 if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 ||
2413 tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) {
2414 dev_err(dev, "Incorrect Pre-Emphasis setting, use either 0=0dB 1=3.5dB 2=6dB\n");
2415 of_node_put(node);
2416 return -EINVAL;
2417 }
2418 }
2419 }
2420
2421 if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {
2422 tc->input_connector_dsi = false;
2423 return tc_probe_edp_bridge_endpoint(tc);
2424 } else if (mode == mode_dsi_to_dpi) {
2425 tc->input_connector_dsi = true;
2426 return tc_probe_dpi_bridge_endpoint(tc);
2427 } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {
2428 tc->input_connector_dsi = true;
2429 return tc_probe_edp_bridge_endpoint(tc);
2430 }
2431
2432 dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
2433
2434 return -EINVAL;
2435}
2436
2437static int tc_probe(struct i2c_client *client)
2438{
2439 struct device *dev = &client->dev;
2440 struct tc_data *tc;
2441 int ret;
2442
2443 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
2444 if (!tc)
2445 return -ENOMEM;
2446
2447 tc->dev = dev;
2448
2449 ret = tc_probe_bridge_endpoint(tc);
2450 if (ret)
2451 return ret;
2452
2453 tc->refclk = devm_clk_get_enabled(dev, "ref");
2454 if (IS_ERR(tc->refclk))
2455 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2456 "Failed to get and enable the ref clk\n");
2457
2458 /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
2459 usleep_range(10, 15);
2460
2461 /* Shut down GPIO is optional */
2462 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2463 if (IS_ERR(tc->sd_gpio))
2464 return PTR_ERR(tc->sd_gpio);
2465
2466 if (tc->sd_gpio) {
2467 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2468 usleep_range(5000, 10000);
2469 }
2470
2471 /* Reset GPIO is optional */
2472 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2473 if (IS_ERR(tc->reset_gpio))
2474 return PTR_ERR(tc->reset_gpio);
2475
2476 if (tc->reset_gpio) {
2477 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2478 usleep_range(5000, 10000);
2479 }
2480
2481 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2482 if (IS_ERR(tc->regmap)) {
2483 ret = PTR_ERR(tc->regmap);
2484 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
2485 return ret;
2486 }
2487
2488 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
2489 &tc->hpd_pin);
2490 if (ret) {
2491 tc->hpd_pin = -ENODEV;
2492 } else {
2493 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2494 dev_err(dev, "failed to parse HPD number\n");
2495 return -EINVAL;
2496 }
2497 }
2498
2499 if (client->irq > 0) {
2500 /* enable SysErr */
2501 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2502
2503 ret = devm_request_threaded_irq(dev, client->irq,
2504 NULL, tc_irq_handler,
2505 IRQF_ONESHOT,
2506 "tc358767-irq", tc);
2507 if (ret) {
2508 dev_err(dev, "failed to register dp interrupt\n");
2509 return ret;
2510 }
2511
2512 tc->have_irq = true;
2513 }
2514
2515 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2516 if (ret) {
2517 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2518 return ret;
2519 }
2520
2521 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2522 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2523 return -EINVAL;
2524 }
2525
2526 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2527
2528 if (!tc->reset_gpio) {
2529 /*
2530 * If the reset pin isn't present, do a software reset. It isn't
2531 * as thorough as the hardware reset, as we can't reset the I2C
2532 * communication block for obvious reasons, but it's getting the
2533 * chip into a defined state.
2534 */
2535 regmap_update_bits(tc->regmap, SYSRSTENB,
2536 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2537 0);
2538 regmap_update_bits(tc->regmap, SYSRSTENB,
2539 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2540 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
2541 usleep_range(5000, 10000);
2542 }
2543
2544 if (tc->hpd_pin >= 0) {
2545 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2546 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2547
2548 /* Set LCNT to 2ms */
2549 regmap_write(tc->regmap, lcnt_reg,
2550 clk_get_rate(tc->refclk) * 2 / 1000);
2551 /* We need the "alternate" mode for HPD */
2552 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2553
2554 if (tc->have_irq) {
2555 /* enable H & LC */
2556 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2557 }
2558 }
2559
2560 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2561 ret = tc_aux_link_setup(tc);
2562 if (ret)
2563 return ret;
2564 }
2565
2566 tc->bridge.of_node = dev->of_node;
2567 drm_bridge_add(&tc->bridge);
2568
2569 i2c_set_clientdata(client, tc);
2570
2571 if (tc->input_connector_dsi) { /* DSI input */
2572 ret = tc_mipi_dsi_host_attach(tc);
2573 if (ret) {
2574 drm_bridge_remove(&tc->bridge);
2575 return dev_err_probe(dev, ret, "Failed to attach DSI host\n");
2576 }
2577 }
2578
2579 return 0;
2580}
2581
2582static void tc_remove(struct i2c_client *client)
2583{
2584 struct tc_data *tc = i2c_get_clientdata(client);
2585
2586 drm_bridge_remove(&tc->bridge);
2587}
2588
2589static const struct i2c_device_id tc358767_i2c_ids[] = {
2590 { "tc358767", 0 },
2591 { }
2592};
2593MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
2594
2595static const struct of_device_id tc358767_of_ids[] = {
2596 { .compatible = "toshiba,tc358767", },
2597 { }
2598};
2599MODULE_DEVICE_TABLE(of, tc358767_of_ids);
2600
2601static struct i2c_driver tc358767_driver = {
2602 .driver = {
2603 .name = "tc358767",
2604 .of_match_table = tc358767_of_ids,
2605 },
2606 .id_table = tc358767_i2c_ids,
2607 .probe = tc_probe,
2608 .remove = tc_remove,
2609};
2610module_i2c_driver(tc358767_driver);
2611
2612MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
2613MODULE_DESCRIPTION("tc358767 eDP encoder driver");
2614MODULE_LICENSE("GPL");