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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/of.h>
30#include <linux/pci.h>
31
32#include <drm/drm_atomic_helper.h>
33#include <drm/drm_drv.h>
34#include <drm/drm_gem.h>
35#include <drm/drm_managed.h>
36
37#include "ast_drv.h"
38
39static void ast_detect_widescreen(struct ast_device *ast)
40{
41 u8 jreg;
42
43 /* Check if we support wide screen */
44 switch (AST_GEN(ast)) {
45 case 1:
46 ast->support_wide_screen = false;
47 break;
48 default:
49 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
50 if (!(jreg & 0x80))
51 ast->support_wide_screen = true;
52 else if (jreg & 0x01)
53 ast->support_wide_screen = true;
54 else {
55 ast->support_wide_screen = false;
56 if (ast->chip == AST1300)
57 ast->support_wide_screen = true;
58 if (ast->chip == AST1400)
59 ast->support_wide_screen = true;
60 if (ast->chip == AST2510)
61 ast->support_wide_screen = true;
62 if (IS_AST_GEN7(ast))
63 ast->support_wide_screen = true;
64 }
65 break;
66 }
67}
68
69static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
70{
71 static const char * const info_str[] = {
72 "analog VGA",
73 "Sil164 TMDS transmitter",
74 "DP501 DisplayPort transmitter",
75 "ASPEED DisplayPort transmitter",
76 };
77
78 struct drm_device *dev = &ast->base;
79 u8 jreg, vgacrd1;
80
81 /*
82 * Several of the listed TX chips are not explicitly supported
83 * by the ast driver. If these exist in real-world devices, they
84 * are most likely reported as VGA or SIL164 outputs. We warn here
85 * to get bug reports for these devices. If none come in for some
86 * time, we can begin to fail device probing on these values.
87 */
88 vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK);
89 drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ITE66121_VBIOS,
90 "ITE IT66121 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
91 drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_CH7003_VBIOS,
92 "Chrontel CH7003 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
93 drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ANX9807_VBIOS,
94 "Analogix ANX9807 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
95
96 /* Check 3rd Tx option (digital output afaik) */
97 ast->tx_chip = AST_TX_NONE;
98
99 /*
100 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
101 * enabled, in that case, assume we have a SIL164 TMDS transmitter
102 *
103 * Don't make that assumption if we the chip wasn't enabled and
104 * is at power-on reset, otherwise we'll incorrectly "detect" a
105 * SIL164 when there is none.
106 */
107 if (!need_post) {
108 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
109 if (jreg & 0x80)
110 ast->tx_chip = AST_TX_SIL164;
111 }
112
113 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
114 /*
115 * On AST GEN4+, look the configuration set by the SoC in
116 * the SOC scratch register #1 bits 11:8 (interestingly marked
117 * as "reserved" in the spec)
118 */
119 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
120 AST_IO_VGACRD1_TX_TYPE_MASK);
121 switch (jreg) {
122 case AST_IO_VGACRD1_TX_SIL164_VBIOS:
123 ast->tx_chip = AST_TX_SIL164;
124 break;
125 case AST_IO_VGACRD1_TX_DP501_VBIOS:
126 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
127 if (ast->dp501_fw_addr) {
128 /* backup firmware */
129 if (ast_backup_fw(ast, ast->dp501_fw_addr, 32*1024)) {
130 drmm_kfree(dev, ast->dp501_fw_addr);
131 ast->dp501_fw_addr = NULL;
132 }
133 }
134 fallthrough;
135 case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
136 ast->tx_chip = AST_TX_DP501;
137 }
138 } else if (IS_AST_GEN7(ast)) {
139 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
140 AST_IO_VGACRD1_TX_ASTDP) {
141 int ret = ast_dp_launch(ast);
142
143 if (!ret)
144 ast->tx_chip = AST_TX_ASTDP;
145 }
146 }
147
148 drm_info(dev, "Using %s\n", info_str[ast->tx_chip]);
149}
150
151static int ast_get_dram_info(struct ast_device *ast)
152{
153 struct drm_device *dev = &ast->base;
154 struct device_node *np = dev->dev->of_node;
155 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
156 uint32_t denum, num, div, ref_pll, dsel;
157
158 switch (ast->config_mode) {
159 case ast_use_dt:
160 /*
161 * If some properties are missing, use reasonable
162 * defaults for GEN5
163 */
164 if (of_property_read_u32(np, "aspeed,mcr-configuration",
165 &mcr_cfg))
166 mcr_cfg = 0x00000577;
167 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
168 &mcr_scu_mpll))
169 mcr_scu_mpll = 0x000050C0;
170 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
171 &mcr_scu_strap))
172 mcr_scu_strap = 0;
173 break;
174 case ast_use_p2a:
175 ast_write32(ast, 0xf004, 0x1e6e0000);
176 ast_write32(ast, 0xf000, 0x1);
177 mcr_cfg = ast_read32(ast, 0x10004);
178 mcr_scu_mpll = ast_read32(ast, 0x10120);
179 mcr_scu_strap = ast_read32(ast, 0x10170);
180 break;
181 case ast_use_defaults:
182 default:
183 ast->dram_bus_width = 16;
184 ast->dram_type = AST_DRAM_1Gx16;
185 if (IS_AST_GEN6(ast))
186 ast->mclk = 800;
187 else
188 ast->mclk = 396;
189 return 0;
190 }
191
192 if (mcr_cfg & 0x40)
193 ast->dram_bus_width = 16;
194 else
195 ast->dram_bus_width = 32;
196
197 if (IS_AST_GEN6(ast)) {
198 switch (mcr_cfg & 0x03) {
199 case 0:
200 ast->dram_type = AST_DRAM_1Gx16;
201 break;
202 default:
203 case 1:
204 ast->dram_type = AST_DRAM_2Gx16;
205 break;
206 case 2:
207 ast->dram_type = AST_DRAM_4Gx16;
208 break;
209 case 3:
210 ast->dram_type = AST_DRAM_8Gx16;
211 break;
212 }
213 } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) {
214 switch (mcr_cfg & 0x03) {
215 case 0:
216 ast->dram_type = AST_DRAM_512Mx16;
217 break;
218 default:
219 case 1:
220 ast->dram_type = AST_DRAM_1Gx16;
221 break;
222 case 2:
223 ast->dram_type = AST_DRAM_2Gx16;
224 break;
225 case 3:
226 ast->dram_type = AST_DRAM_4Gx16;
227 break;
228 }
229 } else {
230 switch (mcr_cfg & 0x0c) {
231 case 0:
232 case 4:
233 ast->dram_type = AST_DRAM_512Mx16;
234 break;
235 case 8:
236 if (mcr_cfg & 0x40)
237 ast->dram_type = AST_DRAM_1Gx16;
238 else
239 ast->dram_type = AST_DRAM_512Mx32;
240 break;
241 case 0xc:
242 ast->dram_type = AST_DRAM_1Gx32;
243 break;
244 }
245 }
246
247 if (mcr_scu_strap & 0x2000)
248 ref_pll = 14318;
249 else
250 ref_pll = 12000;
251
252 denum = mcr_scu_mpll & 0x1f;
253 num = (mcr_scu_mpll & 0x3fe0) >> 5;
254 dsel = (mcr_scu_mpll & 0xc000) >> 14;
255 switch (dsel) {
256 case 3:
257 div = 0x4;
258 break;
259 case 2:
260 case 1:
261 div = 0x2;
262 break;
263 default:
264 div = 0x1;
265 break;
266 }
267 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
268 return 0;
269}
270
271struct drm_device *ast_device_create(struct pci_dev *pdev,
272 const struct drm_driver *drv,
273 enum ast_chip chip,
274 enum ast_config_mode config_mode,
275 void __iomem *regs,
276 void __iomem *ioregs,
277 bool need_post)
278{
279 struct drm_device *dev;
280 struct ast_device *ast;
281 int ret;
282
283 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
284 if (IS_ERR(ast))
285 return ERR_CAST(ast);
286 dev = &ast->base;
287
288 ast->chip = chip;
289 ast->config_mode = config_mode;
290 ast->regs = regs;
291 ast->ioregs = ioregs;
292
293 ast_detect_widescreen(ast);
294 ast_detect_tx_chip(ast, need_post);
295
296 ret = ast_get_dram_info(ast);
297 if (ret)
298 return ERR_PTR(ret);
299
300 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
301 ast->mclk, ast->dram_type, ast->dram_bus_width);
302
303 if (need_post)
304 ast_post_gpu(ast);
305
306 ret = ast_mm_init(ast);
307 if (ret)
308 return ERR_PTR(ret);
309
310 /* map reserved buffer */
311 ast->dp501_fw_buf = NULL;
312 if (ast->vram_size < pci_resource_len(pdev, 0)) {
313 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
314 if (!ast->dp501_fw_buf)
315 drm_info(dev, "failed to map reserved buffer!\n");
316 }
317
318 ret = ast_mode_config_init(ast);
319 if (ret)
320 return ERR_PTR(ret);
321
322 return dev;
323}