1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 4 */
 5
 6#ifndef __SOC_TEGRA_FUSE_H__
 7#define __SOC_TEGRA_FUSE_H__
 8
 9#define TEGRA20		0x20
10#define TEGRA30		0x30
11#define TEGRA114	0x35
12#define TEGRA124	0x40
13#define TEGRA132	0x13
14#define TEGRA210	0x21
15#define TEGRA186	0x18
16#define TEGRA194	0x19
17
18#define TEGRA_FUSE_SKU_CALIB_0	0xf0
19#define TEGRA30_FUSE_SATA_CALIB	0x124
20#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
21
22#ifndef __ASSEMBLY__
23
24u32 tegra_read_chipid(void);
25u8 tegra_get_chip_id(void);
26
27enum tegra_revision {
28	TEGRA_REVISION_UNKNOWN = 0,
29	TEGRA_REVISION_A01,
30	TEGRA_REVISION_A02,
31	TEGRA_REVISION_A03,
32	TEGRA_REVISION_A03p,
33	TEGRA_REVISION_A04,
34	TEGRA_REVISION_MAX,
35};
36
37struct tegra_sku_info {
38	int sku_id;
39	int cpu_process_id;
40	int cpu_speedo_id;
41	int cpu_speedo_value;
42	int cpu_iddq_value;
43	int soc_process_id;
44	int soc_speedo_id;
45	int soc_speedo_value;
46	int gpu_process_id;
47	int gpu_speedo_id;
48	int gpu_speedo_value;
49	enum tegra_revision revision;
50};
51
52u32 tegra_read_straps(void);
53u32 tegra_read_ram_code(void);
54int tegra_fuse_readl(unsigned long offset, u32 *value);
55
56extern struct tegra_sku_info tegra_sku_info;
57
58struct device *tegra_soc_device_register(void);
59
60#endif /* __ASSEMBLY__ */
61
62#endif /* __SOC_TEGRA_FUSE_H__ */